ETC SC16C2550B

SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with
16-byte FIFOs
Rev. 01 — 29 March 2004
Product data
1. Description
The SC16C2550B is a two channel Universal Asynchronous Receiver and
Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s.
The SC16C2550B is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550B provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and
RXRDY signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loop-back capability allows
on-board diagnostics. Independent programmable baud rate generators are provided
to select transmit and receive baud rates.
The SC16C2550B operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.
2. Features
■
■
■
■
■
■
■
■
■
■
■
■
2 channel UART
5 V, 3.3 V and 2.5 V operation
Industrial temperature range
Pin and functionally compatible to 16C2450 and software compatible with
INS8250, SC16C550
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU
16 byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive FIFO interrupt trigger levels
Software selectable Baud Rate Generator
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
■ Fully programmable character formatting:
◆ 5, 6, 7, or 8-bit characters
◆ Even, Odd, or No-Parity formats
◆ 1, 11⁄2, or 2-stop bit
◆ Baud generation (DC to 5 Mbit/s)
■ False start-bit detection
■ Complete status reporting capabilities
■ 3-State output TTL drive capabilities for bi-directional data bus and control bus
■ Line Break generation and detection
■ Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
■ Prioritized interrupt system controls
■ Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
SC16C2550BIN40
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
SC16C2550BIA44
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
SC16C2550BIB48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
2 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
4. Block diagram
SC16C2550B
A0–A2
CSA
CSB
TRANSMIT
SHIFT
REGISTER
TXA, TXB
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
D0–D7
IOR
IOW
RESET
TRANSMIT
FIFO
REGISTER
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
MODEM
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
CLOCK AND
BAUD RATE
GENERATOR
002aaa595
XTAL1
XTAL2
Fig 1. SC16C2550B block diagram.
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9397 750 11982
Product data
Rev. 01 — 29 March 2004
3 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
5. Pinning information
5.1 Pinning
40 VCC
D1 2
39 RIA
D2 3
38 CDA
D3 4
37 DSRA
D4 5
36 CTSA
D5 6
35 RESET
D6 7
34 DTRB
D7 8
33 DTRA
RXB 9
RXA 10
TXA 11
TXB 12
SC16C2550BIN40
D0 1
32 RTSA
31 OP2A
30 INTA
29 INTB
OP2B 13
28 A0
CSA 14
27 A1
CSB 15
26 A2
XTAL1 16
25 CTSB
XTAL2 17
24 RTSB
IOW 18
23 RIB
CDB 19
22 DSRB
GND 20
21 IOR
002aaa596
Fig 2. DIP40 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
4 of 42
SC16C2550B
Philips Semiconductors
40 CTSA
41 DSRA
42 CDA
43 RIA
44 VCC
1 TXRDYA
2 D0
3 D1
4 D2
5 D3
6 D4
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D5
7
39 RESET
D6
8
38 DTRB
D7
9
37 DTRA
RXB 10
36 RTSA
RXA 11
35 OP2A
SC16C2550BIA44
TXRDYB 12
34 RXRDYA
TXA 13
33 INTA
TXB 14
32 INTB
CTSB 28
RTSB 27
RIB 26
DSRB 25
IOR 24
RXRDYB 23
29 A2
GND 22
CSB 17
CDB 21
30 A1
IOW 20
CSA 16
XTAL2 19
31 A0
XTAL1 18
OP2B 15
002aaa597
Fig 3. PLCC44 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
5 of 42
SC16C2550B
Philips Semiconductors
37 N.C.
38 CTSA
39 DSRA
40 CDA
41 RIA
42 VCC
43 TXRDYA
44 D0
45 D1
46 D2
47 D3
48 D4
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
D5
1
36 RESET
D6
2
35 DTRB
D7
3
34 DTRA
RXB
4
33 RTSA
RXA
5
32 OP2A
TXRDYB
6
31 RXRDYA
SC16C2550BIB48
26 A2
N.C. 12
25 N.C.
N.C. 24
CSB 11
CTSB 23
27 A1
RTSB 22
CSA 10
RIB 21
28 A0
DSRB 20
9
IOR 19
OP2B
RXRDYB 18
29 INTB
GND 17
8
CDB 16
TXB
IOW 15
30 INTA
XTAL2 14
7
XTAL1 13
TXA
002aaa598
Fig 4. LQFP48 pin configuration.
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type Description
DIP40 PLCC44 LQFP48
A0
28
31
28
I
Address 0 select bit. Internal register address selection.
A1
27
30
27
I
Address 1 select bit. Internal register address selection.
A2
26
29
26
I
Address 2 select bit. Internal register address selection.
CSA, CSB 14, 15 16, 17
10, 11
I
Chip Select A, B (Active-LOW). This function is associated with individual
channels, A through B. These pins enable data transfers between the user
CPU and the SC16C2550B for the channel(s) addressed. Individual UART
sections (A, B) are addressed by providing a logic 0 on the respective CSA,
CSB pin.
D0-D7
1-8
2-9
44-48,
1-3
I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for
transferring information to or from the controlling CPU. D0 is the least
significant bit and the first data bit in a transmit or receive serial data
stream.
GND
20
22
17
I
Signal and power ground.
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9397 750 11982
Product data
Rev. 01 — 29 March 2004
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2:
Pin description…continued
Symbol
Pin
Type Description
DIP40 PLCC44 LQFP48
INTA,
INTB
30, 29 33, 32
30, 29
O
Interrupt A, B (3-State). This function is associated with individual channel
interrupts, INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a
logic 1, interrupts are enabled in the interrupt enable register (IER), and is
active when an interrupt condition exists. Interrupt conditions include:
receiver errors, available receiver buffer data, transmit buffer empty, or
when a modem status flag is detected.
IOR
21
24
19
I
Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load
the contents of an internal register defined by address bits A0-A2 onto the
SC16C2550B data bus (D0-D7) for access by external CPU.
IOW
18
20
15
I
Write strobe (Active-LOW strobe). A logic 0 transition on this pin will
transfer the contents of the data bus (D0-D7) from the external CPU to an
internal register that is defined by address bits A0-A2.
OP2A,
OP2B
31, 13 35, 15
32, 9
O
Output 2 (user-defined). This function is associated with individual
channels, A through B. The state at these pin(s) are defined by the user
and through MCR register bit 3. INTA, INTB are set to the active mode and
OP2 to logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the
3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0. See
bit 3, Modem Control Register (MCR[3]). Since these bits control both the
INTA, INTB operation and OP2 outputs, only one function should be used
at one time, INT or OP2.
RESET
35
39
36
I
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers
and all the outputs. The UART transmitter output and the receiver input will
be disabled during reset time. (See Section 7.10 “SC16C2550B external
reset condition” for initialization details.)
RXRDYA,
RXRDYB
-
34, 23
31, 18
O
Receive Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. This function provides the
RX FIFO/RHR status for individual receive channels (A-B). RXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the receive data
FIFOs. A logic 0 indicates there is a receive data to read/upload, i.e.,
receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the
programmed trigger level has not been reached. This signal can also be
used for single mode transfers (DMA mode 0).
TXRDYA,
TXRDYB
-
1, 12
43, 6
O
Transmit Ready A, B (Active-LOW). This function is associated with
PLCC44 and LQFP48 packages only. These outputs provide the
TX FIFO/THR status for individual transmit channels (A-B). TXRDYn is
primarily intended for monitoring DMA mode 1 transfers for the transmit
data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer ready status
is indicated by logic 0, i.e., at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are
no more empty locations in the FIFO or THR. This signal can also be used
for single mode transfers (DMA mode 0).
VCC
40
44
42
I
Power supply input.
XTAL1
16
18
13
I
Crystal or external clock input. Functions as a crystal input or as an
external clock input. A crystal can be connected between this pin and
XTAL2 to form an internal oscillator circuit. Alternatively, an external clock
can be connected to this pin to provide custom data rates. (See Section 6.5
“Programmable baud rate generator”.) See Figure 5.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
7 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2:
Pin description…continued
Symbol
Pin
Type Description
DIP40 PLCC44 LQFP48
XTAL2
17
CDA,
CDB
14
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.)
Crystal oscillator output or buffered clock output. Should be left open if an
external clock is connected to XTAL1. For extended frequency operation,
this pin should be tied to VCC via a 2 kΩ resistor.
38, 19 42, 21
40, 16
I
Carrier Detect (Active-LOW). These inputs are associated with individual
UART channels A through B. A logic 0 on this pin indicates that a carrier
has been detected by the modem for that channel.
CTSA,
CTSB
36, 25 40, 28
38, 23
I
Clear to Send (Active-LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on the CTS pin indicates the
modem or data set is ready to accept transmit data from the SC16C2550B.
Status can be tested by reading MSR[4]. This pin has no effect on the
UART’s transmit or receive operation.
DSRA,
DSRB
37, 22 41, 25
39, 20
I
Data Set Ready (Active-LOW). These inputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates the
modem or data set is powered-on and is ready for data exchange with the
UART. This pin has no effect on the UART’s transmit or receive operation.
DTRA,
DTRB
33, 34 37, 38
34, 35
O
Data Terminal REady (Active-LOW). These outputs are associated with
individual UART channels, A through B. A logic 0 on this pin indicates that
the SC16C2550B is powered-on and ready. This pin can be controlled via
the modem control register. Writing a logic 1 to MCR[0] will set the DTR
output to logic 0, enabling the modem. This pin will be a logic 1 after writing
a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s
transmit or receive operation.
RIA, RIB
39, 23 43, 26
41, 21
I
Ring Indicator (Active-LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
RTSA,
RTSB
32, 24 36, 27
33, 22
O
Request to Send (Active-LOW). These outputs are associated with
individual UART channels, A through B. A logic 0 on the RTS pin indicates
the transmitter has data ready and waiting to send. Writing a logic 1 in the
modem control register MCR[1] will set this pin to a logic 0, indicating data
is available. After a reset this pin will be set to a logic 1. This pin has no
effect on the UART’s transmit or receive operation.
11, 10
5, 4
I
Receive data A, B. These inputs are associated with individual serial
channel data to the SC16C2550B receive input circuits, A-B. The RX signal
will be a logic 1 during reset, idle (no data), or when the transmitter is
disabled. During the local loop-back mode, the RX input pin is disabled and
TX data is connected to the UART RX input, internally.
TXA, TXB 11, 12 13, 14
7, 8
O
Transmit data A, B. These outputs are associated with individual serial
transmit channel data from the SC16C2550B. The TX signal will be a
logic 1 during reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the TX output pin is disabled and TX data
is internally connected to the UART RX input.
RXA, RXB 10, 9
19
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6. Functional description
The SC16C2550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The electronic circuitry to provide all these functions is
fairly complex, especially when manufactured on a single integrated silicon chip. The
SC16C2550B represents such an integration with greatly enhanced features. The
SC16C2550B is fabricated with an advanced CMOS process.
The SC16C2550B is an upward solution that provides a dual UART capability with
16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The
SC16C2550B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is
realized in the SC16C2550B by the transmit and receive FIFOs. This allows the
external processor to handle more networking tasks within a given time. For example,
the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (this example uses a character length of 11 bits, including start/stop
bits at 115.2 kbit/s). This means the external CPU will have to service the receive
FIFO less than every 100 microseconds. However, with the 16 byte FIFO in the
SC16C2550B, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the
four selectable receive FIFO trigger interrupt levels is uniquely provided for maximum
data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the
external controlling CPU, increases performance, and reduces power consumption.
The SC16C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature set of the SC16C2550B is available through internal registers.
Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem
interface controls are all standard features. Following a power-on reset or an external
reset, the SC16C2550B is software compatible with the previous generation,
ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C2550B package, and an external serial device.
A logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are
shown in Table 3.
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 3:
Serial port selection
Chip Select
Function
CSA-CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
6.2 Internal registers
The SC16C2550B provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
Table 4:
A2
Internal registers decoding
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
Interrupt Enable Register
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
1
Line Control Register
Line Control Register
1
0
0
Modem Control Register
Modem Control Register
1
0
1
Line Status Register
n/a
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
[1]
[2]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
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9397 750 11982
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.3 FIFO operation
The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control
Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but
not the transmit trigger level. The receiver FIFO section includes a time-out function
to ensure data is delivered to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read following the loading of a
character or the receive trigger level has not been reached.
Table 5:
Flow control mechanism
Selected trigger level (characters)
INT pin activation
1
1
4
4
8
8
14
14
6.4 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C2550B will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The ISR register provides the current singular
highest priority interrupt only. A condition can exist where a higher priority interrupt
may mask the lower priority interrupt(s). Only after servicing the higher pending
interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing
the interrupt without investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C2550B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,
1.5×, or 2× bit times.
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
6.5 Programmable baud rate generator
The SC16C2550B supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C2550B can support a standard data rate of
921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate,
it is necessary to use full rail swing on the clock input. The SC16C2550B can be
configured for internal or external clock operation. For internal clock oscillator
operation, an industry standard microprocessor crystal is connected externally
between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to 216 − 1. The
SC16C2550B divides the basic external clock by 16. The basic 16× clock provides
table rates to support standard and custom applications using the same system
design. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
X1
1.8432 MHz
C1
22 pF
XTAL2
XTAL1
XTAL2
XTAL1
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 6 shows the selectable baud rate table available when using a 1.8432 MHz
external clock input.
X1
1.8432 MHz
C2
33 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa586
Fig 5. Crystal oscillator connection.
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 6:
Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
Output
Output
DLM
16 × clock divisor 16 × clock divisor program value
(decimal)
(HEX)
(HEX)
DLL
program value
(HEX)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
6.6 DMA operation
The SC16C2550B FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[5,6] provide an indication when the transmitter is empty or has
an empty location(s). The user can optionally operate the transmit and receive FIFOs
in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and
the DMA mode is de-activated (DMA Mode 0), the SC16C2550B activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is
activated (DMA Mode 1), the user takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the receive trigger
level and the transmit FIFO. In this mode, the SC16C2550B sets the TXRDY (or
RXRDY) output pin when characters in the transmit FIFO is below 16, or the
characters in the receive FIFOs are above the receive trigger level.
6.7 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see Figure 6). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
SC16C2550B
TRANSMIT
FIFO
REGISTER
D0–D7
IOR
IOW
RESET
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL LOGIC
A0–A2
CSA, CSB
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MCR[4] = 1
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
MODEM
CONTROL
LOGIC
DSRA, DSRB
(OP1A, OP1B)
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
RIA, RIB
CLOCK AND
BAUD RATE
GENERATOR
(OP2A, OP2B)
CDA, CDB
002aaa599
XTAL1
XTAL2
Fig 6. Internal loop-back mode diagram.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7. Register descriptions
Table 7 details the assigned bit functions for the SC16C2550B internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.10.
Table 7:
SC16C2550B internal registers
A2
A0
A1
Register Default[1] Bit 7
General Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set[2]
0
0
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
IER
00
0
0
0
0
modem receive
status
line
interrupt status
interrupt
transmit
holding
register
interrupt
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
reserved
0
reserved
0
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
0
0
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
1
LCR
00
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
bit 1
1
0
0
MCR
00
0
0
1
0
1
LSR
60
FIFO
data
error
1
1
0
MSR
X0
1
1
1
SPR
Special Register
word
length
bit 0
loop back OP2/INT (OP1)
enable
RTS
DTR
THR and THR
TSR
empty
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
∆CTS
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
Set[3]
0
0
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
[1]
[2]
[3]
The value shown in represents the register’s initialized HEX value; X = n/a.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the
SC16C2550B and receive FIFO by reading the RHR register. The receive section
provides a mechanism to prevent false starts. On the falling edge of a start or false
start bit, an internal receiver counter starts counting clocks at the 16× clock rate. After
7-1⁄2 clocks, the start bit time should be shifted to the center of the start bit. At this
time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start
bit in this manner prevents the receiver from assembling a false character. Receiver
status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 8:
Interrupt Enable Register bits description
Bit
Symbol
Description
7-4
IER[7-4]
Not used.
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1-4].
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO is empty.
Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)
interrupt (normal default condition).
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
0
IER[0]
Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger level or is cleared when
the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)
interrupt (normal default condition).
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
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7.2.1
IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550B in the FIFO
polled mode of operation. In this mode, interrupts are not generated and the user
must poll the LSR register for TX and/or RX data status. Since the receiver and
transmitter have separate bits in the LSR either or both can be used in the polled
mode by selecting respective transmit or receive control bit(s).
•
•
•
•
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
• LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) on
PLCC44 and LQFP48 packages will go to a logic 0 whenever the FIFO (THR, if FIFO
is not enabled) is empty. Receive Ready (RXRDY) on PLCC44 and LQFP48
packages will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded
with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO is empty. TXRDY on PLCC and
LQFP48 packages remains a logic 0 as long as one empty FIFO location is available.
The receive interrupt is set when the receive FIFO fills to the programmed trigger
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level. However, the FIFO continues to fill regardless of the programmed level until the
FIFO is full. RXRDY on PLCC44 and LQFP48 packages transitions LOW when the
FIFO reaches the trigger level, and transitions HIGH when the FIFO empties.
7.3.2
FIFO mode
Table 9:
FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7-6]
RCVR trigger. These bits are used to set the trigger level for the
receive FIFO interrupt.
Logic 0 (or cleared) = normal default condition.
Logic 1 = RX trigger level.
An interrupt is generated when the number of characters in the
FIFO equals the programmed trigger level. However, the FIFO will
continue to be loaded until it is full. Refer to Table 10.
5-4
FCR[5-4]
Not used; initialized to logic 0.
3
FCR[3]
DMA mode select.
Logic 0 = Set DMA mode ‘0’
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C2550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO
mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and
when there are no characters in the transmit FIFO or transmit
holding register, the TXRDY pin in PLCC44 or LQFP48 packages
will be a logic 0. Once active, the TXRDY pin will go to a logic 1
after the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C2550B is in
mode ‘0’ (FCR[0] = logic 0), or in the FIFO mode (FCR[3] = logic 0)
and there is at lease one character in the receive FIFO, the
RXRDY pin will be a logic 0. Once active, the RXRDY pin on
PLCC44 and LQFP48 packages will go to a logic 1 when there are
no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C2550B is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin on
PLCC44 and LQFP48 packages will be a logic 1 when the transmit
FIFO is completely full. It will be a logic 0 if one or more FIFO
locations are empty.
Receive operation in mode ‘1’: When the SC16C2550B is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger
level has been reached, or a Receive Time-Out has occurred, the
RXRDY pin on PLCC44 and LQFP48 packages will go to a logic 0.
Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
Logic 0 = Transmit FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets
the FIFO counter logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing the FIFO.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 9:
FIFO Control Register bits description…continued
Bit
Symbol
Description
1
FCR[1]
RCVR FIFO reset.
Logic 0 = Receive FIFO not reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFOs enabled.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
Table 10:
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0
0
01
0
1
04
1
0
08
1
1
14
7.4 Interrupt Status Register (ISR)
The SC16C2550B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits. Table 11
“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 11:
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
1
0
LSR (Receiver Line Status Register)
2
0
1
0
0
RXRDY (Received Data Ready)
2
1
1
0
0
RXRDY (Receive Data time-out)
3
0
0
1
0
TXRDY (Transmitter Holding Register Empty)
4
0
0
0
0
MSR (Modem Status Register)
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Table 12:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2550B mode.
Logic 0 or cleared = default condition.
5-4
ISR[5-4]
Not used.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 11).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 13:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5-3
LCR[5-3]
Programs the parity conditions (see Table 14).
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 15).
Logic 0 or cleared = default condition.
1-0
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 16).
Logic 0 or cleared = default condition.
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Table 14:
LCR[5-3] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
X
0
1
ODD parity
0
1
1
EVEN parity
0
0
1
forced parity ‘1’
1
1
1
forced parity ‘0’
Table 15:
LCR[2] stop bit length
LCR[2]
Word length
0
5, 6, 7, 8
1
1
5
1-1⁄2
1
6, 7, 8
2
Table 16:
Stop bit length (bit times)
LCR[1-0] word length
LCR[1]
LCR[0]
Word length
0
0
5
0
1
6
1
0
7
1
1
8
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 17:
Modem Control Register bits description
Bit
Symbol
Description
7-5
MCR[7-5]
Reserved; set to ‘0’.
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, CD, and RI are disconnected from the SC16C2550B I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 6). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OP2/INT enable
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition).
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0.
2
MCR[2]
(OP1). OP1A/OP1B are not available as an external signal in the
SC16C2550B. This bit is instead used in the Loop-back mode only. In
the loop-back mode, this bit is used to write the state of the modem RI
interface signal.
1
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
0
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
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7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550B and
the CPU.
Table 18:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break
indication is in the current FIFO data. This bit is cleared when
there are no remaining error flags associated with the remaining
data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This
bit is set to a logic 1 whenever the transmit holding register and the
transmit shift register are both empty. It is reset to logic 0 whenever
either the THR or TSR contains a data character. In the FIFO
mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit
shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty
indicator. This bit indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes the UART to
issue an interrupt to CPU when the THR interrupt enable is set.
The THR bit is set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift register. The
bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit
is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0
for one character frame time). In the FIFO mode, only one break
character is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a
valid stop bit(s). In the FIFO mode, this error is associated with
the character at the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition.
Logic 1 = Parity error. The receive character does not have
correct parity information and is suspect. In the FIFO mode, this
error is associated with the character at the top of the FIFO.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 18:
Line Status Register bits description…continued
Bit
Symbol
Description
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the
receive shift register. This happens when additional data arrives
while the FIFO is full. In this case, the previous data in the shift
register is overwritten. Note that under this condition, the data
byte in the receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal
default condition).
Logic 1 = Data has been received and is saved in the receive
holding register or FIFO.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C2550B is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 19:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD
input. Reading this bit in the loop-back mode produces the state of
MCR[3] (OP2).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI
input. Reading this bit in the loop-back mode produces the state of
MCR[2] (OP1).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the
DSR input. During the loop-back mode, this bit is equivalent to
MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the
CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (RTS).
3
MSR[3]
∆CD [1]
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C2550B has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
2
MSR[2]
∆RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C2550B has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
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Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 19:
Modem Status Register bits description…continued
Bit
Symbol
Description
1
MSR[1]
∆DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C2550B has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C2550B has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C2550B provides a temporary data register to store 8 bits of user
information.
7.10 SC16C2550B external reset condition
Table 20:
Reset state for registers
Register
Reset state
IER
IER[7-0] = 0
FCR
FCR[7-0] = 0
ISR
ISR[7-1] = 0; ISR[0] = 1
LCR
LCR[7-0] = 0
MCR
MCR[7-0] = 0
LSR
LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0
MSR
MSR[7-4] = input signals; MSR[3-0] = 0
SPR
SFR[7-0] = 1
DLL
DLL[7-0] = X
DLM
DLM[7-0] = X
Table 21:
Reset state for outputs
Output
Reset state
TXA, TXB
Logic 1
OP2A, OP2B
Logic 1
RTSA, RTSB
Logic 1
DTRA, DTRB
Logic 1
INTA, INTB
3-State condition
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
8. Limiting values
Table 22: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
supply voltage
Vn
Tamb
Conditions
Min
Max
Unit
-
7
V
voltage at any pin
GND − 0.3
VCC + 0.3
V
operating temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ptot(pack)
total power dissipation per package
-
500
mW
9. Static characteristics
Table 23: DC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Min
Max
Min
Max
Min
Max
Unit
VIL(CK)
LOW-level clock input voltage
−0.3
0.45
−0.3
0.6
−0.5
0.6
V
VIH(CK)
HIGH-level clock input voltage
1.8
VCC
2.4
VCC
3.0
VCC
V
VIL
LOW-level input voltage
(except X1 clock)
−0.3
0.65
−0.3
0.8
−0.5
0.8
V
VIH
HIGH-level input voltage
(except X1 clock)
1.6
-
2.0
-
2.2
-
V
VOL
LOW-level output voltage
on all outputs[1]
IOL = 5 mA
(databus)
-
-
-
-
-
0.4
V
IOL = 4 mA
(other outputs)
-
-
-
0.4
-
-
V
IOL = 2 mA
(databus)
-
0.4
-
-
-
-
V
IOL = 1.6 mA
(other outputs)
-
0.4
-
-
-
-
V
IOH = −5 mA
(databus)
-
-
-
-
2.4
-
V
IOH = −1 mA
(other outputs)
-
-
2.0
-
-
-
V
IOH = −800 µA
(data bus)
1.85
-
-
-
-
-
V
IOH = −400 µA
(other outputs)
1.85
-
-
-
-
-
V
-
±10
-
±10
-
±10
µA
-
±30
-
±30
-
±30
µA
-
3.5
-
4.5
-
4.5
mA
-
5
-
5
-
5
pF
VOH
HIGH-level output voltage
ILIL
LOW-level input leakage
current
ICL
clock leakage
ICC
supply current
Ci
input capacitance
[1]
f = 5 MHz
Except x2, VOL = 1 V typical.
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
10. Dynamic characteristics
Table 24: AC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
10
-
6
-
6
-
ns
-
48
-
80
80
MHz
t1w, t2w
clock pulse duration
t3w
oscillator/clock frequency
t6s
address set-up time
0
-
0
-
0
-
ns
t6h
address hold time
0
-
0
-
0
-
ns
t7d
IOR delay from chip select
10
-
10
-
10
-
ns
t7w
IOR strobe width
77
-
26
-
23
-
ns
t7h
chip select hold time from IOR
0
-
0
-
0
-
ns
t9d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
[1]
25 pF load
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
t13w
IOW strobe width
20
-
20
-
15
-
ns
t13h
chip select hold time from IOW
0
-
0
-
0
-
ns
t15d
write cycle delay
25
-
25
-
20
-
ns
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from Modem
input
25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from IOR
25 pF load
-
100
-
24
-
23
ns
-
1
-
1
-
1
Rclk
25 pF load
-
100
-
29
-
28
ns
t20d
delay from stop to set interrupt
t21d
delay from IOR to reset interrupt
t22d
delay from start to set interrupt
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit start
8
24
8
24
8
24
Rclk
t24d
delay from IOW to reset interrupt
-
100
-
45
-
40
ns
t25d
delay from stop to set RXRDY
-
1
-
1
-
1
Rclk
t26d
delay from IOR to reset RXRDY
-
100
-
45
-
40
ns
t27d
delay from IOW to set TXRDY
-
100
-
45
-
40
ns
t28d
delay from start to reset TXRDY
-
8
-
8
-
8
Rclk
tRESET
Reset pulse width
200
-
40
-
40
-
ns
N
baud rate divisor
1
216 − 1
1
216 − 1
1
216 − 1
Rclk
[1]
Applies to external clock, crystal oscillator max 24 MHz.
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9397 750 11982
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
10.1 Timing diagrams
t6h
VALID
ADDRESS
A0–A2
t6s
t13h
ACTIVE
CSx
t13d
t15d
t13w
IOW
ACTIVE
t16s
D0–D7
t16h
DATA
002aaa109
Fig 7. General write timing.
t6h
VALID
ADDRESS
A0–A2
t6s
t7h
ACTIVE
CSx
t7d
t9d
t7w
IOR
ACTIVE
t12h
t12d
D0–D7
DATA
002aaa110
Fig 8. General read timing.
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SC16C2550B
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5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
IOW
ACTIVE
t17d
RTS
DTR
CHANGE OF STATE
CHANGE OF STATE
DCD
CHANGE OF STATE
CTS
CHANGE OF STATE
DSR
t18d
INT
t18d
ACTIVE
ACTIVE
ACTIVE
t19d
IOR
ACTIVE
ACTIVE
ACTIVE
t18d
RI
CHANGE OF STATE
002aaa111
Fig 9. Modem input/output timing.
t 2w
t 1w
EXTERNAL
CLOCK
002aaa112
t 3w
Fig 10. External clock timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
t20d
7 DATA BITS
ACTIVE
INT
t21d
ACTIVE
IOR
16 BAUD RATE CLOCK
002aaa113
Fig 11. Receive timing.
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa578
Fig 12. Receive ready timing in non-FIFO mode.
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa579
Fig 13. Receive ready timing in FIFO mode.
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Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
ACTIVE TX READY
INT
t22d
t24d
t23d
IOW
ACTIVE
ACTIVE
16 BAUD RATE CLOCK
002aaa116
Fig 14. Transmit timing.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
32 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
TX
IOW
D0-D7
D0
D1
D2
D3
D4
D5
D6
D7
ACTIVE
BYTE #1
t28d
t27d
ACTIVE
TRANSMITTER READY
TXRDY
TRANSMITTER
NOT READY
002aaa580
Fig 15. Transmit ready timing in non-FIFO mode.
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9397 750 11982
Product data
Rev. 01 — 29 March 2004
33 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
IOW
ACTIVE
t28d
D0–D7
BYTE #16
t27d
TXRDY
FIFO FULL
002aaa581
Fig 16. Transmit ready timing in FIFO mode (DMA mode ‘1’).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
11. Package outline
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4
1.70
1.14
0.53
0.38
0.36
0.23
52.5
51.5
inches
0.19
0.02
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.1
0.6
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT129-1
051G08
MO-015
SC-511-40
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 17. DIP40 package outline (SOT129-1).
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
bp
ZE
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
UNIT A
A3
D(1) E(1)
e
eD
eE
HD
bp b1
max.
min.
4.57
4.19
mm
inches
0.81
0.66
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
0.51
0.25
3.05
0.53
0.33
0.180
0.02
0.165
0.01
0.12
0.021 0.032 0.656 0.656
0.05
0.013 0.026 0.650 0.650
0.63
0.59
0.63
0.59
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.695 0.695 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.685 0.685 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT187-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 18. PLCC44 package outline (SOT187-2).
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9397 750 11982
Product data
Rev. 01 — 29 March 2004
36 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 19. LQFP48 package outline (SOT313-2).
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9397 750 11982
Product data
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SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
12. Soldering
12.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.
12.2 Through-hole mount packages
12.2.1
Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (Tstg(max)).
If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
12.2.2
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit
temperature is between 300 and 400 °C, contact may be up to 5 seconds.
12.3 Surface mount packages
12.3.1
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all the BGA and SSOP-T packages
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
38 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3.2
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.3.3
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
39 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
12.4 Package related soldering information
Table 25:
Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Soldering method
Wave
Reflow[2]
Dipping
−
suitable
Through-hole
mount
DBS, DIP, HDIP, RDBS,
SDIP, SIL
suitable[3]
Through-holesurface mount
PMFP[4]
not suitable
not
suitable
−
Surface mount
BGA, LBGA, LFBGA,
SQFP, SSOP-T[5],
TFBGA, VFBGA
not suitable
suitable
−
DHVQFN, HBCC, HBGA,
HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP,
HVQFN, HVSON, SMS
not suitable[6]
suitable
−
PLCC[7], SO, SOJ
suitable
suitable
−
suitable
−
suitable
−
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
recommended[7][8]
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO,
VSSOP
not recommended[9]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.
Hot bar soldering or manual soldering is suitable for PMFP packages.
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
13. Revision history
Table 26:
Revision history
Rev Date
01
20040329
CPCN
Description
-
Product data (9397 750 11982)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Product data
Rev. 01 — 29 March 2004
40 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
14. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11982
Rev. 01 — 29 March 2004
41 of 42
SC16C2550B
Philips Semiconductors
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
UART A-B functions . . . . . . . . . . . . . . . . . . . . . 9
Internal registers. . . . . . . . . . . . . . . . . . . . . . . 10
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
Hardware/software and time-out interrupts. . . 11
Programmable baud rate generator . . . . . . . . 12
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 13
Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 13
Register descriptions . . . . . . . . . . . . . . . . . . . 15
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 15
Interrupt Enable Register (IER) . . . . . . . . . . . 16
IER versus Transmit/Receive FIFO interrupt
mode operation . . . . . . . . . . . . . . . . . . . . . . . 17
IER versus Receive/Transmit FIFO polled
mode operation . . . . . . . . . . . . . . . . . . . . . . . 17
FIFO Control Register (FCR) . . . . . . . . . . . . . 17
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt Status Register (ISR) . . . . . . . . . . . . 19
Line Control Register (LCR) . . . . . . . . . . . . . . 20
Modem Control Register (MCR) . . . . . . . . . . . 22
Line Status Register (LSR) . . . . . . . . . . . . . . . 23
Modem Status Register (MSR). . . . . . . . . . . . 24
Scratchpad Register (SPR) . . . . . . . . . . . . . . 25
SC16C2550B external reset condition . . . . . . 25
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 29 March 2004
Document order number: 9397 750 11982
8
9
10
10.1
11
12
12.1
12.2
12.2.1
12.2.2
12.3
12.3.1
12.3.2
12.3.3
12.4
13
14
15
16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Through-hole mount packages . . . . . . . . . . .
Soldering by dipping or by solder wave . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Surface mount packages . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
28
35
38
38
38
38
38
38
38
39
39
40
40
41
41
41