CDT2516 16-Bit Constant Current LED Drivers General Description * The CDT2516 is specifically designed for LED and LED DISPLAY constant current drivers. * The value of constant Can be varide using an external resistor(Iout=5~90mA). * The devices include a 16-bit shift register,latches, and constant current drivers. Features * * * * Constant current output: Current wuth one Resister for 5mA to 90mA Maximum clock frequency: 25MHz (cascade operation) 5V CMOS compatible input Constant current matching: Between Bit: ±6.0% Between Chip: ±10.0% @Iout=5~90mA * Package:DIP24P,SOP24P,SSOP24P Pin Assignment DIP 24 PIN 1 24 VDD SERIAL-IN 2 23 R-EXT CLOCK 3 22 SERIAL-OUT LATCH 4 21 /ENABLE OUT0 5 20 OUT15 OUT1 6 19 OUT14 OUT2 7 18 OUT13 OUT3 8 17 OUT12 OUT4 9 16 OUT11 OUT5 10 15 OUT10 OUT6 11 14 OUT9 OUT7 12 13 OUT8 GND 1 z Pin Description NO. PIN NAME I/O FUNCTION 1 GND P Ground terminal 2 SERIAL-IN I Input terminal of a data shift register 3 CLOCK I Input terminal of a clock for shift register 4 LATCH I Input terminal of data strobe 5 OUT0 O 6 OUT1 O 7 OUT2 O 8 OUT3 O 9 OUT4 O 10 OUT5 O 11 OUT6 O 12 OUT7 O 13 OUT8 O 14 OUT9 O 15 OUT10 O 16 OUT11 O 17 OUT12 O 18 OUT13 O 19 OUT14 O 20 OUT15 O 21 ENABLE I Input terminal of output enable (active low) 22 SERIAL-OUT O Output terminal of a data shift register 23 R-EXT I Input terminal of an external resistor 24 VDD P 5V supply voltage terminal Output terminals z Block Diagram VDD R-EXT I-REG. ENABLE OUT0 LATCH ST Q D SERIAL-IN D OUT1 Q ST Q CLOCK CK D D Q CK D OUT15 Q ST Q CK D D CK VSS Q SERIAL-OUT z Absolute Maximum Ratings Characteristic Symbol Rating Unit. Supply Voltage VDD 0 ~ 7.0 V Input Voltage VIN -0.4 ~ VDD+0.4 V Output Current IOUT 90 mA Output Voltage VOUT -0.5 ~ 9.5 V Clock Frequency fCLK 15 MHz GND Terminal Current PD 1440 mA 2.87 (DIP-24：Ta=25℃) Power Dissipation VDD 1.45 (SOP-24：Ta=25℃) W 1.27 (SSOP-24：Ta=25℃) 40.0 (DIP-24) Thermal Resistance Rth(j-a) 79.2 (SOP-24) ℃/W 90.2 (SSOP-24) Storage Temperature TSTG ℃ -55 ~ 150 z Recommended Operating Condition Characteristic Symbol Condition Min. Typ. Max. Unit. Supply Voltage VDD － 4.5 5.0 5.5 V Output Voltage VOUT － － － 9 V Operating Temperature TOPR － -40 － 85 ℃ IO OUTn 5 － 85 IOH SERIAL-OUT － － 1.0 IOL SERIAL-OUT － － -1.0 VIH － 0.7VDD － VDD+0.3 VIL － -0.3 － 0.3VDD Output Current Input Voltage mA V LATCH Pulse Width tw LAT 15 － － ns CLOCK Pulse Width tw CLK 15 － － ns Set-up Time for DATA testup(D) 20 － － ns Hold Time for DATA thold(D) 20 － － ns Set-up Time for LATCH testup(L) 15 － － Ns Clock Frequency fCLK Cascade operation － － 15 MHz Ta=85℃(DIP-24) － － 1.37 － 0.69 － 0.61 Power Dissipation PD VDD=4.5V~5.5V Ta=85℃(SOP-24) Ta=85℃(SSOP-24) － W z Electrical Characteristics ( VDD=5.0V, Ta = 25℃, unless otherwise specified) Characteristic Symbol Condition Min. Typ. Max. Unit. Input Voltage “H” Level VIH － 0.7VDD － VDD V Input Voltage “L” Level VIL － GND － 0.3VDD V Output Leakage Current IOH VOH=9.5V － － 1.0 µA VOL IOL=1.0mA － － 0.4 VOH IOH=-1.0mA 4.6 － － VOUT=0.7±0.25V, REXT=910Ω VOUT=0.7±0.25V, REXT=360Ω － 3 6 － 3 6 IOL3 VOUT=0.7V, REXT=910Ω － 5 10 IOL4 VOUT=0.7V, REXT=360Ω － 5 10 Supply Voltage Regulation % / VDD － 1.5 5.0 %/V Pull-Up Resistor RIN(up) REXT=470Ω, Ta=-40 ~ 85℃ － 150 300 600 KΩ Pull-Down Resistor RIN(down) 100 200 400 KΩ － 0.3 0.6 3.9 5.5 7.7 7.2 10.1 14.1 3.9 5.5 7.7 7.2 10.1 14.1 Output Voltage (SERIAL-OUT) IOL1 Output Current (Between Bit) IOL2 Output Current (Between Chip) IDD(off)1 Supply Current “OFF” IDD(off)2 IDD(off)3 Supply Current “ON” IDD(on)1 IDD(on)1 － REXT=Open, OUT0 15=Off REXT=470Ω, OUT0 15 Off REXT=250Ω, OUT0 15 Off REXT=470Ω, OUT0 15 O REXT=250Ω, OUT0 15 O V % mA z Switching Characteristics ( Ta = 25℃, unless otherwise specified) Characteristic Symbol Condition CLK-OUTn Propagation Delay Time (“L” to “H”) LATCH-OUTn ENABLE-OUTn tpLH CLK-SERIAL-OUT CLK-OUTn Propagation Delay Time (“H” to “L”) LATCH-OUTn ENABLE-OUTn tpHL CLK-SERIAL-OUT VDD = 5.0V VIH = VDD VIL = GND REXT = 470Ω VL = 3.0V RL = 65Ω CL = 13pF Min. Typ. Max. － 450 550 － 450 550 － 450 550 － 15 20 － 20 40 － 20 40 － 20 40 － 15 20 Unit. ns ns Output Current Rise Time tor － 450 550 ns Output Current Fall Time tof － 20 40 ns z Timing Chart 1 2 3 15 16 CLOCK 5V 0V SERIAL-IN 5V 0V LATCH 5V 0V ENABLE 5V 0V OUT0 On Off OUT1 On Off OUT2 On Off OUT15 On Off SERIAL-OUT 5V 0V Note. Latches are level sensitive (not edge triggered). LATCH-terminal = H level, latches become transparent; LATCH-terminal = L level, latches hold data. ENABLE-terminal = H level, all outputs (OUT0~OUT15) are off. An external resistor is connected between R-EXT and GND for setting up the value of constant current. SERIAL-OUT changes state on the falling edges of clock. y CLOCK-SERIAL-IN, SERIAL-OUT, OUTn y CLOCK-LATCH 50% CLOCK SERIAL-IN “L” level = DATA HOLD t hold(L) 50% LATCH 50% t setup(L) y ENABLE-OUTn 50% ENABLE t pHL t pLH 50% OUTn 50% z Test Circuit y DC Characteristic y DC Characteristic z Application Circuit LED supply voltage (VLED) setup VLED = VCE (Tr Vsat)+ Vf (LED forward voltage) + Vo (IC supply voltage) zPackage Information y 24-pin DIP outline dimensions D 13 24 E E1 1 eB 12 A2 H A SEATING PLANE L A1 0.018typ. 0.100typ. 0.060typ. Symbols A A1 A2 D E E1 L eB Θ0 MIN. － 0.010 0.150 1.245 0.540 0.115 0.630 0 NOR. MAX. － 0.210 － － 0.155 0.160 1.250 1.260 0.600 BSC. 0.545 0.550 0.130 0.150 0.650 0.670 7 15 UNIT：INCH NOTES. 1. JEDEC OUTLINE：MS-011 AA 2. “E1” DOES NOT INCLUDE MOLD FLASH. y 24-pin SOP outline dimensions E H 0.020X45 0.016 typ. 0.050 typ. D A 0.004max. A1 0.010 L GAUGE PLANE SEATING PLANE Symbols MIN. NOM. A A1 D E H L Θ0 0.093 0.004 0.599 0.291 0.394 0.016 0 0.099 － 0.600 0.295 0.406 0.035 － MAX. 0.104 0.012 0.614 0.299 0.419 0.050 8 UNIT：INCH NOTES. 1. JEDEC OUTLINE：MS-013 AD 2. DIMENSIONS “D” DOES NOT INCLUDE MOLD FLASH, P R O T R U S I O N S O R G AT E B U R R S . M O L D F L A S H , PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED 0.15mm (0.006in) PER SIDE. 3. DIMENSIONS “E” DOES NOT INCLUDE INTER-LEAD FLASH, OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25mm (0.010in) PER SIDE. y 24-pin SSOP outline dimensions D 24 13 E1 E 1 “A” 12 b e C 0.004 A2 H A GAUGE PLANE SEATING PLANE L A1 L1 DETAIL A Symbols A A1 A2 b c D E E1 e L L1 Θ0 MIN. NOR. － 0.004 － 0.008 0.006 0.335 0.228 0.150 0.020 0.016 － 0 0.064 － － － － 0.341 0.236 0.154 0.025 0.025 0.041 － MAX. 0.070 － 0.059 0.012 0.010 0.346 0.244 0.157 0.030 － － 8 UNIT：INCH NOTES. 1. DIMENSIONS D DOES NOT INCLUDE MOLD PROTRUSIONS OR GATE BURRS. MOLD PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED 0.006” PER SIDE. DIMENSIONS E1 DOES NOT INCLUDE INTERLEAD MOLD PROTRUSIONS. INTERLEAD MOLD PROTRUSIONS SHALL NOT EXCEED 0.010” PER SIDE. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/ INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.004” TOTAL IN EXCESS OF b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION b BY MORE THAN 0.002” AT LEAST. ＊ CDT assumes no responsibility for the use of the specification described. CDT reserves the right to modify the product specification without notice. ( 以上規格僅供參考，本公司得逕行修正，不另通知 )