ETC CP8P07

Preliminary
DATA SHEET
CP8P07
OTP-BASED 8-BIT MICROCONTROLLER
1
Preliminary
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ............................................................................. PAGE 5
2. FEATURES ..................................................................................................... PAGE 5
3. PIN DESCRIPTION ........................................................................................ PAGE 5
4. ARCHITECTURE ............................................................................................ PAGE 7
5. MEMORY MAPS AND REGISTERS............................................................... PAGE 8
5.1 PROGRAM MEMORY MAP ...................................................................... PAGE 8
5.2 CONFIGURATION MEMORY MAP........................................................... PAGE 10
5.3 DATA MEMORY MAP AND REGISTERS.................................................. PAGE 12
5.4 CONTROL REGISTERS ........................................................................... PAGE 16
6. CLOCKS ......................................................................................................... PAGE 18
6.1 CLOCK SYSTEM ...................................................................................... PAGE 18
6.2 CRYSTAL OSCILLATOR........................................................................... PAGE 18
6.3 EXTERNAL RC OSCILLATOR .................................................................. PAGE 19
6.4 INTERNAL 16MHZ RC OSCILLATOR ...................................................... PAGE 19
7. I/O PORTS...................................................................................................... PAGE 21
7.1 PORTA ...................................................................................................... PAGE 21
7.2 PORTB ...................................................................................................... PAGE 21
7.3 PORTC...................................................................................................... PAGE 21
8. ON-CHIP PERIPHERAL ................................................................................. PAGE 26
8.1 TIMER0 ..................................................................................................... PAGE 26
8.2 WATCHDOG TIMER ................................................................................. PAGE 27
9. SPECIAL FEATURES ..................................................................................... PAGE 28
9.1 INTERRUPTS ........................................................................................... PAGE 28
2
Preliminary
10. INSTRUCTION SET ..................................................................................... PAGE 29
10.1 INSTRUCTION DESCRIPTION .............................................................. PAGE 32
11. ABSOLUTE MAXIMUM RATINGS ................................................................ PAGE 38
12. DC CHARACTERISTICS.............................................................................. PAGE 38
3
Preliminary
Revision History:
Date
Revision#
7/12/2005
101
Revised oscillator types
Description
7/12/2005
102
Revised oscillator types
7/15/2005
8/1/2005
8/2/2005
8/9/2005
103
104
105
106
Revised instruction set
Revised instruction set
Revised description of INTCON
Corrected the initial values of PORTA, PORTB, and PORTC
Page
5-7,10-11,
16-20,39
6-7,10-11,
16-20
29-37
30,31,35,36
12,14,28
14
4
Preliminary
CP8P07
OTP-Based 8-bit CMOS Microcontroller
1. General Description
CP8P07 is an 8-bit microprocessor with low-power and
high-speed CMOS technology. It is equipped with a
2048*16-bit electrical one time programmable memory
and 72*8-bit data memory. Both program and data
memories can be configured as linear-addressable or
nonlinear-addressable. CP8P07 provides flexible interrupt
handling capability and eight-level deep stack. An
internal 16 MHz oscillator with 5% accuracy is
integrated to reduce cost. With internal divider, this
oscillator can be adopted to replace expensive crystal in
application where time accuracy is not strictly required.
CP8P07 is designed to work in noisy environment,
especially to resist electronic fast transient burst (EFT
burst). Therefore, it is suitable to be used in application
of home appliance motor control. Because CP8P07
operates in a very low current consumption, it is
advantageous in low-power application, like remote
controller and battery-powered system.
2. Features
Table 2-1: Power consumption
Mode
LP(32.768K)
XT(4MHz)
XT(4MHz EMI)
HS(16MHz)
HS(16MHz EMI)
HS(20MHz)
HS(20MHz EMI)
BR16M(8.62MHz)
BR16M(15.62MHz)
BR16M(22.25MHz)
Standby
(WDT disable)
2.2V
2uA
200uA
180uA
X
X
X
X
X
X
X
3.3V
7uA
400uA
340uA
1.6mA
1.4mA
1.8mA
1.6mA
750uA
1.1mA
1.5mA
0.6uA
5.5V
32uA
1mA
0.8mA
4.5mA
3.5mA
5.2mA
4.9mA
1.75mA
2.4mA
3.1mA
VDDMIN
2.2V
2.2V
2.2V
3.0V
3.0V
3.3V
3.3V
3. Pin Description
T0CKI/PA4
1
28
RESET/ VPP
VDD
2
27
OSC1/PA5/RT
OSC2/PA6
NC
3
26
VSS
4
25
PC7
NC
5
24
PC6
PA0
6
23
PC5
PA1
7
22
PC4
PA2
8
21
PC3
PA3
9
20
PC2
19
PC1
CP8P07
46 powerful instructions to ease coding complexity
Except for branches taking place, all instructions
need only one cycle
Memory configuration:
OTP ROM: 2K x 16 bits
RAM: 72 x 8 bits
16-bit wide instructions
8-bit wide data path
Full-range branches without confusing bank select if
in linear addressing mode
Data memory is linear-mapped so that it can be
accessed without bank select firstly when in linear
addressing mode
8/9 special function hardware registers in
non-interrupt/interrupt mode
Interrupt handling
Eight-level deep hardware stack (2/4/8 configurable)
Operation speed: DC – 20 MHz clock input
Bi-directional IO: Port A, B, C
Built-in pull-up: Port B
Wake-up/Interrupt (Port B)
8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler and overflow interrupt
Readable prescaler counter for 16-bit timer
capability
Power-on Reset (POR)
Device Reset Timer (DRT)
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC
oscillator ([email protected] [email protected])
Configurable WDT wake-up: Reset/Continue
Power saving HALT mode
Oscillator types:
RC4M: Low cost external-RC oscillator
LP32K: Low frequency crystal for power saving
XT4M: Standard crystal/resonator
HS16M: High speed crystal/resonator
BR16M: High accuracy 16MHz built-in OSC (±
5%, after calibration)
Main clock divider (1/2/4/16)
EMI configuration bit to reduce 2nd-order harmonic
power of crystal output
CMOS OTP technology with fully static design
Wide operation voltage and temperature range: 2.2V
to 5.5V, -40 to 85 degree C
I/O Driving capability:
VDD=5.0V
Source Current: -6.0mA (Voh = 4.5v)
Sink Current: 22.0mA (Vol = 0.5v)
VDD=3.0V
Source Current: -2.5mA (Voh = 2.7v)
Sink Current: 10.0mA (Vol = 0.3v)
Low power consumption:
PB0/INT
10
PB1
11
18
PC0
PB2
12
17
PB7
PB3
13
16
PB6
PB4
14
15
PB5
5
Preliminary
Table 3-1: Device Pin Description
Pin #
1
Pin Name
T0CKI/PA4
Pin
Type
I/O
Buffer
Type
CMOS
Description
External timer/counter input
General purpose I/O pin
2
VDD
P
–
Power supply
3
NC
–
–
No connection
4
VSS
P
–
Ground
5
NC
–
–
No connection
6
PA0
I/O
CMOS General purpose I/O pin
7
PA1
I/O
CMOS General purpose I/O pin
8
PA2
I/O
CMOS General purpose I/O pin
9
PA3
I/O
CMOS General purpose I/O pin
10
PB0/INT
I/O
CMOS General purpose I/O pin (IPU)
External interrupt pin
11
PB1
I/O
CMOS General purpose I/O pin (IPU)
12
PB2
I/O
CMOS General purpose I/O pin (IPU)
13
PB3
I/O
CMOS General purpose I/O pin (IPU)
14
PB4
I/O
CMOS General purpose I/O pin (IPU)
Interrupt on change pin
15
PB5
I/O
CMOS General purpose I/O pin (IPU)
Interrupt on change pin
16
PB6
I/O
CMOS General purpose I/O pin (IPU)
Interrupt on change pin
17
PB7
I/O
CMOS General purpose I/O pin (IPU)
Interrupt on change pin
18
PC0
I/O
CMOS General purpose I/O pin
19
PC1
I/O
CMOS General purpose I/O pin
20
PC2
I/O
CMOS General purpose I/O pin
21
PC3
I/O
CMOS General purpose I/O pin
22
PC4
I/O
CMOS General purpose I/O pin
23
PC5
I/O
CMOS General purpose I/O pin
24
PC6
I/O
CMOS General purpose I/O pin
25
PC7
I/O
CMOS General purpose I/O pin
26
OSC2/PA6
I/O
CMOS Crystal oscillator output
General purpose I/O pin
27
OSC1/PA5/RT
I/O
CMOS Crystal oscillator input
General purpose I/O pin
ER16M external resistor analog
input
External clock source input
External RC oscillator input
28
RESET/VPP
I/P
ST
External reset input, active low
Programming voltage input
Abbreviations: I=input, O=output, P=supply, IPU=input pull-up, ST=Schmitt Trigger input
6
Preliminary
4. Architecture
The block diagram of CP8P07 is shown below. Harvard architecture is adopted, which referred to computer
architectures that uses physically separate storage and signal pathways for their instructions and data. Therefore,
program and data memory blocks are separated and can be organized with different bus width. 16-bit and 8-bit wide
buses are used in the program and data memory, respectively. The program memory size of the CP8P07 is 2048 words.
Data memory is divided into two parts: special function registers (SFR) and general purpose registers (GPR) with
the size of 8 and 72 bytes respectively (9 and 71 bytes when in interrupt mode). The ALU is 8 bits wide and can do
operations with operands from A (accumulator register), GPR, SFR, or immediate constant. Register A is a special
register used for ALU operations with no address. The control register (CR) block includes 6 bytes register for
hardware control. It can only be accessed through A which is the default source/destination for most instructions.
Internal power-on reset (POR) and external reset can be used as device reset source. Watchdog timer (WDT),
Timer 0(TMR 0), internal OSC, eight-level deep stack and interrupt handling capability are helpful to improve
system cost and power. Twenty three bi-directional I/O pins are grouped into A, B, and C. Oscillator start-up timer
(OST) increases the reliability of the oscillators.
Figure 4-1: CP8P07 Block Diagram
OST
CLK Module
DIV
Internal
OSC
IO PortA
CLK
IO PortB
IO PortC
1/16,1/4,1/2,1/1
8 - bit Data Bus
ALU
WDT
Central
Control Unit
…
A
CR
GPR
SFR
TMR0
POR
Prog Memory
Stack
INT
PortB
RESET
PC
7
Preliminary
5. Memory Maps and Registers
Memory in CP8P07 includes program memory, configuration memory, data memory, and control registers. There are
two addressing mode in CP8P07: non-linear addressing mode and linear addressing mode. In non-linear addressing
mode, a paging scheme is used. In linear addressing mode, all memory data are addressable without any page
selection.
5.1 Program Memory Map
Program memory contains user program code data in OTP, which is addressed via the 11-bit program counter (PC)
register. Its capacity is 2048 words with length of 16 bits. While the PC overflows during execution, it will cause a
wraparound. Two locations are reserved as default vector. The RESET vector is at 07FFh, and the interrupt vector
is at 0004h.
There are non-linear addressing and linear addressing modes in CP8P07. When LIN (Configuration 1 bit 5) is cleared,
CP8P07 is in non-linear addressing mode. PG1-0 (STATUS bit 5 and 6) are used to access program memory pages.
Figure 5-1 shows the program memory map in non-linear addressing mode.
Figure 5-1: Program Memory Map and Stack in Non-linear Addressing Mode
Program Memory
PC[10:0 ]
Page 0
004h
000h
Interrupt Vector
1FFh
200h
Page 1
3FFh
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Page 2
Stack Level 5
Stack Level 6
Stack Level 7
Page 3
Stack Level 8
400h
5FFh
600h
RESET Vector
7FFh
8
Preliminary
When LIN (Configuration 1 bit 5) is set, CP8P07 is in linear addressing mode. JMP and JSR instructions can access all
memory data without any page selection. Figure 5-2 shows the program memory map in linear addressing mode.
Figure 5-2: Program Memory Map and Stack in Linear Addressing Mode
PC[10:0]
000h
004h
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Program Memory
Interrupt Vector
Program Memory
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
7FFh
RESET Vector
Program Counter (PC). The PC is an 11-bit register which contains the OTP address of the next instruction to be
executed. Its 11-bit width can access 2048 words in program address. The PC is auto-incremented after the content
of current address is fetched. The least significant byte of the PC (PCL) is accessible and mapped in data memory
at address 02h. To execute a relative jump, operate PCL and offset in ALU and store result in PCL, which causes
update of PC value. Ways to change program counter includes:
JMP Instruction
CALL Instruction
Relative Branch
(modify PCL)
Reset
Interrupt
RET and RETI
Instructions
Normal Instructions
Linear Addressing Mode (LIN=1)
Non-linear Addressing Mode (LIN=0)
PC = instruction word[10:0]
PC = instruction word[10:0]
PC = +/- offset ( {PG[2:0], PCL}
PC = {PG[1:0],instruction word[8:0]}
PC = {PG[1:0],0,instruction word[7:0]}
PC = +/- offset ( {PG[1:0],0,PCL}
PC )
PC )
PC = 7FFh
PC = 004h
PC = STACK[top]
PC = 7FFh
PC = 004h
PC = STACK[top]
PC = PC + 1
PC = PC + 1
STACK. The CP8P07 includes an eight-level deep hardware stack. The stack consists of eight separate 11-bit register
and a 3-bit counter. The counter always points an empty location. When a subroutine call or an interrupt request
occurs, the content of PC is firstly pushed into STACK and then the counter is incremented. When a return occurs
(either from subroutine or interrupt), the counter is firstly decremented and STACK value pointed by the counter is
then stored back into the PC.
9
Preliminary
5.2 Configuration Memory Map
Configuration memory contains device configuration data in OTP, which is addressed only in device programming
mode.
Table 5-1: Configuration 0
–
–
–
–
–
–
–
–
–
6
OST
5
WDT
4
3
2
DIV
0
CLK
OST: Oscillator start-up timer enable bit
1 = Enable, a delay of 1024 cycles for crystal mode starting up
0 = Disable, a delay of 128 cycles for crystal mode starting up
WDT: Watchdog Timer enable bit
1 = Enable
0 = Disable
DIV: Main clock divider
11 = divide ratio 1
10 = divide ratio 2
01 = divide ratio 4
00 = divide ratio 16
CLK: Clock selection
111 = RC4M (external RC oscillator) with clock output
110 = RC4M (external RC oscillator) with port A6 enable
101 = BR16M (internal RC oscillator) with port A5 enable and clock output
100 = BR16M (internal RC oscillator) with port A5 and A6 enable
011 = ER16M (internal RC oscillator) using ext. R with port A6 enable
010 = HS16M crystal oscillator 4 MHz – 20 MHz
001 = XT4M crystal oscillator 200 KHz – 4 MHz
000 = LP32K crystal oscillator 32 KHz – 200 KHz
Table 5-2: Configuration 1
15
EMI
14
–
13
12
STACK
–
–
–
–
7
WUP
6
INT
5
LIN
4
0
OC
EMI: Crystal oscillator output swing control
1 = Normal swing
0 = Low swing
STACK: Stack level
1x = 8 levels
01 = 4 levels
00 = 2 levels
WUP: Watchdog timer wakes CPU up under HALT mode
1 = CPU continues to execute next instruction after Watchdog Timer is overflow
0 = CPU is reset after Watchdog Timer is overflow
INT: Interrupt mode enable bit
1 = Enable, CPU has interrupt function
0 = Disable
LIN: Linear addressing mode enable bit
1 = Enable
0 = Disable
OC: Internal OSC calibration data
The output frequency of internal OSC is proportional to OC[4:0]. The tuning step is 2.5%.
11111 = Slowest
10
Preliminary
00000 = Fastest
11
Preliminary
5.3 Data Memory Map and Registers
There are two addressing modes for data memory: non-linear addressing mode and linear addressing mode. In
non-linear addressing mode (LIN=0), a banking scheme is used. Data memory banks are accessed using FSR bits
5 and 6. In linear addressing mode (LIN=1), the data memory is linear-mapped without any partition. The
addressing range is from 00h to 7Fh. However, either in non-linear or linear addressing mode, address 00h-0Fh,
20h-2Fh, 40h-4Fh, and 60h-6Fh contain the same data. We can say that memory locations 20h-2Fh, 40h-4Fh, and
60h-6Fh map back to address 00h-0Fh. Data memory contains the General Purpose Registers (GPR) and the
Special Functions Registers (SFR). The General Purpose Registers are used for data under command of the
instructions and can be accessed directly or indirectly. The Special Function Registers have various specific
functions, like addressing control, flags indicator, or peripheral control. CP8P07 contains 8 Special Function Registers
and 72 General Purpose Registers in non-interrupt mode, or 9 Special Function Registers and 71 General Purpose
Registers in interrupt mode. 08h is used as a Special Function Register (INTCON) when in interrupt mode or as a
General Purpose Register when in non-interrupt mode. Figures 5-3 and 5-4 show the SFR & GPR memory map in
non-linear and linear addressing modes.
Figure 5-3: SFR & GPR Memory Map in Non-linear Addressing Mode
FSR[6:5]=00
00h
INDX
01h
02h
TMR0
PCL
STATUS
03h
04h
05h
06h
07h
08h
FSR[6:5]=01
Addresses map
back to addresses
00h – 0Fh
PORTC
INTCON
FSR[6:5]=11
60h
40h
20h
FSR
PORTA
PORTB
FSR[6:5]=10
Addresses map
back to addresses
00h – 0Fh
Addresses map
back to addresses
00h – 0Fh
09h
General Registers
0Fh
10h
General Registers
General Registers
1Fh
General Registers
Bank 1
General Registers
7Fh
5Fh
3Fh
Bank 0
6Fh
70h
4Fh
50h
2Fh
30h
Bank 2
Bank 3
12
Preliminary
Figure 5-4: SFR & GPR Memory Map in Linear Addressing Mode
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
INDX
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
INTCON
General Registers
0Fh
10h
General Registers
1Fh
20h
Addresses map back to
addresses 00h - 0Fh
2Fh
30h
General Registers
3Fh
40h
Addresses map back to
addresses 00h - 0Fh
4Fh
50h
General Registers
5Fh
60h
Addresses map back to
addresses 00h - 0Fh
6Fh
70h
General Registers
7Fh
13
Preliminary
Table 5-3: Special Function Registers summary
Address
Label
B7
B6
B5
B4
B3
B2
B1
B0
Value on
POR
Value on
other reset
0000 0000
0000 0000
Address this location for indirect addressing
00h
INDX
xxxx xxxx
uuuu uuuu
Timer 0 counter value
01h
TMR0
1111 1111
1111 1111
PCL7
PCL6
PCL5
PCL4
PCL3
PCL2
PCL1
PCL0
02h
PCL
0001 1xxx
000p puuu
PG2
PG1
PG0
TO_
PD_
Z
H
C
03h
STATUS
1000 0000
uuuu uuuu
Pointer for indirect addressing
04h
FSR
-xxx
xxxx
-uuu uuuu
PA6
PA5
PA4
PA3
PA2
PA1
PA0
05h
PORTA
xxxx
xxxx
uuuu
uuuu
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
06h
PORTB
xxxx xxxx
uuuu uuuu
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
07h
PORTC
0000 0000
0000 0000
GIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
08h
INTCON
Abbreviations: x = unknown, u = unchanged, p = value depends on conditions, - = unimplemented, read as ‘0’
Note: 08h is used as a SFR when in interrupt mode or as a GPR when in non-interrupt mode.
INDX (00h)
Indirect data addressing uses the registers INDX(00h) and FSR(04h). INDX is not physically implemented and FSR
is a pointer. Any instruction addressing INDX actually accesses data pointed by the FSR register.
TMR0 (01h)
TMR0 contains the value in the counter of the Timer 0.
PCL (02h)
Program counter (PC) is an 11-bit register, which contains the address of the next instruction to be executed. The
least significant byte of the PC (PC[7:0]) is defined as PCL which is accessible in date memory address 02h.
STATUS (03h)
7
PG2
C:
H:
Z:
PD_:
TO_:
PG2-0:
6
PG1
5
PG0
4
TO_
3
PD_
2
Z
1
H
0
C
Carry flag. This bit is set when a carry or a borrow occurs during arithmetic operations; otherwise it
is clear.
0: No carry-out has occurred
1: A carry-out has occurred
Half carry flag. This bit is set when a carry or a borrow occurs from the lower nibble (the 4th low
order bit) occurs during arithmetic operations; otherwise it is clear.
0: No carry-out has occurred from the lower nibble
1: A carry-out has occurred from the lower nibble
Zero flag. This bit is set if the result of the last arithmetic or logical operation was equal to zero;
otherwise it is clear.
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Power down bit, read only
0: By executing HALT instruction
1: After power-up, or executing CLRW instruction
Time-out bit, read only
0: Reset by watchdog timer time-out
1: After power-up, or executing CLRW instruction or HALT instruction
Once PCL is modified, the 8-bit PCL and these three bits are copied to the 11-bit PC with the
operation of {PG[2:0], PCL[7:0]}
PC.
FSR (04h)
The FSR is an 8-bit index register used in indirect addressing mode as pointers to memory locations. Any
instruction addressing INDX(00h) actually accesses data pointed by the FSR(04h) register.
PORTA (05h)
PORTA is the value of the I/O port A.
PORTB (06h)
PORTB is the value of the I/O port B.
PORTC (07h)
14
Preliminary
PORTC is the value of the I/O port C.
INTCON(08h)
7
GIE
RBIF:
INTF:
T0IF:
RBIE:
INTE:
T0IE:
GIE:
6
-
5
T0IE
4
INTE
3
RBIE
2
T0IF
1
INTF
0
RBIF
PB7:PB4 interrupt flag bit
0: No interrupt
1: Interrupt occurs on one of PB7:PB4 pins. An edge transition will generate interrupt.
PB0/INT external interrupt flag bit
0: PB0/INT external interrupt does not occur
1: PB0/INT external interrupt occurs, clear by software
Timer 0 overflow interrupt flag bit
0: Timer 0 does not overflow
1: Timer 0 has overflowed, clear by software
PB7:PB4 interrupt enable bit
0: Disable interrupt
1: Enable interrupt
PB0/INT external interrupt enable bit
0: Disable PB0/INT external interrupt
1: Enable PB0/INT external interrupt
Timer 0 overflow interrupt enable bit
0: Disable Timer 0 overflow interrupt
1: Enable Timer 0 overflow interrupt
Global interrupt enable bit
0: Disable all interrupt
1: Enable interrupt function
15
Preliminary
5.4 Control registers
Control registers contain six special function registers, including readable/writable OPTION, OC, TRISA, TRISB,
TRISC registers and read-only PSCCNT register. These registers can only be accessed through A register using
directly addressing. Like load/store instructions in RISC machine, CP8P07 uses PEEK and POKE instruction to load
control registers to A and save A to control registers, respectively.
Figure 5-5: Control Registers Memory Map
00h
01h
OPTION
OC
Unimplemented
05h
06h
07h
TRISA
TRISB
TRISC
Unimplemented
PSC
0Dh
Unimplemented
0Fh
Table 5-4: Control Registers summary
Address
00h
Label
OPTION
B7
B6
B5
B4
RBP
INTE
T0CS T0SE
U_
DG
Internal OSC calibration data
b6
b5
b4
b7
b6
b5
b4
b7
b6
b5
b4
Prescaler counter value
B3
B2
B1
B0
Value on
POR
Value on
other reset
PSA
PS2
PS1
PS0
1111 1111
1111 1111
(1)
000c cccc
uuuu uuuu
01h
OC
b3
b2
b1
b0
-111 1111
-111 1111
05h
TRISA
b3
b2
b1
b0
1111
1111
1111
1111
06h
TRISB
b3
b2
b1
b0
1111 1111
1111 1111
07h
TRISC
0000 0000
0000 0000
0Dh
PSCCNT
Abbreviations: x = unknown, u = unchanged, p = value depends on conditions, - = unimplemented, read as ‘0’
Note 1: The lower 5 bits of OC is loaded from configuration word 1 on POR.
OPTION (00h)
7
RBPU_
PS2-0:
PSA:
T0SE:
6
INTEDG
5
T0CS
4
T0SE
3
PSA
2
PS2
1
PS1
0
PS0
Prescaler divide ratio
PS[2:0] TMR0 WDT
000
2
1
001
4
2
010
8
4
011
16
8
100
32
16
101
64
32
110
128
64
111
256
128
Prescaler assignment bit
0: Prescaler is assigned to Timer 0
1: Prescaler is assigned to WDT
Timer 0 source edge select bit
0: Increment on rising edge of T0CKI pin
1: Increment on falling edge of T0CKI pin
16
Preliminary
T0CS:
Timer 0 clock source select bit
0: T0CKI pin
1: Internal instruction cycle clock
INTDEG: Interrupt edge select bit
0: interrupt on falling edge of PB0/INT pin
1: interrupt on rising edge of PB0/INT pin
RBPU_: Port B pull-up enable bit
0: Port B pull-up are enabled. Note that it works in linear mode (LIN=1).
1: Port B pull-up are disabled
OC (01h)
OC contains internal OSC (Built-in RC16MHz) calibration data. Setting “11111” causes the slowest of internal OSC
and “00000” causes the fastest. The tuning step is 2.5%.
TRISA (05h)
Port A input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
TRISB (06h)
Port B input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
TRISC (07h)
Port C input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
PSCCNT (0Dh)
PSCCNT is a read-only register which contains the value in the counter of the prescaler. The prescaler is
programmable for Timer0 or watchdog timer.
Note: Any read from unimplemented locations returns unknown data.
17
Preliminary
6. Clocks
6.1 Clock System
There are three oscillators integrated in this CPU, including crystal oscillator, external RC oscillator, and internal 16
MHz RC oscillator.
An optional oscillator start-up timer (OST) is used to ensure that the oscillator has started and stabilized. Except for
external RC mode, it provides a delay of 128 or 1024 cycles after oscillator is enable for OST configuration bit being
clear or set, respectively. In external RC mode, a delay of 32 is provided. A clock divider provides divide ratio of 1,
2, 4 or 16. The CPU clock is derived after this divider.
Figure 6-1: Block Diagram of Clock System
OSC2
OSC1
÷4
Crystal
Oscillator
External RC
Oscillator
Oscillator
Start-up Timer
32, 128, 1024
Divider
1, 2, 4, 16
FSYS
Internal
16 MHz RC
Oscillator
Table 6-1: CPU Start-up Time
Mode
HS16M, XT4M, LP32K
RC4M, BR16M, ER16M
Power-up
OST=0
OST=1
16ms+128
16ms+1024
cycles
cycles
16ms+32 cycles 16ms+32 cycles
Wake-up from HALT
OST=0
OST=1
128 cycles
1024 cycles
32 cycles
32 cycles
6.2 Crystal Oscillator (HS16M, XT4M, and LP32K)
The crystal oscillator can be driven by:
External clock
External AT-cut parallel-resonant crystal
External ceramic resonator Crystal
This oscillator works in three modes, including low power crystal mode (LP32K), crystal mode (XT4M), and high
speed crystal (HS16M) mode. Each mode is optimized for a suitable frequency range. A crystal or ceramic
resonator is connected to the OSC1 and OSC2 pins to start oscillation. In addition, when external clock input
operation is required, a clock source can drive OSC1 pin directly.
18
Preliminary
Figure 6-2: Crystal/Resonator Oscillator
OSC1
CL1
OSC2
CL2
Figure 6-3: External Clock Input
OSC1
OSC2
NC
External
Clock
6.3 External RC Oscillator (RC4M)
This RC oscillator consist an external resistor, an external capacitor, a Schmitt trigger comparator, and a NMOS
device. If timing accuracy is no concern, this oscillator offers cost savings. The oscillation frequency depends on
supply voltage, operating temperature, resistor value and capacitor value. The OSC1 pin connects the resistor and
the capacitor. The OSC2 pin can be configured to either output a clock pulse of 1/4 system frequency or be an I/O
pin of PORTA (PA6).
Figure 6-4: External RC Oscillator
VDD
OSC1
REXT
C EXT
OSC2
FSYS/4 or PA 6
6.4 Internal 16MHz RC Oscillator (BR16M and ER16M)
The CP8P07 integrated an internal RC oscillator that provides an 16 MHz output clock at VDD = 5V and 25 °C with an
accuracy of ± 5% after calibration. The resistor can be replaced by an external resistor connected to OSC1 for
better performance over wide temperature range.
The Oscillator Calibration Register (OC) contains the calibration date fetched from the Configuration1[4:0] after
power-up. The OC register (01h) can be modified dynamically while program is running. The output frequency of
internal OSC is proportional to the complement of OC[4:0], that is, the frequency of internal OSC is lowest when
OC[4:0]=0x1F and highest frequency when OC[4:0]=0x00. The tuning step of OC is about 2.5% of 16 MHz.
When this oscillator is chosen as system clock source, the OSC1 pin can be configured as an analog pin which
connects an external resistor or A5 of PORTA. The OSC2 pin can be configured as a clock source of 1/4 system
frequency or PA6 of PORTA.
19
Preliminary
Figure 6-5: Internal RC Oscillator
OSC1
OSC2
REXT or PA5
FSYS/4 or PA 6
REXT
Configuration 0
–
–
–
–
–
–
–
–
–
6
OST
5
WDT
4
3
2
DIV
0
CLK
OST: Oscillator start-up timer enable bit
1 = Enable, a delay of 1024 cycles for crystal mode starting up
0 = Disable, a delay of 128 cycles for crystal mode starting up
DIV: Main clock divider
11 = divide ratio 1
10 = divide ratio 2
01 = divide ratio 4
00 = divide ratio 16
CLK: Clock selection
111 = RC4M (external RC oscillator) with clock output
110 = RC4M (external RC oscillator) with port A6 enable
101 = BR16M (internal RC oscillator) with port A5 enable and clock output
100 = BR16M (internal RC oscillator) with port A5 and A6 enable
011 = ER16M (internal RC oscillator) using ext. R with port A6 enable
010 = HS16M crystal oscillator 4 MHz – 20 MHz
001 = XT4M crystal oscillator 200 KHz – 4 MHz
000 = LP32K crystal oscillator 32 KHz – 200 KHz
Configuration 1
15
14
13
12
EMI
–
STACK
–
–
–
–
7
WUP
6
INT
5
LIN
4
0
OC
EMI: Crystal oscillator output swing control
1 = Normal swing
0 = Low swing
OC (01h)
OC contains internal OSC (Built-in RC16MHz) calibration data. Setting “11111” causes the slowest of internal OSC
and “00000” causes the fastest. The tuning step is 2.5%.
20
Preliminary
7. I/O Ports
The I/O registers (PORTA, PORTB, and PORTC) and I/O control registers (TRISA, TRISB, TRISC) are used to
manipulate I/O pins. I/O register can be read and written. However, read instructions always read the states of the
corresponding I/O pins. All input buffers are CMOS type.
7.1 PORTA
The width of the PORTA register varies from 5 to 7 bits, which depends on the function of the OSC1/PA5 and
OSC2/PA6 pins. Circuit of PA4/T0CKI, PA[3:0] pins and corresponding I/O register are shown in Figure 7-1. The
PA5 and PA6 pin diagram shown in Figure 7-2 has two additional disable gates when these ports are not enabled.
When PA5 or PA6 is not enabled, it is read as ‘0’.
7.2 PORTB
PORTB is an 8-bit I/O Register. Each PB pin integrates a weak pull-up function, which can be turn on by clearing
RBPU_ bit in OPTION register in linear addressing mode (LIN=1). In output mode, the pull-up will be turned off
automatically. PB[7:4] pins have an interrupt-on-change feature. Only input pins can cause interrupt to occur. To
use the interrupt-on-change feature, user needs to read PORTB first. The value on PORTB will be latched. After
that, the input pins of PB[7:4] are compared with the old value latched on the last read of PORTB. An interrupt will
be generated when a mismatch occurs. PB0/INT is an external interrupt input pin. Figure 7-3, 7-4, and 7-5 show the
PB pins circuit diagram.
7.3 PORTC
PORTC is an 8-bit I/O Register. The PC pins circuit diagram is shown in Figure 7-1.
Figure 7-1: Block Diagram of PA[4:0] and PC[7:0] Pins
WRITE
BUS
D
Q
Pin
PWR
CLK
PORT REG
D
TWR
READ
BUS
Q
CMOS
Buffer
CLK
TRIS REG
21
Preliminary
Figure 7-2: Block Diagram of PA5 and PA6 Pins
WRITE
BUS
D
Q
Pin
PWR
CLK
PORT REG
D
Q
Disable
TWR
READ
BUS
CLK
CMOS
Buffer
TRIS REG
To Oscillators
22
Preliminary
Figure 7-3: Block Diagram of PB0 Pins
LIN
WRITE
BUS
VDD
Weak
Pull-up
RBPU_
D
Q
Pin
PWR
CLK
PORT REG
D
TWR
READ
BUS
Q
CMOS
Buffer
CLK
TRIS REG
INTDEG
INT
Figure 7-4: Block Diagram of PB[3:1] Pins
LIN
VDD
WRITE
BUS
Weak
Pull-up
RBPU_
D
Q
Pin
PWR
CLK
PORT REG
D
TWR
READ
BUS
Q
CMOS
Buffer
CLK
TRIS REG
23
Preliminary
Figure 7-5: Block Diagram of PB[7:4] Pins
LIN
VDD
WRITE
BUS
Weak
Pull-up
RBPU_
D
Q
Pin
PWR
CLK
PORT REG
D
TWR
READ
BUS
Q
CMOS
Buffer
CLK
TRIS REG
D
READ PB
Q
CLK
To Interrupt
PORTA (05h)
7
-
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
PA0
5
PB5
4
PB4
3
PB3
2
PB2
1
PB1
0
PB0
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
PORTA is the value of the I/O port A.
PORTB (06h)
7
PB7
6
PB6
PORTB is the value of the I/O port B.
PORTC (07h)
7
PC7
6
PC6
PORTC is the value of the I/O port C.
24
Preliminary
OPTION Accessed by PEEK/POKE Instruction
7
6
5
4
RBPU_
INTEDG
T0CS
T0SE
RBPU_:
3
PSA
2
PS2
1
PS1
0
PS0
Port B pull-up enable bit
0: Port B pull-up are enabled. Note that it works in linear addressing mode (LIN=1).
1: Port B pull-up are disabled
TRISA Accessed by PEEK/POKE Instruction
7
6
5
4
b6
b5
b4
3
b3
2
b2
1
b1
0
b0
2
b2
1
b1
0
b0
2
b2
1
b1
0
b0
Port A input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
TRISB Accessed by PEEK/POKE Instruction
7
6
5
4
b7
b6
b5
b4
3
b3
Port B input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
TRISC Accessed by PEEK/POKE Instruction
7
6
5
4
b7
b6
b5
b4
3
b3
Port C input/output mode selection. ‘1’ is input mode and ‘0’ is output mode.
25
Preliminary
8 On-Chip Peripherals
8.1 Timer 0
The Timer0 is an 8-bit up-count counter. It is readable and writable. The Timer0 has internal or external clock
source. Besides, an 8-bit readable prescaler is provided to Timer0 if PSA (OPTION.3) is 1. When selecting clock
source input from T0CKI, Timer0 will increment either on every rising or falling edge of T0CKI according to the
setting of T0SE (OPTION.4).
Figure 8-1: Timer0 Block Diagram
R/W
Fosc/4
0
8-bit
Prescaler
T0CKI
T0SE
0
1
8-bit
Up-count Timer
SYN
TMR0
1
T0CS
PSA
TMR0 (01h)
7
b7
6
b6
5
b5
4
b4
3
b3
2
b2
1
b1
0
b0
3
PSA
2
PS2
1
PS1
0
PS0
3
b3
2
b2
1
b1
0
b0
TMR0 contains the value in the counter of the Timer 0.
OPTION Accessed by PEEK/POKE Instruction
7
6
5
4
RBPU_
INTEDG
T0CS
T0SE
PS2-0:
PSA:
T0SE:
T0CS:
Prescaler divide ratio
PS[2:0] TMR0 WDT
000
2
1
001
4
2
010
8
4
011
16
8
100
32
16
101
64
32
110
128
64
111
256
128
Prescaler assignment bit
0: Prescaler is assigned to Timer 0
1: Prescaler is assigned to WDT
Timer 0 source edge select bit
0: Increment on rising edge of T0CKI pin
1: Increment on falling edge of T0CKI pin
Timer 0 clock source select bit
0: T0CKI pin
1: Internal instruction cycle clock
PSCCNT Accessed by PEEK/POKE Instruction
7
6
5
4
b7
b6
b5
b4
PSCCNT is a read-only register which contains the value in the counter of the prescaler.
26
Preliminary
8.2 Watchdog Timer
Watchdog Timer is enabled when bit 5 of Configuration 0 is set. The period of time-out (WDTOV) is 16ms (with no
prescaler). If the prescaler is assigned to the Watchdog Timer, it causes a longer time-out period depending on the
setting on PS[2:0] of OPTION register. A reset is generated when Watchdog Timer is overflow. The TO_ bit in the
STATUS register will be cleared upon a Watchdog Timer time-out. The CLRW and HALT instructions clear
Watchdog Timer.
Figure 8-2: Watchdog Timer Block Diagram
PS[2:0]
Fosc/4
To Timer0
0
0
T0CKI
T0SE
8-bit
Prescaler
1
1
1
WDTOV
0
T0CS
PSA
WDT
Watchdog Timer
Configuration 0
–
–
–
–
–
–
–
–
–
–
–
7
WUP
6
OST
5
WDT
4
6
INT
5
LIN
4
3
2
DIV
0
CLK
WDT: Watchdog timer enable bit
1 = Enable
0 = Disable
Configuration 1
15
14
13
12
EMI
–
STACK
–
–
0
OC
WUP: Watchdog timer wakes CPU up under HALT mode
1 = CPU continues to execute next instruction after Watchdog Timer is overflow
0 = CPU is reset after Watchdog Timer is overflow
OPTION Accessed by PEEK/POKE Instruction
7
6
5
4
RBPU_
INTEDG
T0CS
T0SE
PS2-0:
PSA:
3
PSA
2
PS2
1
PS1
0
PS0
Prescaler divide ratio
PS[2:0] TMR0 WDT
000
2
1
001
4
2
010
8
4
011
16
8
100
32
16
101
64
32
110
128
64
111
256
128
Prescaler assignment bit
0: Prescaler is assigned to Timer 0
1: Prescaler is assigned to WDT
27
Preliminary
9 Special Features
9.1 Interrupts
In interrupt mode there are three sources of interrupt: external INT, interrupt from PORTB, and interrupt from
time-out of Timer 0. When the global interrupt enable bit (GIE) is set and an interrupt condition occurs, its
corresponding flag in register file 08h (INTCON) will be set to ‘1’. If its corresponding interrupt enable bit in register
file 08h (INTCON) is set, it will request to go into interrupt service routine. After it enters Interrupt Service Routine
(ISR), the hardware will clear GIE and will not generate any interrupt request even though there is another interrupt
to prevent recursive interrupts. Within ISR, user needs to judge from INTCON to decide which kind of interrupt
and then interrupt flag needs to be cleared by program. If multiple interrupt sources request simultaneously, the
priority should be determined by program. When the first ISR is complete and returns from RETI, it enters ISR
again if there is another interrupt request until all interrupts are taking care.
GIE
RBIF
RBIE
INTERRUPT
T0IF
T0IE
WAKE-UP
INTF
INTE
INTCON(08h)
7
GIE
RBIF:
INTF:
T0IF:
RBIE:
INTE:
T0IE:
GIE:
6
-
5
T0IE
4
INTE
3
RBIE
2
T0IF
1
INTF
0
RBIF
PB7:PB4 interrupt flag bit
0: No interrupt
1: Interrupt occurs on one of PB7:PB4 pins. An edge transition will generate interrupt.
PB0/INT external interrupt flag bit
0: PB0/INT external interrupt does not occur
1: PB0/INT external interrupt occurs, clear by software
Timer 0 overflow interrupt flag bit
0: Timer 0 does not overflow
1: Timer 0 has overflowed, clear by software
PB7:PB4 interrupt enable bit
0: Disable interrupt
1: Enable interrupt
PB0/INT external interrupt enable bit
0: Disable PB0/INT external interrupt
1: Enable PB0/INT external interrupt
Timer 0 overflow interrupt enable bit
0: Disable Timer 0 overflow interrupt
1: Enable Timer 0 overflow interrupt
Global interrupt enable bit
0: Disable all interrupt
1: Enable interrupt function
28
Preliminary
10 Instruction Set
XXX dest, src
dest= 0~127 or A
src= 0~127 or A
XXX A, #k
dest= A
Table 10-1:
CP8P07 Instruction Set
Instruction
Arithmetic
ADC
A, r
ADC
r, A
ADC
A, #k
ADD
A, r
ADD
r, A
ADD
A, #k
DAA
A, A
DAA
r, A
DAA
A, r
DAA
r, r
SBC
A, r
SBC
r, A
SBC
A, #k
SUB
A, r
SUB
r, A
SUB
A, #k
Flag
Cycles
C, H, Z
C, H, Z
C, H, Z
C, H, Z
C, H, Z
C, H, Z
C
C
C
C
C, H, Z
C, H, Z
C, H, Z
C, H, Z
C, H, Z
C, H, Z
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Instruction
Logic Operation
ANL
A, r
ANL
r, A
ANL
A, #k
CPL
A, A
CPL
r, A
CPL
A, r
CPL
r, r
ORL
A, r
ORL
r, A
ORL
A, #k
XNL
A, r
XNL
r, A
XNL
A, #k
XRL
A, r
XRL
r, A
XRL
A, #k
Flag
Cycles
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Instruction
Rotate & Shift
ASR
A, A
ASR
r, A
ASR
A, r
ASR
r, r
RL
A, A
RL
r, A
RL
A, r
RL
r, r
RLC
A, A
RLC
r, A
RLC
A, r
RLC
r, r
RR
A, A
RR
r, A
RR
A, r
RR
r, r
RRC
A, A
Flag
Cycles
C, Z
C, Z
C, Z
C, Z
C
C
C
C
C
C
C
C
C
C
C
C
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Description
r+A+C A
r+A+C r
k + A+C A
r+A A
r+A r
k+A A
A DAA A
A DAA r
r DAA A
r DAA r
r – A –C A
r – A –C
r
k–A–C A
r–A A
r–A r
k–A A
Description
r&A A
r&A r
k&A A
~A A
~A r
~r A
~r
r
r|A A
r|A r
k|A A
~(r ⊕ A) A
~(r ⊕ A)
r
~(k ⊕ A) A
r⊕A A
r⊕A r
k⊕A A
Description
{ A[7], A[7:1]} A, A[0] C
{ A[7], A[7:1]}
r, A[0]
C
{ r[7], r[7:1]} A, r[0]
C
{ r[7], r[7:1]}
r, r[0]
C
{A[6:0], A[7]} A, A[7]
C
{A[6:0], A[7]}
r, A[7]
C
{r[6:0], r[7]} A, r[7]
C
{r[6:0], r[7]}
r, r[7]
C
{A[6:0], C} A, A[7]
C
{A[6:0], C}
r, A[7]
C
{r[6:0], C} A, r[7]
C
{r[6:0], C}
r, r[7]
C
{A[0], A[7:1]} A, A[0]
C
{A[0], A[7:1]}
r, A[0]
C
{r[0], r[7:1]} A, r[0]
C
{r[0], r[7:1]} r, r[0]
C
{C, A[7:1]} A, A[0]
C
29
Preliminary
RRC
RRC
RRC
SHL
SHL
SHL
SHL
SHR
SHR
SHR
SHR
r, A
A, r
r, r
A, A
r, A
A, r
r, r
A, A
r, A
A, r
r, r
C
C
C
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
1
1
1
1
1
1
1
1
1
1
1
Instruction
Bit Operation
RMB0-7
A
RMB0-7
r
SMB0-7
A
SMB0-7
r
Flag
Cycles
Instruction
Data Move
MOV
r, A
MOV
A, r
MOV
A, #k
PEEK
r
POKE
r
Flag
1
1
1
1
{C, A[7:1]}
r, A[0]
{C, r[7:1]} A, r[0]
{C, r[7:1]}
r, r[0]
{A[6:0], 0} A, A[7]
{A[6:0], 0} r, A[7]
{r[6:0], 0} A, r[7]
{r[6:0], 0}
r, r[7]
{0, A[7:1]} A, A[0]
{0, A[7:1]}
r, A[0]
{0, r[7:1]} A, r[0]
{0, r[7:1]}
r, r[0]
C
C
C
C
C
C
C
C
C
C
C
Description
0
0
1
1
A[0-7]
r[0-7]
A[0-7]
r[0-7]
Cycles
Description
1
1
1
1
1
A r
r A
k A
CR[r] A
A CR[r]
Instruction
Flag
Increment & Decrement
DEC
A, A
Z
DEC
r, A
Z
DEC
A, r
Z
DEC
r, r
Z
INC
A, A
Z
INC
r, A
Z
INC
A, r
Z
INC
r, r
Z
Cycles
Description
Instruction
Branch
DSZ
A, A
DSZ
r, A
DSZ
A, r
DSZ
r, r
ISZ
A, A
ISZ
r, A
ISZ
A, r
ISZ
r, r
JMP
k
Cycles
Description
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
2
A -1 A, skip if 0
A -1
r, skip if 0
r -1 A, skip if 0
r -1
r, skip if 0
A +1 A, skip if 0
A +1
r, skip if 0
r +1 A, skip if 0
r +1
r, skip if 0
{status[6:5],k[8:0]}
PC if LIN=0.
{k[10:0]}
PC if LIN=1.
PC + 1
STACK[top],
{status[6:5], 0, k[7:0]}
PC if LIN=0.
{k[10:0]}
PC if LIN=1.
STACK[top]
PC
k A, STACK[top] PC
1 GIE, STACK[top] PC
Skip if A[0-7] = 0
Skip if r[0-7] = 0
Skip if A[0-7] ≠ 0
Skip if r[0-7] ≠ 0
Skip if A = r
Skip if A= k
Skip if A > r
SKip if A > k
Skip if A ≥ r
SKip if A ≥ k
Skip if A < r
SKip if A < k
Skip if A ≤ r
SKip if A ≤ k
JSR
RET
RET
RETI
SBR0-7
SBR0-7
SBS0-7
SBS0-7
SE
SE
SG
SG
SGE
SGE
SL
SL
SLE
SLE
k
#k
A
r
A
r
r
#k
r
#k
r
#k
r
#k
r
#k
Z
Z
Flag
1
1
1
1
1
1
1
1
2
2
2
2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
1 or 2
A -1 A
A -1
r
r -1 A
r -1
r
A +1 A
A +1
r
r +1 A
r +1
r
30
Preliminary
SNE
SNE
r
#k
Instruction
Miscellaneous
CLR
A
CLR
r
CLRW
HALT
NOP
SET
SET
SWAP
SWAP
SWAP
SWAP
TEST
TEST
XCH
A
r
A, A
r, A
A, r
r, r
A
r
r
1 or 2
1 or 2
Skip if A ≠ r
SKip if A ≠ k
Flag
Cycles
Description
Z
Z
TO_,
PD_
TO_,
PD_
1
1
1
Z
Z
Z
Z
1
1
1
1
1
1
1
1
1
1
1
0 A
0
r
0
WDT, 0
WDT prescaler
1
TO_, 1
PD_
0
WDT, 0
WDT prescaler
1
TO_, 0
PD_
No operation
0xFF A
0xFF
r
{A[3:0], A[7:4]} A
{A[3:0], A[7:4]}
r
{r[3:0], r[7:4]} A
{r[3:0], r[7:4]}
r
A A
r
r
A
r
31
Preliminary
10.1 Instruction Description
ADC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Add A and Reg and Carry
ADC X, Y
1
0 ≤ X ≤ 127
Y = X or A
X + Y + C -> Y
C, H, Z
Add A with register X and C. Result
is stored back in X or A.
ADC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Add A and literal and Carry
ADC A, #k
1
0 ≤ k ≤ 255
k + A + C -> A
C, H, Z
Add A with 8-bit literal ‘k’ and C.
Result is stored back in A.
ADD
Format:
Cycles:
Operands:
Add A and Reg
ADD X, Y
1
0 ≤ X ≤ 127
Y = X or A
X + Y -> Y
C, H, Z
Add A with register X. Result is
stored back in X or A.
Operations:
Flag Affected:
Description:
ADD
Binary:
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
ANL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
ANL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Add A and literal
1111 0001 kkkk kkkk
ADD A, #k
1
0 ≤ k ≤ 255
k + A -> A
C, H, Z
Add A with 8-bit literal ‘k’. Result is
stored back in A.
Logic AND A with Reg
ANL X, Y
1
0 ≤ X ≤ 127
Y = X or A
X & Y -> Y
Z
Logic AND A with register X. Result
is stored back in X or A.
Logic AND A with literal
ANL A, #k
1
0 ≤ k ≤ 255
k & A -> A
Z
Logic AND A with 8-bit literal ‘k’.
Result is stored back in A.
ASR
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Shift right arithmetic
ASR X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[7], X[7:1]} -> Y, X[0] -> C
C, Z
Shift register X one bit from left to
right arithmetically. The MSB of X is
stay unchanged and LSB of X is
moved to C. Result is stored back
in X or A.
CLR
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Clear register
CLR X
1
X = A or 0 ≤ X ≤ 127
0 -> X, 1 -> Z
Z
Register X is clear and Z is set.
CLRW
Format:
Cycles:
Operands:
Operations:
Clear watchdog timer
CLRW
1
None
0 -> WDT, 0 -> WDT prescaler
1 -> TO_ ->PD_
TO_, PD_
Clear watchdog time and prescaler
of the WDT. Flags TO_ and PD_
are set.
Flag Affected:
Description:
CPL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
DAA
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Complement
CPL X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
~X -> Y
Z
Complement X. Result is stored
back in X or A.
Decimal-adjust after addition
DAA X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
If X[3:0] > 9 or H = 1
X[3:0] + 6 -> Y[3:0]
else X[3:0] -> Y[3:0]
If X[7:4] > 9 or C = 1
X[7:4] + 6 -> Y[7:4]
else X[7:4] -> Y[7:4]
C
Adjust data in register X from
hexadecimal to decimal. Result is
stored back in X or A.
32
Preliminary
DEC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
DSZ
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
HALT
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
INC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
ISZ
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Decrement
DEC X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
X – 1 -> Y
Z
Decrement X. Result is stored back
in X or A.
Decrement, skip if 0
DSZ X, Y
1 (2)
0 ≤ X ≤ 127 or X = A
Y = X or A
X – 1 -> Y, skip if 0
None
Decrement X. Result is stored back
in X or A. If result is 0, skip next
instruction by executing a NOP.
Standby
HALT
1
None
0 -> WDT, 0 -> WDT prescaler
1 -> TO_, 0 -> PD_
TO_, PD_
Clear watchdog time and prescaler
of the WDT. Flags TO_ and PD_
are set. Then the device is put into
power-down mode and the
oscillator stopped.
Increment
INC X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
X + 1 -> Y
Z
Increment X. Result is stored back
in X or A.
Increment, skip if 0
ISZ X, Y
1 (2)
0 ≤ X ≤ 127 or X = A
Y = X or W
X + 1 -> Y, skip if 0
None
Increment X. Result is stored back
in X or A. If result is 0, skip next
instruction by executing a NOP.
JMP
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
JSR
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Unconditional branch
JMP k
2
0 ≤ k ≤ 2047
{Status[6:5],K[8:0]}
PC if LIN=0,
K[10:0] -> PC if LIN=1
None
JMP is an unconditional branch.
The immediate address k is loaded
into PC.
Call subroutine
JSR k
2
0 ≤ k ≤ 2047
PC + 1 -> STACK[top],
{Status[6:5],0,K[7:0]}
PC if
LIN=0,
K[10:0] -> PC if LIN=1
None
Call subroutine. Return address
(PC+1) is pushed onto the STACK.
The immediate address k is loaded
into PC.
MOV
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Move between Register and A
MOV X, A
1
0 ≤ X ≤ 127
A -> X
MOV
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Move between Register and A
MOV A, X
1
0 ≤ X ≤ 127
X -> A
Z
Move X to A.
MOV
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Move literal to A
MOV A, #k
1
0 ≤ k ≤ 255
k -> A
None
Move 8-bit literal ‘k’ to A.
NOP
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
No Operation
NOP
1
None
None
None
No operation.
Move A to X.
33
Preliminary
Logic OR A with Reg
ORL X, Y
1
0 ≤ X ≤ 127
Y = X or A
X | Y -> Y
Z
Logic OR A with register X. Result
is stored back in X or A.
RETI
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Return from interrupt
RETI
2
None
1 -> GIE, STACK[top] -> PC
None
Return from interrupt. Set GIE flag.
The top of the stack is poped and
loaded into PC.
ORL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Logic OR A with literal
ORL A, # k
1
0 ≤ k ≤ 255
k | A -> A
Z
Logic OR A with 8-bit literal ‘k’.
Result is stored back in A.
RL
Format:
Cycles:
Operands:
PEEK
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Read value from CM
PEEK X
1
0 ≤ X ≤ 15
CR[X] -> A
Z
Read value from control register
and store back in A.
Rotate left
RL X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[6:0], X[7]} -> Y, X[7] -> C
C
Rotate register X one bit from right
to left. Result is stored back in X or
A. The MSB of X is also moved to
C.
POKE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Write A to CM
POKE X
1
0 ≤ X ≤ 15
A -> CR[X]
Z
Write A to control register.
RET
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Return from subroutine
RET
2
None
STACK[top] -> PC
None
Return from subroutine. The top of
the stack is poped and loaded into
PC.
RET
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Return with literal in A
RET #k
2
0 ≤ k ≤ 255
K -> A, STACK[top] -> PC
None
Return from interrupt. 8-bit literal ‘k’
is stored in A. The top of the stack
is poped and loaded into PC.
ORL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Operations:
Flag Affected:
Description:
RLC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Rotate left through carry
RLC X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[6:0], C} -> Y, X[7] -> C
C
Rotate register X one bit from right
to left through carry flag. The LSB
of X is replaced by C flag and the
MSB value is moved to C flag.
Result is stored back in X or A.
RMB0-7
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Bit clear
RMB0-7 X
1
X = A or 0 ≤ X ≤ 127
0 -> X[b]
None
Bit ‘b’ in register X is clear.
RR
Format:
Cycles:
Operands:
Rotate right
RR X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[0], X[7:1]} -> Y, X[0] -> C
C
Rotate register X one bit from left to
right. The LSB of X is also moved to
C. Result is stored back in X or A.
Operations:
Flag Affected:
Description:
34
Preliminary
RRC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
SBC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Rotate right through carry
RRC X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{C, X[7:1]} -> Y, X[0] -> C
C
Rotate register X one bit from left to
right through carry flag. The MSB of
X is replaced by C flag and the LSB
value is moved to C flag. Result is
stored back in X or A.
Subtract A from Reg and Carry
SBC X, Y
1
0 ≤ X ≤ 127
Y = X or A
X – Y – C -> Y
C, H, Z
Subtract A from register X and C.
Result is stored back in X or A.
SBC
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Subtract A from literal and Carry
SBC A, #k
1
0 ≤ k ≤ 255
k – A – C -> A
C, H, Z
Subtract A from 8-bit literal ‘k’ and
C. Result is stored back in A.
SBR0-7
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Bit test, skip if zero
SBR0-7 X
1 (2)
X = A or 0 ≤ X ≤ 127
Skip if X[b] = 0
None
If X[b] = 0, skip next instruction by
executing a NOP.
SBS0-7
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Bit test, skip if not zero
SBS0-7 X
1 (2)
X = A or 0 ≤ X ≤ 127
Skip if X[b] ≠ 0
None
If X[b] ≠ 0, skip next instruction by
executing a NOP.
SE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if equal
SE X
1 (2)
0 ≤ X ≤ 127
Skip if A = X
None
If A = X, skip next instruction by
executing a NOP.
SE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if equal literal
SE #k
1 (2)
0 ≤ k ≤ 255
Skip if A = k
None
If A = k, skip next instruction by
executing a NOP.
SET
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Set register
SET X
1
X = A or 0 ≤ X ≤ 127
0xFF -> X
Z
Register X is set.
SG
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if greater
SG X
1 (2)
0 ≤ X ≤ 127
Skip if A > X
None
If A > X, skip next instruction by
executing a NOP.
SG
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if greater than literal
SG #k
1 (2)
0 ≤ k ≤ 255
Skip if A > k
None
If A > k, skip next instruction by
executing a NOP.
SGE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if greater or equal
SGE X
1 (2)
0 ≤ X ≤ 127
Skip if A ≥ X
None
If A ≥ X, skip next instruction by
executing a NOP.
SGE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if greater than or equal literal
SGE #k
1 (2)
0 ≤ k ≤ 255
Skip if A ≥ k
None
If A ≥ k, skip next instruction by
executing a NOP.
35
Preliminary
SHL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
SHR
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
SL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Shift left
SHL X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[6:0], 0} -> Y, X[7] -> C
C, Z
Shift register X one bit from right to
left. The MSB of X is moved to C
and 0 is moved to LSB of X. Result
is stored back in X or A.
Shift right logical
SHR X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{0, X[7:1]} -> Y, X[0] -> C
C, Z
Shift register X one bit from left to
right logically. 0 is moved to MSB of
X and LSB of X is moved to C.
Result is stored back in X or A.
Skip if less
SL X
1 (2)
0 ≤ X ≤ 127
Skip if A < X
None
If A < X, skip next instruction by
executing a NOP.
SL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if less than literal
SL #k
1 (2)
0 ≤ k ≤ 255
Skip if A < k
None
If A < k, skip next instruction by
executing a NOP.
SLE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if less or equal
SLE X
1 (2)
0 ≤ X ≤ 127
Skip if A ≤ X
None
If A ≤ X, skip next instruction by
executing a NOP.
SLE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if less than or equal literal
SLE #k
1 (2)
0 ≤ k ≤ 255
Skip if A ≤ k
None
If A ≤ k, skip next instruction by
executing a NOP.
SMB0-7
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Bit set
SMB0-7 X
1
X = A or 0 ≤ X ≤ 127
1 -> A[b]
None
Bit ‘b’ in register A is set.
SNE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if not equal
SNE X
1 (2)
0 ≤ X ≤ 127
Skip if A ≠ X
None
If A ≠ X, skip next instruction by
executing a NOP.
SNE
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Skip if not equal literal
SNE #k
1 (2)
0 ≤ k ≤ 255
Skip if A ≠ k
None
If A ≠ k, skip next instruction by
executing a NOP.
SUB
Format:
Cycles:
Operands:
Subtract A from Reg
SUB X, Y
1
0 ≤ X ≤ 127
Y = X or A
X – Y -> Y
C, H, Z
Subtract A from register X. Result is
stored back in X or A.
Operations:
Flag Affected:
Description:
SUB
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Subtract A from literal
SUB A, #k
1
0 ≤ k ≤ 255
k – A -> A
C, H, Z
Subtract A from 8-bit literal ‘k’.
Result is stored back in A.
SWAP
Format:
Cycles:
Operands:
Swap nibbles
SWAP X, Y
1
0 ≤ X ≤ 127 or X = A
Y = X or A
{X[3:0], X[7:4]] -> Y
None
The upper and lower nibbles of X
are exchange. Result is stored
back in X or A.
Operations:
Flag Affected:
Description:
36
Preliminary
TEST
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Test Register
TEST A
1
TEST
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Test Register
TEST X
1
0 ≤ X ≤ 127
X -> X
Z
Test a file register. Z flag is affected.
XCH
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Exchange between A and Reg
XCH X
1
0 ≤ X ≤ 127
A <-> X
None
The contents of A and register X are
exchanged.
XNL
Format:
Cycles:
Operands:
Logic exclusive NOR A with Reg
XNL X, Y
1
0 ≤ X ≤ 127
Y = X or A
~(X ⊕ Y) -> X
Z
Logic exclusive NOR A with register
X. Result is stored back in X or A.
Operations:
Flag Affected:
Description:
A -> A
Z
Test A. Z flag is affected.
XNL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Logic exclusive NOR A with literal
XNL A, #k
1
0 ≤ k ≤ 255
~(k ⊕ A) -> A
Z
Logic exclusive NOR A with 8-bit
literal ‘k’. Result is stored back in A.
XRL
Format:
Cycles:
Operands:
Logic exclusive OR A with Reg
XRL X, Y
1
0 ≤ X ≤ 127
Y = X or A
X ⊕ Y -> X
Z
Logic exclusive OR A with register
X. Result is stored back in X or A.
Operations:
Flag Affected:
Description:
XRL
Format:
Cycles:
Operands:
Operations:
Flag Affected:
Description:
Logic exclusive OR A with literal
XRL A, #k
1
0 ≤ k ≤ 255
k ⊕ A -> A
Z
Logic exclusive OR A with 8-bit
literal ‘k’. Result is stored back in A.
37
Preliminary
11. Absolute Maximum Ratings
Supply Voltage ……………... -0.3V~5.5V
Input Voltage ……… VSS-0.3V~VDD+0.3V
Storage temperature ………...… -50℃~125℃
Operation temperature ……….…-40℃~85℃
(Industrial Grade)
12. DC Characteristics
Symbol
Parameter
VDD1 Operating Voltage
VDD2 Operating Voltage
VDD3 Operating Voltage
FOSC
Main Oscillator Frequency
VDD
5V
Conditions
XT4M
LP32K
HS16M
XT4M
LP32K
HS16M
Min.
2.2
2.2
3.0
0.2
32
4
TA=25℃
Typ. Max. Unit
5.5
V
5.5
V
5.5
V
4 MHz
200 KHz
20 MHz
1
mA
0.4
mA
4.5
mA
1.6
mA
32
uA
7
uA
1
uA
1
uA
-6
mA
-2.5
mA
20
mA
10
mA
KΩ
11
KΩ
32
5V
3V
5V
Operating Current 2
3V
5V
Operating Current 3
3V
5V
Standby Current
3V
I/O Port Source Current (PA, PB, 5V
PC)
3V
I/O Port Sink Current (PA, PB,
5V
PC)
3V
5V
PB Pull-high R
3V
VOH=4.5V
VOH=2.7V
VOL=0.5V
VOL=0.3V
-
VIL1
Input Low Voltage for Input Port
-
-
0
-
VIH1
Input High Voltage for Input Port
-
-
0.7VDD
-
VIL2
Input Low Voltage for RESET_
-
-
0
-
VIH2
Input High Voltage for RESET_
-
-
0.9VDD
-
IDD1
IDD2
IDD3
ISTB
IOH
IOL
RPH
Operating Current 1
XT4M (4MHz)
HS16M (16MHz)
LP32K (32KHz)
System halt, WDT disable
-
0.3VDD V
VDD
V
0.4VDD V
VDD
V
38