ETC LGDP4525

LGDP4525
176RGBx220-dot, 262,144-color 1-chip TFT LCD driver IC
Rev 0.9.0
2007-12-10
Description................................................................................................................................... 5
Features........................................................................................................................................ 6
Power Supply Specifications ..................................................................................................... 7
Block Diagram ............................................................................................................................. 8
Pin Function................................................................................................................................. 9
PAD Arrangement ..................................................................................................................... 13
PAD Coordinate ......................................................................................................................... 14
Bump Arrangement................................................................................................................... 18
Block Function........................................................................................................................... 19
External Display Interface........................................................................................................ 19
Bit Operations .......................................................................................................................... 20
Address Counter (AC) ............................................................................................................. 20
Graphics RAM (GRAM) ........................................................................................................... 20
Grayscale Voltage Generating Circuit ..................................................................................... 20
Timing Generator..................................................................................................................... 20
Oscillator (OSC)....................................................................................................................... 20
LCD Driver Circuit.................................................................................................................... 20
LCD Drive Power Supply Circuit.............................................................................................. 20
GRAM Address MAP ................................................................................................................. 21
Instructions ................................................................................................................................ 29
Outline...................................................................................................................................... 29
Index (IR) ................................................................................................................................. 31
Status Read (SR)..................................................................................................................... 31
ID CODE (R00h)...................................................................................................................... 31
Driver Output Control (R01h)................................................................................................... 31
LCD Driving Waveform Control (R02h) ................................................................................... 33
Entry Mode (R03h) .................................................................................................................. 33
LGDP4525
Rev 0.9.0
Resize Control (R04h) ............................................................................................................. 36
Display Control 1 (R07h) ......................................................................................................... 36
Display Control 2 (R08h) ......................................................................................................... 38
Display Control 3 (R09h) ......................................................................................................... 39
Frame Cycle Control (R0Bh) ................................................................................................... 40
External Display Interface Control 1 (R0Ch) ........................................................................... 41
Oscillator Control (R0Fh) ......................................................................................................... 43
Power Control 1 (R10h) ........................................................................................................... 44
Power Control 2 (R11h) ........................................................................................................... 44
Power Control 3 (R12h) ........................................................................................................... 46
Power Control 4 (R13h) ........................................................................................................... 46
Power Control 5 (R14h) ........................................................................................................... 48
Power Control 6 (R15h) ........................................................................................................... 49
RAM Address Set (R21h) ........................................................................................................ 49
Write Data to GRAM (R22h) .................................................................................................... 50
RAM Access via RGB I/F and System I/F ............................................................................... 54
Read Data Read from GRAM (R22h)...................................................................................... 55
Software Reset (R28h) ............................................................................................................ 57
γ Control (R30h to R3Fh)......................................................................................................... 58
Gate Scan Position (R40h) ...................................................................................................... 58
Vertical Scroll Control (R41h) .................................................................................................. 60
1st-Screen Drive Position (R42h) ............................................................................................ 60
2nd-Screen Drive Position (R43h) ........................................................................................... 60
Horizontal RAM Address Position (R44h) ............................................................................... 61
Vertical RAM Address Position (R45h).................................................................................... 61
Test Register 1 (R71h) ............................................................................................................ 61
Test Register 2 (R72h) ............................................................................................................ 62
Instruction List........................................................................................................................... 63
Interface Specifications ............................................................................................................ 64
System Interface........................................................................................................................ 66
80-System 18-Bit Interface ...................................................................................................... 67
80-System 16-Bit Interface ...................................................................................................... 68
Data Transfer Synchronizing in 16-Bit Bus Interface Mode .................................................... 69
80-System 9-Bit Interface ........................................................................................................ 70
Data Transfer Synchronizing in 9-Bit Bus Interface Mode ...................................................... 71
80-System 8-Bit Interface ........................................................................................................ 72
2
LGDP4525
Rev 0.9.0
Data Transfer Synchronization in 8-Bit Bus Interface Mode ................................................... 74
Serial Peripheral Interface (SPI) .............................................................................................. 75
VSYNC Interface ........................................................................................................................ 77
External Display Interface ........................................................................................................ 80
Interfacing Timing with LCD Panel .......................................................................................... 90
RGB I/F Mode .......................................................................................................................... 90
Internal Clock Operation Mode ................................................................................................ 91
Scan Mode Setting .................................................................................................................... 92
γ-Correction Function ............................................................................................................... 93
Grayscale Amplifier Unit Configuration.................................................................................... 94
γ-Correction Register............................................................................................................... 96
Ladder Resistors and 8-to-1 Selector...................................................................................... 98
Relationship between RAM Data and Voltage Output Levels ............................................... 102
8-Color Display Mode.............................................................................................................. 103
Configuration of Power Supply Circuit ................................................................................. 105
Specification of External Elements Connected to LGDP4525 Power Supply ....................... 106
Instruction Setting................................................................................................................... 107
Display On/Off ....................................................................................................................... 107
Standby and Sleep Modes..................................................................................................... 108
Deep Standby Mode .............................................................................................................. 108
Power Supply Setting ............................................................................................................. 109
Pattern Diagram for Voltage Setting ..................................................................................... 110
Oscillator .................................................................................................................................. 111
n-Line Inversion AC Drive ...................................................................................................... 112
Interlaced Scan ........................................................................................................................ 113
Alternating Timing................................................................................................................... 114
Frame Frequency Adjustment Function ............................................................................... 115
Partial Display Function ......................................................................................................... 116
Absolute Maximum Ratings ................................................................................................... 119
Electrical Characteristics ....................................................................................................... 120
DC Characteristics................................................................................................................. 120
3
LGDP4525
Rev 0.9.0
80-System Bus Interface Timing Characteristics (18/16-Bit Bus) ......................................... 120
80-System Bus Interface Timing Characteristics (8/9-Bit Bus) ............................................. 121
Serial Peripheral Interface Timing Characteristics ................................................................ 121
Reset Timing Characteristics................................................................................................. 121
RGB Interface Timing Characteristics ................................................................................... 122
Notes to Electrical Characteristics......................................................................................... 122
Timing Characteristics Diagram............................................................................................. 125
4
LGDP4525
Rev 0.9.0
Description
The LGDP4525 is a 262,144-color one-chip controller driver LSI for a TFT liquid crystal display
with resolution of 176 RGB x 220 dots, comprising a 528-channel source driver, RAM for
graphics data of 176 RGB x 220 dots at maximum, a gate driver and a power supply circuit.
The LGDP4525 supports high-speed parallel interfaces to 8-, 9-, 16-, 18-bit ports and a function
to write RAM data in high speed for transferring data efficiently and rewriting RAM graphics data
in high speed. In addition, the LGDP4525 incorporates 6-, 16-, 18-bit RGB interfaces (VSYNC,
HSYNC, DOTCLK, ENABLE, and DB[17:0]) and a VSYNC interface (system interface +
VSYNC) for displaying a moving picture, which, with use of window address function, enable the
LGDP4525 to display a moving picture easily at a position specified by a user and still pictures
in other areas on the screen simultaneously. Since this combination allows transferring only
moving picture data while retaining still picture data in the internal RAM intact, data transfer can
be minimized and power consumption by the entire system is reduced.
The LGDP4525 can operate with low I/O interface power supply up to 1.65V, with an
incorporated voltage follower circuit to generate voltage levels for driving an LCD. The
LGDP4525 also supports a function to display in 8 colors and a standby mode, allowing for
precise power control by software. These features make the LGDP4525 an ideal LCD driver for
medium or small sized portable products supporting WWW browsers such as digital cellular
phones or small PDAs, where long battery life is a measure concern.
5
LGDP4525
Rev 0.9.0
Features
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A controller driver for a liquid crystal TFT display with resolution of 176RGB x 220-dot,
capable of graphics display in 262,144 colors
Single chip solution for a liquid crystal TFT display
System interfaces
− High-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports
− Serial Peripheral Interface (SPI)
Interfaces for moving picture display
− 6-, 16-, 18-bit RGB interfaces (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])
− VSYNC interface (System interface + VSYNC)
Window address function to specify a rectangular area on the internal RAM for moving
picture display
− Facilitate moving picture display at any area on the screen via a moving picture display
interface
− Limit the data rewriting area and reduce data transfer
− Enable moving and still picture display at the same time
Bit operation function for facilitating graphics data processing
− Bit-unit write data mask function
− Pixel-unit logical/conditional write function
Abundant functions for color display control
− γ-correction function enabling display in 262,144 colors
− Line-unit vertical scrolling function
Low -power consumption architecture
− Low operating power supplies: VCI = 2.5 to 3.3 V (To generate logic voltage & analog)
VDD = 1.7 to 1.9 V (internal logic)
VDD3 = 1.65 to 3.3 V (interface I/O)
− Low voltage drive:
AVDD = 4.5 to 5.5 V
− Power saving functions (standby mode etc.)
− Liquid crystal partial drive function, enabling partially driving an LCD panel at positions
specified by a user
− A voltage follower circuit for generating LCD driving voltage levels with a small direct
current through bleeder resistors
Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times
(x6)
87,120 byte internal RAM
Incorporate a 528-channel source driver and a 220-channel gate driver
n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily set n lines (n: 0 ~ 64)
Internal oscillator and hardware reset
Internal oscillator uses an internal resistor and also an external resistor optionally.
Reversible source driver shift direction
For Cst structure only
6
LGDP4525
Rev 0.9.0
Power Supply Specifications
Table 1
No.
1
2
3
4
Item
TFT source lines
TFT gate lines
Capacitor structure of TFT display
Liquid crystal
S1 to S528
drive output
G1 to G220
VCOM
5
Input voltage
6
Internal step-up
circuits
VDD3
VCI
VDD
AVDD
VGH
VGL
VCL
LGDP4525
528 pins (176 x RGB)
220 pins
Cst structure only (common VCOM formula)
V0 to V63 grayscales
VGH to VGL
VCOMH – VCOML: amplitude = electronic volumes
VCOMH = VCOMR: adjusted with an external resistor
1.65 – 3.30 V
2.50 – 3.30 V
1.70 – 1.90 V
VCI1 ×2
VCI1 ×4, ×5, ×6
VCI1 ×-3, ×-4, ×-5
VCI1 ×-1
7
LGDP4525
Rev 0.9.0
Block Diagram
Index
register
VDD3
E_RDB
SDI
SDO
Write data
latch
18-bit bus
16-bit bus
9-bit bus
8-bit bus
SPI
Read data
latch
18
Graphics RAM
87,120 bytes
18
Source driver circuit
RW_WRB
Bit
operation
Latch circuit
RS
System
interface
M alternating circuit
CSB
Latch circuit
IM[3:0]
VSS
VSSC
AVSS
Address
counter
Control
registers
S1 - S528
DB[17:0]
V63-0
DOTCLK
External
display
interface
Timing
generator
ENABLE
RESETB
RESETEN
Oscillator
OSC1
CL1
VREF
VREF_BUF
BandGap
Reference
Gate driver circuit
OSC2
Scan data generation
FLM
TEST_
MODE[1:0]
Grayscale voltage
generating circuit
VSYNC
Gamma correction
HSYNC
VGS
G1 – G220
Internal
reference voltage
generating circuit
VCOM
VCOML
VCOMH
GVDD
VCOMR
VCL
VGL
VGH
AVDD
C22P/C22M
C21P/C21M
C12P/C12M
C31P/C31M
C11P/C11M
VCI
VCI
Liquid crystal drive level generating circuit
Logic power
supply regulator
VCI1
VDD
RVDD
Figure 1 Block Diagram of LGDP4525
8
LGDP4525
Rev 0.9.0
Pin Function
Table 2
Name
IM[3:0]
#
pins
4
I/O
I
Connected
to
GND or
VDD3
Function
MPU interface mode select signal.
In SPI mode, the IM[0] pin is used to set the ID of device
code.
IM[3:0]
0000
Interface mode
68-system 16 bit interface
0001
0010
68-system 8 bit interface
80-system 16 bit interface
0011
010*
CSB
1
I
MPU
RS
1
I
MPU
RW_WRB / SCL 1
I
MPU
E_RDB
1
I
MPU
SDI
1
I
MPU
SDO
1
O
MPU
DB[17:0]
18
I/O
MPU
ENABLE
1
I
MPU
VSYNC
1
I
MPU
HSYNC
1
I
MPU
DOTCLK
1
I
MPU
Data pins
DB[17:10],
DB[8:1]
DB[17:10],
DB[17:10],
DB[8:1]
DB[17:10]
SDI, SDO
80-system 8 bit interface
Serial peripheral interface
(SPI)
1000
68-system 18 bit interface
DB[17:0]
1001
68-system 9 bit interface
DB[17:9]
1010
80-system 18 bit interface
DB[17:0]
1011
80-system 9 bit interface
DB[17:9]
11**
Setting disabled
Chip select signal (active low).
Low: LGDP4525 is selected and accessible.
High: LGDP4525 is not selected and not accessible.
Fix to the GND level when not in use.
Register select signal.
Low: selects the index/status register.
High: selects a control register.
Write strobe (active low) in 80-system bus interface mode.
Serial clock input in SPI mode.
Read strobe (active low) in 80-system bus interface mode.
Fix to either VDD3 or GND level in SPI mode.
Serial data input in SPI mode.
Data are input on the rising edge of the SCL signal. Fix to
either VDD3 or GND level when not in use.
Serial data output in SPI mode.
Data are output on the falling edge of the SCL signal. Leave
the pin open when not in use.
Parallel bidirectional data bus.
Unused pins must be fixed either VDD3 or GND level.
Data enable signal in RGB interface mode.
Low: select (accessible).
High: not select (inaccessible).
The EPL bit inverts the polarity of the ENABLE signal. Fix to
either VDD3 or GND level when not in use.
Frame synchronization signal.
When VSPL = “0”, it is active low.
When VSPL = “1”, it is active high.
Fix to either VDD3 or GND level when not in use.
Line synchronization signal.
When HSPL = “0”, it is active low.
When HSPL = “1”, it is active high.
Fix to either VDD3 or GND level when not in use.
Dot clock signal.
When DPL = “0”, input data on the rising edge of DOTCLK.
When DPL = “1”, input data on the falling edge of DOTCLK.
Fix to either VDD3 or GND level when not in use.
9
LGDP4525
Name
Rev 0.9.0
I/O
RESETB
#
pins
1
RESETEN
1
I
FLM
1
I/O
CL1
OSC1
1
1
O
I
OSC2
1
O
I
Connected
to
MPU
Function
VDD3, GND
or OPEN
VDD3, GND
or OPEN
LCD
LCD
TFT panel
common
electrode
Dummy pins.
Hardware reset (active low).
Be sure to execute a power-on reset after supplying power.
MPU or GND Enable for RESETB Pin. If this connected to VDD3, the
RESETB Pin is invalid and the LGDP4525 cannot be reset.
Otherwise, RESETB Pin is valid to LGDP4525.
MPU or
Frame head pulse signal.
OPEN
This is used when writing RAM data in synchronization with
display frame. Leave the pin open when not in use.
OPEN
Output Pin for test purpose.
OPEN or
This pin can be used to connect to an external resistor for
external R
oscillator with OSC2.
OPEN or
This pin can be used to connect to an external resistor for
external R
oscillator wth OSC1.
GND
Input Pins for test purpose.
TEST_MODE
2
[1:0]
TEST_MUX[2:1] 2
I
TEST_DA
1
I
S1 to S528
G1 to G220
VCOM
528
220
1
O
O
O
VCOMH
1
O
VCOML
1
O
VCOMR
1
I
Variable
resistor or
OPEN
C11P, C11M
2
I/O
C12P, C12M
2
I/O
C31P, C31M
C21P, C21M
C22P, C22M
VCI
6
I/O
Step-up
capacitor
Step-up
capacitor or
GND or
OPEN
Step-up
capacitor
1
-
Power
supply
VCI1
1
I/O
Stabilizing
capacitor
I
Stabilizing
capacitor
Stabilizing
capacitor or
OPEN
Dummy pin.
Source line outputs to LCD.
Gate line outputs to LCD.
Supply voltage to the common electrode of TFT panel.
VCOM is AC voltages alternating between the VCOMH and
VCOML levels. The alternating cycle is set by M signal.
Connect to the common electrode of TFT panel. All outputs
come from the same node.
The high level of VCOM AC voltage.
Connect to a stabilizing capacitor.
The low level of VCOM AC voltage.
Adjust the VCOML level with the VDV bits. Connect to a
stabilizing capacitor. To fix the VCOML level to GND, set
VCOMG to “0”. In this case, capacitor connection is not
necessary.
Reference level to generate the VCOMH level either with an
externally connected variable resistor or by setting the
register of the LGDP4525.
When using a variable resistor, halt the internal VCOMH
adjusting circuit by setting the register and place the resister
between GVDD and GND. When generating the VCOMH
level by setting the register, leave this pin open.
Pins to connect a capacitor for the internal step-up circuit 1.
Pins to connect a capacitor when using the dual mode stepup1 circuit. Leave the pins open or connect to GND, when
not using the dual mode step-up1 circuit.
Pins to connect capacitors for the internal step-up circuit 2.
Connect capacitors according to step-up rate. Leave the pins
open when not using the circuit.
Power supply to generate the internal logic power supply.
Supply voltage to the analog circuit.
Connect to an external power supply of 2.5 to 3.3V.
Internal reference voltage level of amplitude VCI−GND.
Place a stabilizing capacitor between GND.
Reference voltage input to the step-up circuit 1.
When not using the internal reference voltage, connect to an
external power supply up to 2.75V.
10
LGDP4525
Name
Rev 0.9.0
I/O
AVDD
#
pins
1
VGH
1
I/O
Stabilizing
capacitor,
Schottky
diode
VGL
1
I/O
Stabilizing
capacitor,
Schottky
diode
VCL
1
I/O
Stabilizing
capacitor
GVDD
1
I/O
Stabilizing
capacitor,
variable
resistor
when
generating
VCOMR
VDD
1
-
RVDD
1
I/O
VDD3
1
-
Power
supply
Stabilizing
capacitor,
VDD
Power
supply
VSS, AVSS,
VSSC
VGS
1
-
1
VREF
1
I/O
VREF_BUF
1
I/O
M
1
-
CONTACT
DUMMY1~12
DUMMY13~37
2
1
1
-
I/O
Connected
to
Stabilizing
capacitor,
Schottky
diode
Power
supply
GND or
external
resistor
OPEN or
stabilizing
capacitor
OPEN or
stabilizing
capacitor
VDD3, GND
or OPEN
-
Function
Output voltage from the step-up circuit 1.
Place a stabilizing capacitor between GND.
Place a schottky diode between VGH.
AVDD = 4.5 to 5.5V (twice the VCI1 level).Power supply to
the source driver’s LCD output unit and an input voltage to
the step-up circuit 2.
An output voltage from the step-up circuit 2.
The step-up rate is set with the BT bits.
Place a stabilizing capacitor between GND.
Place a schottky diode between AVDD.
VGH = max 16.5V (4 to 6 times the VCI1 level)
A supply voltage to drive gate lines of the TFT panel.
An output voltage from the step-up circuit 2.
The step-up rate is set with the BT bits.
Place a stabilizing capacitor between GND.
Place a schottky diode between GND.
VGL = min −16.5V (−3 to −5 times the VCI1 level)
A supply voltage to drive gate lines of the TFT panel.
An output voltage from the step-up circuit 2.
Place a stabilizing capacitor between GND.
VCL = 0 to −3.3V (−1 times the VCI1 level)
A supply voltage to generate the VCOML level.
A voltage level of AVDD−GND, generated from the reference
level of VCI−GND according to the rate set with the VRH bits.
GVDD is (1) a source driver grayscale reference voltage
VDH, (2) a VCOMH level reference voltage, and (3) a VCOM
amplitude reference voltage. Connect to a stabilizing
capacitor.
GVDD = 3.0 to (AVDD – 0.5) V. When using a variable
resistor for VCOMH(VCOMR), place the resister between
GVDD and GND.
Generated power supply to the internal logic.
VDD = 1.7 to 1.9V
Internal logic regulator output.
Power supply to the interface pins: VDD3 = 1.65 to 3.3V.
VDD3 and the internal logic voltage VDD must be supplied in
the same condition. In case of COG, connect to VDD on the
FPC if VDD3 = VDD to prevent noise.
Circuit ground : GND = 0V.
Reference level for the grayscale voltage generation circuit.
The VGS level can be changed by connecting to an external
resistor.
Reference voltage pin for test.
Reference voltage pin for test.
Dummy pin.
Dummy pins.
Dummy pins.
Dummy pins.
11
LGDP4525
Rev 0.9.0
12
LGDP4525
Rev 0.9.0
PAD Arrangement
(1-a)
DUMMY1
DUMMY2
VCOM
VCOM
VCOM
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DUMMY37
DUMMY36
DUMMY35
DUMMY34
G<1>
G<3>
G<5>
G<7>
G<9>
G<11>
G<13>
988
987
986
985
984
983
982
981
980
979
978
1
2
3
4
5
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G<213>
G<215>
G<217>
G<219>
DUMMY33
DUMMY32
DUMMY31
DUMMY30
DUMMY29
DUMMY28
DUMMY27
DUMMY26
S<1>
S<2>
S<3>
S<4>
878
877
876
875
874
873
872
871
870
869
868
867
866
865
864
863
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LGDP 4525
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610
609
608
607
606
605
604
603
S<257>
S<258>
S<259>
S<260>
S<261>
S<262>
S<263>
S<264>
602
601
600
599
598
597
596
595
S<265>
S<266>
S<267>
S<268>
S<269>
S<270>
S<271>
S<272>
Top view
Y
X
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VCOM
VCOM
VCOM
DUMMY11
DUMMY12
342
341
340
339
338
337
336
335
334
333
332
331
330
329
328
327
326
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S<525>
S<526>
S<527>
S<528>
DUMMY25
DUMMY24
DUMMY23
DUMMY22
DUMMY21
DUMMY20
DUMMY19
DUMMY18
DUMMY17
G<220>
G<218>
G<216>
G<214>
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211
212
213
214
215
(1-b)
226
225
224
223
222
221
220
219
218
217
216
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
G<14>
G<12>
G<10>
G<8>
G<6>
G<4>
G<2>
DUMMY16
DUMMY15
DUMMY14
DUMMY13
13
LGDP4525
Rev 0.9.0
PAD Coordinate
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Pad name
DUMMY1
DUMMY2
VCOM
VCOM
VCOM
VCOM
DUMMY3
VGH
VGH
VGH
VGH
VGH
DUMMY4
VGL
VGL
VGL
VGL
VGL
DUMMY5
C22P
C22P
C22P
C22M
C22M
C22M
C21P
C21P
C21P
C21M
C21M
C21M
DUMMY6
DUMMY7
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
VSSC
VCI1
VCI1
VCI1
VCI1
VCI1
VCI1
C11P
C11P
C11P
C11P
C11P
C11P
C11P
C11P
C11M
C11M
C11M
C11M
C11M
C11M
C11M
C11M
C12P
C12P
C12P
C12P
C12P
C12P
C12M
C12M
C12M
C12M
C12M
C12M
C31P
C31P
C31P
C31P
C31P
C31M
X
-6695
-6635
-6575
-6515
-6455
-6395
-6335
-6275
-6215
-6155
-6095
-6035
-5975
-5915
-5855
-5795
-5735
-5675
-5615
-5555
-5495
-5435
-5375
-5315
-5255
-5195
-5135
-5075
-5015
-4955
-4895
-4835
-4775
-4715
-4655
-4595
-4535
-4475
-4415
-4355
-4295
-4235
-4175
-4115
-4055
-3995
-3935
-3875
-3815
-3755
-3695
-3635
-3575
-3515
-3455
-3395
-3335
-3275
-3215
-3155
-3095
-3035
-2975
-2915
-2855
-2795
-2735
-2675
-2615
-2555
-2495
-2435
-2375
-2315
-2255
-2195
-2135
-2075
-2015
-1955
-1895
-1835
-1775
Y
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
Pad #
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
Pad name
C31M
C31M
C31M
C31M
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCL
VCL
VCL
VCL
VCL
DUMMY8
RS
CSB
VSYNC
HSYNC
DOTCLK
ENABLE
RESETB
SDI
E_RDB
RW_WRB
DB<17>
DB<16>
DB<15>
DB<14>
DB<13>
DB<12>
DB<11>
DB<10>
DB<9>
DB<8>
DB<7>
DB<6>
DB<5>
DB<4>
DB<3>
DB<2>
DB<1>
DB<0>
IM<3>
IM<2>
IM<1>
IM<0>
SDO
M
FLM
CL1
RESETEN
TEST_MODE<1>
TEST_MODE<0>
TEST_MUX<2>
TEST_MUX<1>
VREF_BUF
TEST_DA
OSC2
OSC1
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VSS
X
-1715
-1655
-1595
-1535
-1475
-1415
-1355
-1295
-1235
-1175
-1115
-1055
-995
-935
-875
-815
-755
-695
-635
-575
-515
-455
-395
-335
-275
-215
-155
-95
-35
25
85
145
205
265
325
385
445
505
565
650
735
820
905
990
1075
1160
1245
1330
1415
1500
1585
1670
1755
1840
1925
2010
2095
2155
2215
2275
2335
2420
2505
2590
2675
2735
2795
2855
2915
2975
3035
3095
3155
3215
3275
3335
3395
3455
3515
3575
3635
3695
3755
Y
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
Pad #
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
Pad name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VGS
VGS
RVDD
RVDD
RVDD
RVDD
RVDD
RVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
DUMMY9
VREF
GVDD
GVDD
GVDD
GVDD
VCOMH
VCOMH
VCOML
VCOML
VCOMR
CONTACT
CONTACT
DUMMY10
VCOM
VCOM
VCOM
VCOM
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
G<2>
G<4>
G<6>
G<8>
G<10>
G<12>
G<14>
G<16>
G<18>
G<20>
G<22>
G<24>
G<26>
G<28>
G<30>
G<32>
G<34>
G<36>
G<38>
G<40>
G<42>
G<44>
G<46>
G<48>
G<50>
G<52>
G<54>
G<56>
G<58>
G<60>
X
3815
3875
3935
3995
4055
4115
4175
4235
4295
4355
4415
4475
4535
4595
4655
4715
4775
4835
4895
4955
5015
5075
5135
5195
5255
5315
5375
5435
5495
5555
5615
5675
5735
5795
5855
5915
5975
6035
6095
6155
6215
6275
6335
6395
6455
6515
6575
6635
6695
6772
6756
6740
6724
6708
6692
6676
6660
6644
6628
6612
6596
6580
6564
6548
6532
6516
6500
6484
6468
6452
6436
6420
6404
6388
6372
6356
6340
6324
6308
6292
6276
6260
6244
Y
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
-335
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
14
LGDP4525
Pad #
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
Pad name
G<62>
G<64>
G<66>
G<68>
G<70>
G<72>
G<74>
G<76>
G<78>
G<80>
G<82>
G<84>
G<86>
G<88>
G<90>
G<92>
G<94>
G<96>
G<98>
G<100>
G<102>
G<104>
G<106>
G<108>
G<110>
G<112>
G<114>
G<116>
G<118>
G<120>
G<122>
G<124>
G<126>
G<128>
G<130>
G<132>
G<134>
G<136>
G<138>
G<140>
G<142>
G<144>
G<146>
G<148>
G<150>
G<152>
G<154>
G<156>
G<158>
G<160>
G<162>
G<164>
G<166>
G<168>
G<170>
G<172>
G<174>
G<176>
G<178>
G<180>
G<182>
G<184>
G<186>
G<188>
G<190>
G<192>
G<194>
G<196>
G<198>
G<200>
G<202>
G<204>
G<206>
G<208>
G<210>
G<212>
G<214>
G<216>
G<218>
G<220>
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
DUMMY23
Rev 0.9.0
X
6228
6212
6196
6180
6164
6148
6132
6116
6100
6084
6068
6052
6036
6020
6004
5988
5972
5956
5940
5924
5908
5892
5876
5860
5844
5828
5812
5796
5780
5764
5748
5732
5716
5700
5684
5668
5652
5636
5620
5604
5588
5572
5556
5540
5524
5508
5492
5476
5460
5444
5428
5412
5396
5380
5364
5348
5332
5316
5300
5284
5268
5252
5236
5220
5204
5188
5172
5156
5140
5124
5108
5092
5076
5060
5044
5028
5012
4996
4980
4964
4948
4932
4916
4900
4884
4868
4852
Y
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
Pad #
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
Pad name
DUMMY24
DUMMY25
S<528>
S<527>
S<526>
S<525>
S<524>
S<523>
S<522>
S<521>
S<520>
S<519>
S<518>
S<517>
S<516>
S<515>
S<514>
S<513>
S<512>
S<511>
S<510>
S<509>
S<508>
S<507>
S<506>
S<505>
S<504>
S<503>
S<502>
S<501>
S<500>
S<499>
S<498>
S<497>
S<496>
S<495>
S<494>
S<493>
S<492>
S<491>
S<490>
S<489>
S<488>
S<487>
S<486>
S<485>
S<484>
S<483>
S<482>
S<481>
S<480>
S<479>
S<478>
S<477>
S<476>
S<475>
S<474>
S<473>
S<472>
S<471>
S<470>
S<469>
S<468>
S<467>
S<466>
S<465>
S<464>
S<463>
S<462>
S<461>
S<460>
S<459>
S<458>
S<457>
S<456>
S<455>
S<454>
S<453>
S<452>
S<451>
S<450>
S<449>
S<448>
S<447>
S<446>
S<445>
S<444>
X
4836
4820
4804
4788
4772
4756
4740
4724
4708
4692
4676
4660
4644
4628
4612
4596
4580
4564
4548
4532
4516
4500
4484
4468
4452
4436
4420
4404
4388
4372
4356
4340
4324
4308
4292
4276
4260
4244
4228
4212
4196
4180
4164
4148
4132
4116
4100
4084
4068
4052
4036
4020
4004
3988
3972
3956
3940
3924
3908
3892
3876
3860
3844
3828
3812
3796
3780
3764
3748
3732
3716
3700
3684
3668
3652
3636
3620
3604
3588
3572
3556
3540
3524
3508
3492
3476
3460
Y
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
Pad #
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
Pad name
S<443>
S<442>
S<441>
S<440>
S<439>
S<438>
S<437>
S<436>
S<435>
S<434>
S<433>
S<432>
S<431>
S<430>
S<429>
S<428>
S<427>
S<426>
S<425>
S<424>
S<423>
S<422>
S<421>
S<420>
S<419>
S<418>
S<417>
S<416>
S<415>
S<414>
S<413>
S<412>
S<411>
S<410>
S<409>
S<408>
S<407>
S<406>
S<405>
S<404>
S<403>
S<402>
S<401>
S<400>
S<399>
S<398>
S<397>
S<396>
S<395>
S<394>
S<393>
S<392>
S<391>
S<390>
S<389>
S<388>
S<387>
S<386>
S<385>
S<384>
S<383>
S<382>
S<381>
S<380>
S<379>
S<378>
S<377>
S<376>
S<375>
S<374>
S<373>
S<372>
S<371>
S<370>
S<369>
S<368>
S<367>
S<366>
S<365>
S<364>
S<363>
S<362>
S<361>
S<360>
S<359>
S<358>
S<357>
X
3444
3428
3412
3396
3380
3364
3348
3332
3316
3300
3284
3268
3252
3236
3220
3204
3188
3172
3156
3140
3124
3108
3092
3076
3060
3044
3028
3012
2996
2980
2964
2948
2932
2916
2900
2884
2868
2852
2836
2820
2804
2788
2772
2756
2740
2724
2708
2642
2626
2610
2594
2578
2562
2546
2530
2514
2498
2482
2466
2450
2434
2418
2402
2386
2370
2354
2338
2322
2306
2290
2274
2258
2242
2226
2210
2194
2178
2162
2146
2130
2114
2098
2082
2066
2050
2034
2018
Y
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
15
LGDP4525
Pad #
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
Pad name
S<356>
S<355>
S<354>
S<353>
S<352>
S<351>
S<350>
S<349>
S<348>
S<347>
S<346>
S<345>
S<344>
S<343>
S<342>
S<341>
S<340>
S<339>
S<338>
S<337>
S<336>
S<335>
S<334>
S<333>
S<332>
S<331>
S<330>
S<329>
S<328>
S<327>
S<326>
S<325>
S<324>
S<323>
S<322>
S<321>
S<320>
S<319>
S<318>
S<317>
S<316>
S<315>
S<314>
S<313>
S<312>
S<311>
S<310>
S<309>
S<308>
S<307>
S<306>
S<305>
S<304>
S<303>
S<302>
S<301>
S<300>
S<299>
S<298>
S<297>
S<296>
S<295>
S<294>
S<293>
S<292>
S<291>
S<290>
S<289>
S<288>
S<287>
S<286>
S<285>
S<284>
S<283>
S<282>
S<281>
S<280>
S<279>
S<278>
S<277>
S<276>
S<275>
S<274>
S<273>
S<272>
S<271>
S<270>
Rev 0.9.0
X
2002
1986
1970
1954
1938
1922
1906
1890
1874
1858
1842
1826
1810
1794
1778
1762
1746
1730
1714
1698
1682
1666
1650
1634
1618
1602
1586
1570
1554
1538
1522
1506
1490
1474
1458
1442
1426
1410
1394
1378
1362
1346
1330
1314
1298
1282
1266
1250
1234
1218
1202
1186
1170
1154
1138
1122
1106
1090
1074
1058
1042
1026
1010
994
978
962
946
930
914
898
882
866
850
834
818
802
786
770
754
738
722
706
690
674
658
642
626
Y
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
Pad #
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
Pad name
S<269>
S<268>
S<267>
S<266>
S<265>
S<264>
S<263>
S<262>
S<261>
S<260>
S<259>
S<258>
S<257>
S<256>
S<255>
S<254>
S<253>
S<252>
S<251>
S<250>
S<249>
S<248>
S<247>
S<246>
S<245>
S<244>
S<243>
S<242>
S<241>
S<240>
S<239>
S<238>
S<237>
S<236>
S<235>
S<234>
S<233>
S<232>
S<231>
S<230>
S<229>
S<228>
S<227>
S<226>
S<225>
S<224>
S<223>
S<222>
S<221>
S<220>
S<219>
S<218>
S<217>
S<216>
S<215>
S<214>
S<213>
S<212>
S<211>
S<210>
S<209>
S<208>
S<207>
S<206>
S<205>
S<204>
S<203>
S<202>
S<201>
S<200>
S<199>
S<198>
S<197>
S<196>
S<195>
S<194>
S<193>
S<192>
S<191>
S<190>
S<189>
S<188>
S<187>
S<186>
S<185>
S<184>
S<183>
X
610
594
578
562
546
-554
-570
-586
-602
-618
-634
-650
-666
-682
-698
-714
-730
-746
-762
-778
-794
-810
-826
-842
-858
-874
-890
-906
-922
-938
-954
-970
-986
-1002
-1018
-1034
-1050
-1066
-1082
-1098
-1114
-1130
-1146
-1162
-1178
-1194
-1210
-1226
-1242
-1258
-1274
-1290
-1306
-1322
-1338
-1354
-1370
-1386
-1402
-1418
-1434
-1450
-1466
-1482
-1498
-1514
-1530
-1546
-1562
-1578
-1594
-1610
-1626
-1642
-1658
-1674
-1690
-1706
-1722
-1738
-1754
-1770
-1786
-1802
-1818
-1834
-1850
Y
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
Pad #
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
Pad name
S<182>
S<181>
S<180>
S<179>
S<178>
S<177>
S<176>
S<175>
S<174>
S<173>
S<172>
S<171>
S<170>
S<169>
S<168>
S<167>
S<166>
S<165>
S<164>
S<163>
S<162>
S<161>
S<160>
S<159>
S<158>
S<157>
S<156>
S<155>
S<154>
S<153>
S<152>
S<151>
S<150>
S<149>
S<148>
S<147>
S<146>
S<145>
S<144>
S<143>
S<142>
S<141>
S<140>
S<139>
S<138>
S<137>
S<136>
S<135>
S<134>
S<133>
S<132>
S<131>
S<130>
S<129>
S<128>
S<127>
S<126>
S<125>
S<124>
S<123>
S<122>
S<121>
S<120>
S<119>
S<118>
S<117>
S<116>
S<115>
S<114>
S<113>
S<112>
S<111>
S<110>
S<109>
S<108>
S<107>
S<106>
S<105>
S<104>
S<103>
S<102>
S<101>
S<100>
S<99>
S<98>
S<97>
S<96>
X
-1866
-1882
-1898
-1914
-1930
-1946
-1962
-1978
-1994
-2010
-2026
-2042
-2058
-2074
-2090
-2106
-2122
-2138
-2154
-2170
-2186
-2202
-2218
-2234
-2250
-2266
-2282
-2298
-2314
-2330
-2346
-2362
-2378
-2394
-2410
-2426
-2442
-2458
-2474
-2490
-2506
-2522
-2538
-2554
-2570
-2586
-2602
-2618
-2634
-2650
-2716
-2732
-2748
-2764
-2780
-2796
-2812
-2828
-2844
-2860
-2876
-2892
-2908
-2924
-2940
-2956
-2972
-2988
-3004
-3020
-3036
-3052
-3068
-3084
-3100
-3116
-3132
-3148
-3164
-3180
-3196
-3212
-3228
-3244
-3260
-3276
-3292
Y
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
16
LGDP4525
Pad #
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
Pad name
S<95>
S<94>
S<93>
S<92>
S<91>
S<90>
S<89>
S<88>
S<87>
S<86>
S<85>
S<84>
S<83>
S<82>
S<81>
S<80>
S<79>
S<78>
S<77>
S<76>
S<75>
S<74>
S<73>
S<72>
S<71>
S<70>
S<69>
S<68>
S<67>
S<66>
S<65>
S<64>
S<63>
S<62>
S<61>
S<60>
S<59>
S<58>
S<57>
S<56>
S<55>
S<54>
S<53>
S<52>
S<51>
S<50>
S<49>
S<48>
S<47>
S<46>
S<45>
S<44>
S<43>
S<42>
S<41>
S<40>
S<39>
S<38>
S<37>
S<36>
S<35>
S<34>
S<33>
S<32>
S<31>
S<30>
S<29>
S<28>
S<27>
S<26>
S<25>
S<24>
S<23>
S<22>
S<21>
Rev 0.9.0
X
-3308
-3324
-3340
-3356
-3372
-3388
-3404
-3420
-3436
-3452
-3468
-3484
-3500
-3516
-3532
-3548
-3564
-3580
-3596
-3612
-3628
-3644
-3660
-3676
-3692
-3708
-3724
-3740
-3756
-3772
-3788
-3804
-3820
-3836
-3852
-3868
-3884
-3900
-3916
-3932
-3948
-3964
-3980
-3996
-4012
-4028
-4044
-4060
-4076
-4092
-4108
-4124
-4140
-4156
-4172
-4188
-4204
-4220
-4236
-4252
-4268
-4284
-4300
-4316
-4332
-4348
-4364
-4380
-4396
-4412
-4428
-4444
-4460
-4476
-4492
Y
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
Pad #
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
Pad name
S<20>
S<19>
S<18>
S<17>
S<16>
S<15>
S<14>
S<13>
S<12>
S<11>
S<10>
S<9>
S<8>
S<7>
S<6>
S<5>
S<4>
S<3>
S<2>
S<1>
DUMMY26
DUMMY27
DUMMY28
DUMMY29
DUMMY30
DUMMY31
DUMMY32
DUMMY33
G<219>
G<217>
G<215>
G<213>
G<211>
G<209>
G<207>
G<205>
G<203>
G<201>
G<199>
G<197>
G<195>
G<193>
G<191>
G<189>
G<187>
G<185>
G<183>
G<181>
G<179>
G<177>
G<175>
G<173>
G<171>
G<169>
G<167>
G<165>
G<163>
G<161>
G<159>
G<157>
G<155>
G<153>
G<151>
G<149>
G<147>
G<145>
G<143>
G<141>
G<139>
G<137>
G<135>
G<133>
G<131>
G<129>
G<127>
X
-4508
-4524
-4540
-4556
-4572
-4588
-4604
-4620
-4636
-4652
-4668
-4684
-4700
-4716
-4732
-4748
-4764
-4780
-4796
-4812
-4828
-4844
-4860
-4876
-4892
-4908
-4924
-4940
-4956
-4972
-4988
-5004
-5020
-5036
-5052
-5068
-5084
-5100
-5116
-5132
-5148
-5164
-5180
-5196
-5212
-5228
-5244
-5260
-5276
-5292
-5308
-5324
-5340
-5356
-5372
-5388
-5404
-5420
-5436
-5452
-5468
-5484
-5500
-5516
-5532
-5548
-5564
-5580
-5596
-5612
-5628
-5644
-5660
-5676
-5692
Y
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
Pad #
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
Pad name
G<125>
G<123>
G<121>
G<119>
G<117>
G<115>
G<113>
G<111>
G<109>
G<107>
G<105>
G<103>
G<101>
G<99>
G<97>
G<95>
G<93>
G<91>
G<89>
G<87>
G<85>
G<83>
G<81>
G<79>
G<77>
G<75>
G<73>
G<71>
G<69>
G<67>
G<65>
G<63>
G<61>
G<59>
G<57>
G<55>
G<53>
G<51>
G<49>
G<47>
G<45>
G<43>
G<41>
G<39>
G<37>
G<35>
G<33>
G<31>
G<29>
G<27>
G<25>
G<23>
G<21>
G<19>
G<17>
G<15>
G<13>
G<11>
G<9>
G<7>
G<5>
G<3>
G<1>
DUMMY34
DUMMY35
DUMMY36
DUMMY37
Alignment mark
(1-a)
(1-b)
X
-5708
-5724
-5740
-5756
-5772
-5788
-5804
-5820
-5836
-5852
-5868
-5884
-5900
-5916
-5932
-5948
-5964
-5980
-5996
-6012
-6028
-6044
-6060
-6076
-6092
-6108
-6124
-6140
-6156
-6172
-6188
-6204
-6220
-6236
-6252
-6268
-6284
-6300
-6316
-6332
-6348
-6364
-6380
-6396
-6412
-6428
-6444
-6460
-6476
-6492
-6508
-6524
-6540
-6556
-6572
-6588
-6604
-6620
-6636
-6652
-6668
-6684
-6700
-6716
-6732
-6748
-6764
X
-6827.5
6827.5
Y
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
151
304
Y
-297.5
-297.5
17
LGDP4525
Rev 0.9.0
Bump Arrangement
17
15
S1 – S528
G1 – G220
I/O pins
16
Bump size
= 2006 um2
56
16
Figure 2 Bump Arrangement
18
LGDP4525
Rev 0.9.0
Block Function
System Interface
The LGDP4525 supports 2-system high-speed interfaces: 80-system high-speed interfaces to
8-, 9-, 16-, 18-bit parallel ports and a Serial Peripheral Interface (SPI). The interface mode is
selected by setting the IM[3:0] pins.
The LGDP4525 has a 16-bit index register (IR); an 18-bit write-data register (WDR); and an 18bit read-data register (RDR). The IR is the register to store index information from control
registers and the internal GRAM. The WDR is the register to temporarily store data to be written
to control registers and the internal GRAM. The RDR is the register to temporarily store data
read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to
the WDR and then automatically written to the internal GRAM in internal operation. Data are
read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus
when the LGDP4525 read the first data from the internal GRAM. Valid data are read out after
the LGDP4525 performs the second read operation.
Instructions are written consecutively as the instruction execution time except starting oscillator
takes 0 clock cycle.
Table 3: Register Selection (80-system 8-/9-/16-/18-bit Parallel Interface)
80-system I/F
RW_WRB E_RDB
0
1
1
0
0
1
1
0
Function
RS
0
0
1
1
Write an index to IR
Read an internal status
Write to control registers or the internal GRAM via WDR
Read from the internal GRAM via RDR
Table 4: Register Selection (Serial Peripheral Interface)
Start Byte (SPI)
R/W
RS
0
0
1
0
0
1
1
1
Function
Write an index to IR
Read an internal status
Write into control registers and the internal GRAM via WDR
Read from the internal GRAM via RDR
External Display Interface
The LGDP4525 supports the RGB interface and the VSYNC interface as the external interface
for displaying a moving picture. When the RGB interface is selected, display operations are
synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface
mode, data (DB[17:0]) are written in synchronization with these signals according to the polarity
of enable signal (ENABLE) to prevent flicker on display while updating display data.
In VSYNC interface mode, the display operation is synchronized with the internal clock except
frame synchronization, where the operation is synchronized with the VSYNC signal. Display
data are written to the internal GRAM via the system interface. In this case, there are
constraints in speed and method in writing data to the internal RAM. For details, see the
“External Display Interface” section.
The LGDP4525 allows for switching between the external display interface and the system
interface by instruction so that the optimum interface is selected for the kind of picture to be
displayed on the screen (still and/or moving picture(s)). The RGB interface, by writing all display
data to the internal RAM, allows for transferring data only when updating the frames of a moving
picture, contributing to low power requirement for moving picture display.
19
LGDP4525
Rev 0.9.0
Bit Operations
The LGDP4525 supports a write data mask function for selectively writing data to the internal
RAM in units of bits and a logical/compare operation to write data to the GRAM only when a
condition is met as a result of comparing the data and the compare register bits.
Address Counter (AC)
The address counter (AC) gives an address to the internal GRAM. When the index of the
register for setting a RAM address in the AC is written to the IR, the address information is sent
from the IR to the AC. As writing data to the internal GRAM, the address in the AC is
automatically updated plus or minus 1. The window address function enables writing data only
in the rectangular area arbitrarily set by users on the GRAM.
Graphics RAM (GRAM)
GRAM is graphics RAM storing bit-pattern data of 87,120 (176 x 220 x 18/8) bytes, using 18
bits per pixel.
Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates a liquid crystal drive voltage according to
grayscale data set in the γ-correction register to display in 262,144 colors. For details, see the
“γ-Correction Function” section.
Timing Generator
The timing generator generates a timing signal for operation of internal circuits such as the
internal GRAM. The timing for the display operation such as RAM read operation and the timing
for the internal operation such as access from the MPU are generated in the way not to interfere
each other.
Oscillator (OSC)
The LGDP4525 generates RC oscillation with both an internal oscillator resistor(default) and an
external oscillation resistor optionally placed between the OSC1 and OSC2 pins. The oscillation
frequency is changed according to the value of FCNT bit of the register set or the value of an
external resistor. Adjust the oscillation frequency in accordance to the operating voltage or the
frame frequency. An operating clock can be input externally. During standby mode, RC
oscillation is halted to reduce power consumption. For details, see “Oscillator” section.
LCD Driver Circuit
The LCD driver circuit of the LGDP4525 consists of a 528-output source driver (S1 to S528) and
a 220-output gate driver (G1 to G220). Display pattern data are latched when the 528th bit data
are input. The latched data control the source driver and generate a drive waveform. The gate
driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 528-bit
source outputs from the source driver is set with the SS bit and the shift direction of gate
outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with
the SM bit. These bits allow setting an appropriate scan method for an LCD module.
LCD Drive Power Supply Circuit
The LCD drive power supply circuit generates the voltage levels GVDD, VGH, VGL and VCOM
for driving an LCD.
20
LGDP4525
Rev 0.9.0
GRAM Address MAP
S528
S527
…
S526
S525
S524
S523
…
S522
S521
…
S520
S519
…
S518
S517
…
S11
…
S10
…
S9
…
S8
…
S7
…
S6
…
S5
DB[17:0] DB[17:0] DB[17:0] DB[17:0]
00AC
00AD
00AE
00AF
01AC
01AD
01AE
01AF
02AC
02AD
02AE
02AF
03AC
03AD
03AE
03AF
04AC
04AD
04AE
04AF
05AC
05AD
05AE
05AF
06AC
06AD
06AE
06AF
07AC
07AD
07AE
07AF
08AC
08AD
08AE
08AF
09AC
09AD
09AE
09AF
0AAC
0AAD
0AAE
0AAF
0BAC
0BAD
0BAE
0BAF
0CAC
0CAD
0CAE
0CAF
0DAC
0DAD
0DAE
0DAF
0EAC
0EAD
0EAE
0EAF
0FAC
0FAD
0FAE
0FAF
10AC
10AD
10AE
10AF
11AC
11AD
11AE
11AF
12AC
12AD
12AE
12AF
13AC
13AD
13AE
13AF
S4
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
S3
GS=0 GS=1 DB[17:0] DB[17:0] DB[17:0] DB[17:0]
G1 G220 0000
0001
0002
0003
G2 G219 0100
0101
0102
0103
G3 G218 0200
0201
0202
0203
G4 G217 0300
0301
0302
0303
G5 G216 0400
0401
0402
0403
G6 G215 0500
0501
0502
0503
G7 G214 0600
0601
0602
0603
G8 G213 0700
0701
0702
0703
G9 G212 0800
0801
0802
0803
G10 G211 0900
0901
0902
0903
G11 G210 0A00
0A01
0A02
0A03
G12 G209 0B00
0B01
0B02
0B03
G13 G208 0C00
0C01
0C02
0C03
G14 G207 0D00
0D01
0D02
0D03
G15 G206 0E00
0E01
0E02
0E03
G16 G205 0F00
0F01
0F02
0F03
G17 G204 1000
1001
1002
1003
G18 G203 1100
1101
1102
1103
G19 G202 1200
1201
1202
1203
G20 G201 1300
1301
1302
1303
S2
…
S/G pin
S1
S12
Table 5: GRAM address and display panel position (SS = “0”, BGR = “0”)
G213
G214
G215
G217
G217
G218
G219
G220
G8
G7
G6
G5
G4
G3
G2
G1
D400
D500
D600
D700
D800
D900
DA00
DB00
D401
D501
D601
D701
D801
D901
DA01
DB01
D402
D502
D602
D702
D802
D902
DA02
DB02
D403
D503
D603
D703
D803
D903
DA03
DB03
…
…
…
…
…
…
…
…
D4AC
D5AC
D6AC
D7AC
D8AC
D9AC
DAAC
DBAC
D4AD
D5AD
D6AD
D7AD
D8AD
D9AD
DAAD
DBAD
D4AE
D5AE
D6AE
D7AE
D8AE
D9AE
DAAE
DBAE
D4AF
D5AF
D6AF
D7AF
D8AF
D9AF
DAAF
DBAF
21
LGDP4525
Rev 0.9.0
18-bit interface (262k colors)
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (65k colors) – TRI = “0”
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1 17 16
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
1
2 17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
Figure 3: GRAM data and display data: system interface (SS = “0”, BGR = “0”)
22
LGDP4525
Rev 0.9.0
9-bit interface (262k colors)
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
8-bit interface or SPI (2 transfers/pixel, 65k colors) – TRI = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
8-bit interface or SPI (3 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
8-bit interface (3 transfers/pixel, 65k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
Figure 4: GRAM data and display data: system interface (SS = “0”, BGR = “0”)
23
LGDP4525
Rev 0.9.0
18-bit RGB interface (262k colors)
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
16-bit RGB interface (65k colors)
GRAM data
DB DB DB DB DB
17 16 15 14 13
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
DB DB DB DB DB DB DB DB DB DB DB
11 10 9
8
7
6
5
4
3
2
1
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
6-bit RGB interface (262k colors)
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (3n + 1)
S (3n + 1)
S (3n + 1)
Note: n = lower eight bits of address (0 to 175)
Figure 5: GRAM data and display data: system interface (SS = “0”, BGR = “0”)
24
LGDP4525
Rev 0.9.0
S528
S527
…
S526
S525
S524
S523
…
S522
S521
…
S520
S519
…
S518
S517
…
S11
…
S10
…
S9
…
S8
…
S7
…
S6
…
S5
DB[17:0] DB[17:0] DB[17:0] DB[17:0]
0003
0002
0001
0000
0103
0102
0101
0100
0203
0202
0201
0200
0303
0302
0301
0300
0403
0402
0401
0400
0503
0502
0501
0500
0603
0602
0601
0600
0703
0702
0701
0700
0803
0802
0801
0800
0903
0902
0901
0900
0A03
0A02
0A01
0A00
0B03
0B02
0B01
0B00
0C03
0C02
0C01
0C00
0D03
0D02
0D01
0D00
0E03
0E02
0E01
0E00
0F03
0F02
0F01
0F00
1003
1002
1001
1000
1103
1102
1101
1100
1203
1202
1201
1200
1303
1302
1301
1300
S4
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
…
S3
GS=0 GS=1 DB[17:0] DB[17:0] DB[17:0] DB[17:0]
G1 G220 00AF
00AE
00AD
00AC
G2 G219 01AF
01AE
01AD
01AC
G3 G218 02AF
02AE
02AD
02AC
G4 G217 03AF
03AE
03AD
03AC
G5 G216 04AF
04AE
04AD
04AC
G6 G215 05AF
05AE
05AD
05AC
G7 G214 06AF
06AE
06AD
06AC
G8 G213 07AF
07AE
07AD
07AC
G9 G212 08AF
08AE
08AD
08AC
G10 G211 09AF
09AE
09AD
09AC
G11 G210 0AAF
0AAE
0AAD
0AAC
G12 G209 0BAF
0BAE
0BAD
0BAC
G13 G208 0CAF
0CAE
0CAD
0CAC
G14 G207 0DAF
0DAE
0DAD
0DAC
G15 G206 0EAF
0EAE
0EAD
0EAC
G16 G205 0FAF
0FAE
0FAD
0FAC
G17 G204 10AF
10AE
10AD
10AC
G18 G203 11AF
11AE
11AD
11AC
G19 G202 12AF
12AE
12AD
12AC
G20 G201 13AF
13AE
13AD
13AC
S2
…
S/G pin
S1
S12
Table 6: GRAM address and display panel position (SS = “1”, BGR = “1”)
G213
G214
G215
G217
G217
G218
G219
G220
G8
G7
G6
G5
G4
G3
G2
G1
D4AF
D5AF
D6AF
D7AF
D8AF
D9AF
DAAF
DBAF
D4AE
D5AE
D6AE
D7AE
D8AE
D9AE
DAAE
DBAE
D4AD
D5AD
D6AD
D7AD
D8AD
D9AD
DAAD
DBAD
D4AC
D5AC
D6AC
D7AC
D8AC
D9AC
DAAC
DBAC
…
…
…
…
…
…
…
…
D403
D503
D603
D703
D803
D903
DA03
DB03
D402
D502
D602
D702
D802
D902
DA02
DB02
D401
D501
D601
D701
D801
D901
DA01
DB01
D400
D500
D600
D700
D800
D900
DA00
DB00
25
LGDP4525
Rev 0.9.0
18-bit interface (262k colors)
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (65k colors) – TRI = “0”
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1 17 16
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
1
2 17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
Figure 6: GRAM data and display data: system interface (SS = “1”, BGR = “1”)
26
LGDP4525
Rev 0.9.0
9-bit interface (262k colors)
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
8-bit interface or SPI (2 transfers/pixel, 65k colors) – TRI = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
8-bit interface or SPI (3 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 8-bit interface (3 transfers/pixel, 65k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
Figure 7: GRAM data and display data: system interface (SS = “1”, BGR = “1”)
27
LGDP4525
Rev 0.9.0
18-bit RGB interface (262k colors)
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
16-bit RGB interface (65k colors)
GRAM data
DB DB DB DB DB
17 16 15 14 13
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
DB DB DB DB DB DB DB DB DB DB DB
11 10 9
8
7
6
5
4
3
2
1
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
6-bit RGB interface (262k colors)
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output pin
S (528 – 3n)
S (527 – 3n)
S (526 – 3n)
Note: n = lower eight bits of address (0 to 175)
Figure 8: GRAM data and display data: system interface (SS = “1”, BGR = “1”)
28
LGDP4525
Rev 0.9.0
Instructions
Outline
The LGDP4525 adopts 18-bit bus architecture to interface to a high-performance
microcomputer. The LGDP4525 starts internal processing after storing control information of
externally sent 18-, 16-, 9-, 8-bit data in the instruction register IR and the data register DR.
Since internal operations of the LGDP4525 are controlled by the signals sent from the
microcomputer, the register selection signal RS, the read/write signal R/W, and the internal 16bit data bus signals IB[15:0] are called instructions. The LGDP4525 use the 18-bit format
internally for operations involving internal GRAM access. The instructions of the LGDP4525 are
categorized into the following groups.
1.
2.
3.
4.
5.
6.
7.
8.
Specify the index of register
Read a status
Display control
Power management Control
Graphics data processing
Set internal GRAM address
Transfer data to and from the internal GRAM
γ-correction
Normally, the instruction for writing data to the internal GRAM is used the most often. Since the
LGDP4525 can update internal GRAM address automatically as it writes data to the internal
GRAM and minimize data transfer by using the window address function, there is less load on
the program in the microcomputer. Since instructions are executed in 0 cycles, it is possible to
write instructions consecutively.
As the following figure shows, the way of assigning data to the 16 instruction bits IB[15:0] varies
for each interface. Send instructions in accordance with the following data transfer format.
29
LGDP4525
Rev 0.9.0
18-bit interface
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Instruction bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
16-bit interface
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
Instruction bit
(IB)
IB
15
IB
7
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
9-bit interface
2nd transfer
1st transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
8-bit interface or SPI (2/3 transfers)
1st transfer
IB
4
IB
3
IB
2
IB
1
IB
0
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
Instruction bit
(IB)
IB
15
IB
7
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
Figure 9: Instruction bits
30
LGDP4525
Rev 0.9.0
Explanation of each instruction
The following are detailed explanations of instructions with illustrations of instruction bits
IB[15:0] assigned to each interface.
Index (IR)
R/W
RS
W
0
IB15 IB14 IB13 IB12 IB11 IB10
*
*
*
*
*
*
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
*
*
*
ID6
ID5
ID4
ID3
ID2
ID1
ID0
The index register specifies the index (R00h to RFFh) of a control register or RAM control to be
accessed using binary numbers “000_0000” to “111_1111”. An access to the register as well as
instruction bits contained in it is prohibited unless its index is represented in this register.
Status Read (SR)
R/W
RS
R
0
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
L[7:0]
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
0
0
0
0
0
0
The SR bits represent an internal status of the LGDP4525.
L[7:0] – Indicates the position of the line that is currently driving liquid crystal.
ID CODE (R00h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
W
1
*
*
*
*
*
R
1
0
1
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
*
*
*
*
*
*
*
*
*
*
*
1
0
1
0
0
1
0
0
1
0
1
The start oscillation instruction restarts an oscillator in halt state in standby mode. After
executing this instruction, wait at least 10 ms for stabilizing oscillator before issuing a next
instruction.
The device code 4525 is read out when reading out this register forcibly.
Driver Output Control (R01h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
VSPL HSPL DPL EPL
SM
IB9
IB8
IB7
IB6
IB5
GS
SS
0
0
0
IB4
IB3
IB2
IB1
IB0
NL[4:0]
SS – Selects the shift direction of outputs from the source pins.
If SS = “0”, the source pins output from S1 to S528.
If SS = “1”, the source pins output from S528 to S1.
The combination of SS and BGR bits controls the order of assigning RGB dots to the source
driver pins S1 to S528.
If SS = “0” and BGR = “0”, RGB dots are assigned interchangeably from S1 to S528.
If SS = “1” and BGR = “1”, RGB dots are assigned interchangeably from S528 to S1.
When changing SS or BGR bits, RAM data must be rewritten.
GS – Sets the shift direction of outputs from the gate driver. GS enables setting the scan order
in accordance to the scan mode adopted in the module.
SM – Sets the scan order by the gate driver. SM enables setting the scan order in accordance
to the scan mode adopted in the module. See “Scan Mode Setting” section for details.
EPL – Sets the polarity of the signal from the ENABLE pin in RGB interface mode.
If EPL = “0”, ENABLE is low active.
If EPL = “1”, ENABLE is high active.
31
LGDP4525
Rev 0.9.0
The following table shows the relationship between the EPL, ENABLE bits, and RAM access.
Table 7
EPL
0
0
1
1
ENABLE
0
1
0
1
RAM write
Enabled
Inhibited
Inhibited
Enabled
RAM address
Updated
Retained
Retained
Updated
VSPL – Inverts the polarity of signals from the VSYNC pin.
If VSPL = “0”, VSYNC is low active.
If VSPL = “1”, VSYNC is high active.
HSPL – Inverts the polarity of signals from the HSYNC pin.
If HSPL = “0”, HSYNC is low active.
If HSPL = “1”, HSYNC is high active.
DPL – Inverts the polarity of signals from the DOTCLK pin.
If DPL = “0”, data are read on the rising edge of the DOTCLK.
If DPL = “1”, data are read on the falling edge of the DOTCLK.
NL[4:0] – Sets the number of gate lines for driving a liquid crystal display panel at an interval of
8 lines as the following table. The GRAM address mapping is independent from the number of
gate lines set with the NL bits. Select the number of gate lines that is equal to or more than that
of the panel in use.
Table 8
NL[4:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
Display size
Setting disabled
528 x 16 dots
528 x 24 dots
528 x 32 dots
528 x 40 dots
528 x 48 dots
528 x 56 dots
528 x 64 dots
528 x 72 dots
528 x 80 dots
528 x 88 dots
528 x 96 dots
528 x 104 dots
528 x 112 dots
528 x 120 dots
528 x 128 dots
528 x 136 dots
528 x 144 dots
528 x 152 dots
528 x 160 dots
528 x 168 dots
528 x 176 dots
528 x 184 dots
528 x 192 dots
528 x 200 dots
528 x 208 dots
528 x 216 dots
528 x 220 dots
Lines
Driven gate lines
16
24
32
40
48
56
64
72
80
88
96
104
112
120
128
136
144
152
160
168
176
184
192
200
208
216
220
G1 to G16
G1 to G24
G1 to G32
G1 to G40
G1 to G48
G1 to G56
G1 to G64
G1 to G72
G1 to G80
G1 to G88
G1 to G96
G1 to G104
G1 to G112
G1 to G120
G1 to G128
G1 to G136
G1 to G144
G1 to G152
G1 to G160
G1 to G168
G1 to G176
G1 to G184
G1 to G192
G1 to G200
G1 to G208
G1 to G216
G1 to G220
32
LGDP4525
Rev 0.9.0
LCD Driving Waveform Control (R02h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
FLD[1:0]
IB9
IB8
B/C EOR
IB7
IB6
0
0
IB5
IB4
IB3
IB2
IB1
IB0
NW[5:0]
NW[5:0] – Specifies “n”, the number of gate lines from 1 to 64, to set the interval of inverting
polarity when the LGDP4525 is set to generate a C-pattern waveform (B/C = “1”). The polarity is
inverted at an interval of n+1 gate lines.
EOR – When EOR = “1”, the polarity is inverted according to the result of EOR (exclusive OR)
operation, which is performed on a signal for selecting either odd or even frames and a signal
for inverting polarity in units of n lines when the LGDP4525 is set to generate a C-pattern
waveform (B/C = “1”). This instruction is used when the number of gate lines for driving an LCD
panel is at odds with the interval of n lines set for inverting polarity. For details, see “n-Line
Inversion AC Drive” section.
B/C – When the LGDP4525 is set to generate a field-inversion waveform (B/C = “0”), polarity is
inverted at an interval of fields. The LGDP4525 inverts polarity at an interval of n lines, when a
C-pattern waveform is generated (B/C = “1”) according to NW and EOR bits. For details, see “nLine Inversion AC Drive”.
FLD[1:0] – Sets the number of fields for n-field interlaced scan. See “Interlaced Scan” for details.
The FLD bits are disabled in external display interface mode. When using the external display
interface, set FLD[1:0] = “01”.
Table 9
FLD
00
01
10
11
Number of fields
Setting disabled
1 field (= 1 frame)
Setting disabled
3 fields
Entry Mode (R03h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
TRI
DFM
0
BGR
0
0
IB9
IB8
IB7
IB6
0
0
0
0
IB5
IB4
I/D[1:0]
IB3
IB2
IB1
IB0
AM
0
0
0
The LGDP4525 modifies data sent from a microcomputer before writing them to the internal
GRAM in order to write the GRAM data in high speed and reduce software processing load on
the microcomputer.
TRI – When TRI = “1”, data are transferred to the internal RAM in 8-bit x 3 transfers mode via
the 8-bit interface. It is also possible to send data via the 16-bit interface or SPI in the transfer
mode that realizes display in 262k colors in combination with DFM bits. When not using these
interface modes, be sure to set TRI to “0”.
DFM – Sets the mode of transferring data to the internal RAM when TRI = “1”. See the following
figures for details.
33
LGDP4525
Rev 0.9.0
Table 10
TRI
0
DFM
*
RAM write data transfer via serial peripheral interface (SPI)
SPI (2 transfers/pixel) – 65k colors available
1st transfer
GRAM
D15 D14 D13 D12 D11 D10 D9
data
RGB
assign
1
0
R5
R4
R3
R2
R1
R0
G5
2nd transfer
D8
G4
G3
D7
D6
D5
D4
D3
D2
D1
D0
G2
G1
G0
B5
B4
B3
B2
B1
B0
SPI (3 transfers/pixel) – 262k colors available
1st transfer
2nd transfer
GRAM
D23 D22 D21 D20 D19 D18 D15 D14 D13 D12 D11 D10 D7
data
RGB
assign
1
1
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
3rd transfer
D6
D5
D4
D3
D2
B4
B0
G1
G0
B5
B3
B2
B1
DB
17
DB
16
DB
15
2nd transfer
DB DB DB
14 13 12
DB
11
DB
10
G2
G1
G0
B5
B4
B2
B1
B0
2nd transfer
DB DB DB
15 14 13
DB
12
DB
17
DB
16
3rd transfer
DB DB DB
15 14 13
DB
12
G1
G0
B5
B4
2nd transfer
DB DB DB
15 14 13
DB
12
DB
17
DB
16
G0
B5
B4
Setting disabled
Table 11
TRI
0
1
1
DFM
*
0
1
RAM write data transfer via 8-bit interface
8-bit interface (2 transfers/pixel) – 65k colors available
GRAM
data
DB
17
DB
16
DB
15
1st transfer
DB DB DB
14 13 12
DB
11
DB
10
RGB
assign
R5
R4
R3
R2
G5
G4
R1
R0
G3
B3
8-bit interface (3 transfers/pixel) – 262k colors available
GRAM
data
DB
17
DB
16
RGB
assign
R5
R4
1st transfer
DB DB DB
15 14 13
R3
R2
R1
DB
12
DB
17
DB
16
R0
G5
G4
G3
G2
B3
B2
B1
B0
3rd transfer
DB DB DB
15 14 13
DB
12
8-bit interface (3 transfers/pixel) – 65k colors available
GRAM
data
DB
17
DB
16
RGB
assign
R5
R4
1st transfer
DB DB DB
15 14 13
DB
12
DB
17
DB
16
R1
R0
G5
G4
R3
R2
G3
G2
G1
B3
B2
B1
B0
34
LGDP4525
Rev 0.9.0
Table 12
TRI
0
1
1
DFM
*
0
1
RAM write data transfer via 16-bit interface
16-bit interface (1 transfers/pixel) – 65k colors available
GRAM
data
DB
17
DB
16
DB
15
1st transfer
DB DB DB
14 13 12
DB
11
DB
10
RGB
assign
R5
R4
R3
R2
G5
G4
R1
R0
G3
DB
8
DB
7
DB
6
2nd transfer
DB DB DB
5
4
3
DB
2
DB
1
G2
G1
G0
B5
B4
B3
B2
B1
B0
16-bit interface MSB mode (2 transfers/pixel) – 262k colors available
GRAM
data
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
RGB
assign
R5
R4
R3
R2
R1
R0
G5
1st transfer
DB DB DB
10
8
7
G4
G3
G2
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
2nd
DB DB
17 16
G1
G0
B5
B4
B3
B2
B1
B0
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
B5
B4
B3
B2
B1
B0
16-bit interface LSB mode (2 transfers/pixel) – 262k colors available
GRAM
data
RGB
assign
1st
DB DB
2
1
DB
17
DB
16
DB
15
DB
14
DB
13
DB
12
DB
11
R5
R3
R2
R1
R0
G5
G4
G3
R4
2nd transfer
DB DB DB
10
8
7
G2
G1
G0
BGR – Reverses the order of RGB dots to BGR when writing 18-bit pixel data to the internal
GRAM. Note that the orders of RGB dots in both WM[17:0] and CP[17:0] bits are automatically
changed upon setting BGR to “1”.
I/D[1:0] – The address counter is automatically incremented by 1 as writing data to the internal
GRAM when I/D = “1”. The address counter is automatically decremented by 1 as writing data
to the internal GRAM when I/D = “0”. The increment/decrement can be set separately to each
upper (AD[15:8]) / lower (AD[7:0]) byte of address. The transition direction of address
(vertical/horizontal) when writing data to the internal GRAM is set with the AM bit.
AM – Sets the direction of automatically updating address for writing data to the internal RAM in
the address counter (AC). When AM = “0”, the address is updated in horizontal writing direction.
When AM = “1”, the address is updated in vertical writing direction. When a window address
area is set, data are written only to the GRAM area specified with window address in the writing
direction set with I/D[1:0] and AM bits.
35
LGDP4525
Rev 0.9.0
Table 13: Address transition directions
I/D[1:0] = “00”
Horizontal
decrement
Vertical decrement
AM = “0”
Horizontal
0000h
AM = “1”
Vertical
0000h
I/D[1:0] = “01”
Horizontal
increment
Vertical decrement
I/D[1:0] = “10”
Horizontal
decrement
Vertical increment
0000h
EFAFh
0000h
EFAFh
0000h
EFAFh
0000h
EFAFh
I/D[1:0] = “11”
Horizontal
increment
Vertical increment
EFAFh
0000h
EFAFh
0000h
EFAFh
EFAFh
Resize Control (R04h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
RCV[1:0]
IB7
IB6
0
0
IB5
IB4
RCH[1:0]
IB3
IB2
0
0
IB1
IB0
RSZ[1:0]
RSZ[1:0] – Sets the resizing factor. When the RSZ bits are set for resizing, the LGDP4525
writes the data of the resized image in both horizontal and vertical directions according to the
resizing factor on the internal GRAM.
RCH[1:0] – Sets the number of pixels made as the remainder in horizontal direction as a result
of resizing a picture. By specifying the number of remainder pixels with RCH bits, the data can
be transferred without taking the reminder pixels into consideration. Make sure that RCH = 2’h0
when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels.
RCV[1:0] – Sets the number of pixels made as the remainder in vertical direction as a result of
resizing a picture. By specifying the number of remainder pixels with the RCV bits, the data can
be transferred without taking the reminder pixels into consideration. Make sure that RCV = 2’h0
when not using the resizing function (RSZ = 2’h0) or there are no remainder pixels.
Table 14: Resizing scale
RSZ[1:0]
00
01
10
11
Resizing scale
No resizing (x 1)
x 1/2
Setting disabled
x 1/4
Table 15: Surplus pixels in horizontal/vertical directions
RCH[1:0]/RCV[1:0]
00
01
10
11
Surplus pixels
0 pixel
1 pixel
2 pixels
3 pixels
Display Control 1 (R07h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
PTS[2:0]
IB9
IB8
IB7
IB6
VLE[1:0]
SPT
0
0
IB5
IB4
IB3
IB2
GON DTE
CL
REV
IB1
IB0
D[1:0]
PTS[2:0] – Sets the kind of source output in non-display area in partial display mode. For
details, see the “Partial Display Function” section.
36
LGDP4525
Rev 0.9.0
Table 16
PTS
Source output in non-display area
Positive polarity
Negative polarity
000
001
010
011
100
101
110
111
V63
Setting disabled
GND
High impedance
V63
Setting disabled
GND
High impedance
V0
Setting disabled
GND
High impedance
V0
Setting disabled
GND
High impedance
Operating grayscale
amplifier
in non-display area
V0 to V63
V0 to V63
V0 to V63
V0, V63
V0, V63
V0, V63
VLE[1:0] – When VLE[0] = “1”, the first display is scrolled up in vertical direction. When VLE[1]
= “1”, the second display is scrolled up in vertical direction. The first and second displays cannot
be scrolled simultaneously. This function is not available with the external display interface. In
this case, set VLE to “00”.
Table 17
VLE
00
01
10
11
2nd display image
Fixed
Fixed
Scroll up
Setting disabled
1st display image
Fixed
Scroll up
Fixed
SPT – When SPT = “1”, the LCD is driven in 2 split screens. For details, see the “Partial Display
Function” section. This function is not available with the external display interface. In this case,
set SPT to “0”.
GON, DTE – Sets the output level of gate lines G1 to G220 as follows.
Table 18
GON
0
0
1
1
DTE
0
1
0
1
Gate output G1 to G220
VGH
VGH
VGL
VGH/VGL
CL – When CL = “1”, the 8-color display mode is selected. For details, see the “8-Color Display
Mode” section. The 8-color display mode is not available in external interface mode.
REV – By setting REV = “1”, the grayscale levels can be inverted. This means, the REV bit
allows both normally black and normally white panels to display a same image from the same
data. The source output level during front and back porch periods and a blank period in partial
display mode is set with the PTS bits.
37
LGDP4525
Rev 0.9.0
…
1
3Fh
00h
V0
V0
V63
V63
…
…
Source output in display area
Positive polarity Negative polarity
V63
V0
…
REV
…
0
GRAM data
(RGB each)
00h
…
Table 19
3Fh
V63
V0
D[1:0] – A graphics display appears on the screen when D[1] = “1”, and is turned off upon
setting D[1] = “0”. When setting D[1] = “0”, the graphics display data are retained in the internal
GRAM and the display appears instantly on the screen upon setting D[1] to “1”. When the D[1]
bit is “0”, i.e. while no display is shown on the screen, all source outputs are at the GND level to
reduce charging/discharging current on liquid crystal cells, which is generated during liquid
crystal AC drive.
Upon setting D = “00”, the display is turned off and internal display operations are halted
completely.In combination with the GON, DTE bit, the D[1:0] bits controls ON/OFF of graphics
display. For details, see the flowcharts in the “Instruction Setting” section.
Table 20
D[1:0]
00
01
10
11
Source and VCOM outputs
GND
GND
Non-lit display
Display
IC internal operation
Halt
Operate
Operate
Operate
Notes:
1. Data write operations from the microcomputer are performed irrespective of the D[1:0]
bits.
2. When D[1:0] = “00”, the LGDP4525 is in the same state as the standby mode. However,
this does not mean the D[1:0] bits are written over to “00” upon setting the standby
mode.
Display Control 2 (R08h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
FP[7:0]
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
BP[7:0]
FP[7:0]/BP[7:0] – Sets the blank period made at the beginning and the end of a display (front
porch and back porch, respectively). The FP[3:0] and BP[3:0] bits specify the number of lines
for the front and back porch periods, respectively. In setting, be sure:
BP + FP ≤ 16 lines
FP ≥ 2 lines
BP ≥ 2 lines
In external display interface mode, a back porch (BP) period starts on the falling edge of the
VSYNC signal, followed by a display operation period. After driving the number of lines set with
NL bits, a front porch period starts. After the front porch period, a blank period continues until
the next input of VSYNC signal.
38
LGDP4525
Rev 0.9.0
Table 21
FP/BP
0
1
2
3
4
5
6
7
Number of lines for the front/back porches
Setting disabled
Setting disabled
2 lines
3 lines
4 lines
5 lines
6 lines
7 lines
15
15 lines
253
254
255
253 lines
254 lines
255 lines
VSYNC
Back porch
Display area
Front porch
Note: The output timing to the LCD is delayed by a 2-line period from the input of synchronizing signal.
Figure 10: Back/front porches
Set the BP[7:0], FP[7:0] bits as follows in each operation mode.
Table 22
Internal clock
operation
RGB interface
VSYNC interface
FLD[1:0] = “01”
FLD[1:0] = “11”
BP ≥ 2 lines
BP = 3 lines
BP ≥ 2 lines
BP ≥ 2 lines
FP ≥ 2 lines
FP = 5 lines
FP ≥ 2 lines
FP ≥ 2 lines
FP + BP ≤ 16 lines
FP + BP ≤ 16 lines
FP + BP = 16 lines
Display Control 3 (R09h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
IB7
IB6
0
0
0
0
IB5
IB4
PTG[1:0]
IB3
IB2
IB1
IB0
ISC[3:0]
PTG[1:0] – Sets the scan mode by the gate driver in non-display area.
39
LGDP4525
Rev 0.9.0
Table 23
PTG
00
01
10
11
Gate outputs in non-display area
Normal scan
VGL (fixed)
Interval scan
Setting disabled
ISC[3:0] – Sets the scan cycle by the gate driver when the PTG bits are set to the interval scan
mode in non-display area. The scan cycle can be set as (2 * ISC + 1) frames, where ISC is from
1 to 15. In this case, polarity is inverted as gate lines are scanned.
Frame Cycle Control (R0Bh)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
NO[1:0]
SDT[1:0]
EQ[1:0]
IB9
IB8
DIV[1:0]
IB7
IB6
IB5
0
IB4
IB3
IB2
RTN[6:1]
IB1
IB0
0
RTN[6:0] - Sets the 1H (1 line) period in internal oscillator cycles. RTN[6:0] should be greater
than or equal to 44 (= 2Ch).
Table 24
RTN[6:0]
2Ch
2Eh
30h
….
7Ah
7Ch
7Eh
Clock cycles per line
44
46
48
….
122
124
126
DIV[1:0] – The internal operation is synchronized with the clock, which is divided with the
division ratio set with the DIV bits. Set the RTN and DIV bits to adjust frame frequency. If the
number of lines for driving liquid crystal is changed, the frame frequency must also be adjusted.
See “Frame Frequency Adjustment Function”. In RGB interface mode, the DIV bits are disabled.
Table 25
DIV
0
1
2
3
Division ratio
1
2
4
8
Internal operation clock frequency
fosc/1
fosc/2
fosc/4
fosc/8
Note: fosc = Frequency of RC oscillation
Formula to calculate frame frequency
Frame frequency =
Fosc
(Clock cycles per line * Division ratio * (Active line + BP + FP))
Where,
fosc = frequency of RC oscillation,
Active line = number of active lines for driving liquid crystal (NL bits),
Division ratio = DIV bits,
Clock cycles per line = RTN bits,
FP = the number of lines for the front porch period and
BP = the number of lines for the back porch period.
EQ[1:0] – Sets the equalization. Recommend that EQ[1:0] sets 11.
SDT[1:0] – Sets the source output delay from the falling edge of gate output.
40
LGDP4525
Rev 0.9.0
Table 26
SDT[1:0]
0
1
2
3
Source output delay
Internal operation (internal oscillator)
2 clocks
4 clocks
6 clocks
8 clocks
RGB I/F operation (DOTCLK)
8 clocks
16 clocks
24 clocks
32 clocks
NO[1:0] – Sets the non-overlap period of outputs from adjacent gate lines.
Table 27
NO[1:0]
0
1
2
3
Gate output non-overlap period
Internal operation (internal oscillator)
0 clocks
8 clocks
12 clocks
16 clocks
RGB I/F operation (DOTCLK)
0 clocks
32 clocks
48 clocks
64 clocks
Note that the clock mentioned in the above description refers to different clocks according to the
interface mode in use as follows.
Table 28
Interface mode in use
Internal operation mode
RGB interface mode
VSYNC interface mode
Reference clock
Internal oscillator
DOTCLK
Internal oscillator
External Display Interface Control 1 (R0Ch)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
IB7
IB6
0
RM
0
0
IB5
IB4
DM[1:0]
IB3
IB2
0
0
IB1
IB0
RIM[1:0]
RM – Selects the interface to access the LGDP4525’s internal GRAM. The RAM access is
possible only via the interface selected with the RM bit. Set RM to “1” when writing display data
via the RGB interface. The LGDP4525 allows for setting the RM bit not constrained by the mode
used for the display operation. This means it is possible to rewrite display data via a system
interface by setting RM = “0” even while display operations are performed via the RGB interface.
Table 29: RM bit
RM
0
1
Interface for RAM access
System interface/VSYNC interface
RGB interface
RIM[1:0] – Selects one of the following RGB interface modes when the RGB interface mode is
selected with the RM and DM bits. Make this setting before display operation via external
display interface. Do not make changes to the setting during display operation.
Table 30: RIM[1:0] bits
RIM
0
1
2
3
RGB interface mode
18-bit RGB interface (1 transfer/pixel)
16-bit RGB interface (1 transfer/pixel)
6-bit RGB interface (3 transfers/pixel)
Setting disabled
DM[1:0] – Sets the display operation mode. By setting DM[1:0] as follows, it is possible to
switch between the internal clock operation mode and the external display interface mode. Do
not switch between different external interface modes (RGB interface and VSYNC interface).
41
LGDP4525
Rev 0.9.0
Table 31: DM[1:0] bits
DM
0
1
2
3
Display operation mode
Internal clock operation
RGB interface
VSYNC interface
Setting disabled
Notes:
1. Instructions are set only via the system interface.
2. Be sure that data transfer and dot clock input are performed in units of RGB dots in 6-bit
RGB interface mode.
As the following table, the optimum interface for the state of display can be selected by setting
the external display interface mode.
Table 32
Display State
Still pictures
Moving pictures
Rewrite still picture area while
display moving pictures
Moving pictures
Operation mode
Internal clock
operation
RGB interface (1)
RGB interface (2)
VSYNC interface
RAM access (RM)
System interface
(RM = 0)
RGB interface
(RM = 1)
RGB interface
(RM = 0)
System interface
(RM = 0)
Display mode (DM)
Internal clock operation
(DM = 00)
RGB interface
(DM = 01)
RGB interface
(DM = 01)
VSYNC interface
(DM = 10)
Notes:
1. Instructions are set only via the system interface.
2. The RGB-I/F and the VSYNC-I/F are not used simultaneously.
3. Do not make changes to the RGB-I/F mode setting (RIM) while the RGB I/F is in
operation.
4. See the “External Display Interface” section for the flowcharts to follow when switching
from one mode to another.
Internal clock operation mode
All display operations are synchronized with the signals generated from the internal operating
clock in this mode. None of inputs via the external display interface are valid. The internal RAM
is accessible only via the system interface.
RGB interface mode (1)
In RGB interface mode, display operations are synchronized with the frame synchronizing
signal (VSYNC), the line synchronizing signal (HSYNC), and the dot clock (DOTCLK). These
signals must be supplied through a display period using the RGB interface.
Display data are transferred in units of pixels via the DB[17:0] pins. All display data are stored in
the internal RAM. The combined use of the high-speed RAM write mode and the widow address
function enables not only displaying data in moving picture area and data in the internal RAM in
other than the moving picture area at a time but also minimizing data transfer by transferring
data only when rewriting screen.
The front porch (FP) and back porch (BP) periods, and the display duration period (NL) are
automatically calculated inside the LGDP4525 by internally counting the number of line
synchronizing signal clocks (HSYNC) from the falling edge of the frame synchronizing signal
(VSYNC). Take this into consideration when transferring RGB data via the DB[17:0] pins.
42
LGDP4525
Rev 0.9.0
RGB interface mode (2)
The LGDP4525 enables rewriting RAM data via the system interface while the RGB interface is
selected for display operation. In this case, Be sure to write RAM data while display data are not
being transferred via the RGB interface (ENABLE = High). To return to the display data transfer
mode via the RGB interface, change the ENABLE bit first and then set a new address
(AD[15:0]) in the AC and the index register to R22h.
VSYNC interface mode
In VSYNC interface mode, internal display operations are synchronized with the frame
synchronizing signal (VSYNC). In this mode, a moving picture can be displayed via the system
interface by writing data to the internal RAM at more than the minimum speed from the falling
edge of frame synchronizing signal (VSYNC). In this case, there are constraints in the RAM
writing speed and method. For details, see “External Display Interface”.
No external signal input except VSYNC input is accepted in VSYNC interface mode.
The timings and durations of front porch (FP), back porch (BP) periods and display duration
period (NL) are automatically calculated from the falling edge of the frame synchronization
signal (VSYNC) according to the instructions set in the relevant registers.
Oscillator Control (R0Fh)
R/W RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
0
0
0
IB8
FCNT[4:0]
IB7
IB6
0
0
IB5
IB4
IB3
FLM_CLK
0
IB2
IB1
IB0
FFO EXR Halt_OSC
Halt_OSC – Stop oscillator circuit and internal clock is disabled.
EXR – If set, an external resistor is used for oscillator circuit instead of an internal resistor. An
external resistor should be connected to OSC1 and OSC2 pin.
FFO – Register for test purpose at IC-side. In normal operation, fix to FFO=0.
FLM_CLK – If set, FLM pin is used as an external clock input.
FCNT – Set the frequency of oscillator.
Table 33
FCNT[4:0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FOSC(MHZ)
0.29
0.38
0.47
0.57
0.65
0.74
0.83
0.88
0.99
1.07
1.17
1.24
1.33
1.41
1.52
1.56
FCNT[4:0]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FOSC(MHZ)
1.66
1.74
1.82
1.88
1.99
2.07
2.14
2.18
2.31
2.39
2.47
2.53
2.66
2.72
2.77
2.79
43
LGDP4525
Rev 0.9.0
Power Control 1 (R10h)
Power Control 2 (R11h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
W
1
0
SAP[2:0]
0
0
0
IB3
IB2
IB1
0
BT[2:0]
IB9
IB8
IB7
0
IB6
AP[2:0]
IB5
IB4
STB
DK
SLP DSTB
IB0
0
DC1[2:0]
0
DC0[2:0]
0
VC[2:0]
SAP[2:0] – Adjusts the constant current in the operational amplifier circuit for the source driver.
Setting a larger constant current stabilizes the operational amplifier circuit, but current
consumption also increases. Adjust the constant current taking the trade-off between display
quality and current consumption into account. During no display period, set SAP[2:0] = “000” to
halt the operational amplifier circuit to reduce current consumption.
Table 34
SAP[2:0]
0
1
2
3
4
5
6
7
DC current of op-amp
Halt
Setting disable
0.5
0.75
1
1.25
1.5
1.75
Note: The DC current in the table is shown as the ratio to the DC current when SAP[2:0] = “100”.
BT[2:0] – Changes the rate applied to the step-up circuit. Adjust the step-up rate according to
the voltage in use. To reduce current consumption, set a smaller step-up rate.
Table 35
BT[2:0]
0
AVDD
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
VCI1 x 2
[x2]
1
2
3
4
5
6
7
VCL
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VCI1 x -1
[x-1]
VGH
AVDD x 3
[x6]
AVDD x 3
[x6]
AVDD x 3
[x6]
VCI1 + AVDD x 2
[x5]
VCI1 + AVDD x 2
[x5]
VCI1 + AVDD x 2
[x5]
AVDD x 2
[x4]
AVDD x 2
[x4]
VGL
(VCI1 + AVDD x2)
[x-5]
(AVDD x2)
[x-4]
(VCI1 + AVDD)
[x-3]
(VCI1 + AVDD x2)
[x-5]
(AVDD x2)
[x-4]
(VCI1 + AVDD)
[x-3]
(AVDD x2)
[x-4]
(VCI1 + AVDD)
[x-3]
Capacitor
connection pins
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±, C22±
AVDD, VGH, VGL, VCL,
C11±, C13±, C21±
Notes:
1. The step-up rate from the VCI1 level is shown in the bracket [ ] in the above table.
2. When using the AVDD, VCL, VGH and VGL voltage levels, connect a capacitor to each
capacitor connection pin.
3. Set the following voltages within the limits: AVDD = max 5.5V, VCL = min –3.3V, VGH =
max 16.5V, VGL = min –16.5V.
AP[2:0] – Adjusts the constant current in the operational amplifier circuit in the LCD power
supply circuit. Setting a larger constant current stabilizes the operational amplifier circuit, but
current consumption increases. Adjust the constant current taking the trade-off between display
44
LGDP4525
Rev 0.9.0
quality and current consumption into account. During no display period, set AP[2:0] = “000” to
halt the operational amplifier circuit and step-up circuits to reduce current consumption.
Table 36
AP[2:0]
0
1
2
3
4
5
6
7
DC current of op-amp
Halt
0.25
0.5
1
2
3
4
5
Note: The DC current in the table is shown as the ratio to the DC current when AP[2:0] = “100”.
STB – When STB = “1”, the LGDP4525 enters the standby mode. In standby mode, display
operations are completely halted, and all internal operations including internal RC oscillation
and reception of external clocks are halted. See the “Instruction Setting” section for the
sequence. Only the instruction to exit the standby mode (STB = “0”) or that to start oscillators is
accepted during standby mode. In standby mode, the GRAM data and the instruction sets
before entering the standby mode are retained.
DK – Controls the operation of step-up circuit 1. In supplying power to the LGDP4525, stop
generating AVDD for a moment, and wait until the VGH level is stabilized. Then start generating
the AVDD level. For details, see the “Power Supply Setting” section.
Table 37
DK
0
1
Operation of step-up circuit 1
Operate
Halt
SLP – When SLP = “1”, the LGDP4525 enters the sleep mode. In sleep mode, internal display
operation except RC oscillation is halted to reduce current consumption. In sleep mode, only the
following instructions, BT, DC0, DC1, AP, SLP, STB, VRH, VINIT, and VCM, are accepted. No
changes to the GRAM data or other instruction sets are accepted. In sleep mode, the GRAM
data and the instruction sets before entering the sleep mode are retained.
DSTB – When DSTB = “1”, the LGDP4525 enters the deep standby mode. In deep standby
mode, display operations are completely halted, with shutdown internal vdd regulator used as
logic supply voltage and all internal operations including internal RC oscillation and reception of
external clocks are halted. See the “Instruction Setting” section for the sequence. Only the
sequence to exit the deep standby mode is hardware reset or 6 tmes CSB pin low consecutively.
GRAM data and instruction sets are susceptible to destruction and must be set again after
exiting the deep standby mode
DC1[2:0] – Selects the operating frequency of the step-up circuit 2. A higher step-up operating
frequency enhances the driving capacity of the step-up circuit and the quality of display. Adjust
the frequency taking the trade-off between display quality and current consumption into account.
DC0[2:0] – Selects the operating frequency of the step-up circuit 1. A higher step-up operating
frequency enhances the driving capacity of the step-up circuit and the quality of display. Adjust
the frequency taking the trade-off between display quality and current consumption into account.
Note: Setting step-up cycles of step-up circuits 1/2, be sure the step-up cycle of the step-up
circuit 1 is more than that of the step-up circuit 2 (step-up frequency 1 ≥ step-up frequency 2).
45
LGDP4525
Rev 0.9.0
Table 38
DC1[2:0]
0
1
2
3
4
5
6
7
fDCDC2
Oscillation clock / 16
Oscillation clock / 32
Oscillation clock / 64
Oscillation clock / 128
Oscillation clock / 256
Oscillation clock / 512
Oscillation clock / 1024
Oscillation clock / 2048
Table 39
DC0[2:0]
0
1
2
3
4
5
6
7
fDCDC1
Oscillation clock / 8
Oscillation clock / 16
Oscillation clock / 32
Oscillation clock / 64
Oscillation clock / 128
Oscillation clock / 256
Oscillation clock / 512
Oscillation clock / 1024
Note: Be sure fDCDC1 ≥ fDCDC2 when setting DC0, DC1.
VC[2:0] – Sets the rate applied to VCI to generate the reference voltage for the GVDD and
VCI1 levels.
Table 40
VC[2:0]
0
1
2
3
4
5
6
7
VCI1 output voltage
VCI
0.93 x VCI
0.88 x VCI
0.82 x VCI
0.78 x VCI
0.74 x VCI
0.70 x VCI
Halt(Hi-z)
Power Control 3 (R12h)
Power Control 4 (R13h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
W
1
0
0
0
W
1
0
0
VCOMG
0
0
0
VDV[4:0]
IB9
IB8
IB7
IB6
IB5
IB4
0
0
0
0
0
PON
0
IB3
IB2
IB1
IB0
VRH[3:0]
VCM[6:0]
PON – Controls ON/OFF of VGL output. To stop VGL output, set PON to “0”. To start
VGLoutput, set PON to “1”.
VRH[3:0] – Sets the amplifying rate (1.38 to 1.83) applied to REGP to output the GVDD level,
which is a reference level for the VCOM level and the grayscale voltage level.
46
LGDP4525
Rev 0.9.0
Table 41: VRH
VRH[3:0]
0 to 7
8
9
A
B
C
D
E
F
GVDD voltage
Halt
VCI1 x 1.38
VCI1 x 1.45
VCI1 x 1.53
VCI1 x 1.60
VCI1 x 1.68
VCI1 x 1.75
VCI1 x 1.83
Setting disable
VCOMG – When VCOMG = “1”, the LGDP4525 can output a negative voltage level for VCOML
(1.0V to –VCI1+0.5V Max.). When VCOMG = “0”, the LGDP4525 halts the amplifier for negative
voltage to save power. When VCOMG = “0”, the VDV bits are disabled. In this case, adjust the
amplitude of VCOM AC voltage with the VCM bits (VCOMH setting). Set PON to “1” before
setting VCOMG to “1”.
VDV[4:0] – Sets the amplitude of VCOM AC voltage. The VDV bits can set the VCOM
amplitude 0.6 to 1.23 times the GVDD level. If VCOMG = “0”, the VDV bits are disabled.
Table 42
VDV[4:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
VCOM amplitude
GVDD x 0.60
GVDD x 0.63
GVDD x 0.66
GVDD x 0.69
GVDD x 0.72
GVDD x 0.75
GVDD x 0.78
GVDD x 0.81
GVDD x 0.84
GVDD x 0.87
GVDD x 0.90
GVDD x 0.93
GVDD x 0.96
GVDD x 0.99
GVDD x 1.02
Setting disabled
VDV[4:0]
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
VCOM amplitude
GVDD x 1.05
GVDD x 1.08
GVDD x 1.11
GVDD x 1.14
GVDD x 1.17
GVDD x 1.20
GVDD x 1.23
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Notes:
1. Adjust GVDD and VCM so that VCOMH are set within the range 3.0 to (AVDD – 0.5)V
2. Adjust GVDD and VDV so that the amplitude of VCOM are set to 6.0V or less.
VCM[6:0] – Set the VCOMH level (the high level of VCOM AC voltage). The VCM bits can set
the VCOMH level 0.4 to 0.98 times the GVDD level. To stop adjusting VCOMH with the internal
volume and adjust it with an external resistor from VCOMR, set VCM = “11111”.
47
LGDP4525
Rev 0.9.0
Table 43
VCM
[6:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
VCOMH
VCM
[6:0]
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
GVDD x 0.400
GVDD x 0.405
GVDD x 0.410
GVDD x 0.415
GVDD x 0.420
GVDD x 0.425
GVDD x 0.430
GVDD x 0.435
GVDD x 0.440
GVDD x 0.445
GVDD x 0.450
GVDD x 0.455
GVDD x 0.460
GVDD x 0.465
GVDD x 0.470
GVDD x 0.475
GVDD x 0.480
GVDD x 0.485
GVDD x 0.490
GVDD x 0.495
GVDD x 0.500
GVDD x 0.505
GVDD x 0.510
GVDD x 0.515
GVDD x 0.520
GVDD x 0.525
GVDD x 0.530
GVDD x 0.535
GVDD x 0.540
GVDD x 0.545
GVDD x 0.550
GVDD x 0.555
VCOMH
VCM
[6:0]
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
GVDD x 0.560
GVDD x 0.565
GVDD x 0.570
GVDD x 0.575
GVDD x 0.580
GVDD x 0.585
GVDD x 0.590
GVDD x 0.595
GVDD x 0.600
GVDD x 0.606
GVDD x 0.610
GVDD x 0.615
GVDD x 0.620
GVDD x 0.625
GVDD x 0.630
GVDD x 0.635
GVDD x 0.640
GVDD x 0.645
GVDD x 0.650
GVDD x 0.655
GVDD x 0.660
GVDD x 0.665
GVDD x 0.670
GVDD x 0.675
GVDD x 0.680
GVDD x 0.685
GVDD x 0.690
GVDD x 0.695
GVDD x 0.700
GVDD x 0.705
GVDD x 0.710
GVDD x 0.715
VCOMH
VCM[
6:0]
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
GVDD x 0.720
GVDD x 0.725
GVDD x 0.730
GVDD x 0.735
GVDD x 0.740
GVDD x 0.745
GVDD x 0.750
GVDD x 0.755
GVDD x 0.760
GVDD x 0.765
GVDD x 0.770
GVDD x 0.775
GVDD x 0.780
GVDD x 0.785
GVDD x 0.790
GVDD x 0.795
GVDD x 0.800
GVDD x 0.805
GVDD x 0.810
GVDD x 0.815
GVDD x 0.820
GVDD x 0.825
GVDD x 0.830
GVDD x 0.835
GVDD x 0.840
GVDD x 0.845
GVDD x 0.850
GVDD x 0.855
GVDD x 0.860
GVDD x 0.865
GVDD x 0.870
GVDD x 0.875
VCOMH
GVDD x 0.880
GVDD x 0.885
GVDD x 0.890
GVDD x 0.895
GVDD x 0.900
GVDD x 0.905
GVDD x 0.910
GVDD x 0.915
GVDD x 0.920
GVDD x 0.925
GVDD x 0.930
GVDD x 0.935
GVDD x 0.940
GVDD x 0.945
GVDD x 0.950
GVDD x 0.955
GVDD x 0.960
GVDD x 0.965
GVDD x 0.970
GVDD x 0.975
GVDD x 0.980
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Power Control 5 (R14h)
R/W RS
W
IB15 IB14 IB13 IB12 IB11 IB10 IB9
1
0
0
0
0
0
RI[2:0]
IB8
IB7
0
IB6
IB5
RV[2:0]
IB4
IB3
IB2
0
0
IB1
IB0
LbiasEnb S_MULTI
RI[2:0] – Adjusts the constant current in the operational amplifier circuit for the logic voltage
regulator.
Table 44
RI[2:0]
0
1
2
3
4
5
6
7
DC current of op-amp
0.2
1
2
3
3
4
5
6
RV[2:0] – Set the logic voltage(RVDD) level. The RV bits can set the logic voltage(RVDD) level
0.45 to 0.80 times the VCI level.
48
LGDP4525
Rev 0.9.0
Table 45
RV[2:0]
0
1
2
3
4
5
6
7
RVDD voltage level
VCI x 0.80
VCI x 0.75
VCI x 0.70
VCI x 0.65
VCI x 0.60
VCI x 0.55
VCI x 0.50
VCI x 0.45
LbiasEnb – It enables bias circuit operate in minimum current consumption when standby
mode is invoked. Default value of LbiasEnb is low which means enabling minimum current
consumption.
S_MULTI – It controls output size of Amp used for source output .Recommend value is low.
Power Control 6 (R15h)
R/W RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
0
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
TRIM[7:0]
TRIM[7:0] – Adjusts option of band gap regulator.
RAM Address Set (R21h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
AD[15:0]
AD[15:0] – Represents the GRAM address set in the AC (Address Counter) initially. The
address in the AC is automatically updated in accordance with the AM, I/D bits as data are
written to the internal GRAM so that data are written consecutively without resetting an address
in the AC. The address is not automatically updated when reading data from the internal GRAM.
It is not possible to set an address in the AC when the LGDP4525 is in standby mode. Also be
sure to set an address within the window address area.
Notes:
1. When the RGB interface is selected (RM = “1”), the address AD is set in the address
counter every frame on the falling edge of VSYNC.
2. When the internal clock operation or the VSYNC interface mode is selected (RM = “0”),
the address AD is set when executing an instruction.
49
LGDP4525
Rev 0.9.0
Table 46: GRAM address range
…
GRAM setting
Bitmap data for G1
Bitmap data for G2
Bitmap data for G3
Bitmap data for G4
…
AD[15:0]
0000 – 00AF
0100 – 01AF
0200 – 02AF
0300 – 03AF
D800 – D8AF
D900 – D9AF
DA00 – DAAF
DB00 – DBAF
Bitmap data for G217
Bitmap data for G218
Bitmap data for G219
Bitmap data for G220
Write Data to GRAM (R22h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
WD[17:0]
WD[17:0] – If data are less than 18 bits in unit, the LGDP4525 expands the data into 18 bits
internally before written to the internal GRAM. How the data are expanded into 18 bits differs for
each interface and data transfer mode.
The grayscale level is selected according to GRAM data. The GRAM address is automatically
updated according to the AM and I/D bits as data are written to the internal GRAM. In standby
mode, no access to the internal GRAM is allowed. When the 8 or 16 bit interface mode is
selected, data are expanded into 18 bits internally by writing the MSBs of R and B dots to the
LSBs of R and B dots respectively.
When writing data to the GRAM via a system interface while using the RGB interface, be sure
there is no conflict between writing operations via respective interfaces (RGB and system
interfaces). When the18-bit RGB interface is selected, 18-bit data are written via the DB[17:0]
pins and 262,144 colors are available. When the 16-bit RGB interface is selected, the MSBs of
R and B dots are also written to the LSBs of R and B dots respectively, and 65,536 colors are
available.
50
LGDP4525
Rev 0.9.0
18-bit interface (262k colors)
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
16-bit interface (65k colors) – TRI = “0”
Input
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1 17 16
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
16-bit interface (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
2
1 17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 11: Write data to GRAM in 18-/16-bit interface mode
51
LGDP4525
Rev 0.9.0
9-bit interface (262k colors)
1st transfer
2nd transfer
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
8-bit interface (65k colors) – TRI = “0”
1st transfer
2nd transfer
Input
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
8-bit interface (3 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
Input
2nd transfer
3rd transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
8-bit interface (3 transfers/pixel, 65k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 12: Write data to GRAM in 9-/8-bit interface mode
52
LGDP4525
Rev 0.9.0
18-bit RGB interface (262k colors)
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
16-bit RGB interface (65k colors)
Input
DB DB DB DB DB
17 16 15 14 13
DB DB DB DB DB DB DB DB DB DB DB
11 10 9
8
7
6
5
4
3
2
1
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
6-bit RGB interface (262k colors)
1st transfer
2nd transfer
3rd transfer
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
Write data
to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
assignment
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 13: Write data to GRAM in 18-/16-/6-bit RGB interface mode
53
LGDP4525
Rev 0.9.0
Table 47: GRAM data and LCD output level
…
Positive
V63
V62
V61
V60
…
Grayscale
Negative
V0
V1
V2
V3
…
GRAM data setting:
RGB each
0
1
2
3
60
61
62
63
V60
V61
V62
V63
V3
V2
V1
V0
RAM Access via RGB I/F and System I/F
In RGB interface mode, the LGDP4525 stores all display data in the internal RAM, enabling
transferring only moving picture data only when updating the frames of a moving picture. While
the moving picture frames are not updated, it is possible to write data displayed in the area
outside the moving picture area via the system interface.
In RGB interface mode, the LGDP4525 writes data to the internal RAM in synchronization with
DOTCLK during ENABLE = “Low”. To access the internal RAM via the system interface while
using the RGB interface for display operation, set ENABLE “High” to stop writing via the RGB
interface. To start accessing the internal RAM via the RGB interface after accessing the RAM
via the system interface, wait at least for a write/read bus cycle time. Data will not be written
properly to the internal RAM when writing operations via both RGB and system interfaces are
conflicting.
54
LGDP4525
Rev 0.9.0
VSYNC
ENABLE
DOTCLK
PD17-0
*See Note 2)
System
interface
Set IR
to
R22h
Set
RM=0
Set AD
Rewrite data in the
area
other than the moving
picture area
Set
IR to
R22h
Updating moving
picture area
Set
RM=1
Set AD
Set
IR to
R22h
Rewrite still picture area
*See Note 1)
Updating moving
picture area
Note 1) An address (AD[15:0]) is set in the AC on ever falling edge of VSYNC in RGB interface mode.
Note 2) Set the address AD[15:0] in the AC and the index register to R22h (RAM data write/read) before starting RAM access through
the RGB interface.
6/25 00:00
6/25 00:00
Moving picture
area
Moving picture
area
Figure 14 RAM Acess via RGB Interface and System Interface
Read Data Read from GRAM (R22h)
R/W
RS
R
1
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
RD[17:0]
RD[17:0] – Reads 18-bit data from the GRAM. The bit assignment between the data read out
from the
GRAM and the DB[17:0] pins differs for each interface.
When data are read out from the GRAM to the microcomputer, the first word read immediately
after executing RAM address set is taken in the internal read data latch and invalid data are
sent to the data bus DB[17:0]. Valid data are sent to the data bus as the LGDP4525 reads out
the second word data from the internal GRAM.
The 1st word data read into the internal read data latch are used for a bit operation
(logical/compare operation) is performed inside the LGDP4525. Accordingly, the bit operation is
processed with one read out operation. Note that the bit operation is performed on the data in
units of 18 bits.
When the 8 or 16-bit interface is selected, the LSBs of R and B dots are not read out.
Note: This register is not available with the RGB interface.
55
LGDP4525
Rev 0.9.0
18-bit interface
GRAM data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
16-bit interface
GRAM data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
9-bit interface
GRAM data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
1st transfer
2nd transfer
8-bit interface/SPI
GRAM data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Output
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
1st transfer
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
2nd transfer
Figure 15: Read data from GRAM
56
LGDP4525
Rev 0.9.0
Set ID, AM, HAS/HEA, VSA/VEA bits
Set ID, AM, HAS/HEA, VSA/VEA bits
Set address N
Set address N
1st word
Dummy read (invalid data)
GRAM → read data latch
1st word
Dummy read (invalid data)
GRAM → read data latch
2nd word
Read (data of address N)
read data latch → DB[17:0]
2nd word
Write (data of address N)
DB[17:0] → read data latch
Set address M
Automatic update of address counter
1st word
Dummy read (invalid data)
GRAM → read data latch
1st word
Dummy read (invalid data)
GRAM → read data latch
2nd word
Read (data of address M)
read data latch → DB[17:0]
2nd word
Write (data of address M)
DB[17:0] → read data latch
1) Read data to the MPU
2) Logical operation inside LGDP4525
Figure 16: GRAM read sequence
Software Reset (R28h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
0
0
1
1
0
0
1
1
1
0
If write 00CE value to this register, an internal software reset is generated.
57
LGDP4525
Rev 0.9.0
γ Control (R30h to R3Fh)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
W
1
0
0
0
0
0
W
1
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
PKP1[2:0]
0
0
0
0
0
PKP0[2:0]
PKP3[2:0]
0
0
0
0
0
PKP2[2:0]
W
1
0
0
0
0
0
PKP5[2:0]
0
0
0
0
0
PKP4[2:0]
W
1
0
0
0
0
0
PRP1[2:0]
0
0
0
0
0
PRP0[2:0]
W
1
0
0
0
0
0
PKN1[2:0]
0
0
0
0
0
PKN0[2:0]
W
1
0
0
0
0
0
PKN3[2:0]
0
0
0
0
0
PKN2[2:0]
W
1
0
0
0
0
0
PKN5[2:0]
0
0
0
0
0
PKN4[2:0]
W
1
0
0
0
0
0
PRN1[2:0]
0
0
0
0
0
PRN0[2:0]
W
1
0
0
0
0
0
0
W
1
0
0
0
0
0
0
W
1
0
0
0
0
0
PFP1[2:0]
0
0
0
0
0
PFP0[2:0]
W
1
0
0
0
0
0
PFP3[2:0]
0
0
0
0
0
PFP2[2:0]
W
1
0
0
0
0
0
PFN1[2:0]
0
0
0
0
0
PFN0[2:0]
W
1
0
0
0
0
0
PFN3[2:0]
0
0
0
0
0
PFN2[2:0]
W
1
0
0
0
0
0
0
0
0
0
0
PMP[2:0]
W
1
0
0
0
0
0
0
0
0
0
0
PMN[2:0]
VRP1[4:0]
VRN1[4:0]
VRP0[4:0]
VRN0[4:0]
PKP5-0[2:0]
– γ fine adjustment register bits for positive polarity
PRP1-0[2:0]
– γ gradient adjustment register bits for positive polarity
PKN5-0[2:0]
– γ fine adjustment register bits for negative polarity
PRN1-0[2:0]
– γ gradient adjustment register bits for negative polarity
VRP1-0[4:0]
– amplitude adjustment register bits for positive polarity
VRN1-0[4:0]
– amplitude average adjustment register bits for negative polarity
PFP3-0[2:0]
– γ fine adjustment register bits for positive polarity
PFN3-0[2:0]
– γ fine adjustment register bits for negative polarity
PMP[2:0]
– γ fine adjustment register bits for positive polarity
PMN[2:0]
– γ fine adjustment register bits for negative polarity
For details see “γ-Correction Function” section
Gate Scan Position (R40h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
IB7
IB6
IB5
0
0
0
0
0
IB4
IB3
IB2
IB1
IB0
SCN[4:0]
SCN[4:0] – The LGDP4525 allows specifying the gate line from which the gate driver starts
scan by setting the SCN4-0 bits.
58
LGDP4525
Rev 0.9.0
G1
G1
G57
G176
G220
G220
GS = 0
NL = 10101
SCN = 00000
GS = 0
NL = 10101
SCN = 00111
Note: Set the NL bits (the number of lines for driving the LCD panel) and the SCN bits so that the
position of the gate line at the scan ends does not exceed the 220th.
Figure 17 Example of Setting NL, GS & SCN
Table 48
SCN[4:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
Scan start position (gate line)
GS = “0”
GS = “1”
G1
G220
G9
G212
G17
G204
G25
G196
G33
G188
G41
G180
G49
G172
G57
G164
G65
G156
G73
G148
G81
G140
G89
G132
G97
G124
G105
G116
G113
G108
G121
G100
G129
G92
G137
G84
G145
G76
G153
G68
G161
G60
G169
G52
G177
G44
G185
G36
G193
G28
G201
G20
G209
G12
G217
G4
59
LGDP4525
Rev 0.9.0
Vertical Scroll Control (R41h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
0
0
0
IB9
IB8
0
0
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
VL[7:0]
VL[7:0] – Sets the scrolling amount of an image on the screen in vertical direction. The scrolling
amount can be set from 0 line to 220 lines. The start position for displaying the image is shifted
vertically by the number of lines set with the VL bits. The part of the image, which is scrolled out
from the end line (the 220th line) as a result of scrolling, is displayed from the 1st line of the
physical display. The VL bits are enabled when either first display vertical scroll enable bit
VLE[0] or the second display vertical scroll enable bit VLE[1] is set to “1”. When VLE[1:0] = “00”,
the image on the screen is displayed at the position set with the SS and SE bits. The vertical
scrolling function is not available with the external display interface.
Table 49
…
Scrolling lines
0 line
1 line
2 lines
…
VL[7:0]
0
1
2
218
219
218 line
219 lines
1st-Screen Drive Position (R42h)
2nd-Screen Drive Position (R43h)
R/W
RS
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
W
1
SE1[7:0]
SS1[7:0]
W
1
SE2[7:0]
SS2[7:0]
IB2
IB1
IB0
SS1[7:0] – Sets the position of the start line from which the first display starts. The gate driver
starts scan from the line of the number set with the SS1 bits + 1.
SE1[7:0] – Sets the position of the end line at which the first display ends. The gate driver ends
scan at the line of the number set with the SE1 bits + 1. For instance, when SS1 = 07h and SE1
= 10h, the first display is shown on the gate lines from G8 to G17, and gate lines G1 to G7 and
G18 thereafter are driven to show a blank screen. Be sure that SS1 ≤ SE1 ≤ EFh. For details,
see the “Partial Display Function” section.
SS2[7:0] – Sets the position of the start line from which the second display starts. The gate
driver starts scan from the line of the number set with the SS2 bits + 1. The second display is
shown when SPT = “1”.
SE2[7:0] – Sets the position of the end line at which the second display ends. The gate driver
ends scan at the line of the number set with the SE2 bits + 1. For instance, when SPT = “1”, and
SS2 = 20h, SE2 = 4Fh, the second display is shown on the gate lines from G33 to G80.
Be sure that SS1 ≤ SE1 < SS2 ≤ SE2 ≤ EFh. For details, see the “Partial Display Function”
section.
60
LGDP4525
Rev 0.9.0
Horizontal RAM Address Position (R44h)
Vertical RAM Address Position (R45h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
HEA[7:0]
IB9
IB8
IB7
IB6
IB5
IB4
HSA[7:0]
IB3
W
1
VEA[7:0]
VSA[7:0]
IB2
IB1
IB0
HSA[7:0]/HEA[7:0] – HSA and HEA represent the respective addresses at the start and end of
the window address area in horizontal direction. By setting HSA and HEA bits, it is possible to
limit the area on the GRAM horizontally for writing data. The HSA and HEA bits must be set
before starting RAM write operation. In setting these bits, be sure 00h ≤ HSA < HEA ≤ AFh.
VSA[7:0]/VEA[7:0] – VSA and VEA represent the respective addresses at the start and end of
the window address area in vertical direction. By setting VAS and VEA bits, it is possible to limit
the area on the GRAM vertically for writing data. The VSA and VEA bits must be set before
starting RAM write operation. In setting, be sure 00h ≤ VSA < VEA ≤ EFh.
HSA
HEA
0000h
Window address area
VSA
Window address
area
00h ≤ HSA ≤ HEA ≤ AFh
00h ≤ VSA ≤ VEA ≤ EFh
VEA
GRAM address area
Notes:
1.
2.
EFAFh
Make a window address area within the GRAM address area.
Set a RAM address within the window address area.
Figure 18: GRAM address and window address area
Test Register 1 (R71h)
R/W
RS
W
1
IB15 IB14 IB13 IB12 IB11 IB10
0
0
0
R_OV
0
0
IB9
IB8
TDLY
IB7
0
IB6
IB5
IB4
T8CL TPOL[1:0]
IB3
0
IB2
IB1
IB0
TMEM TOSC TFN
TFN – Sets the chip to function test mode.
TOSC – Sets the pin FLM to output the internal oscillator signal instead of the frame head pulse
signal
TMEM – Sets the pin FLM to output the internal memory A read enable signal instead of the
frame head pulse signal.
TPOL[1:0] – When TPOL[1] = “1”, liquid crystal polarity is fixed to positive polarity if TPOL[0] =
“0” or negative polarity if TPOL[0] = “1”. Affected are VCOM and source outputs. When TPOL[0]
= “0”, field/line polarity inversion takes place.
T8CL – Set Power Saving for particular images. T8CL= “1”, that means it has a chance to
reserve power and “0” means it operates normally when images are displayed.
TDLY[1:0] – Set the delay of arbiter logic,
Delay of TDLY[1:0] : 11 < 00 < 01 < 10
61
LGDP4525
Rev 0.9.0
R_OV – Disable overwriten command if comman occurs many times...
Test Register 2 (R72h)
R/W RS
W
1
IB15 IB14 IB13
0
0
0
IB12
REGULPD
IB11 IB10 IB9
0
0
0
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
S_HIZ
0
0
0
MVCOML
0
MVCI
0
0
MVCOML – Set Multiple Option for VCOM regulator.
S_HIZ – “0” Normal stepup2 operation
“1” Disable stepup2 and Hi-z stepup2 output for test mode.
REGULPD – Regulator Power Down
MVCI–
VCI1 level control signal
62
LGDP4525
Rev 0.9.0
Instruction List
Table 50
Index
Register
00
ID Read
01
Driver output control
02
LCD drive AC control
03
Entry mode
04
Resize control
05
-
06
-
07
Display control 1
08
Display control 2
09
Display control 3
0A
-
0B
Frame cycle
adjustment
0C
External display I/F
ctrl
0F
Oscillation Control
10
Power control 1
11
Power control 2
12
Power control 3
13
Power control 4
14
Power control 5
15
Power control 6
21
RAM address set
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
1
0
1
VSPL HSPL
DPL
EPL
SM
GS
SS
B/C
EOR
DFM
BGR
FLD[1:0]
TRI
NL[4:0]
RCV[1:0]
PTS[2:0]
VLE[1:0]
0030
GON
RSZ[1:0]
DTE
CL
REV
FP[3:0]
PTG[1:0]
NO[1:0]
SDT[1:0]
EQ[1:0]
DIV[1:0]
0000
0808
ISC[3:0]
0000
002C
DM[1:0]
RIM[1:0]
FLM_C
LK
FCNT[4:0]
BT[2:0]
AP[2:0]
STB
DC1[2:0]
DC0[2:0]
FFO
EXR
HALT
OSC
DK
SLP
DSTB
VC[2:0]
PON
VCOM
G
D[1:0]
VDV[4:0]
0000
1000
0004
0000
VRH[3:0]
0000
VCM[6:0]
RI[2:0]
0000
BP[3:0]
RTN[6:1]
RM
SAP[2:0]
0400
AM
RCH[1:0]
SPT
4525
001B
NW[5:0]
ID[1:0]
Default
0000
LbaisE S_MUL
0040
TI
n
RV[2:0]
TRIM[7:0]
0000
AD[15:0]
0000
22
RAM data R/W
28
Softwafe Reset
30
Gamma control 1
PKP1[2:0]
PKP0[2:0]
0000
31
Gamma control 2
PKP3[2:0]
PKP2[2:0]
0000
32
Gamma control 3
PKP5[2:0]
PKP4[2:0]
0000
33
Gamma control 4
PRP1[2:0]
PRP0[2:0]
0000
34
Gamma control 5
PKP1[2:0]
PKP0[2:0]
0000
35
Gamma control 6
PKP3[2:0]
PKP2[2:0]
0000
36
Gamma control 7
PKP5[2:0]
PKP4[2:0]
0000
37
Gamma control 8
PRP1[2:0]
PRP0[2:0]
38
Gamma control 9
VRP1[4:0]
VRP0[3:0]
VRN1[4:0]
VRN0[3:0]
39
Gamma control 10
3A
Gamma selection
40
Gate scan start
position
RAM 18-bit R/W data
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0000
0000
0000
SREF
SCN[4:0]
0000
0000
41
Vertical scroll control
VL[7:0]
0000
42
First screen position
SE1[7:0]
SS1[7:0]
FF00
43
Second screen
position
SE2[7:0]
SS2[7:0]
FF00
44
Horizontal RAM
address
HEA[7:0]
HSA[7:0]
AF00
45
Vertical RAM
address
VEA[7:0]
VSA[7:0]
DB00
71
Test register 1
R_OV
72
Test register 2
REGUL
PD
T8CL
S_HIZ
TPOL[1:0]
MVCOM
L
TMEM TOSC
MVCI
TFN
0000
0000
63
LGDP4525
Rev 0.9.0
Interface Specifications
The LGDP4525 has the system interface for making instruction setting and other settings, and
the external display interface for displaying a moving picture. The LGDP4525 allows selecting
an optimum interface for the display (moving or still picture) in order to transfer data efficiently.
As the external display interface, the LGDP4525 has the RGB interface and the VSYNC
interface, enabling data rewrite operation without flicker the moving picture on the screen.
In RGB interface mode, display operations are performed in synchronization with synchronizing
signals VSYNC, HSYNC, and DOTCLK. Display data are written to the internal RAM according
to the polarity of the data enable signal ENABLE via the moving picture display data bus
DB[17:0] in synchronization with VSYNC, HSYNC, and DOTCLK. All display data are stored in
the LGDP4525’s GRAM to limit data transfer to only when switching the frames of a moving
picture. By using the window address function, it is possible to limit the RAM area to be
rewritten for displaying a moving picture and display both the moving picture and the data
written on the RAM at a time.
In VSYNC interface mode, the internal display operations are synchronized with the frame
synchronization signal VSYNC. The VSYNC interface enables a moving picture display via the
system interface by writing data to the internal GRAM at more than the minimum speed in
synchronization with the falling edge of VSYNC. In this case, there are constraints in speed and
method for writing data to the internal RAM.
The LGDP4525 operates in one of the following 4 modes in line with the state of display. The
mode for display operation is set in the external interface control register. When switching from
one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC
interfaces.
Table 51
Operation mode
Internal operating clock only:
Displaying still pictures
RGB interface (1):
Displaying moving pictures
RGB interface (2):
Rewriting still pictures while
displaying moving pictures
VSYNC interface:
Displaying moving pictures
RAM access setting (RM)
System interface
(RM = 0)
RGB interface
(RM = 1)
RGB interface
(RM = 1)
Display operation mode (DM)
Internal operating clock
(DM = 0)
RGB interface
(DM = 1)
RGB interface
(DM = 1)
System interface
(RM = 0)
VSYNC interface
(DM = 2)
Notes:
1. Instructions are set only via the system interface.
2. The RGB I/F and the VSYNC I/F are not available simultaneously.
3. Do not make changes to the RGB I/F mode (RIM[1:0] bits) while an RGB I/F is in
operation.
4. See the sections of RGB and VSYNC interfaces for the sequences to follow when
switching from one mode to another.
64
LGDP4525
Rev 0.9.0
CSB*
RS
WR*
(RD*)
DB[17:0]
System interface
System
RGB interface
18/16/9/8
LGDP4525
ENABLE
VSYNC
HSYNC
DOTCLK
Figure 19: Interfaces between system and LGDP4525
65
LGDP4525
Rev 0.9.0
System Interface
The following are the system interfaces available with the LGDP4525. The interface is selected
by setting the IM[3:0] pins. The system interface is used for setting instructions and RAM access.
Table 52
IM[3:0]
0000
MPU interface mode
68-system 16-bit interface
0001
0010
68-system 8-bit interface
80-system 16-bit interface
0011
010*
011*
1000
1001
1010
1011
11**
80-system 8-bit interface
Serial peripheral interface (SPI)
Setting disabled
68-system 18-bit interface
68-system 9-bit interface
80-system 18-bit interface
80-system 9-bit interface
Setting disabled
DB pin in use
DB[17:10],
DB[8:1]
DB[17:10]
DB[17:10],
DB[8:1]
DB[17:10]
SDI, SDO
DB[17:0]
DB[17:9]
DB[17:0]
DB[17:9]
-
66
LGDP4525
Rev 0.9.0
80-System 18-Bit Interface
The 80-system 18-bit parallel system interface is selected by setting the IM[3:0] pins to “1010”.
CSn*
A1
HWR*
(RD*)
D[17:0]
MPU
CSB LGDP4525
RS
RW_WRB
(E_RDB)
DB[17:0]
18
Figure 20: 18-bit microcomputer and LGDP4525
Instruction
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
RAM data write (1 transfer/pixel, 262k colors)
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GRAM write
data
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 21: Data format for 18-bit interface
67
LGDP4525
Rev 0.9.0
80-System 16-Bit Interface
The 80-system 16-bit parallel system interface is selected by setting the IM[3:0] pins to “0010”.
The unused pins, “DB[9] and DB[0] must be tied to GND.
CSn*
A1
HWR*
(RD*)
D[15:0]
MPU
CSB LGDP4525
RS
RW_WRB
(E_RDB)
DB[17:10], DB[8:1]
16
Figure 22: 16-bit microcomputer and LGDP4525
Instruction
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
RAM data write (1 transfer/pixel, 65k colors) – TRI = “0”
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
8
7
6
5
4
3
2
1
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1 17 16
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (2 transfers/pixel, 262k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
2
1 17 16 15 14 13 12 11 10 8
7
6
5
4
3
2
1
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 23: Data format for 16-bit interface
68
LGDP4525
Rev 0.9.0
Data Transfer Synchronizing in 16-Bit Bus Interface Mode
The LGDP4525 supports a data transfer synchronization function, which resets the counter to
count the numbers of upper 16/2-bit and lower 2/16-bit transfers in 16 bits x 2 transfer mode.
When a mismatch occurs in data transfers due to noise and so on, the 000h instruction is
written 4 times consecutively to reset the upper and lower counters to restart data transfers from
the upper 2/16 bits. The synchronization function, when executed periodically, will prevent the
runaway of the display system.
RS
E_RDB
RW_WRB
DB[17:10]
DB[8:1]
upper/
lower
000h
000h
000h
000h
upper
synchronization
Figure 24: 16-bit data transfer synchronization
69
LGDP4525
Rev 0.9.0
80-System 9-Bit Interface
The 80-system 9-bit parallel system interface using the DB17 to DB9 pins is selected by setting
the IM[3:0] pins to “1011”. When transferring a 16-bit instruction, it is divided into upper and
lower 8 bits (the LSB is not used), and the upper 8 bits are transferred first. The RAM write data
are also divided into the upper and lower 9 bits, and the upper bits are transferred first. The
unused DB[8:0] pins must be fixed at either VDD3 or GND level. When writing the index register,
the upper byte (8 bits) must be written.
The unused pins, “DB[8:0] must be tied to GND
CSn*
A1
HWR*
(RD*)
D[8:0]
MPU
CSB LGDP4525
RS
RW_WRB
(E_RDB)
DB[17:9]
9
Figure 25: 9-bit microcomputer and LGDP4525
Instruction
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
RAM data write (2 transfers/pixel, 262k colors)
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 26: Data format for 9-bit interface
70
LGDP4525
Rev 0.9.0
Data Transfer Synchronizing in 9-Bit Bus Interface Mode
The LGDP4525 supports a data transfer synchronization function to reset upper and lower
counters counting the number of transfers of upper and lower 9 bits in 9-bit bus interface mode.
If a mismatch arises in the numbers of transfers between the upper and lower 9 bit counters due
to noise and so on, the 000h instruction is written 4 times consecutively to reset the upper and
lower counters so that data transfer will restart with a transfer of upper 9 bits. This
synchronization function, when executed periodically, can effectively prevent runaway of display
system.
RS
E_RDB
RW_WRB
DB[17:9]
upper/
lower
000h
000h
000h
000h
upper
synchronization
Figure 27: 9-bit data transfer synchronization
71
LGDP4525
Rev 0.9.0
80-System 8-Bit Interface
The 80-system 8-bit parallel system interface using the DB17 to DB10 pins is selected by
setting the IM[3:0] pins to “0011”. When transferring a 16-bit instruction, it is divided into upper
and lower 8 bits and the upper 8 bits are transferred first. The RAM data is also divided into the
upper and lower 8 bits, and the upper bits are transferred first. The RAM write data are
expanded into 18 bits internally (see the figure below). The unused pins DB[9:0] must be fixed
at either VDD3 or GND level. When writing the index register, the upper byte (8 bits) must be
written.
The unused pins, “DB[9:0] must be tied to GND
MPU
CSn*
A1
HWR*
(RD*)
D[7:0]
CSB LGDP4525
RS
RW_WRB
(E_RDB)
DB[17:10]
8
Figure 28: 8-bit microcomputer and LGDP4525
72
LGDP4525
Rev 0.9.0
Instruction
Input
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Instruction Bit
(IB)
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
RAM data write (2 transfers/pixel, 65k colors) – TRI = “0”
1st transfer
2nd transfer
GRAM data
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 65k colors) – TRI = “1”, DFM = “1”
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 29: Data format for 8-bit interface
73
LGDP4525
Rev 0.9.0
Data Transfer Synchronization in 8-Bit Bus Interface Mode
The LGDP4525 supports a data transfer synchronization function to reset upper and lower
counters counting the number of transfers of upper and lower 8 bits in 8-bit bus interface mode.
If a mismatch arises in the numbers of transfers between the upper and lower 8 bit counters due
to noise and so on, the 00h instruction is written 4 times consecutively to reset the upper and
lower counters so that data transfer will restart with a transfer of upper 8 bits. This
synchronization function, when executed periodically, can effectively prevent runaway of display
system.
RS
E_RDB
RW_WRB
DB[17:10]
upper/
lower
00h
00h
00h
00h
upper
synchronization
Figure 30: 8-bit data transfer synchronization
74
LGDP4525
Rev 0.9.0
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is selected by setting the IM[3:1] pins to “010”. The SPI is
available via the chip select line (CSB), the serial transfer clock line (SCL), the serial data input
(SDI), and the serial data output (SDO). In SPI mode, the IM0/ID pin functions as the ID pin and
the DB[17:0] pins, which are not used, must be fixed at either VDD3 or GND level.
The LGDP4525 recognizes the start of data transfer on the falling edge of CSB input and
transfers the start byte. It recognizes the end of data transfer on the rising edge of CSB input.
The LGDP4525 is selected when the 6-bit chip address in the start byte transferred from the
transmission unit and the 6-bit device identification code assigned to the LGDP4525 correspond
as a result of comparison. When selected, the LGDP4525 starts taking subsequent data. The ID
pin sets the least significant bit of the identification code. Send “01110” to the identification code,
which is the five upper bits of the start byte. Two different chip addresses must be assigned to
the LGDP4525 because the seventh bit of the start byte is assigned to the register select bit
(RS). When RS = “0”, either index register write operation or status read operation is executed.
When RS = “1”, either instruction write operation or RAM read/write operation is executed. The
eighth bit of the start byte is to select either read or write operation (R/W bit). Data are received
when the R/W bit is “0”, and are transferred when the R/W bit is “1”.
After receiving the start byte, the LGDP4525 starts transferring or receiving data in units of
bytes. Data transfer is executed from the MSB. All instructions of the LGDP4525 take a 16-bit
format and are executed internally after transferring two bytes (DB[15:0]) from the MSB. GRAM
write data are internally expanded into 18 bits. After receiving the start byte, the LGDP4525
takes the first and the second byte as the upper and the lower eight bits of a 16-bit instruction,
respectively.
In SPI mode, invalid data are sent to the data bus until 4-byte data are read out from the internal
GRAM after the start byte. Valid data are read out as the LGDP4525 reads out the 5th byte data
from the internal GRAM.
Table 53: Start byte format
Transferred bits
Start byte format
1
2
3
Device ID code
0
1
1
4
5
6
1
0
ID
7
RS
8
R/W
Note: ID bit is selected by setting the IM0/ID pin.
Table 54
RS
0
0
1
1
R/W
0
1
0
1
Function
Set an index register
Read a status
Write an instruction or RAM data
Read an instruction or RAM data
75
LGDP4525
Rev 0.9.0
Instruction
Input
Instruction Bit
(IB)
1st transfer
2nd transfer
D15 D14 D13 D12 D11 D10 D9 D8
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
D7 D6 D5 D4 D3 D2 D1 D0
IB
7
IB
6
IB
5
IB
4
IB
3
IB
2
IB
1
IB
0
RAM data write (2 transfers/pixel, 65k colors) – TRI = “0”
1st transfer
2nd transfer
GRAM data
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
RAM data write (3 transfers/pixel, 262k colors) – TRI = “1”, DFM = “0”
1st transfer
2nd transfer
3rd transfer
GRAM data
D23 D22 D21 D20 D19 D18 D15 D14 D13 D12 D11 D10 D7 D6 D5 D4 D3 D2
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 31: Data format for SPI
76
LGDP4525
Rev 0.9.0
VSYNC Interface
The LGDP4525 has the VSYNC interface, which enables moving picture display with the
system interface in synchronization with the frame-synchronizing signal (VSYNC). The VSYNC
interface enables the system interface to display a moving picture with minimum modification.
VSYNC
LGDP4525
CSB
RS
RW_WRB
(E_RDB)
DB[17:10]
MPU/
LCDC
18/16/9/8
Figure 32: VSYNC interface
The VSYNC interface is selected by setting DM1-0 = “10” and RM = “0”. In VSYNC interface
mode, the internal display operation is synchronized with the VSYNC signal. By writing data to
the internal RAM via the system interface at a speed faster to a certain degree than that of
internal display operation, the VSYNC interface enables moving picture display with the system
interface and screen rewriting operation without flicker.
The display operation in VSYNC mode is executed in synchronization with the internal clock
generated from internal oscillators and VSYNC input. All display data are stored in the internal
RAM to limit the data to be transferred to those overwritten on the moving picture RAM area and
minimize total data transfer required for moving picture display.
VSYNC
Write data to RAM
through system
interface
Update screen
Update screen
Display operation
synchronized with
the internal clock
Figure 33: Moving picture data transfer via VSYNC interface
The VSYNC interface has the minimum speed of writing data to the internal RAM via the system
interface and the minimum internal clock frequency, which are calculated from the following
formulae.
Internal clock frequency (fosc)
= FrameFrequency × (DisplayLines (NL) + FrontPorch (FP) + BackPorch (BP)) × 16 clocks ×
variance
RAMWriteSpeed >
176 × DisplayLines (NL)
(BackPorch (BP) + DisplayLines (NL) − margins) × 16 clocks ×
1
fosc
Note: When the RAM write operation does not start on the falling edge of VSYNC, the time from
the falling edge of VSYNC until the start of RAM write operation must also be taken into account.
An example of minimum RAM writing speed and internal clock frequency in VSYNC interface
mode is as follows.
[Example]
77
LGDP4525
Rev 0.9.0
Display size
Lines
Back/front porch
Frame frequency
176 RGB × 220 lines
220 lines (NL = 11001)
14/2 lines (BP = 1110/FP = 0010)
60 Hz
Internal clock frequency (fosc)
= 60 Hz × (220 + 2 + 14) lines × 44 Clocks × 1.1 / 0.9 = 760 kHz
When setting the internal clock frequency, possible causes of variances must also be taken into
consideration. In this example, the calculated internal clock frequency with the above register
setting allows for a margin of ±10% for variances and ensures to complete the display operation
within one VSYNC cycle.
In this example, variances attributed to the fabrication process of LSI and room temperature are
counted in. Other possible causes of variances, such as differences in external resistors or
voltage changes are not in consideration. It is necessary to allow for an enough margin if these
factors must be incorporated.
Minimum speed for RAM writing
> 176 × 220 / {((14 + 220 - 2) lines × 44 clock) / 760 kHz} = 2.88 MHz
The above theoretical value is calculated on the premise that the LGDP4525 starts writing data
to the internal RAM on the falling edge of VSYNC. There must at least be a margin of 2 lines
between the physical display line where display operation is performed and the RAM line
address where data write operation is performed.
The RAM write speed of 2.88MHz or more on the falling edge of VSYNC will guarantee the
completion of RAM write operation before the LGDP4525 starts displaying the RAM data on the
screen, enabling rewriting the entire screen without flicker.
VSYNC
Due to Fosc
variation of ±10%
[lines]
Back porch (14 lines)
220
RAM write
(10MHz)
RAM write
(2.88MHz)
Display
(220 lines)
Display
operation
Front porch (2 lines)
Blank period
0
[ms]
VSYNC
Figure 34: Write/display operation timing via VSYNC interface
Notes in Using the VSYNC Interface
1. The above example of calculation gives a theoretical value. In the actual setting, other
possible causes of variances not counted in the above example such as differences in
78
LGDP4525
2.
3.
4.
5.
6.
Rev 0.9.0
internal oscillators should also be taken into consideration. It is strongly recommended
to allow for an enough margin in setting a RAM writing speed.
The above example of calculation gives a minimum value in case of rewriting the entire
screen. If the moving picture display area is smaller than that, the range for setting a
minimum RAM writing speed can have extra margins.
After drawing 1 frame, a front porch period continues until the next input of VSYNC is
detected.
When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC
interface mode, or the other way around, it is enabled from the next VSYNC cycle, i.e.
after completing the display of the frame, which the LGDP4525 was internally
processing when switching the modes.
The partial display, vertical scroll, and interlaced scan functions are not available in
VSYNC interface mode.
In VSYNC interface mode, set the AM bit to “0” to transfer display data in the method
mentioned above.
79
LGDP4525
Rev 0.9.0
External Display Interface
The following are the external display interface (RGB interface) available with the LGDP4525.
The interface is selected by setting the RIM1-0 bits as follows. The RGB interface is used to
access RAM.
Table 55
RIM[1:0]
00
01
10
11
RGB interface
18-bit RGB interface
16-bit RGB interface
6-bit RGB interface
Setting disabled
DB pins
DB[17:0]
DB[17:10], DB[8:1]
DB[17:12]
Note: Multiple RGB interfaces cannot be used simultaneously.
RGB Interface
The display operation via the RGB interface is synchronized with VSYNC, HSYNC, and
DOTCLK. The RGB interface enables transferring minimum necessary data and rewriting the
RAM area need to be overwritten with use of window address function. In RGB interface mode,
it is necessary to set back and front porch periods before and after a display period, respectively.
Figure 35: RGB interface
ENABLE Signal
The combinations of EPL and ENABLE bits and the functions are as follows. Note that it is
necessary to set both EPL and ENABLE bits to automatically update RAM address in the AC
when writing data to the internal RAM. The EPL bit inverts the polarity of ENABLE signal.
Table 56
EPL
0
0
1
1
ENABLE
0
1
0
1
RAM write
Enabled
Disabled
Disabled
Enabled
RAM address
Updated
Retained
Retained
Updated
80
LGDP4525
Rev 0.9.0
RGB Interface Timing
The timing chart of signals in 16/18-bit RGB interface mode is as follows.
1 frame
Back porch period
Front porch period
VSYNC
HSYNC
DOTCLK
ENABLE
DB17-0
VLW >= 1H
VSYNC
1H
HLW >= 1CLK
HSYNC
1 clock
DOTCLK
DTST >= HLW
ENABLE
DB17-0
Valid data
VLW: VSYNC "Low" level
HLW: HSYNC "Low" level
DTST: Data transfer startup time
Note: Use the high-speed write mode (either HWM or LHWM = "1") when writing display data to the internal RAM in RGB interface mode
Figure 36: 16-/18-bit RGB Interface Timing
81
LGDP4525
Rev 0.9.0
The timing chart of signals in 6-bit RGB interface mode is as follows.
1 frame
Back porch period
Front porch period
VSYNC
HSYNC
DOTCLK
ENABLE
DB17-12
VLW >= 1H
VSYNC
1H
HLW >= 3CLK
HSYNC
1 clock
DOTCLK
DTST >= HLW
ENABLE
R G B R G
R G B
DB17-12
Valid data
VLW: VSYNC "Low" level
HLW: HSYNC "Low" level
DTST: Data transfer startup time
Note 1) Use the high-speed write mode (either HWM or LHWM = "1") when writing display data to the internal RAM in RGB interface mode
Note 2) In 6-bit RGB interface mode, RGB dots are transferred each in synchronization with one DOTCLK input.
For this reason, set the cycle of each signal (HSYNC, VSYNC, ENABLE) to contain DOTCLK inputs of a multiple of 3.
Figure 37: 6-bit RGB Interface Timing
82
LGDP4525
Rev 0.9.0
Moving Picture Display
The LGDP4525 has the RGB interface for moving picture display and incorporates RAM for
storing moving picture data, which has following merits in displaying a moving picture.
•
•
•
•
The window address function enables transferring minimum necessary data to be
written on the moving picture RAM area.
Data are transferred only to the moving picture RAM area.
The reduction in data transfer contributes to the reduction in power consumption by the
entire system.
Allowing the use of system interface to rewrite data, such as icons, in still picture RAM
area while displaying a moving picture.
RAM Access via a System Interface in RGB-I/F Mode
The LGDP4525 allows RAM access via the system interface in RGB interface mode. In RGB
interface mode, data are written to the internal RAM in synchronization with DOTCLK while
ENABLE is “Low”. When writing data to the internal RAM via the system interface, set ENABLE
high” to stop writing data via the RGB interface. Then set RM = “0” to make RAM accessible via
the system interface. When restarting RAM access in RGB interface mode, wait a time for one
read/write bus cycle. Then, set RM = “1” and the index register to R22h to start accessing RAM
via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that
data are written to the internal RAM.
The following figure illustrates the operation of the LGDP4525 when displaying a moving picture
via the RGB interface and rewriting data in the still picture RAM area via the system interface.
Figure 38 RAM Access via a system interface and RGB interface
83
LGDP4525
Rev 0.9.0
6-Bit RGB Interface
The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. The display operation is
synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the
internal RAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12])
according to the data enable signal (ENABLE). Unused pins (DB[11:0]) must be fixed at either
VDD3 or GND level.
Instructions are set only via the system interface.
VSYNC
HSYNC LGDP4525
DOTCLK
ENABLE
LCDC
DB[17:12]
6
Figure 39: 6-bit RGB interface
6-bit RGB interface (262k colors)
1st transfer
2nd transfer
3rd transfer
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 40: Data format for 6-bit interface
84
LGDP4525
Rev 0.9.0
Data Transfer Synchronization in 6-Bit RGB Interface Mode
The LGDP4525 has data transfer counters for counting the first, second, third data transfers in
6-bit RGB interface mode. The transfer counters are always reset to the state of first data
transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer,
the counters are reset to the state of first data transfer at the start of the frame (i.e. on the falling
edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is
expedient for moving picture display, which requires consecutive data transfer in light of
minimizing effects from failed data transfer and enabling the system to return to a normal state.
Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of
DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of
3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as
the next frame.
VSYNC
ENABLE
DOTCLK
PD17-12
2nd
Transfer
Transfer synchronization
1st
2nd
3rd
1st
2nd
Transfer Transfer Transfer Transfer Transfer
Figure 41: 6-bit data transmission synchronization
85
LGDP4525
Rev 0.9.0
16-Bit RGB Interface
The 16-bit RGB interface is selected by setting the RIM1-0 bits to “01”. The display operation is
synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the
internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-10,
DB8-1) according to the data enable signal (ENABLE).
Instructions are set only via the system interface.
VSYNC
HSYNC LGDP4525
DOTCLK
ENABLE
LCDC
DB[17:10], DB[8:1]
16
Figure 42: 16-bit RGB interface
16-bit RGB interface (65k colors)
GRAM data
DB DB DB DB DB
17 16 15 14 13
DB DB DB DB DB DB DB DB DB DB DB
11 10 9
8
7
6
5
4
3
2
1
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 43: Data format for 16-bit interface
86
LGDP4525
Rev 0.9.0
18-Bit RGB Interface
The 18-bit RGB interface is selected by setting the RIM1-0 bits to “00”. The display operation is
synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the
internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0])
according to the data enable signal (ENABLE).
Instructions are set only via the system interface.
VSYNC
HSYNC LGDP4525
DOTCLK
ENABLE
LCDC
DB[17:0]
18
Figure 44: 18-bit RGB interface
18-bit RGB interface (262k colors)
GRAM data
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RGB
Arrangement
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Figure 45: Data format for 18-bit interface
87
LGDP4525
Rev 0.9.0
Notes in Using the External Display Interface
1. The following are the functions not available in external display interface mode.
Table 57
Function
Partial display
Scroll function
Interlaced scan
Graphics operation function
External display interface
Not available
Not available
Not available
Not available
Internal display operation
Available
Available
Available
Available
2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display
operation period.
3. The periods set with the NO1-0 bits (gate output non-overlap period), STD1-0 bits
(source output delay period) and EQ1-0 bits (equalization period) are not based on the
internal clock but based on DOTCLK in RGB interface mode.
4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a
DOTCLK input. In other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure
to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode.
5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are
transferred in units of 3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit
interface mode (VSYNC, HSYNC ENABLE, DB[17:0]) to contain DOTCLK inputs of a
multiple of 3 to complete data transfer in units of pixels.
6. When switching from the internal operation mode to the external display interface mode,
or the other way around, follow the sequence below.
7. In RGB interface mode, the front porch period continues until the next VSYNC input is
detected after drawing one frame.
8. In RGB interface mode, a RAM address (AD15-0) is set in the address counter every
frame on the falling edge of VSYNC.
Figure 46: Internal clock operation/RGB interface mode switching sequence
88
LGDP4525
Rev 0.9.0
Figure 47: Switching RAM access modes (between system interface and RGB interface
modes)
89
LGDP4525
Rev 0.9.0
Interfacing Timing with LCD Panel
The following are diagrams of interfacing timing with LCD panel control signals in internal
operation and RGB interface modes.
RGB I/F Mode
Figure 48 RGB Inteface Timing Diagram
90
LGDP4525
Rev 0.9.0
Internal Clock Operation Mode
Figure 49 : Internal Clock Operation Timing diagram
91
LGDP4525
Rev 0.9.0
Scan Mode Setting
SM
0
GS
0
Scan direction
Odd-numbered
lines
G1
G2
Even-numbered
lines
G1, G2, G3, G4, …,
G218, G219, G220
TFT panel
G219
G1
G220
G219
G220
G2
LGDP4525
0
1
Odd-numbered
lines
G1
G2
Even-numbered
lines
G220, G219, G218,
…, G4, G3, G2, G1
TFT panel
G219
G1
G220
G219
G220
G2
LGDP4525
1
0
G1
G1, G3, G5, …,
G217, G219,
G2, G4, G6, …,
G218, G220
TFT panel
G219
G2
G220
G1
G219
G220
G2
LGDP4525
1
1
G1
G220, G218, G216,
…, G6, G4, G2,
G219, G217, G215,
…, G5, G3, G1
TFT panel
G219
G2
G220
G1
G219
G220
G2
LGDP4525
Figure 50
92
LGDP4525
Rev 0.9.0
γ-Correction Function
The LGDP4525 has the γ-correction function to display in 262,144 colors simultaneously. The γcorrection is performed with 3 groups of registers determining eight reference grayscale levels,
which are gradient adjustment, amplitude adjustment and fine-adjustment registers. Each
register groups further consists of register groups of positive and negative polarities. Each
register group is set independently to other register groups, making the LGDP4525 available
with liquid crystal panels of various characteristics.
Display
data
Positive
Polarity
Register
Negative
Polarity
Register
VRN03
VRN14 VRN13
PFP01
PFP11
PFP21
PMP01
PKP01
PKP11
PKP21
PKP31
PKP41
PKP51
PRP01
PRP11
VRP01
VRP11
PFP00
PFP10
PFP20
PMP00
PKP00
PKP10
PKP20
PKP30
PKP40
PKP50
PRP00
PRP10
VRP00
VRP10
PFN02
PFN12
PFN22
PMN02
PKN02
PKN12
PKN22
PKN32
PKN42
PKN52
PRN02
PRN12
VRN02
VRN12
PFN01
PFN11
PFN21
PMN01
PKN01
PKN11
PKN21
PKN31
PKN41
PKN51
PRN01
PRN11
VRN01
VRN11
PFN00
PFN10
PFN20
PMN00
PKN00
PKN10
PKN20
PKN30
PKN40
PKN50
PRN00
PRN10
VRN00
VRN10
6
6
6
V0
8
Grayscale Amplifier
VRP14
VRP03
VRP13
PFP02
PFP12
PFP22
PMP02
PKP02
PKP12
PKP22
PKP32
PKP42
PKP52
PRP02
PRP12
VRP02
VRP12
V1
64-level grayscale
64-level grayscale
Control <R>
Control <G>
64-level grayscale
Control <B>
LCD driver
LCD driver
LCD driver
64
V63
Figure 51
93
LGDP4525
Rev 0.9.0
Grayscale Amplifier Unit Configuration
The following figure illustrates the grayscale amplifier unit of the LGDP4525.
To generate 64 grayscale voltages (V0 to V63), the LGDP4525 first generates eight reference
grayscale voltages (VINP0-7/VINN0-7). The grayscale amplifier unit then divides eight reference
grayscale voltages with the ladder resistors incorporated therein.
Increment
Adjustment
PRP/N0
GVDD
3
3
3
3
Amplitude
Adjustment
Fine Adjustment(6 X 3 bits)
PFP/N0 PFP/N1 PMP/N0 PFP/N2
PRP/N0
3
PFP/N3
3
3
PKP/N0
3
PKP/N1
3
PKP/N2
3
PKP/N3
3
PKP/N4 PKP/N5
3
3
VRP/N0
VRP/N1
5
5
VINP0
/VINN0
V0
V1
VINP1
/VINN1
8 to 1
Selector
V2
VINP2
/VINN2
8 to 1
Selector
VINP3
/VINN3
8 to 1
Selector
VINP4
/VINN4
8 to 1
Selector
VINP5
/VINN5
8 to 1
Selector
8 to 1
Selector
VINP6
/VINN6
V61
VINP7
/VINN7
V62
V63
VGS
Figure 52: Grayscale amplifier unit
94
LGDP4525
GVDD
Rev 0.9.0
VRP0
0-31R
VRN0
0-31R
VR0P
3R~24R
VR0N
3R~24R
4R*7
8to1
SEL
VRHP
0-28R
1R*7
8to1
SEL
8to1
SEL
8to1
SEL
VGS
1R*7
8to1
SEL
1R*7
8to1
SEL
VR2N
3R~24R
8to1
SEL
VRLP
0-28R
4R*7
8to1
SEL
VRMN
8R~64R
VR2P
3R~24R
1R*7
1R*7
VR1N
3R~24R
VRMP
8R~64R
1R*7
8to1
SEL
VRHN
0-28R
VR1P
3R~24R
1R*7
4R*7
1R*7
8to1
SEL
VRLN
0-28R
8to1
SEL
4R*7
VR3P
3R~24R
VR3N
3R~24R
VRP1
0-31R
VRN1
0-31R
8R
8R
8to1
SEL
Figure 53: Ladder resistor units and 8-to-1 selectors
95
LGDP4525
Rev 0.9.0
γ-Correction Register
Grayscale voltage
Grayscale voltage
Grayscale voltage
The γ-correction registers of the LGDP4525 consist of gradient adjustment, amplitude
adjustment, and fine adjustment registers, each of which has registers of positive and negative
polarities. Each different register group can be set independently to others, enabling adjustment
of grayscale voltage levels in relation to grayscales set optimally for γ-characteristics of a liquid
crystal panel. These γ-correction register settings and the reference levels of the 64 grayscales
to which the three kinds of adjustments are made (bold lines in the following figure) are common
to all RGB dots.
Figure 54
1. Gradient adjustment registers
The gradient adjustment registers are used to adjust the gradient of the curve representing the
relationship between the grayscale and the grayscale voltage level around middle grayscales
without changing the dynamic range. To adjust the gradient, the resistance values of grayscale
reference voltage generating variable resistors (VRHP(N)/VRLP(N)) in the middle of the ladder
resistor unit are adjusted. The registers consist of positive and negative polarity registers,
allowing asymmetric drive.
2. Amplitude adjustment registers
The amplitude adjustment registers are used to adjust the amplitude of grayscale voltages. To
adjust the amplitude, the resistance values of the grayscale voltage generating variable
resistors (VRP(N)1/0) at the top and bottom of the ladder resistor unit are adjusted. Same with
the gradient registers, the amplitude adjustment registers consist of positive and negative
polarity registers.
3. Fine adjustment registers
The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust
grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels
for each register generated from the ladder resistor unit, in respective 8-to-1 selectors. Same
with other registers, the fine adjustment registers consist of positive and negative polarity
registers.
96
LGDP4525
Rev 0.9.0
Table 58
Register
Groups
Gradient
adjustment
Amplitude
adjustment
Fine
adjustment
Positive
Polarity
PRP0[2:0]
PRP1[2:0]
PFP0[2:0]
PFP1[2:0]
PFP2[2:0]
PFP3[2:0]
PMP[2:0]
VRP0[3:0]
VRP1[4:0]
PKP0[2:0]
PKP1[2:0]
PKP2[2:0]
PKP3[2:0]
PKP4[2:0]
PKP5[2:0]
Negative
Polarity
PRN0[2:0]
PRN1[2:0]
PFN0[2:0]
PFN1[2:0]
PFN2[2:0]
PFN3[2:0]
PMN[2:0]
VRN0[3:0]
VRN1[4:0]
PKN0[2:0]
PKN1[2:0]
PKN2[2:0]
PKN3[2:0]
PKN4[2:0]
PKN5[2:0]
Description
Variable resistor VRHP(N)
Variable resistor VRHP(N)
Variable resistor VR0P(N)
Variable resistor VR1P(N)
Variable resistor VR2P(N)
Variable resistor VR3P(N)
Variable resistor VRMP(N)
Variable resistor VRP(N)0
Variable resistor VRP(N)1
8-to-1 selector ( voltage level of grayscale 1)
8-to-1 selector ( voltage level of grayscale 8)
8-to-1 selector ( voltage level of grayscale 20)
8-to-1 selector ( voltage level of grayscale 43)
8-to-1 selector ( voltage level of grayscale 55)
8-to-1 selector ( voltage level of grayscale 62)
97
LGDP4525
Rev 0.9.0
Ladder Resistors and 8-to-1 Selector
Block Configuration
The reference voltage generating unit as illustrated in page 100 consists of two ladder resistor
units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8
voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage.
Both variable resistors and 8-to-1 selectors are controlled according to the γ correction registers.
This unit has pins to connect a volume resistor externally to compensate differences in various
characteristics of panels.
Variable Resistors
The LGDP4525 uses variable resistors of the following three purposes: gradient adjustment
(VRHP(N)/VRLP(N)); amplitude adjustment (1) (VRP(N)0); and the amplitude adjustment (2)
(VRP(N)1). The resistance values of these variable resistors are set by gradient adjustment
registers and amplitude adjustment registers as follows.
Table 59:
Gradient adjustment(1)
Gradient adjustment(2)
Gradient adjustment(3)
Contents of
register
PRP(N)0/1[2:0]
000
001
010
011
100
101
110
111
Contents of
register
PFP0/1/2/3(N)
000
001
010
011
100
101
110
111
Contents of
register
VRP(N)1[4:0]
000
001
010
011
100
101
110
111
Resistance
VRHP(N)
VRLP(N)
0R
4R
8R
12R
16R
20R
24R
28R
Resistance
VR0/1P(N)
VR2/3P(N)
3R
6R
9R
12R
15R
18R
21R
24R
Resistance
VRMP(N)
8R
16R
24R
32R
40R
48R
56R
64R
Table 60:
Amplitude adjustment
Contents of
register
VRP(N)0[4:0]
00000
00001
00010
:
:
11101
11110
11111
Resistance
VRP(N)0
VRP(N)1
0R
1R
2R
:
:
29R
30R
31R
8-to-1 Selectors
The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit
according to the fine adjustment register, and output the selected voltage level as a reference
grayscale voltage (VINP(N)1~ VINP(N 6). The table below shows the setting in the fine
adjustment register and the selected voltage levels for respective reference grayscale voltages
98
LGDP4525
Rev 0.9.0
Table 61: Fine adjustment registers and selected voltage
PKP(N)[2:0]
0
1
2
3
4
5
6
7
Selected Voltage
VINP(N)1
VINP(N)2
KVP(N)1
KVP(N)9
KVP(N)2
KVP(N)10
KVP(N)3
KVP(N)11
KVP(N)4
KVP(N)12
KVP(N)5
KVP(N)13
KVP(N)6
KVP(N)14
KVP(N)7
KVP(N)15
KVP(N)8
KVP(N)16
VINP(N3
KVP(N)17
KVP(N)18
KVP(N)19
KVP(N)20
KVP(N)21
KVP(N)22
KVP(N)23
KVP(N)24
VINP(N)4
KVP(N)25
KVP(N)26
KVP(N)27
KVP(N)28
KVP(N)29
KVP(N)30
KVP(N)31
KVP(N)32
VINP(N)5
KVP(N)33
KVP(N)34
KVP(N)35
KVP(N)36
KVP(N)37
KVP(N)38
KVP(N)39
KVP(N)40
VINP(N)6
KVP(N)41
KVP(N)42
KVP(N)43
KVP(N)44
KVP(N)45
KVP(N)46
KVP(N)47
KVP(N)48
99
LGDP4525
Rev 0.9.0
The grayscale voltage levels for V0~V63 grayscales are calculated from the following formulae.
Table 62: Formulae for calculating voltage (1)
Pin
Formula
Fine
adjustment
register
value
KVP0
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
KVP9
KVP10
KVP11
KVP12
KVP13
KVP14
KVP15
KVP16
KVP17
KVP18
KVP19
KVP20
KVP21
KVP22
KVP23
KVP24
KVP25
KVP26
KVP27
KVP28
KVP29
KVP30
KVP31
KVP32
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
KVP49
GVDD - ∆V*VRP0/SUMRP
GVDD - ∆V*(VRP0+VR0P+0R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+4R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+8R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+12R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+16R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+20R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+24R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+28R)/SUMRP
GVDD - ∆V*(VRP0+VR0P+28R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+29R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+30R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+31R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+32R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+33R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+34R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0P+35R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+35R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+36R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+37R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+38R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+39R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+40R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+41R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+42R+VRHP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+42R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+43R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+44R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+45R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+46R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+47R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+48R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1P+49R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+49R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+50R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+51R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+52R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+53R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+54+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+55R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+56R+VRHP +VRMP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+56R+VRHP +VRMP+VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+60R+VRHP +VRMP+VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+64R+VRHP +VRMP+VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+68R+VRHP +VRMP+VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+72R+VRHP +VRMP+VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+76R+VRHP+VRMP +VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+80R+VRHP+VRMP +VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2P+84R+VRHP+VRMP +VRLP)/SUMRP
GVDD - ∆V*(VRP0+VR0/1/2/3P+84R+VRHP+VRMP +VRLP)/SUMRP
PKP0= 0
PKP0= 1
PKP0= 2
PKP0= 3
PKP0= 4
PKP0= 5
PKP0= 6
PKP0= 7
PKP1= 0
PKP1= 1
PKP1= 2
PKP1= 3
PKP1= 4
PKP1= 5
PKP1= 6
PKP1= 7
PKP2= 0
PKP2= 1
PKP2= 2
PKP2= 3
PKP2= 4
PKP2= 5
PKP2= 6
PKP2= 7
PKP3= 0
PKP3= 1
PKP3= 2
PKP3= 3
PKP3= 4
PKP3= 5
PKP3= 6
PKP3= 7
PKP4= 0
PKP4= 1
PKP4= 2
PKP4= 3
PKP4= 4
PKP4= 5
PKP4= 6
PKP4= 7
PKP5= 0
PKP5= 1
PKP5= 2
PKP5= 3
PKP5= 4
PKP5= 5
PKP5= 6
PKP5= 7
-
Referenc
e
voltage
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Sum of positive ladder resistors =
92R+VRHP+VRLP+VRP0+VRP1+VR0P+VR1P+VR2P
+VR3P+VRMP
∆V : Difference in electrical potential between VDH and VGS
100
LGDP4525
Rev 0.9.0
Table 63: Formulae for calculating voltage (2)
Grayscal
e
voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
Formula
VINP0
VINP1
VINP2+(VINP1-VINP2)*(30/48)
VINP2+(VINP1-VINP2)*(23/48)
VINP2+(VINP1-VINP2)*(16/48)
VINP2+(VINP1-VINP2)*(12/48)
VINP2+(VINP1-VINP2)*(8/48)
VINP2+(VINP1-VINP2)*(4/48)
VINP2
VINP3+(VINP2-VINP3)*(22/24)
VINP3+(VINP2-VINP3)*(20/24)
VINP3+(VINP2-VINP3)*(18/24)
VINP3+(VINP2-VINP3)*(16/24)
VINP3+(VINP2-VINP3)*(14/24)
VINP3+(VINP2-VINP3)*(12/24)
VINP3+(VINP2-VINP3)*(10/24)
VINP3+(VINP2-VINP3)*(8/24)
VINP3+(VINP2-VINP3)*(6/24)
VINP3+(VINP2-VINP3)*(4/24)
VINP3+(VINP2-VINP3)*(2/24)
VINP3
VINP4+(VINP3-VINP4)*(22/23)
VINP4+(VINP3-VINP4)*(21/23)
VINP4+(VINP3-VINP4)*(20/23)
VINP4+(VINP3-VINP4)*(19/23)
VINP4+(VINP3-VINP4)*(18/23)
VINP4+(VINP3-VINP4)*(17/23)
VINP4+(VINP3-VINP4)*(16/23)
VINP4+(VINP3-VINP4)*(15/23)
VINP4+(VINP3-VINP4)*(14/23)
VINP4+(VINP3-VINP4)*(13/23)
VINP4+(VINP3-VINP4)*(12/23)
Grayscale
voltage
V32
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
V43
V44
V45
V46
V47
V48
V49
V50
V51
V52
V53
V54
V55
V56
V57
V58
V59
V60
V61
V62
V63
Formula
VINP4+(VINP3-VINP4)*(11/23)
VINP4+(VINP3-VINP4)*(10/23)
VINP4+(VINP3-VINP4)*(9/23)
VINP4+(VINP3-VINP4)*(8/23)
VINP4+(VINP3-VINP4)*(7/23)
VINP4+(VINP3-VINP4)*(6/23)
VINP4+(VINP3-VINP4)*(5/23)
VINP4+(VINP3-VINP4)*(4/23)
VINP4+(VINP3-VINP4)*(3/23)
VINP4+(VINP3-VINP4)*(2/23)
VINP4+(VINP3-VINP4)*(1/23)
VINP4
VINP5+(VINP4-VINP5)*(22/24)
VINP5+(VINP4-VINP5)*(20/24)
VINP5+(VINP4-VINP5)*(18/24)
VINP5+(VINP4-VINP5)*(16/24)
VINP5+(VINP4-VINP5)*(14/24)
VINP5+(VINP4-VINP5)*(12/24)
VINP5+(VINP4-VINP5)*(10/24)
VINP5+(VINP4-VINP5)*(8/24)
VINP5+(VINP4-VINP5)*(6/24)
VINP5+(VINP4-VINP5)*(4/24)
VINP5+(VINP4-VINP5)*(2/24)
VINP5
VINP6+(VINP5-VINP6)*(44/48)
VINP6+(VINP5-VINP6)*(40/48)
VINP6+(VINP5-VINP6)*(36/48)
VINP6+(VINP5-VINP6)*(32/48)
VINP6+(VINP5-VINP6)*(25/48)
VINP6+(VINP5-VINP6)*(18/48)
VINP6
VINP7
Note: Make sure AVDD-V0 > 0.5V
101
LGDP4525
Rev 0.9.0
Relationship between RAM Data and Voltage Output Levels
The relationship between RAM data and source output voltage levels is as follows. See also
Table 47: GRAM data and LCD output level.
Negative polarity
V0
V63
Positive polarity
000000
RAM data
(Common for each RGB pixel)
111111
Figure 55: RAM data and the output voltage (REV = “0”)
Sn
Negative polarity
VCOM
Positive polarity
Figure 56: Source output and VCOM
102
LGDP4525
Rev 0.9.0
8-Color Display Mode
`The LGDP4525 has a function to display in 8colors. In 8-color mode, available grayscale levels
are V0 and V63, and the power supplies of other grayscales (V1 to V62) are halted to reduce
power consumption.
In 8-color display mode, the MSBs of the respective dot data (R5, G5, B5) are written to the rest
of the dot data in order to display in 8 colors without rewriting the RAM data.
The γ- correction registers, PKP0-PKP5 and PKN0-PKN5, are disabled in 8-color display mode.
Display
data
Positive
Polarity
Register
VRP03
VRP14 VRP13
Negative
Polarity
Register
VRN03
VRN14 VRN13
PFP02
PFP12
PFP22
PMP02
PKP02
PKP12
PKP22
PKP32
PKP42
PKP52
PFP01
PFP11
PFP21
PMP01
PKP01
PKP11
PKP21
PKP31
PKP41
PKP51
PFP00
PFP10
PFP20
PMP00
PKP00
PKP10
PKP20
PKP30
PKP40
PKP50
PRP02
PRP12
VRP02
VRP12
PRP01
PRP11
VRP01
VRP11
PRP00
PRP10
VRP00
VRP10
PFN02
PFN12
PFN22
PMN02
PKN02
PKN12
PKN22
PKN32
PFN01
PFN11
PFN21
PMN01
PKN01
PKN11
PKN21
PKN31
PFN00
PFN10
PFN20
PMN00
PKN00
PKN10
PKN20
PKN30
PKN42
PKN52
PRN02
PRN12
VRN02
VRN12
PKN41
PKN51
PRN01
PRN11
VRN01
VRN11
PKN40
PKN50
PRN00
PRN10
VRN00
VRN10
6
6
6
V0
2- level grayscale2- level grayscale 2- level grayscale
Control <R>
Control <G>
Control <B>
8
2
LCD driver
LCD driver
LCD driver
V63
Figure 57
103
LGDP4525
Rev 0.9.0
To switch between the 262,144-color mode and 8-color mode, follow the sequence below.
262,144 color to 8 color mode
8 color to 262,144 color mode
Display OFF
GON = 1
DTE = 1
D1-0 = 10
Display OFF
GON = 1
DTE = 1
D1-0 = 10
Wait for lat least 2 frames
Wait for lat least 2 frames
Display OFF
GON = 1
DTE = 0
D1-0 = 10
Display OFF
GON = 1
DTE = 0
D1-0 = 10
Wait for lat least 2 frames
Wait for lat least 2 frames
Display OFF
GON = 0
DTE = 0
D1-0 = 00
Display OFF
GON = 0
DTE = 0
D1-0 = 00
RAM setting
RAM setting
CL = 1
CL = 0
Wait for at least 40 ms
Wait for at least 40 ms
Display ON
GON = 0
DTE = 0
D1-0 = 01
Display ON
GON = 0
DTE = 0
D1-0 = 01
Wait for lat least 2 frames
Wait for lat least 2 frames
Display ON
GON = 1
DTE = 0
D1-0 = 01
Display ON
GON = 1
DTE = 0
D1-0 = 01
Display ON
GON = 1
DTE = 0
D1-0 = 11
Display ON
GON = 1
DTE = 0
D1-0 = 11
Wait for lat least 2 H periods
Wait for lat least 2 H periods
Display ON
GON = 1
DTE = 1
D1-0 = 11
Display ON
GON = 1
DTE = 1
D1-0 = 11
8 color mode display ON
262,144 color mode display ON
Figure 58
104
LGDP4525
Rev 0.9.0
Configuration of Power Supply Circuit
The follow are the configuration of power supply circuit to generate liquid crystal panel drive
levels.
CB9
GVDD
VCOMR
VGH
Voltage
adjustment
circuit
VCI
CB1
VCI1
Gate
driver
G1-220
Source
driver
S1-528
VCI1
AMP
Grayscale
voltage
generation
circuit
VCOMH
adjustment
circuit
C11P
C12M
see
Note 4 C12
VGL
REGP
C11M
C11
Amplifier1
( VDH
adjustment )
C12P
Step-up
Circuit 1
VCOMH
output
AMP
AVDD
CB2
VCOMH
CB6
VCOM
C31M
see
Note 1
C31
D1
VCOM
amplitude
adjustment
C31P
C21M
C21
Step-up
Circuit 2
VCI
C22P
VGH
see
Note 1,2
CB7
see
Note 3
VREF
VREF_BUF
RVDD
VDD
Regulator
IREF/VREF
D2
VGL
Bandgap
Reference
VCI
CB3
CB4
VCOML
C21P
C22M
C22
VCOML
output
AMP
VDD
CB8
VSSC, AVSS, VSS
VCL
OSC1
CB5
RC-OSC
OSC2
Rf
Note 1) Place a shottkey diode ( VF=about 0.4/20mA, VR = 80V )
Note 2) The Wiring resistance between GND or VGL to the shottkey diode must be 10 or less
Note 3) Capacitor connection is unnecessary when operating at VCOMG = 0 ( VcomL = GND )
Note 4) Capacitor connection is necessary only when operating at dual step up1 mode
Figure 59
105
LGDP4525
Rev 0.9.0
Specification of External Elements Connected to LGDP4525 Power Supply
The follow table shows specifications of external element connected to the LGDP4525’s power
supply circuit.
Table 64: Capacitor
Capacity
1uF
(B
characteristics)
Recommended
voltage
6V
10V
25V
Pin connection
VCI1, C11P/M , C12P/M, C31P/M, VCL(see note), VCOML
(see note), VDD
GVDD, VCOMH, AVDD, C21P/M , C22P/M
VGH, VGL
Note: Capacitor connection is not necessary in some operation modes.
Table 65: Schottky diode
Feature
VF < 0.4V/20mA at 25°C , VR>30V
Pin connection
GND – VGL
AVDD – VGH
Table 66: Variable resistor
Feature
> 200k　Pin connection
VCOMR
106
LGDP4525
Rev 0.9.0
Instruction Setting
When setting the following instructions, follow respective sequences below.
Display On/Off
Display off
Display on
Power supply
EQ = 0
SAP2-0 setting
Display off
GON = 1
DTE = 1
D1-0 = 10
Wait (2 frames or more)
Display off
GON = 1
DTE = 0
D1-0 = 10
Wait (2 frames or more)
Display off
GON = 0
DTE = 0
D1-0 = 00
Power supply off
SAP2-0 = 000
AP2-0 = 000
PON = 0
VOMG = 0
Display on
VCOM_INIT1-0 = 00
GON = 0
DTE = 0
D1-0 = 01
Wait (2 frames or more)
Display on
GON = 1
DTE = 0
D1-0 = 01
Display on
GON = 1
DTE = 0
D1-0 = 11
Wait (2 frames or more)
Display on
GON = 1
DTE = 1
D1-0 = 11
Display off
Display on
Display off flow
Display on flow
Figure 60
107
LGDP4525
Rev 0.9.0
Standby and Sleep Modes
Standby
Sleep
Display off sequence
Display off sequence
Sleep
set
Standby
set
Standby set (STB=1)
Sleep set (SLP=1)
Oscillation Start
Wait 10 ms
Standby
canceled
Sleep canceled (SLP = 0)
Sleep
canceled
Standby canceled (STB = 0)
Power setting
Power setting
Display on flow
Display on flow
Figure 61
Deep Standby Mode
Deep Standby
Display off sequence
Deep Standby
set
Deep Standby set
(DSTB=1)
6 times CSB=0
Wait 10 ms
Exit from
Deep Standby and internal reset
generated.
Initial instruction setting
Ram data setting
Display on sequence
Figure 62
108
LGDP4525
Rev 0.9.0
Power Supply Setting
When supplying and cutting off power, follow the sequence below. The setting time for
oscillators, step-up circuits and operational amplifiers depends on external resistance and
capacitance.
Power supply(VCI,
VDD3) ON
Normal Display
VCI
VDD3
Display ON setting
DTE = 1, D =11
GON = 1
GND
Display OFF sequence
VDD3 => VCI
Or VDD3, VCI
simultaneously
Display OFF
1 ms
Or more
Power ON reset &
Display OFF
10 ms
Or more
Display OFF setting bits
DTE = 0, D=00, GON = 0
PON= 0, VCOMG=0
Oscillating circuit
Stabilizing period
Instructions before starting
Up power supply
Instructions for starting
Up Power supply(1)
Power supply(VCI,
VDD3) ON
Power supply initial setting
bits
Set VC2-0,VRH3-VCM4-0 ,
VDV4-0, PON="0”, DK="1"
Power Supply Operation Start
setting bits
BT2-0="000", Set DC12-10,
DC02-0, AP2-0, PON = 1
Step-up
Circuit
Stabilizing
Period
VCI
VDD3
GND
VDD3 => VCI
Or VDD3, VCI
simultaneously
Power supply
halt
Setting bits
SAP2-0 = 000
AP2-0 = 000,
PON = 0
VCOMG = 0
Power OFF sequence
40ms or more
Instructions for starting
Up Power supply(2)
OP-amp
Stabilizing
period
Instruction for Power supply
setting
Instructions for other mode
settings
Power Supply Operation Start
setting bits
VCOMG = 1
DK="0"
Set BT2-0
100 ms
Or more
Display ON
sequence
Set SAP2-0 bits
Display ON
Display ON setting bit
DTE=1 , D0-1=11
GON=1
Power ON sequence
Figure 63
109
LGDP4525
Rev 0.9.0
Pattern Diagram for Voltage Setting
The pattern diagram for the voltages and the waveforms of the voltages of the LGDP4525 are
as follows.
Figure 64
Note: The AVDD, VGH, VGL, and VCL output voltage levels are lower than their theoretical
levels ( ideal voltage levels ) due to current consumption at respective output. The voltage
levels in the following relationships (AVDD – GVDD) > 0.5V, (VCOML – VCL) > 0.5V are the
actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts
every line cycle), current consumption is large. In this case, check the voltage before use.
Figure 65: Applied voltage to the TFT display
110
LGDP4525
Rev 0.9.0
Oscillator
The LGDP4525 generates oscillation with the LGDP4525’s internal RC oscillators both without
an external resistor and with resistor by placing an external oscillation resistor between the
OSC1 and OSC2 pins. The oscillation frequency varies due to resistance value of external
resistor, wiring distance, and operating supply voltage. For example, placing an Rf resistor of a
larger resistance value, or lowering the supply voltage level brings down the oscillation
frequency. See the “Notes to Electrical Characteristics” section for the relationship between
resistance value of Rf resistor and oscillation frequency.
Figure 66
111
LGDP4525
Rev 0.9.0
n-Line Inversion AC Drive
The LGDP4525, in addition to the frame-inversion liquid crystal AC drive, supports the n-line
inversion AC drive, in which the polarity of liquid crystal is inverted in units of n lines, where n
takes a number from 1 to 64. The quality of display will be improved by using n-line inversion
AC drive.
In determining n (the value set with the NW bits +1), which represents the number of lines that
determines the timing of liquid crystal polarity inversion, check the quality of display on the liquid
crystal panel in use. Note that setting a smaller number of lines will raise the frequency of liquid
crystal polarity inversion and increase charging/discharging current on liquid crystal cells.
Figure 67
112
LGDP4525
Rev 0.9.0
Interlaced Scan
The LGDP4525 supports interlaced scan for driving a frame by splitting it into n fields in order to
prevent flicker.
To determine the number of fields (n: value set with the FLD bits), check the quality of display
on the liquid crystal panel in use. The following table shows the scanned (gate) lines in each
field. When FLD[1:0] = “01”, the number of fields in one frame is one. When FLD[1:0] = “11”, the
number of fields in one frame is three. The figure illustrates the output waveforms of 3-field
interlaced scan.
Table 67: Interlaced scan (GS = “0”)
Table 68: Interlaced scan (GS = “1”)
FLD[1:0]
FLD[1:0]
Field
01
-
Gate
G1
G2
G3
G4
G5
G6
G7
G8
:
G217
G218
G219
G220
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
11
2
3
Field
Gate
G220
G219
G218
G217
G216
G215
G214
G213
:
G4
G3
G2
G1
*
*
*
*
*
*
*
*
*
*
01
-
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
11
2
3
*
*
*
*
*
*
*
*
*
*
*: scanned gate lines
Alternating
polarity
Field 1
1 frame
Blank period
Field 2
Field 3
Field 1
G1
G2
G3
G4
G5
G6
•••
G(3n+1)
G(3n+2)
G(3n+3)
Figure 68: Gate output timing of 3-field interlaced scan
113
LGDP4525
Rev 0.9.0
Alternating Timing
The following figure illustrates the timing of liquid crystal polarity inversion in different driving
formulae. In case of frame-inversion AC drive, the polarity is inverted after drawing one frame,
followed by a blank period lasting for a 16H period, where all outputs from the gate lines
become the VGL level. In case of 3-field interlaced scan, polarity is inverted after drawing one
field, followed by blank periods that add up to a 16H period in one frame. In case of n-line
inversion AC drive, polarity is inverted as drawing n lines, and a blank period lasting for a 16H
period is inserted after drawing one frame.
1 frame period
In the interlaced scan, be sure to set the numbers of back and front porches as follows: BP = 3,
FP = 5.
Figure 69
114
LGDP4525
Rev 0.9.0
Frame Frequency Adjustment Function
The LGDP4525 has a frame frequency adjustment function. The frame frequency for driving
LCDs can be adjusted by instructions (using the DIV, RTN bits) without changing the oscillation
frequency.
To switch frame frequencies between when displaying a moving picture and when displaying a
still picture, set a high oscillation frequency in advance. By doing so, it becomes possible to set
a low frame frequency when displaying a still picture for saving power consumption and to set a
high frame frequency when displaying a moving picture.
Relationship between Liquid Crystal Drive Duty and Frame Frequency
The relationship between the liquid crystal drive duty and the frame frequency is calculated from
the following formula. The frame frequency is adjusted by instruction using the 1H period
adjustment bits (RTN bits) and the operation clock division bits (DIV bits).
frame frequency =
fosc
clock cycles per line * division ratio * (Line + BP + FP)
where
fosc = RC oscillation frequency,
Line = number of lines to drive the LCD (NL bits),
clock cycle per line = RTN bits,
division ratio: DIV bits,
FP = number of lines for front porch and
BP = number of lines for back porch.
Example of Calculation: when maximum frame frequency = 60 Hz
Number of lines to drive the LCD: 220 lines
1H period: 44 clock cycle (RTN[6:0] = 2Ch)
Operational clock division ratio: 1/1
fosc = 60 Hz × (0 + 44) clocks × 1/1 × (220 + 16) lines = 623 kHz
In this case, the RC oscillation frequency is 676 kHz. Adjust the external resistor of the RC
oscillator to 623 kHz.
115
LGDP4525
Rev 0.9.0
Partial Display Function
The LGDP4525 allows selectively driving two images on the screen at arbitrary positions set in
the screen drive position registers (R42h and R43h). Only the lines for displaying two images
are selectively driven in order to reduce current consumption.
The first display drive position register (R42h) includes the start line setting bits (SS1) and the
end line setting bits (SE1) for displaying the first image. The second display drive position
register (R43h) includes the start line setting bits (SS2) and the end line setting bits (SE2) for
displaying the second image. The second display control is effective when the SPT bit is set to
“1”. The total number of lines driven for displaying the first and second display must be less than
the number of lines set with the NL bits.
G1
1
G7
st
Screen:
7 lines
Non-display
area
G26
G42
OCT 14th 10:18am
nd
2 Screen:
17 lines
Non-display
area
The number of lines to drive LCD panel: NL = 1Eh (220 raster-rows)
st
1 screen setting : SS1 = 00h, SE1 = 06h
nd
2 screen setting : SS2 = 19h, SE2 = 29h, SPT = 1
Figure 70
116
LGDP4525
Rev 0.9.0
Constraints in Setting the 1st/2nd Screen Drive Position Registers
When setting the start line setting bits (SS1[7:0]) and the end line setting bits (SE1[7:0]) of the
first display drive position register (R42h), and the start line setting bits (SS2[7:0]) and the end
line setting bits (SE2[7:0]) of the second display drive position register (R43h), it is necessary to
satisfy the following conditions to display screens correctly.
Table 69: One screen drive (SPT = “0”)
Register Settings
(SE1 – SS1) = NL
(SE1 – SS1) < NL
(SE1 – SS1) > NL
Display Operation
Full screen display
The area of (SE1 – SS1) is normally displayed.
Partial screen display
The area of (SE1 – SS1) is normally displayed.
The rest of the area is a white display irrespective of data in RAM.
Setting disabled
Table 70: Two screen drive (SPT = “1”)
Register Settings
((SE1 – SS1) + (SE2 – SS2)) =
NL
((SE1 – SS1) + (SE2 – SS2)) <
NL
((SE1 – SS1) + (SE2 – SS2)) >
NL
Display Operation
Full screen display
The area of (SE2 – SS1) is normally displayed.
Partial screen display
The area of (SE2 – SS1) is normally displayed.
The rest of the area is a white display irrespective of data in RAM.
Setting disabled
Note 1) Be sure that SS1 ≤ SE1 ≤ SS2 ≤ SE2 ≤ EFh.
Note 2) Be sure that (SE2 – SS1) ≤ NL.
The outputs from the source driver in non-display areas of the partial display can be changed as
follows. Select the appropriate kind of source outputs according to the characteristics of the
display panel.
Table 71
PTS
Source output in non-display area
Positive polarity
Negative polarity
000
001
010
011
100
101
110
111
V63
Setting disabled
GND
High impedance
V63
Setting disabled
GND
High impedance
V0
Setting disabled
GND
High impedance
V0
Setting disabled
GND
High impedance
Operating grayscale
amplifier
in non-display area
V0 to V63
V0 to V63
V0 to V63
V0, V63
V0, V63
V0, V63
Table 72
PTG
00
01
10
11
Gate outputs in non-display area
Normal scan
VGL (fixed)
Interval scan
Setting disabled
Follow the sequences below when using the partial display function.
117
LGDP4525
Rev 0.9.0
Full screen display
PTS = 000
Set SS/SE bits
Partial display drive
setting sequence
Wait for 2 frames or more
As required
PTG = 01 or
PTG = 10 or
PTG = 11
Partial display ON
Set SS/SE bits
Full screen display
setting sequence
Full screen display
Figure 71
118
LGDP4525
Rev 0.9.0
Absolute Maximum Ratings
Item
Power supply voltage (2)
Power supply voltage (3)
Power supply voltage (4)
Power supply voltage (5)
Power supply voltage (6)
Power supply voltage (7)
Input voltage
Operating temperature
Storage temperature
Symbol
VCI, VDD3 – GND
AVDD – GND
GND – VCL
VCI –VCL
VGH – GND
GND – VGL
Vt
Topr
Tstg
Unit
V
V
V
V
V
V
V
˚C
˚C
value
-0.3 ~ +4.2
-0.3 ~ +7.7
-0.3 ~ +4.2
-0.3 ~ +7.7
-0.3 ~ +18
-0.3 ~ +18
-0.3 ~ +4.2
-40 ~ +85
-55 ~ +125
Notes
1, 2, 3
1, 4
1
1, 5
1, 6
1, 7
1
1, 8
1
Notes :
1. If used beyond the absolute maximum ratings, the LSI may permanently be damaged.
It is strongly recommended to use the LSI at a condition within the electrical
characteristics for normal operation. Exposure to a condition not within the electrical
characteristics may affect device reliability.
2. Make sure (High) VCI ≥ GND (Low).
3. Make sure (High) VDD3 ≥ GND (Low).
4. Make sure (High) AVDD ≥ GND (Low).
5. Make sure (High) VCI ≥ VCL (Low).
6. Make sure (High) VGH ≥ GND (Low).
7. Make sure (High) GND ≥ VGL (Low).
8. The DC/AC characteristics of die and wafer products is guaranteed at 85 ℃.
119
LGDP4525
Rev 0.9.0
Electrical Characteristics
DC Characteristics
Table 73: DC Characteristics
Item
Input high-level voltage
Input low-level voltage
Output high-level voltage(1)
( DB17-0, SDO, FLM )
Output high-level voltage(2)
( DB17-0, SDO, FLM )
I/O leakage current
Current consumption:
Standby mode
(VDD3-GND) +(VCI-GND)
Symbo
l
VIH
VIL
Unit
Test Condition
Min.
Typ.
Max
V
V
VDD3=1.65~3.3
VDD3=1.65~3.3
0.8VDD3
-0.3
-
VDD3
0.2VDD3
Note
s
2 ,3
2 ,3
VOH1
V
0.8VDD3
-
-
2
VOL1
V
-
-
0.2VDD3
2
ILi
IST
uA
uA
VDD3=1.65~3.3
IOH =0.1mA
VDD3=1.65~3.3
IOL =0.1mA
Vin=0~VDD3
VDD3=VCI=2.8V
Ta=25℃
-1
-
1.4
1
10
4
5
80-System Bus Interface Timing Characteristics (18/16-Bit Bus)
Table 74 (Condition: VDD3 = 1.65 to 3.30V,VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
Bus cycle time
Write
Read
Write
Read
Write
Read
Write “Low” level pulse width
Read “Low” level pulse width
Write “High” level pulse width
Read “High” level pulse width
Write/Read rise/fall time
Setup time
Write (RS to
CSB/RW_WRB)
Read (RS to
CSB/E_RDB)
Address hold time
Write data setup time
Write data hold time
Read data delay time
Read data hold time
Symbol
tCYCW
tCYCR
PWLW
PWLR
PWHW
PWHR
tWRr, tWRf
tAS
tAH
tDSW
tH
tDDR
tDHR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
100
250
40
150
30
100
0
Typ
-
Max
25
-
10
-
-
2
25
2
5
-
100
-
120
LGDP4525
Rev 0.9.0
80-System Bus Interface Timing Characteristics (8/9-Bit Bus)
Table 75 (Condition: VDD3 = 1.65 to 3.30V,VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
Bus cycle time
Symbol
tCYCW
tCYCR
PWLW
PWLR
PWHW
PWHR
tWRr, tWRf
tAS
Write
Read
Write
Read
Write
Read
Write “Low” level pulse width
Read “Low” level pulse width
Write “High” level pulse width
Read “High” level pulse width
Write/Read rise/fall time
Setup time
Write (RS to
CSB/RW_WRB)
Read (RS to
CSB/E_RDB)
Address hold time
Write data setup time
Write data hold time
Read data delay time
Read data hold time
tAH
tDSW
tH
tDDR
tDHR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
100
250
40
150
30
100
0
Typ
-
Max
25
-
10
-
-
2
25
2
5
-
100
-
Serial Peripheral Interface Timing Characteristics
Table 76 (Condition: VDD3 = 1.65 to 3.30V,VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
Serial clock cycle time
Serial clock “High” level
pulse width
Serial clock “Low” level
pulse width
Write (received)
Read
(transmitted)
Write (received)
Read
(transmitted)
Write (received)
Read
(transmitted)
Serial clock rise/fall time
Chip select setup time
Chip select hold time
Serial input data setup time
Serial input data hold time
Serial output data setup time
Serial output data hold time
Symbol
tSCYC
Unit
ns
Min
100
350
Typ
-
Max
20000
20000
tSCH
ns
40
150
-
-
tSCL
ns
40
150
-
-
tscr, tscf
tCSU
tCH
tSISU
tSIH
tSOD
tSOH
ns
ns
ns
ns
ns
ns
ns
20
60
30
30
5
-
20
100
-
Reset Timing Characteristics
Table 77 (Condition: VDD3 = 1.65 to 3.30V,VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
Reset “Low” level width
Reset rise time
Symbol
tRES
trRES
Unit
us
us
Min
-
Typ
10
-
Max
10
121
LGDP4525
Rev 0.9.0
RGB Interface Timing Characteristics
Table 78 (18/16-bit I/F, VDD3 = 1.65 to 3.30V, VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
VSYNC/HSYNC setup time
ENABLE setup time
ENABLE hold time
DOTCLK “Low” level pulse width
DOTCLK “High” level pulse width
DOTCLK cycle time
Data setup time
Date hold time
DOTCLK, VSYNC, HSYNC rise/fall
time
Symbol
tSYNCS
tENS
tENH
PWDL
PWDH
tCYCD
tPDS
tPDH
trgbr, trgbf
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
0
10
20
40
40
100
10
40
Typ
Max
25
Table 79 (6-bit I/F, VDD3 = 1.65 to 3.30V, VCI = 2.50 to 3.30V, VDD = 1.7 to 1.9V)
Item
VSYNC/HSYNC setup time
ENABLE setup time
ENABLE hold time
DOTCLK “Low” level pulse width
DOTCLK “High” level pulse width
DOTCLK cycle time
Data setup time
Date hold time
DOTCLK, VSYNC, HSYNC rise/fall
time
Symbol
tSYNCS
tENS
tENH
PWDL
PWDH
tCYCD
tPDS
tPDH
trgbr, trgbf
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
0
10
20
30
30
100
10
40
Typ
Max
25
Notes to Electrical Characteristics
1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85°C.
2. The following are the configurations of I pin, I/O pin, and O pin.
122
LGDP4525
Rev 0.9.0
Pins: RESETB, RESETEN, CSB,
RW_WRB, E_RDB, RS, IM[3:0], VSYNC,
HSYNC, DOTCLK, ENABLE, SDI,
TEST MODE
VDD3
Pins:OSC1
VDD
VDD3
PMOS
PMOS
NMOS
NMOS
GND
GND
Pins: DB17- DB0
Pins: FLM, SDO
GND
VDD3
CSB
(Input circuit)
VDD3
(Output circuit: three states)
GND
Output enable
Output data
GND
Figure 72
3. The TEST MODE pin must be grounded (GND). The IM[3:0] pins must be fixed at either
GND or the VDD3 level.
4. This excludes currents though the output drive MOS.
5. This excludes currents flowing through input/output units. Be sure that input levels are fixed
to prevent increase in the transient current in input units when a CMOS input level takes
medium range. While not accessing via interface pins, current consumption will not change
fixed the CSB pin to “High”, only.
6. This is the case when an external oscillation resistor Rf is used.
OSC1
Oscillation frequency varies depending on the capacitances of OSC1 and OSC2
pin.
Make the wiring between OSC1 and OSC2 as short as possible.
OSC2
Figure 73
123
LGDP4525
Rev 0.9.0
Table 80: Reference Data, Ta=25°C
Oscillation Resistance (kΩ)
RC Oscillation Frequency: fosc (MHz)
@ VDD = 1.8V
27
1.98
30
1.79
33
1.64
36
1.51
39
1.39
43
1.27
47
1.17
51
1.08
56
0.987
62
0.894
68
0.819
75
0.742
82
0.683
124
LGDP4525
Rev 0.9.0
Timing Characteristics Diagram
VIH
VIL
RS
VIH
VIL
tAH
tAS
VIH
VIL
CSB
See Note 1)
PWLW,PWLR
VIH
VIL
RW_WRB
E_RDB
VIH
VIL
PWHW,PWHR
VIH
VIL
VIH
tWRf
tWRr
tCYCW, tCYCR
tH
tDSW
VIH
VIL
See Note 2)
DB0toDB17
VIH
VIL
Write data
tDDR
tDHR
VOH
VOL
See Note 2)
DB0toDB17
VOH
VOL
Read data
Note 1) PWLW and PWLR are defined by the overlap period when CSB is “Low” and RW_WRB or E_RDB is “Low”.
Note 2) Unused DB pins must be fixed at “VDD3” or “GND”.
Figure 74: 80-system bus interface operation
Start: S
CSB
EndL P
VIH
VIL
VIL
tscr
tCSU
SCL
VIH
VIL
tSOD
SDO
VIL
tSISU
VIH
VIL
SDI
tSCH
tscf
VIH
VIL
tSIH
Input data
VOH
Output data
VOL
VIH
VIL
tSCL
tCH
VIH
VIL
Input data
tSOH
VOH
Output data
VOL
Figure 75: Serial peripheral interface operation
125
LGDP4525
Rev 0.9.0
trRES
tRES
RESETB
VIH
VIL
VIL
No reset
(noise less than 10us will be rejected)
Reset
5us
10us
RESETB
Figure 76: Reset operation
trgbf
trgbr
VSYNC
HSYNC
tSYNCS
VIH
VIH
VIL
VIL
tENS
ENABLE
trgbf
DOTCLK
tENH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
trgbf PW
DH
PWDL
VIH
VIH
VIH
VIL
VIL
VIL
VIL
tCYCD
tPDS
DB17-0
VIH
VIH
VIL
Write data
tPDH
VIH
VIH
VIL
VIL
Figure 77 RGB interface
126