54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ACT899 features independent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. Features n Independent latch enable for A-to-B and B-to-A directions n Select pin for ODD/EVEN parity n ERRA and ERRB output pins for parity checking n Ability to simultaneously generate and check parity n May be used in system applications in place of the ’280 n May be used in system applications in place of the ’657 and ’373 (no need to change T/R to check parity) n 4 kV minimum ESD immunity n Standard Microcircuit Drawing (SMD) 5962-9314101 n Latchable transceiver with output sink of 24 mA n Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A Logic Symbol Pin Names A0–A7 B0–B7 B Bus Data Inputs/Data Outputs APAR, BPAR A and B Bus Parity Inputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity GBA, GAB Output Enables for A or B Bus, Active LOW SEL Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs DS100245-1 Connection Diagram Pin Assignment for LCC Description A Bus Data Inputs/Data Outputs DS100245-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100245 www.national.com 54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker August 1998 Functional Description • Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU). • Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table below). The ACT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA). Function Table Inputs Operation GAB GBA SEL LEA LEB H H X X X Busses A and B are TRI-STATE ® . H L L L H H L L H H H L L X L H L H X H H L H H H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. BPAR/B[0:7] → APAR/A[0:7] L H L H L L H L H H L H L L X L H H H L Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. Generates parity from A latch data based on O/E. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. APAR/A[0:7] → BPAR/B[0:7] H Feed-through mode. Generated parity checked against APAR and output as ERRA. APAR/A[0:7] → BPAR/B[0:7] L H H H Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN www.national.com 2 Functional Block Diagram DS100245-3 AC Path DS100245-4 An, APAR → Bn, BPAR (Bn, BPAR → An, APAR) FIGURE 1. DS100245-5 An → BPAR (Bn → APAR) FIGURE 2. 3 www.national.com AC Path (Continued) DS100245-6 An → ERRA (Bn → ERRB) FIGURE 3. DS100245-7 O/E → ERRA O/E → ERRB FIGURE 4. DS100245-8 O/E → BPAR (O/E → APAR) FIGURE 5. www.national.com 4 AC Path (Continued) DS100245-9 APAR → ERRA (BPAR → ERRB) FIGURE 6. DS100245-10 ZH, HZ FIGURE 7. DS100245-11 ZL, LZ FIGURE 8. 5 www.national.com AC Path (Continued) DS100245-12 SEL → BPAR (SEL → APAR) FIGURE 9. DS100245-13 LEA → BPAR, B[0:7] (LEB → APAR, A[0:7]) FIGURE 10. DS100245-14 TS(H), TH(H) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 11. www.national.com 6 AC Path (Continued) DS100245-15 TS(L), TH(L) LEA → APAR, A[0:7] (LEB → BPAR, B[0:7]) FIGURE 12. DS100245-16 FIGURE 13. 7 www.national.com Absolute Maximum Ratings (Note 2) DC Latch-Up Source or Sink Current Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) −0.5V to +7.0V ± 300 mA 175˚C Recommended Operating Conditions −20 mA +20 mA −0.5V to VCC + 0.5V Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate ∆V/∆t ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. Note 3: PLCC packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. DC Electrical Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA (Note 4) VIN = VIL or VIH VOL 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V IOH = −24 mA V IOH = −24 mA IOUT = 50 µA (Note 4) VIN = VIL or VIH IIN Maximum Input 4.5 0.50 5.5 0.50 V IOL = 24 mA ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 5.5 ± 10.0 µA VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min Leakage Current IOZ Maximum TRI-STATE Leakage Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD Minimum Dynamic Output Current (Note 5) 5.5 50 mA 5.5 −50 mA IOHD www.national.com 8 DC Electrical Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C (Continued) Units Conditions Guaranteed Limits ICC Maximum Quiescent 5.5 160.0 VIN = VCC µA Supply Current or GND (Note 6) Note 4: Maximum of 9 outputs loaded; thresholds on input associated with output under test. Note 5: Maximum test duration 2.0 ms, one output loaded at a time. Note 6: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 7) tPLH Propagation Delay tPHL An, Bn to Bn, An tPLH Propagation Delay tPHL APAR, BPAR to BPAR, APAR tPLH Propagation Delay tPHL An, Bn to BPAR, APAR tPLH Propagation Delay tPHL An, Bn to ERRA, ERRB tPLH Propagation Delay tPHL ODD/EVEN to ERRA, ERRB tPLH Propagation Delay tPHL ODD/EVEN to APAR, BPAR tPLH Propagation Delay tPHL APAR, BPAR to ERRA, ERRB tPLH Propagation Delay tPHL SEL to APAR, BPAR tPLH Propagation Delay tPHL LEB to An, Bn tPLH Propagation Delay tPHL LEA to APAR, BPAR tPLH Propagation Delay tPHL LEA, LEB to ERRA, ERRB tPZH Output Enable Time tPZL GBA or GAB to An, Bn tPZH Output Enable Time tPZL GBA or GAB to BPAR or APAR tPHZ Output Disable Time tPHL GBA or GAB to An, Bn tPHZ Output Disable Time tPLZ GBA or GAB to BPAR, APAR Fig. Units No. Min Max 5.0 1.5 13.5 ns Figure 1 5.0 1.5 11.0 ns Figure 1 5.0 1.5 16.0 ns Figure 2 5.0 1.5 16.0 ns Figure 3 5.0 1.5 16.0 ns Figure 4 5.0 1.5 14.5 ns Figure 5 5.0 1.5 11.5 ns Figure 6 5.0 1.5 12.5 ns Figure 9 5.0 1.5 13.5 ns Figures 10, 11 5.0 1.5 16.0 ns Figures 10, 11 5.0 1.5 16.0 ns Figure 12 5.0 1.5 16.0 ns Figures 7, 8 5.0 1.5 11.0 ns Figures 7, 8 5.0 1.5 11.0 ns Figures 7, 8 5.0 1.5 11.0 ns Figures 7, 8 Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. 9 www.national.com AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 8) Fig. Units No. Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 3.0 ns Figures 11, 12 5.0 3.0 ns Figures 11, 12 5.0 4.0 ns Figure 13 An, Bn, PAR to LEA, LEB th Hold Time, HIGH or LOW An, Bn, PAR to LEA, LEB tw Pulse Width for LEB, LEA Note 8: Voltage Range 5.0 = 5.0V ± 0.5V. Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 210 pF Capacitance www.national.com 10 Conditions VCC = 5.0V VCC = 5.0V 11 54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Chip Carrier (Q) NS Package Number E28A 28-Lead Plastic Chip Carrier (Q) NS Package Number J28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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