ETC NT7534

NT7534
132 X 65 RAM-Map STN LCD
Controller/Driver
V1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
Revision History....................................................................................................................................3
Features .................................................................................................................................................4
General Description..............................................................................................................................4
Pad Configuration.................................................................................................................................5
Block Diagram.......................................................................................................................................6
Pad Descriptions...................................................................................................................................7
Functional Descriptions .....................................................................................................................12
Commands ..........................................................................................................................................27
Command Description........................................................................................................................43
Absolute Maximum Rating.................................................................................................................46
Electrical Characteristics ...................................................................................................................46
Microprocessor Interface (for reference only) .................................................................................55
Bonding Diagram ................................................................................................................................62
Package Information...........................................................................................................................67
Ordering Information ..........................................................................................................................68
2
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Revision History
NT7534 Specification Revision History
Version
1.0
2004/12/06
Content
Date
Released
Dec.
3
2004
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Features
132 x 65-dot graphics display LCD controller/driver for black/white STN LCD
RAM capacity: 132 x 65 = 8,580 bits
8-bit parallel bus interface for both 8080 and 6800 series,
4-wire Serial Peripheral Interface (SPI)
Direct RAM data display using the display data RAM.
When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed.
(At normal display)
Many command functions:
Read/Write display data, display ON/OFF, Normal/Reverse display, page address set, display start
line set, LCD bias set, electronic contrast controls, V0 voltage regulation internal resistor ratio set,
read modify write, segment driver direction select, power save.
Other command functions:
Partial display, partial start line set, N-Line inversion.
Power supply voltage:
- VDD = 1.8 ~ 3.6 V
- VDD2 = 1.8 ~ 3.6 V
- V0
= 4.0 ~ 14.2 V
- VOUT = 14.2 V Max.
2X / 3X / 4X / 5X on chip DC-DC converter
On chip LCD driving voltage generator or external power supply selectable
64-step contrast adjuster and on chip voltage follower
On chip oscillation and hardware reset
General Description
The NT7534 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly
connectable to a microcomputer bus. It accepts 8-bit parallel or serial display data directly sent from a
microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent
of the microprocessor clock.
The set of the on-chip display RAM of 65 x 132 bits and a one-to-one correspondence between LCD
panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of
freedom. The NT7534 contain 65 common output circuits and 132 segment output circuits, so that a
single chip of NT7534 can make maximum 65 x 132 or 49 x 132 or 33 x 132 dots display with the pad
option (DUTY1, DUTY0).
No external operation clock is required for RAM read/write operations. Accordingly, this driver can be
operated with a minimum current consumption and its on-board low-current-consumption liquid crystal
power supply can implement a high-performance handy display system with minimum current
consumption and the smallest LSI configuration.
2004/12/06
4
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad Configuration
2004/12/06
5
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Block Diagram
SEG0
SEG131
COM0
COM63 COMS
VDD, VDD3
V0
V1
V2
V3
V4
VSS2
COM S
VSS, VSS3
Common
driver
Segment driver
Shift register
CAP1+
CAP1CAP2+
CAP2-
Power Supply
Circuit
CAP3+
CAP4+
Display data latch
Output status
selector circuit
/HPM
132*65-dot
display data RAM
Line counter
IRS
line address decoder
VR
VSS2
I/O buffer circuit
VDD2
Initial display line register
VOUT
Column address decoder
Page address
register
DUTY0
8-bit column address counter
DUTY1
Display timing
generator
circuit
FRS
FR
CL
/DOF
M/S
Bus holder
Command decoder
Bus holder
Microprocessor interface
/CS 1
2004/12/06
CS2
A0
/RD /WR C86
(E) (R/W)
Oscillator
CLS
I/O buffer
P/S
/RES
D7
(SI)
D5
D6
(SCL)
6
D4
D3
D2
D1
D0
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad Descriptions
Power Supply
Pad No.
Designation
I/O
Description
42 ~ 44
VDD
Supply
Power supply input. These pads must be connected to each
other.
45
VDD3
46 ~ 49
VDD2
Supply
These are the power supply pads for the step-up voltage
circuit for the LCD. These pads must be connected to each
other.
16, 22,
97,103,107
VDD
O
50 ~ 52
VSS
53
VSS3
54 ~ 57
Power supply output for pad option
Supply
Ground. These pads must be connected to each other.
VSS2
Supply
Ground. These pads must be connected to each other.
13, 40,
100, 105
VSS
O
94, 95
V0
86, 87
V1
88, 89
V2
90, 91
92, 93
V3
V4
Ground output for pad option.
LCD driver supplies voltages. The voltage determined by the
LCD cell is impedance-converted by a resistive driver or an
operation amplifier for application. Voltages should be
according to the following relationship:
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS2
When the on-chip operating power circuit is on, the following
voltages are supplied to V1 to V4 by the on-chip power circuit.
Voltage selection is performed by the LCD Bias Set command.
I/O
LCD bias
V1
V2
V3
V4
1/4 bias
3/4V0
2/4V0
2/4V0
1/4V0
1/5 bias
4/5V0
3/5V0
2/5V0
1/5V0
1/6 bias
5/6V0
4/6V0
2/6V0
1/6V0
1/7 bias
6/7V0
5/7V0
2/7V0
1/7V0
1/8 bias
7/8V0
6/8V0
2/8V0
1/8V0
1/9 bias
8/9V0
7/9V0
2/9V0
1/9V0
Note: VDD and VDD3 pads must be connected together.
2004/12/06
7
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
LCD Power Supply
Pad No.
Designation
I/O
Description
70 ~ 73
C1-
O
Capacitor 1- pad for internal DC/DC voltage converter.
74 ~ 77
C1+
O
Capacitor 1+ pad for internal DC/DC voltage converter.
82 ~ 85
C2-
O
Capacitor 2- pad for internal DC/DC voltage converter.
78 ~ 81
C2+
O
Capacitor 2+ pad for internal DC/DC voltage converter.
66 ~ 69
C3+
O
Capacitor 3+ pad for internal DC/DC voltage converter.
62 ~ 65
C4+
O
Capacitor 4+ pad for internal DC/DC voltage converter.
59 ~ 61
VOUT
I/O
DC/DC voltage converter output
96
VR
I
Voltage adjustment pad. Applies voltage between V0 and VSS
using a resistive divider.
Configuration Pad
Pad No.
Designation
I/O
39, 41
DUTY0
DUTY1
I
2004/12/06
Description
Select the maximum LCD driver duty
DUTY1
DUTY0
LCD driver duty
0
0
1/33
0
1
1/49
1
*
1/65
8
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
System Bus Connection
Pad No.
Designation
23, 24
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
37, 38
D0
D1
D2
D3
D4
D5
D6 (SCL)
D7 (SI)
I/O
Description
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit
or 16-bit standard MPU data bus.
When the serial interface is selected (P/S=“L”), then D7
serves as the serial data input terminal (SI) and D6 serves as
the serial clock input terminal (SCL). At this time, D0 to D5 are
set to high impedance.
When the chip select is inactive, D0 to D7 are set to high
impedance.
18
A0
I
This is connected to the least significant bit of the normal MPU
address bus, and it determines whether the data bits are data
or a command.
A0 = “H”: Indicate that D0 to D7 are display data
A0 = “L”: Indicates that D0 to D7 are control data
17
/RES
I
When /RES is set to “L”, the settings are initialized. The reset
operation is performed by the /RES signal level
14
15
/CS1
CS2
I
This is the chip select signal. When /CS1=“L” and CS2=“H”,
then the chip select becomes active, and data/command I/O is
enabled.
I
When connected to an 8080 MPU, it is active LOW. This pad
is connected to the /RD signal of the 8080MPU, and the
NT7534 data bus is in an output status when this signal is “L”.
When connected to a 6800 Series MPU, this is active HIGH.
This is used as an enable clock input of the 6800 series
MPU
21
/RD
(E)
19
/WR
(R/W)
I
When connected to an 8080 MPU, this is active LOW. This
terminal connects to the 8080 MPU /WR signal. The signals
on the data bus are latched at the rising edge of the /WR
signal.
When connected to a 6800 Series MPU, this is the read/write
control signal input terminal.
When R/W = “H”: Read
When R/W = “L”: Write
101
C86
I
This is the MPU interface switch terminal
C86 = “H”: 6800 Series MPU interface
C86 = “L”: 8080 Series MPU interface
2004/12/06
9
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
System Bus Connection (continuous)
Pad No.
Designation
I/O
Description
This is the parallel data input/serial data input switch terminal
P/S = “H”: Parallel data input
P/S = “L”: Serial data input
The following applies depending on the P/S status:
P/S Data/Command
102
P/S
I
Data
Read/Write Serial Clock
“H”
A0
D0 to D7
/RD, /WR
-
“L”
A0
SI (D7)
Write only
SCL (D6)
When P/S = “L”, D0 to D5 are HZ. D0 to D5 may be “H”, “L” or
Open. /RD (E) and /WR (R/W) are fixed to either “H” or “L”.
With serial data input, RAM display data reading is not
supported.
99
CLS
I
Terminal to select whether enable or disable the display clock
internal oscillator circuit.
CLS = “H”: Internal oscillator circuit for display is enabled
CLS = “L”: Internal oscillator circuit for display is disabled
(requires external input)
When CLS = “L”, input the display clock through the CL pad.
98
M/S
I
This terminal selects the master/slave operation for the
NT7534 chips. Master operation outputs the timing signals
that are required for the LCD display, while slave operation
inputs the timing signals required for the liquid crystal display,
synchronizing the liquid crystal display system.
11
CL
I/O
This is the display clock input terminal. When the NT7534
chips are used in master/slave mode, the various CL terminals
must be connected.
I/O
This is the liquid crystal alternating current signal I/O terminal
M/S = “H”: Output
M/S = “L”: Input
When the NT7534 chip is used in master/slave mode, the
various FR terminals must be connected.
I/O
This is the liquid crystal display blanking control terminal.
M/S = “H”: Output
M/S = “L”: Input
When the NT7534 chip is used in master/slave mode, the
various /DOF terminals must be connected.
O
This is the output terminal for the static drive. This terminal is
only enabled when the static indicator display is ON in master
operation mode, and is used in conjunction with the FR
terminal
10
12
9
2004/12/06
FR
/DOF
FRS
10
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
System Bus Connection (continuous)
Pad No.
106
104
Designation
IRS
/HPM
I/O
Description
I
This terminal selects the resistors for the V0 voltage level
adjustment.
IRS = “H”, Use the internal resistors
IRS = “L”, Do not use the internal resistors
The V0 voltage level is regulated by an external resistive
voltage divider attached to the VR terminal. This pad is
enabled only when the master operation mode is selected. It
is fixed to either “H” or “L” when the slave operation mode is
selected
I
This is the power control terminal for the power supply circuit
for liquid crystal drive.
/HPM = “H”, Normal power mode
/HPM = “L”, High power mode
This pad is enabled only when the master operation mode is
selected and it is fixed to either “H” or “L” when the slave
operation mode is selected.
Description
Liquid Crystal Drive Pads
Pad No.
Designation
I/O
145 ~ 276
SEG0 - 131
O
Segment signal output for LCD display.
133 ~ 143
117 ~ 130
108 ~ 114
277 ~ 288
291 ~ 304
2~7
COM10 – 0
COM24 – 11
COM31 – 25
COM32 – 43
COM44 – 57
COM58 – 63
O
Common signal output for LCD display. When in master/slave
mode, the same signal is output by both master and slave
COMS
O
These are the COM output terminals for the indicator. Both
terminals output the same signal. Do not connect these
terminals if they are not used. When in master/slave mode,
the same signal is output by both master and slave.
Pad No.
Designation
I/O
Description
20
58
TEST0
TEST1
I
8, 144
Test Pad
Test pads. No connection.
No Connected Pad
Pad No.
Designation
I/O
1, 115, 116,
131, 132,
289, 290,
305
DUMMY
-
2004/12/06
Description
Dummy pads, No connection.
11
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Functional Descriptions
Microprocessor Interface
Interface Type Selection
The NT7534 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI).
When high or low is selected for the parity of P/S pad either 8-bit parallel data input or serial data input
can be selected as shown in Table 1. When serial data input is selected, the RAM data cannot be read
out.
Table 1
P/S
Type
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D0 to D5
H
Parallel Input
/CS1
CS2
A0
/RD
/WR
C86
D7
D6
D0 to D5
L
Serial Input
/CS1
CS2
A0
-
-
-
SI
SCL
(HZ)
“-” Must always be high or low
Parallel Interface
When the NT7534 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series
microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2.
Table 2
C86
Type
/CS1
CS2
A0
/RD
/WR
D0 to D7
H
6800 microprocessor bus
/CS1
CS2
A0
E
R/W
D0 to D7
L
8080 microprocessor bus
/CS1
CS2
A0
/RD
/WR
D0 to D7
Data Bus Signals
The NT7534 identifies the data bus signal according to A0, E, R/W (/RD, /WR) signals.
Table 3
Common 6800 processor
8080 processor
Function
A0
(R/W)
/RD
/WR
1
1
0
1
Reads display data
1
0
1
0
Writes display data
0
1
0
1
Reads status
0
0
1
0
Writes control data in internal register. (Command)
2004/12/06
12
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Serial Interface
When the serial interface has been selected (P/S = “L”), then when the chip is in active state (/CS1 =
“L” and CS2 = “H”), the serial data input (SI) and the serial clock input (SCL) can be received. The
serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through
D0, in this order. This data is converted to 8 bits of parallel data in the rising edge of eighth serial clock
for processing.
The A0 input is used to determine whether or not the serial data input is display data, and when A0 =
“L” then the data is command data. The A0 input is read and used for detection of every 8th rising
edge of the serial clock after the chip becomes active. Figure 1 is the serial interface signal chart.
Figure 1
CS
/CS1 = ”L” and CS2 = “H”
SI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
SCL
1
2
3
4
5
6
7
8
9
10
11 12
A0
Note:
1. When the chip is not active, the shift registers and the counters are reset to their initial states.
2. Reading is not possible while in serial interface mode.
3. Caution is required on the SCL signal when it comes to line-end reflections and external noise.
We recommend that the operation can be rechecked on the actual equipment.
Chip Select Inputs
The NT7534 has two chip-select pads. /CS1 and CS2 can interface to a microprocessor when /CS1 is
low and CS2 is high. When these pads are set to any other combination. D0 to D7 are high impedance
and A0, E and R/W inputs are disabled. When serial input interface is selected, the shift register and
counter are reset.
Access to Display Data RAM and Internal Registers
The NT7534 can perform a series of pipeline processing between LSI’s using the bus holder of the
internal data bus in order to match the operating frequency of display RAM and internal registers with
the microprocessor. For example, the microprocessor reads data from display RAM in the first read
(dummy) cycle, stores it in the bus holder, and outputs it onto the system bus in the next data read
cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in
display RAM until the next data write cycle starts.
When viewed from the microprocessor, the NT7534 access speed greatly depends on the cycle time
rather than access time to the display RAM (tACC). This view shows that the data transfer speed to /
from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert
the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the
display RAM read sequence. When an address is set, the specified address data is NOT output at the
immediately following read instruction. The address data is output during the second data read. A
single dummy read must be inserted after address setup and after the write cycle (refer to Figure 2).
2004/12/06
13
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Figure 2
A0
MPU
E
R/W
DATA
N
N
n
n+1
Address preset
Read signal
Internal
timing
Incremented
Preset
Column address
N
N+1
N
BUS holder
Set address n
n
Dummy read
N+2
n+1
Data Read address n
n+2
Data Read address n+1
Busy Flag
When the busy flag is “1” it indicates that the NT7534 chip is running internal processes, and at this
time no command aside from a status read will be received. The busy flag is outputted to D7 pad with
the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag
before each command. This makes vast improvements in MPU processing capabilities possible.
Display Data RAM
The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8
bit+1)*132 bit structure. It is possible to access the desired bit by specifying the page address and the
column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU
corresponds to the liquid crystal display common direction, there are few constraints at the time of
display common direction, and there are few constraints at the time of display data transfer when
multiple NT7534 chips are used, thus display structures can be created easily with a high degree of
freedom.
Moreover, reading from and writing to the display RAM from the MPU side is performed through the
I/O buffer, which is an independent operation from signal reading for the liquid crystal driver.
Consequently, even if the display data RAM is accessed asynchronously during the liquid crystal
display, it will not cause adverse effects on the display (such as flickering).
Figure 3
D0
D1
D2
D3
D4
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
COM0
COM1
COM2
COM3
COM4
0
0
0
0
0
Display data RAM
2004/12/06
Display on LCD
14
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
The Page Address Circuit
As shown in Figure 4, page address of the display data RAM is specified through the Page Address
Set Command. The page address must be specified again when changing pages to perform access.
Page address8 (D3, D2, D1, D0 = 1, 0, 0, 0,) is the page for the RAM region used; only display data
D0 is used.
The Column Address
As shown in Figure 4, the display data RAM column address is specified by the Column Address Set
command. The specified column address is incremented (+1) with each display data read / write
command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination
of column addresses stops with 83H, because the column address is independent of the page address.
Thus, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to
specify both the page address and the column address.
Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command)
can be used to reverse the relationship between the display data RAM column address and the
segment output. Because of this, the constraints on the IC layout when the LCD module is assembled
can be minimized.
Table 4
SEG Output
SEG0
SEG131
ADC “0”
0 (H)
Column Address
83 (H)
(ADC) “1”
83 (H)
Column Address
0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the line address relating to the COM output
when the contents of the display data RAM are displayed. Using the display start line address set
command, what is normally the top line of the display can be specified. This is the COM0 output when
the common output mode is normal and the COM63 output for NT7534, when the common output
mode is reversed. The display area is a 65-line area for the NT7534 from the display start line address.
If the line addresses are changed dynamically using the display start line address set command,
screen scrolling, page swapping, etc. can be performed.
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily stores the display data that is output to the
liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status,
display ON/OFF status, and display all points ON/OFF commands control only the data within the latch,
they do not change the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when
M/S = “H” and CLS = “H”. When CLS = “L” the oscillation stops, and the display clock is input through
the CL terminal.
2004/12/06
15
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Figure 4. Relationship between display data RAM and address. (if initial display line is 1DH)
Line
Address
Page Address Data
2004/12/06
16
83
81
SEG2
82
82
SEG1
00
83
SEG0
SEG131
D0=1
ADC
Page8
LCD
OUT
Column
address
1, 0, 0, 0
Page7
81
0, 1, 1, 1
Page6
01
0, 1, 1, 0
Page5
02
0, 1, 0, 1
Page4
SEG130
0, 1, 0, 0
Page3
SEG129
0, 0, 1, 1
Page2
02
0, 0, 1, 0
Page1
01
0, 0, 0, 1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Page0
00
D3, D2, D1, D0
0, 0, 0, 0
D0=0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
COM
output
Start
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COMS
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the
display data latch circuit using the display clock. The display data is latched into the display data latch
circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to
the display data liquid crystal driver circuits is completely independent of access to the display data
RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during
liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display.
Moreover, the display timing generator circuit generates the common timing and the liquid crystal
alternating current signal (FR) from the display clock. It generates a drive waveform using a 2 frames
alternating current drive method, as shown in Figure 5, for the liquid crystal drive circuit.
Figure 5
64
65
1
2
3
4
5
6
60
61
62
63
64
65
1
2
3
4
5
6
CL
FR
V0
V1
COM0
V4
VSS
V0
V1
COM1
V4
VSS
RAM
data
V0
V2
V3
VSS
SEGn
When multiple NT7534 chips are used, the slave chip must be supplied with the display timing signals
(FR, CL, /DOF) from the master chip. Table 5 shows the status of the FR, CL, and /DOF signals.
Table 5
Operating Mode
FR
CL
/DOF
Master The internal display oscillator is enabled (CLS = “H”) Output Output Output
(M/S = “H”) The internal display oscillator is disabled (CLS = “L”) Output Input Output
Slave
The internal display oscillator is disabled (CLS = “H”)
(M/S = “L”) The internal display oscillator is disabled (CLS = “L”)
2004/12/06
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Input
Input
Input
Input
Input
Input
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Table 6 shows the relationship between oscillation frequency and frame frequency. fOSC can be
selected as 31.4K or 26.3KHz by using Oscilliation Frequency Select command.
Table 6
Duty
1/65
1/49
1/33
1/17
1/9
Item
fCL
On-chip oscillator is used
fFR
fOSC/6
fCL/(2 x 65)
On-chip oscillator is not used External input fCL
fCL/(2 x 65)
On-chip oscillator is used
fCL/(2 x 49)
fOSC/8
On-chip oscillator is not used External input fCL
fCL/(2 x 49)
On-chip oscillator is used
fCL/(2 x 33)
fOSC/12
On-chip oscillator is not used External input fCL
fCL/(2 x 33)
On-chip oscillator is used
fCL/(2 x 17)
fOSC/22
On-chip oscillator is not used External input fCL
fCL/(2 x 17)
On-chip oscillator is used
fCL/(2 x 9)
fOSC/44
On-chip oscillator is not used External input fCL
fCL/(2 x 9)
Common Output Control Circuit
This circuit controls the relationship between the number of common output and specified duty ratio.
Common output mode select instruction specifies the scanning direction of the common output pads.
Table 7
Common output pads
Duty
1/33
1/49
1/65
Status
COM
[0-15]
COM
[16-23]
COM
[24-26]
COM
[27-36]
COM
[37-39]
COM
[40-47]
COM
[48-63]
Normal COM[0-15]
NC
COM[16-31]
Reverse COM[31-16]
NC
COM[15-0]
Normal
COM[0-23]
NC
COM[24-47]
Reverse
COM[47-24]
NC
COM[23-0]
Normal
COM[0-63]
Reverse
COM[63-0]
COMS
COMS
COMS
COMS
The combination of the display data, the COM scanning signals, and the FR signal produces the liquid
crystal drive voltage output. Figure 6 shows example of the SEG and COM output waveform.
Configuration Setting
The NT7534 has two optional configurations, configured by DUTY0, DUTY1.
DUTY1, DUTY0
Common
Segment
1, 0 or 1, 1
65
132
8/9V0, 6/7V0 7/9V0, 5/7V0 2/9V0, 2/7 V0 1/9V0, 1/7V0
0, 1
49
132
7/8V0, 5/6V0 6/8V0, 4/6V0 2/8V0, 2/6 V0 1/8V0, 1/6V0
0, 0
33
132
5/6V0, 4/5V0 4/6V0, 3/5V0 2/6 V0, 2/5V0 1/6V0, 1/5V0
2004/12/06
V1
18
V2
V3
V4
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Figure 6
VDD
VSS
FR
V0
V1
V2
V3
V4
VSS2
COM0
COM1
COM0
COM2
V0
V1
V2
V3
V4
VSS2
COM3
COM4
COM5
COM1
COM6
V0
V1
V2
V3
V4
VSS2
COM7
COM8
COM2
COM9
SEG0
V0
V1
V2
V3
V4
VSS2
SEG1
V0
V1
V2
V3
V4
VSS2
SEG2
V0
V1
V2
V3
V4
VSS2
COM10
COM11
COM12
COM13
COM14
COM15
V0
V1
V2
V3
V4
VSS2
-V4
-V3
-V2
-V1
-V0
COM0 - SEG0
V0
V1
V2
V3
V4
VSS2
-V4
-V3
-V2
-V1
-V0
COM0 - SEG1
2004/12/06
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
The Power Supply Circuit
The power supply circuits are low-power consumption power supply circuits that generate the voltage
levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits,
and voltage follower circuits. They are only enabled in master operation.
The power supply circuits can turn the booster circuits, the voltage regulator circuits, and the voltage
follower circuits ON or OFF independently through the use of the Power Control Set command.
Consequently, it is possible to make an external power supply and the internal power supply function
somewhat in parallel. Table 8 shows the Power Control Set Command 3-bit data control functions, and
Table 9 shows reference combinations.
Table 8
Status
Item
“1”
“0”
D2 Voltage Booster (V/B) circuit control bit
ON
OFF
D1 Voltage regulator (V/R) circuit control bit
ON
OFF
D0 Voltage follower (V/F) circuit control bit
ON
OFF
Table 9
Use Settings
V/B
D2 D1 D0
Circuit
V/R
circuit
V/F
circuit
External
voltage input
Step-up
voltage
system
terminal
Only the internal power
supply is used
1
1
1
ON
ON
ON
VDD2
Used
Only the V/R circuit and the
V/F circuit are used
0
1
1
OFF
ON
ON
VOUT, VDD2
Open
Only the V/F circuit is used
0
0
1
OFF
OFF
ON
V0, VDD2
Open
Only the external power
supply is used
0
0
0
OFF
OFF
OFF
V0 to V4
Open
*The “Step-up system terminals” refer CAP1+, CAP1-, CAP2+, CAP2-, CAP3+ and CAP4+.
*While other combinations, not shown above, are also possible, these combinations are not
recommended because they have no practical use.
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
The Step-up Voltage Circuits
Using the step-up voltage circuits within the NT7534 chips it is possible to product 5X, 4X, 3X, 2X
step-ups of the VDD2-VSS2 voltage levels.
Figure 7
VSS
C1
VSS
C1
VOUT
CAP1-
C1
CAP1+
CAP2-
C1
C1
CAP1+
CAP1-
C1
CAP1+
CAP2+
CAP2-
CAP2-
CAP4+
CAP4+
3x step-up voltage circuit
2x step-up voltage circuit
CAP4+
4x step-up voltage circuit
VOUT
CAP3+
CAP2+
C1
CAP2-
CAP4+
5x step-up voltage circuit
CAP1-
C1
CAP2+
CAP2+
C1
CAP3+
NT7534
CAP1+
C1
C1
VOUT
NT7534
CAP1-
C1
CAP3+
NT7534
C1
NT7534
CAP3+
VSS
VSS
C1
VOUT
VOUT = 5 X VDD2 = 14V
VOUT = 4 X VDD2 = 12V
VOUT = 3 X VDD2 = 9V
VOUT = 2 X VDD2 = 6V
VDD2 = 2.8V
VDD2 = 3V
VDD2 = 3V
VDD2 = 3V
VSS2 = 0V
VSS2 = 0V
VSS2 = 0V
VSS2 = 0V
5x step-up voltage relationships
4x step-up voltage relationships
3x step-up voltage relationships
2x step-up voltage relationships
The Voltage Regulator Circuit
The step-up voltage generated at VOUT outputs the liquid crystal driver voltage V0 through the voltage
regulator circuit. Because the NT7534 chips have an internal high-accuracy fixed voltage power supply
with a 64-level electronic volume function and internal resistors for the V0 voltage regulator, systems
can be constructed without having to include high-accuracy voltage regulator circuit components.
Moreover, NT7534 has thermal gradients: approximately –0.05%/°C.
2004/12/06
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
When the V0 Voltage Regulator Internal Resistors Are Used
Through the use of the V0 voltage regulator internal resistors and the electronic volume function the
liquid crystal power supply voltage V0 can be controlled by commands alone (without adding any
external resistors), making it possible to adjust the liquid crystal display brightness. The V0 voltage
can be calculated using equation A-1 over the range where V0 < VOUT.
V0 = (1 +
Rb
Rb
63 − α
) × VEV = (1 +
) × (1 −
) × VREG
Ra
Ra
162
(Equation A-1)
Rb
VOUT
-
V0
+
Ra
VEV (constant voltage supply
+ electronic volume)
VEV
VSS2
VREG is the IC internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 10.
Table 10
Thermal
Gradient
Equipment Type
Units
VREG
Internal Power Supply
-0.05
%/°C
2.1
α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in
the 6-bit electronic volume register. Table 11 shows the value for α depending on the electronic volume
register settings. Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different
levels through the V0 voltage regulator internal resistor ratio set command. The (1+Rb/Ra) ratio
assumes the values shown in Table 12 depending on the 3-bit data settings in the V0 voltage regulator
internal resistor ratio register.
Table 11
D5
D4
D3
D2
D1
D0
α
V0
0
0
0
0
0
0
0
Minimum
0
0
0
0
0
1
1
:
0
0
0
0
1
0
2
:
:
:
:
0
32
(default)
:
:
:
:
1
0
0
0
0
:
2004/12/06
1
1
1
1
1
0
62
:
1
1
1
1
1
1
63
Maximum
22
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
V0 voltage regulator internal resistance ratio register value and (1+ Rb/Ra) ratio (Reference value)
Table 12
D2
D1
D0
Equipment Type by Thermal Gradient
[Units:%/°C]
-0.05
0
0
0
3.0
0
0
1
3.5
0
1
0
4.0
0
1
1
4.5
1
0
0
5.0 (default)
1
0
1
5.5
1
1
0
6.0
1
1
1
6.4
Register
The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the
electronic volumn register.
Note: When selecting external Rb/Ra resistors, Ra+Rb shoud be greater than 1.5MΩ.
Figure 8. The Contrast Curve of V0 Voltage with internal resistors
16
14
(0,0,0) 3
(0,0,1) 3.5
(0,1,0) 4
(0,1,1) 4.5
(1,0,0) 5
(1,0,1) 5.5
(1,1,0) 6
(1,1,1) 6.4
V0 (V)
12
10
8
6
4
2
0
0
10
20
30
40
50
60
Electronic Volume
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Setup example: When selecting Ta=25°C and V0=7V for a NT7534 model on which the temperture
compemsation is internal, using the equation A-1, the following setup is enable.
Table 13
Contents
Register
D5 D4 D3 D2 D1 D0
For V0 voltage
regulator
-
-
-
0
1
0
Electronic Volume
1
0
0
1
0
1
● When the V0 voltage regulator internal resistors or the electronic volume function is used, it is
necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating
mode using the power control set commands. Moreover, it is necessary to provide a voltage from
VOUT when the Booster circuit is OFF.
● The VR terminal is enabled only when the V0 voltage regulator internal resistors are not used (i.e.
the IRS terminal = “L”). When the V0 voltage regulator internal resistors are used (i.e. when the IRS
ternimal = “H”), then the VR terminal is left open.
● Because the input impedance of the VR terminal is high, it is necessary to take into consideration
short leads, shield cables,etc. to handle noise.
The Liquid Crystal Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1,
V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower
changes the impedance, it provides V1, V2, V3, and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7
bias for NT7534 can be selected when the duty is 1/65.
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
High Power Mode
The power supply circuit equipped in the NT7534 chips has very low power consumption (normal
mode: /HPM=“H”). However for LCDs or panels with large loads, this low-power power supply may
cause display quality to degrade. When this occurs, setting the /HPM terminal to “L” (high power mode)
can improve the quality of the display. We recommend that the display be checked on actual
equipment to determine whether or not to use this mode.
Moreover, if the improvement to the display is inadequate even after the high power mode has been
set, then it is necessary to add a liquid crystal drive power supply externally.
Reference Power Supply Circuit for Driving LCD Panel
-When using all LCD power circuits
--When not using voltage booster circuits
(Voltage booster, regulator and follower)
(In case of external regulator resistors, IRS=0)
(In case of 4X boosting circuit and internal
regulator resistors, IRS=1)
VDD
VDD
M/S
C1
C4+
C1
C1
C1
M/S
External
Power
Supply
VOUT
VOUT
C4+
C3+
C2+
C2+
C2-
C2-
C1+
C1+
C1-
C1-
C3+
Ra
VR
VR
C2
V0
C2
V2
C2
V3
C2
V1
C2
V2
C2
V0
C2
V1
C2
Rb
C2
V3
C2
V4
V4
VSS2
VSS2
-When only using voltage follower
-When not using internal LCD power supply circuits
VDD
VDD
*Value of External Capacitance
M/S
Item
VOUT
C4+
C3+
External
Power
Supply
C2
C2
C2
C2
C2
C1
1.0 - 4.7
C2
0.1 - 2.2
uF
VOUT
C4+
C3+
C2+
C2+
C2-
C2-
C1+
C1+
C1-
C1-
VR
VR
V0
V0
External
Power
Supply
V1
V2
V3
V1
V2
V3
V4
V4
VSS2
2004/12/06
M/S
Value
VSS2
25
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Reset Circuit
When the /RES input falls to “L”, these LSIs reenter their default state. The default settings are shown
below:
1. Display OFF
2. Normal display
3. ADC select: Normal display (ADC command D0 = “L”)
4. Power control register (D2, D1, D0) = (0, 0, 0,)
5. Register data clear in serial interface
6. LCD power supply bias ratio 1/9 (1/65 duty), 1/8 (1/49 duty), 1/6 (1/33 duty)
7. Read modify write OFF
8. Static indicator: OFF
Static indicator register: (D1, D2) = (0, 0)
9. Display start line register set at first line
10. Column address counter set at address 0
11. Page address register set at page 0
12. Common output status normal
13. V0 voltage regulator internal power supply ratio set mode clear:
V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0)
14. Electronic volume register set mode clear
Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,)
15. Test mode clear
16. Oscillation frequency 31.4 KHz
17. Normal display mode and frame inversion status (partial display and N-Line inversion release)
18. Partial display duty register: (D2, D1, D0) = (1, 0, 0), 1/65 duty
19. Partial display bias register: (D2, D1, D0) = (1, 0, 1), 1/9 bias
20. N-Line inversion register: (D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0), 13-Line inversion
21. Partial start line register: (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0), the first line
22. DC/DC clock division register: (D3, D2, D1, D0) = (0, 0, 1, 1), fOSC/6
23. Output condition of COM, SEG
COM: VSS
SEG: VSS
On the other hand, when the reset command is used, only default settings 7 to 15 above are put into
effect.
The MPU interface (Reference Example)”, the /RES terminal is connected to the MPU reset terminal,
making the chip reinitialize simultaneously with the MPU. At the time of power up, it is necessary to
reinitialize using the /RES terminal. Moreover, when the control signal from the MPU is in a high
impedance state, there may be an overcurrent condition; therefore, take measures to prevent the input
terminal from entering a high impedance state.
In the NT7534, if the internal liquid crystal power supply circuit is not used, then it is necessary to
apply an “L” signal to the /RES terminal when the external liquid crystal power supply is applied. Even
though the oscillator circuit operates while the /RES terminal is “L,” the display timing generator circuit
is stopped, and the FR, FRS, and /DOF terminals are fixed to “H,” and the CL pin is fixed to “H” only
when the intermal oscillator circuit is used. There is no influence on the D0 to D7 terminals.
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Commands
The NT7534 uses a combination of A0, /RD (E) and /WR (R/W) signals to identify data bus signals. As
the chip analyzes and executes each command using internal timing clock only regardless of external
clock, its processing speed is very high and its busy check is usually not required. The 8080 series
microprocessor interface enters a read status when a low pulse is input to the /RD pad and a write
status when a low pulse is input to the /WR pad. The 6800 series microprocessor interface enters a
read status when a high pulse is input to the R/W pad and a write status when a low pulse is input to
this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC
Characteristics.). Accordingly, in the command explanation and command table, /RD (E) becomes
1(high) when the 6800 series microprocessor interface reads status of display data. This is the only
different point from the 8080 series microprocessor interface.
Taking the 8080 series microprocessor interface as an example, commands are explained below.
When the serial interface is selected, input data starting from D7 in sequence.
1. Display ON/OFF
Alternatively turns the display on and off.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
0
1
1
1
Hex
Setting
1
AFh
Display ON
0
AEh
Display OFF
When the display OFF command is executed when in the display all points ON mode, power save
mode is entered. See the section on the power saver for details.
2.
Display Start Line Set
Specifies line address (refer to Figure 6) to determine the initial display line, or COM0. The RAM
display data becomes the top line of LCD screen. The higher number of lines in ascending order,
corresponding to the duty cycle follows it. When this command changes the line address, smooth
scrolling or a page change takes place.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
1
A5 A4 A3 A2 A1 A0
Hex
40h to 7Fh
A5
A4
A3
A2
A1
A0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
:
:
1
1
1
1
1
0
62
1
1
1
1
1
1
63
2004/12/06
27
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
3.
Page Address Set
Specifies page address to load display RAM data to page address register. Any RAM data bit can
be accessed when its page address and column address are specified. The display remains
unchanged even when the page address is changed. Page address 8 is the display RAM area
dedicated to the indicator, and only D0 is valid for data change.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
1
4.
A3 A2 A1 A0
A3
A2
A1
A0
Page address
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
:
Hex
B0h to B8h
:
0
1
1
1
7
1
0
0
0
8
Column Address Set
Specifies column address of display RAM. Divide the column address into 4 higher bits and 4
lower bits. Set each of them succession. When the microprocessor repeats to access the display
RAM, the column address counter is incremental by during each access until address 132 is
accessed. The page address is not changed during this time.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
0
0
Hex
1
A7 A6 A5 A4
10h to 18h
High nibble
0
A3 A2 A1 A0
00h to 0Fh
Low nibble
A7
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
0
2
:
:
1
0
0
0
0
0
1
0
130
1
0
0
0
0
0
1
1
131
2004/12/06
28
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
5.
Read Status
A0
E R/W
/RD /WR
0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
BUSY /ADC OFF/ON RESET
BUSY: When high, the NT7534 is busy due to internal operation or reset. Any command is
rejected until BUSY goes low. The busy check is not required if enough time is provided for each
cycle.
/ADC: Indicates the relationship between RAM column address and segment drivers. When low,
the display is reversed and column address “131-n” corresponds to segment driver n. when high,
the display is normal and column address corresponds to segment driver n.
OFF/ON: Indicates whether the display is on or off. When low, the display turns on. When high,
the display turns off. This is the opposite of Display ON/OFF command.
RESET: Indicates the initialization is in progress by /RES signal or by reset command. When low,
the display is on. When high, the chip is being reset.
6.
Write Display Data
Write 8-bit data in display RAM. As the column address automatically increments by 1 after each
write, the microprocessor can continue to write data of multiple words.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
1
7.
1
Write Data
Read Display Data
Reads 8-bit data from display RAM area specified by column address and page address. As the
column address automatically increments by 1 after each write, the microprocessor can continue
to read data of multiple words. A single dummy read is required immediately after column address
setup. Refer to the display RAM section of FUNCTIONAL DESCRIPTION for details. Note that no
display data can be read via the serial interface.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
1
8.
0
0
1
Read Data
ADC Select
Changes the relationship between RAM column address and segment driver. The order of
segment driver output pads could be reversed by software. This allows flexible IC layout during
LCD module assembly. For details, refer to the column address section of Figure 4. When display
data is written or read, the column address is incremented by 1 as shown in Figure 4.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
2004/12/06
1
0
1
0
1
0
0
0
0
29
Hex
Setting
0
A0h
Normal
1
A1h
Reverse
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
9.
Normal/ Reverse Display
Reverses the Display ON/OFF status without rewriting the contents of the display data RAM.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
0
0
1
1
Hex
Setting
0
A6h
RAM Data “H”
LCD ON voltage (normal)
1
A7h
RAM Data “L”
LCD ON voltage (reverse)
10. Entire Display ON
Forcibly turns the entire display on regardless of the contents of the display data RAM. At this
time, the contents of the display data RAM are held. This command has priority over the
Normal/Reverse Display command. When D is low, the normal display status is provided.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
0
0
1
0
Hex
Setting
0
A4h
Normal display mode
1
A5h
Display all points ON
When D0 is high, the entire display ON status is provided. If the Entire Display ON command is
executed in the display OFF status, the LCD panel enters Power save mode. Refer to the Power
Save section for details.
11. LCD Bias Set
This command selects the voltage bias ratio required for the liquid crystal display.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
0
0
0
1
Hex
Duty
1/33
1/49
1/65
0
A2h 1/6 bias 1/8 bias 1/9 bias
1
A3h 1/5 bias 1/6 bias 1/7 bias
12. Read-Modify-Write
A pair of Read-Modify-Write and End commands must always be used. Once Read-Modify-Write
is issued, column address is not incremental by Read Display Data command but incremental by
Write Display Data command only. It continues until End command is issued. When the End is
issued, column address returns to the address when Read-Modify-Write is issued. This can
reduce the microprocessor load when data of a specific display area is repeatedly changed during
cursor blinking or other events.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
0
0
0
0
0
Hex
E0h
Note: Any command except Read/Write Display Data and Column Address Set can be issued
during Read-Modify-Write mode.
2004/12/06
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Cursor display sequence
Set Page Address
Set Column Address
Read-Modify-Write
Dummy Read
Read Data
No
Data process
Write Data
Completed?
Yes
End
13. End
Cancels Read-Modify-Write mode and returns column address to the original address (when
Read-Modify-Write is issued)
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
0
1
1
1
Hex
0
EEh
Return
Column address
N
N+1 N+2 N+3
N+m
Read-Modify-Write
mode is selected
2004/12/06
N
End
31
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
14. Reset
This command resets the Display Start Line register, Column Address counter, Page Address
register, and Common output mode register, the V0 voltage regulator internal resistor ratio
register, the Electronic Volume register, the static indicator mode register, the read-modify-write
mode register, and the test mode. The Reset command does not affect on the contents of display
RAM. Refer to the Reset circuit section of Function Description.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
0
0
0
1
0
Hex
E2h
The Reset command cannot initialize LCD power supply. Only the Reset signal to the /RES pad
can initialize the supplies.
15. Output Status Select Register
When D3 is high or low, the scan direction of the COM output pad is selectable. Refer to Output
Status Selector Circuit in Function Description for details.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
0
0
0
*
*
*
1
Hex
C0h to C7h
C8h to CFh
*: Invalid bit
D3 = 0: Normal (COM0 → COM63/47/31)
D3 = 1: Reverse (COM63/47/31 → COM0)
16. Power Control Set
Select one of eight power circuit functions using 3-bit register. An external power supply and part
of on-chip power circuit can be used simultaneously. Refer to Power Supply Circuit section of
FUNCTIONAL DESCRIPTION for details.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
0
1
0
1
A2 A1 A0
Hex
28h to 2Fh
When A0 goes low, voltage follower turns off. When A0 goes high, it turns on.
When A1 goes low, voltage regulator turns off. When A1 goes high, it turns on.
When A2 goes low, voltage booster turns off. When A2 goes high, it turns on.
2004/12/06
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
17. V0 Voltage Regulator Internal Resistor Ratio Set
This command sets the V0 voltage regulator internal resistor ratio. For details, see explanation
under “The Power Supply Circuits”.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
0
1
0
0
Hex
Rb/Ra Ratio
Small
0
0
0
20h
0
0
1
21h
0
1
0
22h
:
:
1
1
0
26h
1
1
1
27h
:
Large
18. The Electronic Volume (Double Byte Command)
This command makes it possible to adjust the brightness of the liquid crystal display by controlling
the liquid crystal drive voltage V0 through the output from the voltage regulator circuits of the
internal liquid crystal power supply. It is a two-byte command used as a pair with the electronic
volume mode set command and the electronic volume register set command, and both
commands must be issued one after the other.
(1) The Electronic Volume Mode Set
When this command is input, the electronic volume register set command is enabled. Once the
electronic volume mode has been set, no other command except for the electronic volume
register command can be used. Once the electronic volume register set command has been used
to set data into the register, then the electronic volume mode is released.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
0
0
0
0
0
1
Hex
81h
(2) Electronic Volume Register Set
By using this command to set six bits of data to the electronic volume register, the liquid crystal
voltage V0 assumes one of the 64 voltage levels. When this command is input, the electronic
volume mode is released after the electronic volume register has been set.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
*
*
Hex
V0
Small
0
0
0
0
0
1
XX
0
0
0
0
1
0
XX
:
:
1
1
1
1
1
0
XX
1
1
1
1
1
1
XX
:
Large
When the electronic volume function is not used, set D5 - D0 to 100000.
2004/12/06
33
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
19. Static Indicator (Double Byte Command)
This command controls the static drive system indicator display. The static indicator display is
controlled by this command only, and is independent of other display control commands.
This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR
terminal, and the other is connected to the FRS terminal. A different pattern is recommended for
the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it
can result in deterioration of the liquid crystal and of the electrodes.
The static indicator ON command is a double bytes command paired with the static indicator
register set command, and thus command must be executed one after the other. (The static
indicator OFF command is a single byte command)
(1) Static Indicator ON/OFF
When the static indicator ON command is entered, the static indicator register set command is
enabled. Once the static indicator ON command has been entered, no other command aside from
the static indicator register set command can be used. This mode is cleared when data is set in
the register by the static indicator register set command.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
1
0
1
1
0
Hex
Setting
0
ACh
Static Indicator OFF
1
ADh
Static Indicator ON
(2) Static Indicator Register Set
This command sets two bits of data into the static indicator register and used to set the static
indicator into a blinking mode.
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
*
*
*
*
*
*
0
0
A0
2004/12/06
Hex
Indicator Display Status
XX
OFF
0
1
XX
ON (blinking at approximately 1
second intervals)
1
0
XX
ON (blinking at approximately 0.5
second intervals)
1
1
XX
ON (constantly on)
34
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
20. Power Save (Compound Command)
When all displays are turned on during display off, the Power Save command is issued to greatly
reduce current consumption.
If the static indicator is off, the Power Save command makes the system enter sleep mode. If the
static indicator is on, this command makes the system enter standby mode.
Release the Sleep mode using the both Power Save OFF command (Display ON command or
Entire Display OFF command) and Set Indicator On command.
Static Indicator OFF
Static Indicator ON
Power Save
(Display OFF and Entire Display ON)
(Sleep mode)
(Standby mode)
Power Save OFF
(Display ON or Entire Displays OFF )
Static Indicator ON
(Sleep mode released)
(Standby mode released)
Sleep Mode
This mode stops every operation of the LCD display system, and can reduce current consumption
nearly to a static current value if no access is made from the microprocessor. The internal status
in the sleep mode is as follows:
(1) Stops the oscillator circuit and LCD power supply circuit.
(2) Stops the LCD driver and outputs the VSS level as the segment/common driver output.
(3) Holds the display data and operation mode provided before the start of the sleep mode.
(4) The MPU can access the built-in display data RAM.
Standby Mode
Stops the operation of the duty LCD displays system and turns on only the static drive system to
reduce current consumption to the minimum level required for static drive. The ON operation of
the static drive system indicates that the NT7534 is in standby mode. The internal status in the
standby mode is as follows:
(1) Stops the LCD power supply circuit.
(2) Stops the LCD drive and outputs the VSS level as the segment / common driver output.
However, the static drive system still operates.
(3) Holds the display data and operation mode provided before the start of the standby mode.
(4) The MPU can access the built-in display data RAM.
When the Reset command is issued in the standby mode, the sleep mode is set.
● When the LCD drive voltage level is given by an external resistive driver, the current of this
resistor must be cut so that it may be fixed to floating or VSS level, prior to or concurrently with
causing the NT7534 to go to the sleep mode or standby mode.
● When an external power supply is used, likewise, the function of this external power supply
must be stopped so that it may be fixed to floating or VSS level, prior to or concurrently with
causing the NT7534 to go to the sleep mode or standby mode.
2004/12/06
35
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
21. NOP
Non-Operation Command.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
0
0
0
1
1
Hex
E3h
22. Test Command
This is the dedicated IC chip test command. It must not be used for normal operation. If the Test
command is issued inadvertently, set the /RES input to low or issue the Reset command to
release the test mode.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
1
0
1
0
0
Hex
F0h to FFh
*: Invalid bit
Cautions: The NT7534 maintains an operation status specified by each command. However, the
internal operation status may be changed by a high level of ambient noise. Users must
consider how to suppress noise on the package and system or to prevent ambient
noise insertion. To prevent a spike in noise, built-in software for periodical status
refreshment is recommended. The test command can be inserted in an unexpected
place. Therefore it is recommended to enter the test mode reset command F0h during
the refresh sequence.
23. Oscillation Frequency Select
This command is to select the oscillation frequency of driver IC as below.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
2004/12/06
1
0
1
1
1
0
0
1
0
36
Hex Oscillation Frequency
0
E4h
Typical 31.4 KHz
1
E5h
Typical 26.3 KHz
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
24. Partial Display Mode Set
This command enables to select the display mode. When D0 is low, the IC is in normal display
mode, the maximum display duty ratio is decided by pin connection of DUTY0 and DUTY1 and
the command LCD Bias Set decides the LCD bias ratio. The IC enters into partial display mode
when D0 is high, then the commands Partial Display Duty Set and Partial Display Bias Set decide
the LCD display duty and bias ratios.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
0
0
0
0
1
Hex
Display Mode
0
82h
Normal Display
1
83h
Partial Display
25. Partial Display Duty and Bias Set
These two commands set the LCD display duty and bias ratios when the IC is in partial display
mode. They are invalid when the IC is in normal display mode. When the partial display duty is set,
the LCD bias for partial display is set simultaneous as below. The partial display duty will be kept
at maximum duty (decided by pins DUTY0 and DUTY1) when setting duty is larger than
maximum duty.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
0
1
1
0
Hex
Partial
Duty
Scanning Line
Line [0:7], COMS
0
0
0
30h
1/9 duty
0
0
1
31h
1/17 duty Line [0:15], COMS
0
1
0
32h
1/33 duty Line [0:31], COMS
0
1
1
33h
1/49 duty Line [0:47], COMS
1
0
0
34h
1/65 duty Line [0:63], COMS
1
1
0
1
1
*
35h
37h
Reserved
No effect
Using Partial Display Bias Set command to change the LCD bias in partial display mode.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
0
0
1
1
1
Hex
LCD Bias
0
0
0
38h
1/4
0
0
1
39h
1/5
0
1
0
3Ah
1/6
0
1
1
3Bh
1/7
1
0
0
3Ch
1/8
1
0
1
3Dh
1/9
1
1
0
3Eh
Reserved
1
1
1
3Fh
Reserved
Note: The COM waveform of no display area is non-select waveform.
2004/12/06
37
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
26. Partial Start Line Set (Double Byte Command)
This command makes it possible to set the partial start line for partial display. It is a two-byte
command used as a pair and the Number of Start Line Set command must be issued after the
Partial Start Line Set command.
(1) Partial Start Line Set
When this command is input, no other command except for the Number of Start Line Set
command can be used.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
0
1
0
0
1
1
Hex
D3h
(2) Number of Start Line Set
By using this command to set six bits of data to the Partial Start Line register. Once the Number
of the Start Line Set command has been used to set data into the register, then the partial start
line will affect on the LCD display. The number of partial start line is always equal to zero when
the partial start line is larger than maximum duty ratio (decided by pins DUTY0 and DUTY1).
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
*
*
Partial
Start Line
0
0
0
0
0
0
XX
0 line
0
0
0
0
0
1
XX
1 line
0
0
0
0
1
0
XX
2 line
:
:
:
2004/12/06
Hex
1
1
1
1
1
0
XX
62 line
1
1
1
1
1
1
XX
63 line
38
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
27. The N-Line Inversion (Double Byte Command)
This command makes it possible to adjust the number of scan lines for liquid crystal display
inversion. It is a two-byte command used as a pair and the Number of Line Set command must be
issued after the N-Line Inversion Set command.
(1) N-Line Inversion Set
When this command is input, no other command except for the Number of Line Set command
can be used.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
0
0
0
0
1
0
1
Hex
85h
(2) Number of Line Set
By using this command to set five bits of data to the N-Line inversion register. Once the Number
of Line Set command has been used to set the data into the register, then the N-Line inversion
will affect on the LCD display.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
*
*
*
Hex
Line
Inversion
0
0
0
0
0
XX
1 line
0
0
0
0
1
XX
2 line
:
:
XX
32 line
:
1
1
1
1
1
Note 1: The number of inversed scan line = register setting value + 1.
Note 2: When Partial Duty = 1/9 or 1/17, the N-line inversion function release and the LCD
display scan line is back to frame inversion status.
12 3 4 5 6
Frame
Inversion
M
N-line
Inversion
M'
m
n
n
28. Release N-Line Inversion
This command is used to exit the N-Line inversion function. The N-Line inversion function is
released and the LCD display is set back to frame inversion status once this command is
executed.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
2004/12/06
1
0
1
0
0
0
0
1
0
39
0
Hex
84h
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
29. DC/DC Clock Frequency (Double Byte Command)
This command makes it possible to adjust the frequency for DC/DC clock. It is a two-byte
command used as a pair and the DC/DC Frequency Division Set command must be issued after
the DC/DC Clock Set command.
(1) DC/DC Clock Set
When this command is input, no other command except for the DC/DC Frequency Division Set
command can be used.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
1
0
1
1
1
0
0
1
1
0
Hex
E6h
(2) DC/DC Frequency Division Set
By using this command to set five bits of data to the frequency division register.
A0
E R/W
D7 D6 D5 D4 D3 D2 D1 D0
/RD /WR
0
2004/12/06
1
0
*
*
*
*
Hex
Division
0
0
0
0
XX
fOSC
0
0
0
1
XX
fOSC/2
0
0
1
0
XX
fOSC/4
0
0
1
1
XX
fOSC/6
(default)
0
1
0
0
XX
fOSC/8
0
1
0
1
XX
fOSC/10
0
1
1
0
XX
fOSC/12
0
1
1
1
XX
fOSC/14
1
0
0
0
XX
fOSC/16
1
0
0
1
XX
fOSC/18
1
0
1
0
XX
fOSC/20
1
0
1
1
XX
fOSC/22
1
1
0
0
XX
fOSC/24
1
1
0
1
XX
fOSC/26
1
1
1
0
XX
fOSC/28
1
1
1
1
XX
fOSC/30
40
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Table 14. Command Table
Command
A0
/RD
/WR
(1) Display OFF
0
1
(2) Display Start Line Set
0
(3) Page Address Set
Code
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
Page Address
0
1
0
0
0
0
1
Higher Column
Address
0
1
0
0
0
0
0
Lower Column
Address
(5) Read Status
0
0
1
Status
0
(6) Write Display Data
1
1
0
Write Data
(7) Read Display Data
1
0
1
Read Data
0
0
Function
AEh Turn on LCD panel when high, and
AFh turn off when low
40h
to
7Fh
B0h
to
B8h
Display Start Address
(4) Column Address Set
Hex
Specifies RAM display line for
COM0
Set the display data RAM page in
Page Address register
Set 4 higher bits and 4 lower bits
00h of column address of display data
to RAM in register
18h
0
XX Reads the status information
XX Write data in display data RAM
XX Read data from display data RAM
0
1
0
1
A0h
A1h
A6h
A7h
Set the display data RAM address
SEG output correspondence
Normal indication when low, but
full indication when high
0
1
0
1
A4h Select normal display (0) or entire
A5h display on
A2h Sets LCD driving voltage bias ratio
A3h
(8) ADC Select
0
1
0
1
0
1
0
0
0
0
(9) Normal/Reverse Display
0
1
0
1
0
1
0
0
1
1
(10)Entire Display ON/OFF
0
1
0
1
0
1
0
0
1
0
(11)LCD Bias Set
0
1
0
1
0
1
0
0
0
1
(12)Read-Modify-Write
0
1
0
1
1
1
0
0
0
0
0
(13)End
0
1
0
1
1
1
0
1
1
1
0
Increments column address
counter during each write
EEh Releases the Read-Modify-Write
(14)Reset
0
1
0
1
1
1
0
0
0
1
0
E2h Resets internal functions
E0h
C0h
*
*
*
to
CFh
28h
Operation Status to
2Fh
Select COM output scan direction
*: invalid data
(15)Common Output Mode
Select
0
1
0
1
1
0
0
0
1
(16)Power Control Set
0
1
0
0
0
1
0
1
(17)V0 Voltage Regulator
Internal Resistor ratio
Set
0
1
0
0
0
1
0
0
Resistor Ratio
20h Select internal resistor ratio Rb/Ra
to mode
27h
0
1
0
1
0
0
0
0
0
1
81h
0
1
0
*
*
0
1
0
1
0
1
0
1
1
0
1
Sets the V0 output voltage
electronic volume register
ACh Sets static indicator ON/OFF
ADh 0: OFF, 1: ON
0
1
0
*
*
*
*
*
*
Mode
(20)Power Save
0
1
0
-
-
-
-
-
-
-
-
(21)NOP
0
1
0
1
1
1
0
0
0
1
1
(18)Electronic Volume
mode Set
Electronic Volume
Register Set
(19)Set Static indicator
ON/OFF
Set Static Indicator
Register
2004/12/06
0
Electronic Control Value
41
0
Select the power circuit operation
mode
XX
XX
Sets the flash mode
Compound command of Display
OFF and Entire Display ON
E3h Command for non-operation
-
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Command Table (continue)
Command
A0
/RD
/WR
(22)Oscillation Frequency
Select
0
1
(23)Partial Display mode
Set
0
(24)Partial Display Duty Set
Code
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
0
0
1
E4h Select the oscillation frequency
E5h
1
0
1
0
0
0
0
0
1
0
1
82h Enter/Release the partial display
83h mode
0
1
0
0
0
1
1
0
Duty Ratio
30h Sets the LCD duty ratio for partial
37h display mode
(25)Partial Display Bias Set
0
1
0
0
0
1
1
1
Bias Ratio
38h Sets the LCD bias ratio for partial
3Fh display mode
(26)Partial Start Line Set
0
1
0
1
1
0
1
0
Partial Start Line Set
0
1
0
1
1
0
1
0
1
0
0
0
1
0
*
*
*
(28)N-Line Inversion
Release
0
1
0
1
0
0
0
0
1
0
0
84h
(29)DC/DC Clock Set
0
1
0
1
1
1
0
0
1
1
0
E6h Set DC/DC Clock Frequency
0
1
0
1
1
0
0
(30)Test Command
0
1
0
1
1
1
1
*
*
*
*
(31)Test Mode Reset
0
1
0
1
1
1
1
0
0
0
0
(27)N-Line Inversion Set
Number of Line Set
DC/DC Clock Division
Set
0
1
1
Partial Start Line
0
0
1
Hex
Function
D7
D3h
XX
0
1
Number of Line
85h
XX
Enter Partial Start Line Set
Sets the LCD Number of partial
display start line
Enter N-Line inversion
Sets the number of line used for
N-Line inversion
Exit N-Line Inversion
Set the Division of DC/DC Clock
XX Frequency
Clock Division
F1h IC test command. Do not use!
to
FFh
F0h Command of test mode reset
Note: Do not use any other command, or system malfunction may result.
2004/12/06
42
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Command Description
Instruction Setup: Reference
1. Initialization
Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG
pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM.
When electric charge is remaining in the smoothing capacitor connecting between the LCD driving
voltage output pins (V0 - V4) and the VDD pin, the picture on the display may instantaneously
become totally dark when the power is turned on. To avoid such failure, we recommend the
following flow sequence when turning on the power.
1.1. When the built-in power is being used immediately after turning on the power:
Turn ON the VDD-VSS power keeping the /RES pin = "L"
When the power is stabilized
Release the reset state. (/RES pin = "H")
Initialized state (Default)
Function setup by command input (User setup)
(11) LCD bias setting
(8) ADC selection
(15) Common output state selection
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V 0 voltage
(18) Electronic volume control
Function setup by command input (User setup)
(16) Power control setting
This concludes the initialization
2004/12/06
43
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
1.2. When the built-in power is not being used immediately after turning on the power
Turn ON the VDD - VSS power keeping the /RES pin = "L"
When the power is stabilized
Release the reset state. (/RES pin = "H")
Initialized state (Default)
Power saver START (multiple commands)
Function setup by command input (User setup)
(11) LCD bias setting
(8) ADC selection
(15) Common output state selection
Function setup by command input (User setup)
(17) Setting the built-in resistance radio
for regulation of the V 0 voltage
(18) Electronic volume control
Power saver OFF
Function setup by command input (User setup)
(16) Power control setting
This concludes the initialization
2004/12/06
44
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
2. Data Display
End of initialization
Function setup by command input (User setup)
(2) Display start line set
(3) Page address set
(4) column address set
Function setup by command input (user setup)
(6) Display data write
Function setup by command input (User setup)
(1) Display ON/OFF
End of data display
3. Power OFF
Optional status
Function setup by command input (User setup)
(20) Power save
VDD-VSS power OFF
2004/12/06
45
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Absolute Maximum Rating
DC Supply Voltage (VDD, VDD2, VDD3) ..…………………………………………………... -0.3V to +4.0V
DC Supply Voltage (VOUT) ……………………………………………………………… -0.3V to +15.0V
DC Supply Voltage (V0) ……………………………………………………………… -0.3V to +15.0V
Input Voltage (Vin) ……………………………………………………………………….. -0.3V to VDD+0.3V
Operating Ambient Temperature …………………………………………………………… -40°C to +85°C
Storage Temperature ……………………………………………………………………… -55°C to +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this
device. These are stress ratings only. Functional operation of this device under these or any other
conditions above those indicated in the operational sections of this specification is not implied or
intended. Exposure to the absolute maximum rating conditions for extended periods may affect device
reliability.
Electrical Characteristics
DC Characteristics
Symbol
(VSS = 0V, VDD = 1.8 ~ 3.6V, Ta = -40 ~ +85°C unless otherwise specified)
Parameter
Min.
Typ.
1.8
-
3.6
1.8
1.8
1.8
6.0
-
3.6
3.3
2.8
14.2
Voltage Regulator
Operating Voltage
4.0
-
14.2
V
VREG Reference Voltage
2.04
2.10
2.16
V
-
20
35
-
90
160
-
150
255
VDD
VDD3
Operating Voltage
VDD2
Operating Voltage
VOUT Booster Voltage
V0
IDD
Max. Unit
V
Current Consumption
2004/12/06
Condition
46
V
2X, 3X boosting
4X boosting
5X boosting
V
Ta = 25°C, -0.05%/°C
VDD = 3V, V0 = 11V, built-in boosting
power supply off, display on,
µA
display data = checker and no access,
Ta = 25°C
VDD, VDD2 = 3V, V0 = 11V, 4X built-in
boosting power supply, display on,
display data = checker and no access,
µA
temperature gradient is -0.05%/ °C,
Ta = 25°C, V0 voltage internal resistor is
used, /HPM = 1 (normal power mode).
VDD, VDD2 = 3V, V0 = 11V, 4X built-in
boosting power supply, display on,
display data = checker and no access,
µA
temperature gradient is -0.05%/ °C,
Ta = 25°C, V0 voltage internal resistor is
used, /HPM = 0 (high power mode).
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
DC Characteristics (continued)
Symbol
Parameter
Sleep Mode Current
Consumption
Standby Mode
ISB
Current Consumption
High-Level Input
VIHC
Voltage
Low-Level Input
VILC
Voltage
High-Level Output
VOHC
Voltage
Low -Level Output
VOLC
Voltage
ISP
Min.
Typ.
Max. Unit
-
0.01
5
µA During sleep, Ta = 25°C
-
4
8
µA During standby, Ta = 25°C
0.8 x
VDD
-
VDD
V
VSS
-
0.2 x
VDD
V
0.8 x
VDD
-
VDD
V
VDD
-
0.2 x
VDD
V
ILI
Input Leakage
Current
-1.0
-
1.0
µA
IHZ
HZ Leakage Current
-3.0
-
3.0
µA
RON1
LCD Driver ON
Resistance
-
2.0
3.5
KΩ
RON2
LCD Driver ON
Resistance
-
3.2
5.4
KΩ
Input Pad Capacity
-
5.0
8.0
pF
78.0
80.5
83.0
Hz
64.9
67.4
69.9
Hz
CIN
fFRM Frame Frequency
Condition
A0, D0 - D7, /RD (E), /WR (R/W), /CS1,
CS2, CLS, CL, FR, M/S, C86, P/S, /DOF,
/RES, IRS and /HPM
IOH = -0.5mA (D0 - D7, FR, FRS, /DOF,
and CL)
IOL = 0.5mA (D0 - D7, FR, FRS, /DOF,
and CL)
Vin = VDD or VSS (A0, /RD (E), /WR
(R/W), /CS1, CS2, CLS, M/S, C86, P/S,
IRS and /RES)
When the D0 - D7, FR, CL, and /DOF are
in high impedance
Ta = 25°C,
V0 = 11.0V These are the resistance
values for when a 0.1V
voltage is applied between
the output terminals SEGn or
COMn and the various power
V0 = 8.0V
supply terminal (V0, V1, V2,
V3, V4)
Ta = 25°C, f = 1MHz
fOSC = 31.4 KHz, 1/65duty
VDD = 1.8~3.6V
fOSC = 26.3 KHz, 1/65duty
VDD = 1.8~3.6V
Notes: 1. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS2 must always be satisfied.
2004/12/06
47
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
AC Characteristics
1. System Buses Read/Write Characteristics (for 8080 Series MPU)
A0
tAS8
tAH8
/CS1
(CS2)
tCYC8
tCCLW, tCCLR
/WR,
/RD
tCCHW, tCCHR
tDS8
tDH8
D0~D7
(Write)
tACC8
tCH8
D0~D7
(Read)
(VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
TAH8
Address hold time
0
-
-
ns
TAS8
Address setup time
0
-
-
ns
tCYC8
System cycle time
240
-
-
ns
tCCLW
Control low pulse width (write)
90
-
-
ns
/WR
tCCLR
Control low pulse width (read)
120
-
-
ns
/RD
tCCHW
Control high pulse width (write)
100
-
-
ns
/WR
tCCHR
Control high pulse width (read)
60
-
-
ns
/RD
TDS8
Data setup time
40
-
-
ns
TDH8
Data hold time
10
-
-
ns
tACC8
/RD access time
-
-
140
ns
TCH8
Output disable time
5
-
50
ns
2004/12/06
48
A0
D0~D7
D0~D7, CL = 100pF
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
System Buses Read/Write Characteristics (for 8080 Series MPU) (continued)
(VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
tAH8
Address hold time
0
-
-
ns
tAS8
Address setup time
0
-
-
ns
tCYC8
System cycle time
400
-
-
ns
tCCLW
Control low pulse width (write)
150
-
-
ns
/WR
tCCLR
Control low pulse width (read)
150
-
-
ns
/RD
tCCHW
Control high pulse width (write)
120
-
-
ns
/WR
tCCHR
Control high pulse width (read)
120
-
-
ns
/RD
tDS8
Data setup time
80
-
-
ns
tDH8
Data hold time
30
-
-
ns
tACC8
/RD access time
-
-
240
ns
tCH8
Output disable time
10
-
100
ns
A0
D0~D7
D0~D7, CL = 100pF
*1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less.
(tr + tf) < (tCYC8 - tCCLW - tCCHW) for write, (tr + tf) < (tCYC8 - tCCLR - tCCHR) for read.
*2. All timing is specified using 20% and 80% of VDD as the reference.
*3. tCCLW and tCCLR are specified as the overlap interval when /CS1 is low (CS2 is high) and /WR or
/RD is low.
2004/12/06
49
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
2. System Buses Read/Write Characteristics (for 6800 Series MPU)
A0,R/W
tAS6
tAH6
/CS1
(CS2)
tCYC6
tEWLW, tEWLR
E
tEWHW, tEWHR
tDS6
tDH6
D0~D7
(Write)
tACC6
tOH6
D0~D7
(Read)
(VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
tAH6
Address hold time
0
-
-
ns
tAS6
Address setup time
0
-
-
ns
tCYC6
System cycle time
240
-
-
ns
tEWHW
Control high pulse width (write)
90
-
-
ns
E
tEWHR
Control high pulse width (read)
120
-
-
ns
E
tEWLW
Control low pulse width (write)
100
-
-
ns
E
tEWLR
Control low pulse width (read)
60
-
-
ns
E
tDS6
Data setup time
40
-
-
ns
tDH6
Data hold time
10
-
-
ns
tACC6
/RD access time
-
-
140
ns
tOH6
Output disable time
5
-
50
ns
2004/12/06
50
A0, R/W
D0~D7
D0~D7
CL = 100pF
Ver 1.0
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fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
System Buses Read/Write Characteristics (for 6800 Series MPU) (continued)
(VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
tAH6
Address hold time
0
-
-
ns
tAS6
Address setup time
0
-
-
ns
tCYC6
System cycle time
400
-
-
ns
tEWHW
Control high pulse width (write)
150
-
-
ns
E
tEWHR
Control high pulse width (read)
150
-
-
ns
E
tEWLW
Control low pulse width (write)
120
-
-
ns
E
tEWLR
Control low pulse width (read)
120
-
-
ns
E
tDS6
Data setup time
80
-
-
ns
tDH6
Data hold time
30
-
-
ns
tACC6
/RD access time
-
-
240
ns
tOH6
Output disable time
10
-
100
ns
A0, R/W
D0~D7
D0~D7
CL = 100pF
*1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less.
(tr + tf) < (tCYC6 - tEWLW - tEWHW) for write, (tr + tf) < (tCYC6 - tEWLR - tEWHR) for read.
*2. All timing is specified using 20% and 80% of VDD as the reference.
*3. tEWHW and tEWHR are specified as the overlap interval when /CS1 is low (CS2 is high) and E is high.
2004/12/06
51
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
3. Serial Interface Timing
tCSS
tSCYC
tCSH
/CS1
(CS2)
tr
tSHW
tSLW
SCL
tf
tSAS
tSAH
A0
tSDS
tSDH
SI
(VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
tSCYC
Serial clock cycle
120
-
-
ns
SCL
tSHW
Serial clock H pulse width
60
-
-
ns
SCL
tSLW
Serial clock L pulse width
60
-
-
ns
SCL
tSAS
Address setup time
30
-
-
ns
A0
tSAH
Address hold time
20
-
-
ns
A0
tSDS
Data setup time
30
-
-
ns
SI
tSDH
Data hold time
20
-
-
ns
SI
tCSS
Chip select setup time
20
-
-
ns
/CS1, CS2
tCSH
Chip select hold time
40
-
-
ns
/CS1, CS2
2004/12/06
52
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Serial Interface Timing (continued)
(VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
tSCYC
Serial clock cycle
200
-
-
ns
SCL
tSHW
Serial clock H pulse width
80
-
-
ns
SCL
tSLW
Serial clock L pulse width
80
-
-
ns
SCL
tSAS
Address setup time
60
-
-
ns
A0
tSAH
Address hold time
30
-
-
ns
A0
tSDS
Data setup time
60
-
-
ns
SI
tSDH
Data hold time
60
-
-
ns
SI
tCSS
Chip select setup time
40
-
-
ns
/CS1, CS2
tCSH
Chip select hold time
100
ns
*1. The input signal rise time and fall time (tr, tf) is specified as 15ns or less.
*2. All timing is specified using 20% and 80% of VDD as the standard.
/CS1, CS2
2004/12/06
53
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
4. Display Control Timing
CL
(Output)
tDFR
FR
(VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85°C)
Symbol
tDFR
Parameter
FR delay time
Min.
Typ.
Max.
Unit
-
20
80
ns
Condition
CL = 50 pF
(VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85°C)
Symbol
tDFR
Parameter
FR delay time
Min.
Typ.
Max.
Unit
-
40
160
ns
Condition
CL = 50 pF
5. Reset Timing
tRW
tR
/RES
Internal
Status
During Reset
(VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85°C)
Symbol
Parameter
tR
Reset Time
tRW
Reset low pulse width
Min.
Typ.
Max.
Unit
-
-
1.0
µs
10
-
-
µs
Condition
/RES
(VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85°C)
Symbol
Parameter
tR
Reset Time
tRW
Reset low pulse width
2004/12/06
Min.
Typ.
Max.
Unit
-
-
2.0
µs
20
-
-
µs
54
Condition
/RES
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Microprocessor Interface (for reference only)
8080-series microprocessors
VDD
V CC
A0
A1 to A7
/IORQ
A0
VDD
/CS1
Decoder
CS2
MPU
C86
NT7534
D0 to D7
VSS
D0 to D7
/RD
/WR
VDD
/RD
/WR
P/S
/RES
/RES
VSS
GND
V SS
Figure 9
6800-series microprocessors
V DD
V CC
A0
A0
A1 to A15
VMA
Decoder
VDD
VDD
/CS1
CS2
MPU
C86
NT7534
D0 to D7
D0 to D7
E
R/W
E
R/W
P/S
/RES
/RES
VSS
GND
V SS
Figure 10
2004/12/06
55
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Connections between LCD Drivers (for reference only)
The liquid crystal display area can be enlarged with ease through the use of multiple NT7534 chips.
Use same equipment type.
NT7534 (master) ↔ NT7534 (slave)
VDD
CLS
M/S
M/S
FR
FR
CL
CL
/DOF
/DOF
NT7534
Master
VSS
V0
V0
V1
V2
V1
V3
V3
NT7534
Slave
V2
V4
V4
VSS
VSS
V SS
Figure 11
2004/12/06
56
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Application information for LCD panel (for reference only)
1. Type I (ADC Select = 0, COM Output Select = 1)
C
CC
O
OO
M
MM
1
0S
0
COM11
COM12
COM24
CC
OO
MM
2 2
5 6
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S S
E E
G G
9 1
0
S
E
G
1
2
7
S
E
G
1
2
8
S
E
G
1
2
9
S
E
G
1
3
0
S
E
G
1
3
1
COM57
CC
C
OO
O
MM M
S6
5
3
8
IC Bumper
Face Down
C
O
M
3
1
CC
C
OO
O
MM M
3 3
4
2 3
3
COM44
COM45
2. Type II (ADC Select = 1, COM Output Select = 0)
CC
C
OO
O
MM
M
6S
5
8
3
COM57
COM45
COM44
CC
C
OO
O
MM
M
33
4
3
32
2004/12/06
IC Bumper
Face Down
S
E
G
1
3
1
S
E
G
1
3
0
S
E
G
1
2
9
S
E
G
1
2
8
S
E
G
1
2
7
S
E
G
1
2
6
S
E
G
1
2
5
S
E
G
1
2
4
S
E
G
1
2
3
S
E
G
1
2
2
S
E
G
4
57
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
CC
C
OO
O
MM M
3 3
2
1 0
5
COM24
COM12
COM11
C
CC
O
OO M
MM
1
S0
0
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
3. Type III (ADC Select = 1, COM Output Select = 1)
C
CC
O
OO
M
MM
4
33
3
3 2
COM44
COM45
COM57
C
CC
O
OO
M
MM
5
6S
8
3
S
E
G
1
3
1
S
E
G
1
3
0
S
E
G
1
2
9
S
E
G
1
2
8
S
E
G
1
2
7
S
E
G
1
2
6
S
E
G
1
2
5
S
E
G
1
2
4
S
E
G
1
2
3
S
E
G
4
S S
E E
G G
1 1
2 2
2 1
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
IC Bumper
Face Up
CC
OO
MM
S0
C
O
M
1
0
COM11
COM12
COM24
CC
C
OO
O
MM M
3 3
2
1 0
5
4. Type IV (ADC Select = 0, COM Output Select = 0)
C
CC
O
OO
M
MM
2
33
01
5
COM24
COM12
COM11
C
CC
O
OO
M
MM
1
0S
0
2004/12/06
C
CC
O
OO
MM M
5
S6
3
8
COM57
IC Bumper
Face Up
S
E
G
0
S
E
G
1
S
E
G
2
S
E
G
3
S
E
G
4
S
E
G
5
S
E
G
6
S
E
G
7
S
E
G
8
S
E
G
1
2
7
S
E
G
9
58
S
E
G
1
2
8
S
E
G
1
2
9
S
E
G
1
3
0
S
E
G
1
3
1
COM45
COM44
CC
C
OO
O
MM M
3 3
4
2 3
3
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Application information for Pin Connection to MPU (for reference only)
1. 8080 MPU Mode: (DUTY0,1 = 11: 1/65duty, M/S = 1: Master mode, CLS = 1: Internal display OSC,
/HPM = 1: Normal power mode, IRS = 1: Internal Rb/Ra)
COM44
COM63
COMS
COM56
COM57
COM58
COM43
COM42
FR
CL
/DOF
/CS
/CS1
COM35
CS2
COM34
/RES
/RES
A0
A0
/WR
/WR
SEG131
/RD
/RD
SEG130
TEST0
SEG129
D0
D0
SEG128
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
COM33
COM32
SEG127
D7
D7
DUTY0
DUTY1
VDD
VDD
VDD3
VDD2
VSS
VSS3
VSS
VSS2
TEST1
VSS
C1
VOUT
CAP4+
C1
CAP3+
CAP1-
C1
CAP1+
C1
CAP2+
CAP2-
VSS
VSS
VSS
VSS
VSS
C2
C2
V1
V2
C2
V3
C2
V4
C2
V0
SEG4
SEG3
SEG2
SEG1
VR
SEG0
M/S
COMS
CLS
COM0
C86
COM1
P/S
COM2
/HPM
IRS
COM31
59
COM11
2004/12/06
COM23
COM24
COM26
COM25
COM9
COM10
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
2. 6800 MPU Mode: (DUTY0,1 = 11: 1/65duty, M/S = 1: Master mode, CLS = 1: Internal display OSC,
/HPM = 1: Normal power mode, IRS = 1: Internal Rb/Ra)
COM44
COM63
COMS
COM56
COM57
COM58
COM43
COM42
FR
CL
/DOF
/CS
/CS1
COM35
CS2
COM34
COM33
/RES
/RES
A0
A0
R/W
/WR
SEG131
COM32
/RD
SEG130
TEST0
SEG129
D0
D0
SEG128
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
E
D7
SEG127
D7
DUTY0
DUTY1
VDD
VDD
VDD3
VDD2
VSS
VSS3
VSS
VSS2
TEST1
VSS
C1
VOUT
CAP4+
C1
CAP3+
CAP1-
C1
CAP1+
C1
CAP2+
CAP2-
VSS
VSS
VSS
VSS
VSS
C2
C2
V1
V2
C2
V3
C2
V4
C2
V0
SEG4
SEG3
SEG2
SEG1
VR
SEG0
M/S
COMS
CLS
COM0
C86
COM1
P/S
COM2
/HPM
IRS
COM31
60
COM11
2004/12/06
COM23
COM24
COM26
COM25
COM9
COM10
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
3. Serial Mode: (DUTY0,1 = 11: 1/65duty, M/S = 1: Master mode, CLS = 1: Internal display OSC,
/HPM = 1: Normal power mode, IRS = 1: Internal Rb/Ra)
COM44
COM63
COMS
COM56
COM57
COM58
COM43
COM42
FR
CL
/DOF
/CS1
COM35
CS2
COM34
/RES
/RES
COM33
A0
A0
/CS
COM32
/WR
SEG131
/RD
SEG130
TEST0
SEG129
D0
SEG128
SEG127
D1
D2
D3
D4
D5
D6
SCL
D7
SI
DUTY0
DUTY1
VDD
VDD
VDD3
VDD2
VSS
VSS3
VSS
VSS2
TEST1
VSS
C1
VOUT
CAP4+
C1
CAP3+
CAP1-
C1
C1
CAP1+
CAP2+
CAP2-
VSS
VSS
VSS
VSS
VSS
C2
C2
C2
C2
C2
V1
V2
SEG4
V3
SEG3
V4
SEG2
V0
SEG1
VR
SEG0
M/S
COMS
CLS
COM0
C86
COM1
P/S
COM2
/HPM
IRS
COM31
61
COM11
2004/12/06
COM23
COM24
COM26
COM25
COM9
COM10
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Bonding Diagram
8456 um
132
131
DUMMY
116
DUMMY
DUMMY
1000 um
DUMMY
289
DUMMY
290
305
DUMMY
DUMMY
NT7534
ALK_L
ALK_R
DUMMY
1
115
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DUMMY
COM58
COM59
COM60
COM61
COM62
COM63
COMS
FRS
FR
CL
/DOF
VSS
/CS1
CS2
VDD
/RES
A0
/WR
TEST0
/RD
VDD
D0
D0
D1
D1
D2
D2
D3
-3938
-3883
-3833
-3783
-3733
-3683
-3633
-3583
-3465
-3395
-3325
-3255
-3185
-3115
-3045
-2975
-2835
-2765
-2695
-2625
-2555
-2485
-2415
-2345
-2275
-2205
-2135
-2065
-1995
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
D3
D4
D4
D5
D5
D6
D6
D7
D7
DUTY0
VSS
DUTY1
VDD
VDD
VDD
VDD3
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS3
VSS2
VSS2
VSS2
VSS2
TEST1
-1925
-1855
-1785
-1715
-1645
-1575
-1505
-1435
-1365
-1295
-1225
-1155
-1085
-1015
-945
-875
-805
-735
-665
-595
-525
-455
-385
-315
-245
-175
-105
-35
35
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
-360
2004/12/06
62
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
59
VOUT
105
-360
95
V0
2625
-360
60
VOUT
175
-360
96
VR
2695
-360
61
VOUT
245
-360
97
VDD
2765
-360
62
CAP4+
315
-360
98
M/S
2835
-360
63
CAP4+
385
-360
99
CLS
2905
-360
64
CAP4+
455
-360
100
VSS
2975
-360
65
CAP4+
525
-360
101
C86
3045
-360
66
CAP3+
595
-360
102
P/S
3115
-360
67
CAP3+
665
-360
103
VDD
3185
-360
68
CAP3+
735
-360
104
/HPM
3255
-360
69
CAP3+
805
-360
105
VSS
3325
-360
70
CAP1-
875
-360
106
IRS
3395
-360
71
CAP1-
945
-360
107
VDD
3465
-360
72
CAP1-
1015
-360
108
COM31
3583
-360
73
CAP1-
1085
-360
109
COM30
3633
-360
74
CAP1+
1155
-360
110
COM29
3683
-360
75
CAP1+
1225
-360
111
COM28
3733
-360
76
CAP1+
1295
-360
112
COM27
3783
-360
77
CAP1+
1365
-360
113
COM26
3833
-360
78
CAP2+
1435
-360
114
COM25
3883
-360
79
CAP2+
1505
-360
115
DUMMY
3938
-360
80
CAP2+
-360
116
DUMMY
4088
-380
81
CAP2+
1645
-360
117
COM24
4088
-325
82
CAP2-
1715
-360
118
COM23
4088
-275
83
CAP2-
1785
-360
119
COM22
4088
-225
84
CAP2-
1855
-360
120
COM21
4088
-175
85
CAP2-
1925
-360
121
COM20
4088
-125
86
V1
1995
-360
122
COM19
4088
-75
87
V1
2065
-360
123
COM18
4088
-25
88
V2
2135
-360
124
COM17
4088
25
89
V2
2205
-360
125
COM16
4088
75
90
V3
2275
-360
126
COM15
4088
125
91
V3
2345
-360
127
COM14
4088
175
92
V4
2415
-360
128
COM13
4088
225
93
V4
2485
-360
129
COM12
4088
275
94
V0
2555
-360
130
COM11
4088
325
2004/12/06
1575
63
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad No.
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
2004/12/06
Designation
DUMMY
DUMMY
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
X
Y
4088
3938
3883
3833
3783
3733
3683
3633
3583
3533
3483
3433
3383
3333
3275
3225
3175
3125
3075
3025
2975
2925
2875
2825
2775
2725
2675
2625
2575
2525
2475
2425
2375
2325
2275
2225
380
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
Pad No.
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
64
Designation
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
X
Y
2175
2125
2075
2025
1975
1925
1875
1825
1775
1725
1675
1625
1575
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
375
325
275
225
175
125
75
25
-25
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
-975
-1025
-1075
-1125
-1175
-1225
-1275
-1325
-1375
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
-1425
-1475
-1525
-1575
-1625
-1675
-1725
-1775
-1825
-1875
-1925
-1975
-2025
-2075
-2125
-2175
-2225
-2275
-2325
-2375
-2425
-2475
-2525
-2575
-2625
-2675
-2725
-2775
-2825
-2875
-2925
-2975
-3025
-3075
-3125
-3175
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
2004/12/06
65
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
SEG130
SEG131
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
DUMMY
DUMMY
COM44
-3225
-3275
-3333
-3383
-3433
-3483
-3533
-3583
-3633
-3683
-3733
-3783
-3833
-3883
-3938
-4088
-4088
360
360
360
360
360
360
360
360
360
360
360
360
360
360
360
380
325
292
293
294
295
296
297
298
299
300
301
302
303
304
305
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
DUMMY
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
-4088
275
225
175
125
75
25
-25
-75
-125
-175
-225
-275
-325
-380
Alignment Mark Location (Total: 2 pins)
NO
X
Y
L
-3830
-100
R
3830
-100
2004/12/06
66
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Package Information
8456 um
289
132
DUMMY
116
20
30
30
ALK_L
DUMMY
305
30
131
1000 um
NT7534
DUMMY
DUMMY
30 30 30
20
ALK_R
DUMMY
DUMMY
DUMMY
290
DUMMY
1
115
Pad Dimensions
Item
Size
Pad No.
Y
8456
1000
Chip size
-
Chip thickness
-
525
9 ~ 16, 17 ~ 107
70
2 ~ 8, 108 ~ 114, 117 ~ 130,
133 ~ 144, 145 ~ 276, 277 ~ 288,
291 ~ 304
50
8 ~ 9, 107 ~ 108
118
16 ~ 17
140
144 ~ 145, 276 ~ 277
58
1 ~ 2, 114 ~ 115, 116 ~ 117,
130 ~ 131, 132 ~ 133, 288 ~ 289,
290 ~ 291, 304 ~ 305
55
Pad pitch
Output Pad
Bump size
Input Pad
Dummy Pad
Bump height
2004/12/06
Unit
X
µm
µm
2 ~ 8,
108 ~ 114,
133 ~ 288,
32
90
117 ~ 130,
291 ~ 304
90
32
9 ~ 107
45
90
1, 115, 132, 289
40
90
116, 131, 290, 305
90
40
All pads
µm
15 ± 3
67
µm
µm
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
NT7534
Ordering Information
Part No.
NT7534H-BDT
Packages
Gold Bump on Chip Tray
NT7534H-TABF1
48mm Tape Automated Bonding Package
NT7534H-TAB0011
35mm Tape Automated Bonding Package
Cautions
1. The contents of this document will be subjected to change without notice.
2. Precautions against light projection:
Light has the effect of causing the electrons of semiconductor to move; so light projection may
change the characteristics of semiconductor devices. For this reason, it is necessary to take
account of effective protection measures for the packages (such as COB, COG, TCP and COF,
etc.) causing chip to be exposed to a light environment in order to isolate the projection of light
on any part of the chip, including top, bottom and the area around the chip.
Observe the following instructions in using this product:
a. During the design stage, it is necessary to notice and confirm the light sensitivity and
preventive measures for using IC on substrate (PCB, Glass or Film) or product.
b. Test and inspect the product under an environment free of light source penetration.
c. Confirm that all surfaces around the IC will not be exposed to light source.
2004/12/06
68
Ver 1.0
With respect to the information represented on this website, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.