Omni
ision
Advanced Information
Preliminary Datasheet
TM
OV7648 Color CMOS VGA (640 x 480) CAMERACHIPTM
OV7148 B&W CMOS VGA (640 x 480) CAMERACHIPTM
General Description
Applications
The OV7648 (color) and OV7148 (black and white)
CAMERACHIPSTM are low voltage CMOS image sensors
that provide the full functionality of a single-chip VGA
(640 x 480) camera and image processor in a small
footprint package. The OV7648/OV7148 provides
full-frame, sub-sampled or windowed 8-bit images in a
wide range of formats, controlled through OmniVision’s
Serial Camera Control Bus (SCCB) interface.
This product family has an image array capable of
operating at up to 30 frames per second (fps) with
complete user control over image quality, formatting and
output data transfer. All required image processing
functions, including exposure control, gamma, white
balance, color saturation, hue control and more, are also
programmable through the SCCB interface. In addition,
OmniVision CAMERACHIPs use proprietary sensor
technology to improve image quality by reducing or
eliminating common lighting/electrical sources of image
contamination such as fixed pattern noise, smearing,
blooming, etc. to produce a clean, fully stable color image.
Features
•
•
•
•
•
•
High sensitivity for low-light operation
2.5V operating voltage for embedded portable
applications
Standard Serial Camera Control Bus (SCCB)
interface
VGA, QVGA (sub-sampled) and Windowed outputs
with Raw RGB, RGB (GRB 4:2:2), YUV (4:2:2) and
YCbCr (4:2:2) formats
Automatic image control functions including:
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB),
Automatic Brightness Control (ABC), Automatic
Band Filter (ABF) for 60Hz noise and Automatic
Black-Level Calibration (ABLC)
Image quality controls including color saturation,
hue, gamma, sharpness (edge enhancement),
anti-blooming and zero smearing
Ordering Information
•
•
•
•
Cellular Phones
Picture Phones
Toys
PC Multimedia
Key Specifications
Power Supply
Array Size
Core
Analog
I/O
Power
Requirements
Active
Standby
Temperature
Operation
Range Stable Image
Output Formats (8-bit)
Lens Size
VGA
QVGA
B&W
Sensitivity
Color
S/N Ratio
Dynamic Range
Scan Mode
Maximum Exposure Interval
Gamma Correction
Pixel Size
Dark Current
Well Capacity
Fixed Pattern Noise
Image Area
Package Dimensions
Maximum Image
Transfer Rate
640 x 480 (VGA)
2.5VDC + 10%
2.5VDC + 4%
2.25V to 3.3V
40 mW (30 fps, including
I/O power)
30 µW
-10°C to 70°C
0°C to 50°C
• YUV/YCbCr 4:2:2
• RGB 4:2:2
• Raw RGB Data
1/4"
30 fps
60 fps
2.20 V/Lux-sec
1.12 V/Lux-sec
46 dB
62 dB
Progressive/Interlaced
523 x tROW
0.45
5.6 µm x 5.6 µm
30 mV/s
60 Ke
< 0.03% of VPEAK-TO-PEAK
3.6 mm x 2.7 mm
4930 µm x 4760 µm
Figure 1 OV7648/OV7148 Pin Diagram
3
1
22
20
PWDN
AGND
SIO_D
Y0
Y2
4
2
21
19
17
VREF2
AVDD
SIO_C
Y1
Y3
5
OV7648/OV7148
Package
OV7648 (Color)
CSP-22
OV7148 (B&W)
CSP-22
Version 1.2, February 20, 2003
16
Y4
DVDD
Product
18
6
8
10
12
14
VSYNC
PCLK
XCLK1
DGND
Y6
7
9
11
13
15
HREF
DOVDD
RESET
Y7
Y5
Proprietary to OmniVision Technologies
1
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Functional Description
Figure 2 shows the functional block diagram of the OV7648/OV7148 image sensor. The OV7648/OV7148 includes:
•
Image Sensor Array (640 x 480 resolution)
•
Timing Generator
•
Analog Processing Block
•
A/D Converters
•
Output Formatter
•
Digital Video Port
•
SCCB Interface
Figure 2 OV7648/OV7148 Functional Block Diagram
Saturation
Gain
Hue
WB
Brightness
Gamma
Image Array
(640 x 480)
R
G
B
MUX
A/D
Output
Formatter
Data
Formatting
Y
Cb
Row Select
Analog Processing
MUX
A/D
Windowing
Cr
Control
Registers
(To all circuits)
Digital Video
Port
Y[7:0]
Column Sense Amps
RESET
PWDN
Timing Generator
SCCB
Interface
VREF
1.0 µf
CLK
HREF
PCLK
VSYNC
SIO_C
SIO_D
2
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Functional Description
Image Sensor Array
A/D Converters
The OV7648/OV7148 CAMERACHIPS has an active image
array size of 640 columns x 480 rows (307,200 pixels).
However, the full array contains 652 columns and 486
rows, with the extra 6 rows used for black-level calibration
(“Optical Black”) and color interpolation information.
Figure 3 shows a cross-section of the image sensor array.
Figure 3 Image Sensor Array Cross-Section
Microlens
Glass
Blue
Green
Red
Timing Generator
In general, the timing generator controls these functions:
•
Array control and frame generation (VGA and QVGA
outputs)
•
Internal timing signal generation and distribution
•
Frame rate timing
•
Automatic Exposure Control (AEC)
•
External timing outputs (VSYNC, HREF and PCLK)
Analog Processing Block
This block performs all analog image functions including:
•
Automatic Gain Control (AGC)
•
Automatic White Balance (AWB)
•
Image quality controls including:
After the Analog Processing Block, the color channel data
signal is fed to two 8-bit Analog-to-Digital (A/D) converters
via the multiplexers, one for the Y/G channel and one
shared by the CbCr/BR channels. These A/D converters
operate at speeds up to 12MHz, and are fully
synchronous to the pixel rate (Actual conversion rate is
related to the frame rate).
In addition to the A/D conversion, this block also has the
following functions:
•
Digital Black-Level Calibration (BLC)
•
Optional U/V channel delay
•
Additional A/D range controls
In general, the combination of the A/D Range Multiplier
and A/D Range Control sets the A/D range and maximum
value to allow the user to adjust the final image brightness
as a function of the individual application.
Output Formatter
This block controls all output and data formatting required
prior to sending the image out.
Digital Video Port
These two bits increase IOL / IOH drive current and can be
adjusted as a function of the customer’s loading:
SCCB Interface
The Serial Camera Control Bus (SCCB) interface controls
the CAMERACHIP operation. Refer to OmniVision
Technologies Serial Camera Control Bus (SCCB)
Specification for detailed usage of the serial control port.
– Color saturation
– Hue
– Gamma
– Sharpness (edge enhancement)
– Anti-blooming
– Zero smearing
Version 1.2, February 20, 2003
Proprietary to OmniVision Technologies
3
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Pin Description
Table 1
Pin Description
Pin Number
4
Name
Pin Type
Function/Description
01
AGND
Power
Analog ground
02
AVDD
Power
Analog power supply (+2.5 VDC)
03
PWDN
Function
(default = 0)
04
VREF2
VREF
Internal voltage reference (2.3V). Connect to ground through 1µF capacitor
05
DVDD
Power
Power supply (+2.5 VDC) for digital output drive
06
VSYNC
Output
Vertical sync output
07
HREF
Output
HREF output
08
PCLK
Output
Pixel clock output
09
DOVDD
Power
Digital power supply (+2.5 to 3.3VDC)
10
XCLK1
Input
Crystal clock input
11
RESET
Function
(default = 0)
12
DGND
Power
Digital ground
13
Y7
Output
YUV video component output bit[7]
14
Y6
Output
YUV video component output bit[6]
15
Y5
Output
YUV video component output bit[5]
16
Y4
Output
YUV video component output bit[4]
17
Y3
Output
YUV video component output bit[3]
18
Y2
Output
YUV video component output bit[2]
19
Y1
Output
YUV video component output bit[1]
20
Y0
Output
YUV video component output bit[0]
21
SIO_C
Input
22
SIO_D
I/O
Power Down Mode Selection
0: Normal mode
1: Power down mode
Clears all registers and resets them to their default values.
SCCB serial interface clock input
SCCB serial interface data I/O
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Electrical Characteristics
Electrical Characteristics
Table 2
Absolute Maximum Ratings
Ambient Storage Temperature
-40ºC to +125ºC
Supply Voltages (with respect to Ground)
VDD-A
3V
VDD-C
3V
VDD-IO
4V
All Input/Output Voltages (with respect to Ground)
-0.3V to VDD_IO+1V
Lead Temperature, Surface-mount process
+230ºC
ESD Rating, Human Body model
2000V
NOTE:
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.
Table 3
Symbol
DC Characteristics (0°C < TA < 70°C)
Parameter
Condition
Min
Typ
Max
Unit
VDD-A
DC supply voltage – Analog
—
2.40
2.5
2.60
V
VDD-C
DC supply voltage – Core
—
2.25
2.5
2.75
V
VDD-IO
DC supply voltage – I/O
—
2.25
—
3.3
V
IDDA
Active (Operating) Current
IDDS-SCCB
Standby Current
IDDS-PWDN
Standby Current
VIH
Input voltage HIGH
VIL
Input voltage LOW
VOH
Output voltage HIGH
VOL
Output voltage LOW
IOH
Output current HIGH
IOL
Output current LOW
IL
Input/Output Leakage
See Note a
See Note b
CMOS
15
mA
1
mA
10
µA
0.7 x VDD-IO
0.3 x VDD-IO
CMOS
(IOH / IOL)
0.1 x VDD-IO
See Note c
V
V
0.9 x VDD-IO
V
8
mA
15
mA
GND to VDD-IO
a.
VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V
IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 30 fps, no I/O loading
b.
VDD-A = VDD-C = 2.5V, VDD-IO = 3.0V
IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby
c.
Standard Output Loading = 25pF, 1.2KΩ to 3V
Version 1.2, February 20, 2003
V
Proprietary to OmniVision Technologies
±1
µA
5
OV7648/OV7148
Table 4
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Functional and AC Characteristics (0°C < TA < 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
Functional Characteristics
A/D
Differential Non-Linearity
+ 1/2
LSB
A/D
Integral Non-Linearity
+1
LSB
AGC
Range
21
dB
Red/Blue Adjustment Range
12
dB
Inputs (PWDN, CLK, RESET)
fCLK
Input Clock Frequency
10
24
27
MHz
tCLK
Input Clock Period
100
42
37
ns
tCLK:DC
Clock Duty Cycle
45
50
55
%
tS:RESET
Setting time after software/hardware reset
1
ms
tS:REG
Settling time for register change (10 frames required)
300
ms
400
KHz
SCCB (SIO_C and SIO_D - see Figure 4)
fSIO_C
Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
tAA
SIO_C low to Data Out valid
100
tBUF
Bus free time before new START
1.3
µs
tHD:STA
START condition Hold time
600
ns
tSU:STA
START condition Setup time
600
ns
tHD:DAT
Data-in Hold time
0
µs
tSU:DAT
Data-in Setup time
100
ns
tSU:STO
STOP condition Setup time
600
ns
tR, tF
SCCB Rise/Fall times
tDH
Data-out Hold time
900
300
50
ns
ns
ns
Outputs (VSYNC, HREF, PCLK, and Y[7:0] - see Figure 5, Figure 6, and Figure 7)
tPDV
PCLK[↓] to Data-out Valid
tSU
Y[7:0] Setup time
15
ns
tHD
Y[7:0] Hold time
8
ns
tPHH
PCLK[↓] to HREF[↑]
0
5
ns
tPHL
PCLK[↓] to HREF[↓]
0
5
ns
• VDD:
6
ns
VDD-A = VDD-C = 2.5V, VDD-IO = 3.3V
• Rise/Fall Times: I/O:
AC
Conditions:
5
5ns, Maximum
SCCB: 300ns, Maximum
•
•
•
Input Capacitance: 10pf
Output Loading: 25pF, 1.2KΩ to 3V
24MHz
fCLK:
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Timing Specifications
Timing Specifications
Figure 4 SCCB Timing Diagram
tF
t HIGH
tR
t HD:DAT
t SU:DAT
tLOW
SIO_C
t HD:STA
tSU:STA
tSU:STO
SIO_D
IN
t BUF
tAA
t DH
SIO_D
OUT
Figure 5 Row Output Timing Diagram
tPCLK
PCLK
tPHL
t PHL
(Row Data)
HREF
tSU
t HD
Y[7:0]
Last Byte First Byte
Last Byte
tPDV
Version 1.2, February 20, 2003
Proprietary to OmniVision Technologies
7
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Figure 6 VGA Frame Timing Diagram
525 t ROW
VSYNC
3 t ROW
11 t ROW
31 t ROW
764 t PCLK
HREF
640 t PCLK
Y[7:0]
124 t PCLK
(Invalid Data)
(Invalid Data)
Row 0
Row 1
Row 2
Last Row
Figure 7 QVGA Frame Timing Diagram
262.5 t ROW
VSYNC
3 t ROW
9 t ROW
10.5 t ROW
382 t PCLK
HREF
320 t PCLK
Y[7:0]
62 t PCLK
(Invalid Data)
(Invalid Data)
Row 0
Row 1
Row 2
Last Row
Note: As the RGB, YUV and YCbCr formats use the Bayer pattern for interpolation, the first row transferred out on the Y[7:0]
bus will be invalid, as there is no row above Row #1 to provide the 'pair data' required. Because of this, the OV7648
does not enable the HREF signal during the first row read (shown above in the 'invalid data' zone).
8
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Timing Specifications
Figure 8 RGB 565 Output Timing Diagram
tPCLK
PCLK
tPHL
t PHL
(Row Data)
HREF
tSU
t HD
Y[7:0]
Last Byte First Byte
Last Byte
tPDV
Y[7]
First Byte
Second Byte
R4
G2
Y[7]
G0
Y[6]
Y[5]
Y[6]
Y[5]
Y[4]
Y[3]
B4
R0
Y[2]
Y[1]
G5
Y[0]
G3
Y[4]
Y[3]
Y[2]
Y[1]
B0
Y[0]
Figure 9 RGB 555 Output Timing Diagram
tPCLK
PCLK
tPHL
t PHL
(Row Data)
HREF
tSU
t HD
Y[7:0]
Last Byte First Byte
Last Byte
tPDV
First Byte
Second Byte
Y[7]
X
G2
Y[7]
Y[6]
Y[5]
R4
G0
Y[6]
Y[5]
B4
Y[4]
Y[3]
Version 1.2, February 20, 2003
Y[2]
Y[1]
R0
G4
Y[0]
G3
Y[4]
Y[3]
Y[2]
Y[1]
B0
Y[0]
Proprietary to OmniVision Technologies
9
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Register Set
Table 5 provides a list and description of the Device Control registers contained in the OV7648/OV7148. For all register
Enable/Disable bits, ENABLE=1 and DISABLE=0. The device slave addresses for the OV7648/OV7148 are 42 for write and
43 for read.
Table 5
SCCB Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
00
GAIN
00
RW
Description
AGC – Gain control gain setting
• Range: [00] to [FF]
AWB – Blue channel gain setting
01
BLUE
80
RW
• Range: [00] to [FF]
Note: This function is not available on the B&W OV7148.
AWB – Red channel gain setting
02
RED
80
RW
• Range: [00] to [FF]
Note: This function is not available on the B&W OV7148.
03
SAT
84
RW
Image Format – Color saturation value
Bit[7:4]: Saturation value
•
Range: [0] to [F]
Bit[3:0]: Reserved
Note: This function is not available on the B&W OV7148.
04
HUE
34
RW
Image Format – Color hue control
Bit[7:6]: Reserved
Bit[5]:
Hue Enable
Bit[4:0]: Hue setting
Note: This function is not available on the B&W OV7148.
05
CWF
3E
RW
AWB – Red/Blue Pre-Amplifier gain setting
Bit[7:4]: Red channel pre-amplifier gain setting
•
Range: [0] to [F]
Bit[3:0]: Blue channel pre-amplifier gain setting
•
Range: [0] to [F]
Note: This function is not available on the B&W OV7148.
10
ABC – Brightness setting
06
BRT
80
RW
07-09
RSVD
XX
–
Reserved
0A
PID
76
R
Product ID number (Read only)
0B
VER
48
R
Product version number (Read only)
0C-0F
RSVD
XX
–
Reserved
10
AECH
41
RW
• Range: [00] to [FF]
Exposure Value
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Table 5
Address
(Hex)
Register Set
SCCB Register List
Register
Name
Default
(Hex)
R/W
Description
Data Format and Internal Clock
Bit[7:6]: Data Format – HSYNC/VSYNC Polarity
00: HSYNC = NEG VSYNC = POS
01: HSYNC = NEG VSYNC = NEG
10: HSYNC = POS VSYNC = POS
11: HSYNC = POS VSYNC = POS
11
CLKRC
00
RW
POS
Bit[5:0]:
12
COMA
14
RW
NEG
Internal Clock Pre-Scalar
•
Range: [0 0000] to [F FFFF]
Common Control A
Bit[7]:
SCCB – Register Reset
0: No change
1: Reset all registers to default values
Bit[6]:
Output Format – Mirror Image Enable
Bit[5]:
Reserved
Bit[4]:
Data Format – YUV formatting
0: U Y V Y U Y V Y
1: Y U Y V Y U Y V
Bit[3]:
Output Format – Output Channel Select A
0: YUV/YCbCr
1: RGB/Raw RGB
Bit[2]:
AWB – Enable
Bit[1:0]: Reserved
Note: This function is not available on the B&W OV7148.
13
COMB
Version 1.2, February 20, 2003
A3
RW
Common Control B
Bit[7:5]: Reserved
Bit[4]:
Data Format – ITU-656 Format Enable
Bit[3]:
Reserved
Bit[2]:
SCCB – Tri-State Enable – Y[7:0]
Bit[1]:
AGC – Enable
Bit[0]:
AEC – Enable
Proprietary to OmniVision Technologies
11
OV7648/OV7148
Table 5
Address
(Hex)
14
Omni
CMOS VGA (640 x 480) CAMERACHIP™
SCCB Register List
Register
Name
COMC
Default
(Hex)
04
R/W
RW
Description
Common Control C
Bit[7:6]: Reserved
Bit[5]:
Output Format – Resolution
0: VGA (640x480)
1: QVGA (320x240)
Bit[4]:
Reserved
Bit[3]:
Data Format – HREF Polarity
0: HREF Positive
1: HREF Negative
POS
Bit[2:0]:
NEG
Reserved
Common Control D
Bit[7]:
Data Format – Output Flag Bit Disable
0: Frame = 254 data bits (00/FF = Reserved flag bits)
1: Frame = 256 data bits
Bit[6]:
Data Format – Y[7:0]-PCLK Reference Edge
0: Y[7:0] data out on PCLK falling edge
1: Y[7:0] data out on PCLK rising edge
Bit[5:1]: Reserved
Bit[0]:
Data Format – UV Sequence Exchange
0: V Y U Y V Y U Y
1: U Y V Y U Y V Y
Note: Bit[0] is not programmable on the B&W OV7148.
15
COMD
00
RW
16
RSVD
XX
–
17
HSTART
1A
RW
Output Format – Horizontal Frame (HREF Column) Start
18
HSTOP
BA
RW
Output Format – Horizontal Frame (HREF Column) Stop
19
VSTRT
03
RW
Output Format – Vertical Frame (Row) Start
1A
VSTOP
F3
RW
Output Format – Vertical Frame (Row) Stop
RW
Data Format – Pixel Delay Select
(Delays timing of the Y[7:0] data relative to HREF in pixel units)
1B
ision
PSHFT
00
Reserved
• Range: [00] (No delay) to [FF] (256 pixel delay)
12
1C
MIDH
7F
R
Manufacturer ID Byte – High
(Read only = 0x7F)
1D
MIDL
A2
R
Manufacturer ID Byte – Low
(Read only = 0xA2)
1E
RSVD
XX
–
Reserved
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Table 5
Address
(Hex)
1F
Register Set
SCCB Register List
Register
Name
Default
(Hex)
FACT
01
R/W
RW
Description
Output Format – Format Control
Bit[7:5]: Reserved
Bit[4]:
Output Format – RGB:565 Enable
Note: Bit[4] is not programmable on the B&W OV7148.
Bit[3]:
Reserved
Bit[2]:
Output Format – RGB:555 Enable
Note: Bit[2] is not programmable on the B&W OV7148.
Bit[1:0]:
Reserved
Common Control E
Bit[7]:
Reserved
Bit[6]:
AEC – Digital Averaging Enable
Bit[5]:
Reserved
Bit[4]:
Image Quality – Edge Enhancement Enable
Bit[3:1]: Reserved
Bit[0]:
Y[7:0] 2X IOL / IOH Enable
20
COME
C0
RW
21-23
RSVD
XX
–
24
AEW
10
RW
AGC/AEC – Stable Operating Region – Upper Limit
25
AEB
8A
RW
AGC/AEC – Stable Operating Region – Lower Limit
RW
Common Control F
Bit[7:3]: Reserved
Bit[2]:
Data Format – Output Data MSB/LSB Swap Enable
(LSB → MSB (Y[7]) and MSB → LSB (Y[0])
Bit[1:0]: Reserved
26
COMF
A2
Reserved
Common Control G
Bit[7:5]: Reserved
Bit[4]:
Color Matrix – RGB Crosstalk Compensation Enable
(Used to increase each color filter’s efficiency)
Note: Bit[4] is not programmable on the B&W OV7148.
27
COMG
E2
RW
Bit[3:2]:
Bit[1]:
Bit[0]:
28
COMH
Version 1.2, February 20, 2003
20
RW
Reserved
Data Format – Output Full Range Enable
0: Output Range = [10] to [F0] (224 bits)
1: Output Range = [01] to [FE] (254/256 bits)
Reserved
Common Control H
Bit[7]:
Output Format – RGB Output Select
0: RGB
1: Raw RGB
Bit[6]:
Device Select
0: OV7640
1: OV7148
Bit[5]:
Output Format – Scan Select
0: Interlaced
1: Progressive
Bit[4:0]: Reserved
Proprietary to OmniVision Technologies
13
OV7648/OV7148
Table 5
ision
SCCB Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
29
COMI
00
R
2A
Omni
CMOS VGA (640 x 480) CAMERACHIP™
FRARH
00
RW
Description
Common Control I
Bit[7:2]: Reserved
Bit[1:0]: Device Version (Read-only)
Output Format – Frame Rate Adjust High
Bit[7]:
Data Format – Frame Rate Adjust Enable
Bit[6:5]: Data Format – Frame Rate Adjust Setting MSB
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]
Bit[4]:
A/D – UV Channel ‘2 Pixel Delay’ Enable
Note: Bit[4] is not programmable on the B&W OV7148.
Bit[3:0]:
2B
FRARL
00
RW
2C
RSVD
XX
–
2D
COMJ
81
RW
2E-5F
RSVD
XX
–
60
SPCB
06
RW
61-6B
RSVD
XX
–
6C
RMCO
11
RW
Reserved
Data Format – Frame Rate Adjust Setting LSB
FRA[9:0] = MSB + LSB = FRARH[6:5] + FRARL[7:0]
Reserved
Common Control J
Bit[7:3]: Reserved
Bit[2]:
AEC – Band Filter Enable
Bit[1:0]: Reserved
Reserved
Signal Process Control B
Bit[7]:
AGC – 1.5x Multiplier (Pre-amplifier) Enable
Bit[6:0]: Reserved
Reserved
Color Matrix – RGB Crosstalk Compensation – R Channel
Note: This function is not available on the B&W OV7148.
Color Matrix – RGB Crosstalk Compensation – G Channel
6D
GMCO
01
RW
Note: This function is not available on the B&W OV7148.
Color Matrix – RGB Crosstalk Compensation– B Channel
6E
BMCO
06
RW
Note: This function is not available on the B&W OV7148.
6F-70
71
RSVD
COML
XX
00
–
RW
Reserved
Common Mode Control L
Bit[7]:
Reserved
Bit[6]:
Data Format – PCLK output gated by HREF Enable
Bit[5]:
Data Format – Output HSYNC on HREF Pin Enable
Bit[4]:
Reserved
Bit[3:2]: Data Format – HSYNC Rising Edge Delay MSB
Bit[1:0]: Data Format – HSYNC Falling Edge Delay MSB
Data Format – HSYNC Rising Edge Delay LSB
72
HSDYR
10
RW
HSYNCR[9:0] = MSB + LSB = COML[3:2] + HSDYR[7:0]
• Range 000 to 762 pixel delays
14
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Table 5
Address
(Hex)
Register Set
SCCB Register List
Register
Name
Default
(Hex)
R/W
Description
Data Format – HSYNC Falling Edge Delay LSB
73
HSDYF
50
RW
HSYNCF[9:0] = MSB + LSB = COML[1:0] + HSDYF[7:0]
• Range 000 to 762 pixel delays
74
COMM
20
RW
Common Mode Control M
Bit[7]:
Reserved
Bit[6:5]: AGC – Maximum Gain Select
00: +6 dB
01: +12 dB
10: +6 dB
11: +18 dB
Bit[4:0]: Reserved
75
COMN
02
RW
Common Mode Control N
Bit[7]:
Output Format – Vertical Flip Enable
Bit[6:0]: Reserved
Common Mode Control O
Bit[7:6]: Reserved
Bit[5]:
Standby Mode Enable
Bit[4:3]: Reserved
Bit[2]:
SCCB – Tri-State Enable – VSYNC, HREF and PCLK
Bit[1:0]: Reserved
76
COMO
00
RW
77-7D
RSVD
XX
–
7E
AVGY
00
RW
7F
AVGR
00
RW
Reserved
AEC – Digital Y/G Channel Average
(Automatically updated by AGC/AEC, user can only read the values)
AEC – Digital R/V Channel Average
(Automatically updated by AGC/AEC, user can only read the values)
Note: This function is not available on the B&W OV7148.
80
AVGB
00
RW
AEC – Digital B/U Channel Average
(Automatically updated by AGC/AEC, user can only read the values)
Note: This function is not available on the B&W OV7148.
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Version 1.2, February 20, 2003
Proprietary to OmniVision Technologies
15
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
Package Specifications
The OV7648/OV7148 uses a 22-ball Chip Scale Package (CSP). Refer to Figure 10 for package information, Table 6 for
package dimensions and Figure 11 for the array center on the chip.
Figure 10 OV7648/OV7148 Package Specifications
865 µm ± 25 µm
4930 µm ± 25 µm
1
2
3
4
800 µm
780 µm
± 25 µm
5
A
5
4
3
2
1
A
B
Pin 1 Indicator
B
800 µm
0.0
4760 µm
C
± 25 µm
C
Center of BGA =
center of the D
package
E
D
E
Glass
640 µm ± 35 µm
180 µm ± 30 µm
Table 6
350 µm ± 30 µm
Ball diameter
Bottom View (Bumps Up)
Top View (Bumps Down)
406 µm ± 20 µm
Die
820 µm ± 60 µm
Side View
OV7648/OV7148 Package Dimensions
Parameter
Symbol
Minimum
Nominal
Maximum
Unit
Package Body Dimension X
A
4905
4930
4955
µm
Package Body Dimension Y
B
4735
4760
4785
µm
Package Height
C
760
820
880
µm
Package Body Thickness
C2
605
640
675
µm
Ball Height
C1
150
180
210
µm
Ball Diameter
D
320
350
380
µm
Total Pin Count
N
22
Pin Count X-axis
N1
5
µm
Pin Count Y-axis
N2
5
µm
Pins Pitch X-axis
J1
800
µm
Pins Pitch Y-axis
J2
800
µm
Edge-to-Pin Center Distance Analog X
S1
840
865
890
µm
Edge-to-Pin Center Distance Analog Y
S2
755
780
805
µm
16
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Package Specifications
Sensor Array Center
Figure 11 OV7648/OV7148 Sensor Array Center
Pin 1
3584 µm
Array Center
(227.3 µm, 122.2 µm)
2688 µm
OV7648/OV7148
Package Center
(0, 0)
Note: Due to the lens inversion, in order for the image to be right-side up, the OV7648/OV7148
must be mounted Pin 1 down.
Version 1.2, February 20, 2003
Proprietary to OmniVision Technologies
17
OV7648/OV7148
Omni
CMOS VGA (640 x 480) CAMERACHIP™
ision
IR Reflow Ramp Rate Requirements
Figure 12 IR Reflow Ramp Rate Requirements
300.0
275.0
250.0
225.0
Temperature (oC)
200.0
175.0
150.0
125.0
100.0
75.0
50.0
25.0
0.0
0.0
50.0
100.0
150.0
200.0
250.0
300.0
350.0
400.0
450.0
500.0
550.0 580.0
Time (sec)
Peak Temperature(°C)
Peak Time (sec)
> 100°C Time (sec)
> 150°C Time (sec)
> 190°C Time (sec)
216.7
358.00
347.00
167.00
70.00
Environmental Specifications
Table 7
OV7648/OV7148 Reliability Test Results
Parameter
Temperature/Humidity
85°C/85% Relative Humidity, 1000 hrs.a
Temperature Cycling (Air-to-Air)
-25°C / +125°C, 72 cycles/day, 1000 cyclesa
Highly Accelerated Stress Test (HAST)
110°C / 85% Relative Humidity, 168 hrs.a
High Temperature Storage (HTS)
150°C, 1000 hrs.a
High Temperature Static Bias (HTSB)
125°C, 1000 hrs.a
a.
18
Test Condition
Pre-Condition (Moisture Level II): 125°C, 24h → 85°C/60% RH/168h → IR Reflow 235°C, 10 sec, 3 cycles
Proprietary to OmniVision Technologies
Version 1.2, February 20, 2003
Omni
ision
Package Specifications
Note:
•
All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.
•
OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).
•
Reproduction of information in OmniVision product documentation and specifications is
permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.
•
This document is provided with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.
•
‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.
For further information, please feel free to contact OmniVision at [email protected].
OmniVision Technologies, Inc.
Sunnyvale, CA USA
(408) 733-3030
Version 1.2, February 20, 2003
Proprietary to OmniVision Technologies
19
OV7648/OV7148
20
CMOS VGA (640 x 480) CAMERACHIP™
Proprietary to OmniVision Technologies
Omni
ision
Version 1.2, February 20, 2003