CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter General Description Features The CLC5956 is a monolithic 12-bit, 65 MSPS analog-to-digital converter subsystem. The device has been optimized for use in cellular base stations and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5956 features differential analog inputs, low jitter differential PECL clock inputs, a low distortion track-and-hold with DC to 300 MHz input bandwidth, a bandgap voltage reference, TTL compatible CMOS output logic, and a proprietary 12-bit multi-stage quantizer. The CLC5956 is fabricated on the ABIC-IV 0.8 micron BiCMOS process. The part features a 73 dB spurious free dynamic range (SFDR) and 67 dB SNR. The wideband track-and-hold allows sampling of IF signals to greater than 250 MHz. The part produces two-tone, dithered, spurious-free dynamic range of 83 dBFS at 75 MHz input frequency. The differential analog input provides excellent common-mode rejection, while the differential PECL clock inputs permit the use of balanced transmission to minimize jitter in distributed systems. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5956 operates from a single +5V power supply over the industrial temperature range of −40˚C to +85˚C. National thoroughly tests each part to verify full compliance with the guaranteed specifications. n n n n n n Wide dynamic range IF sampling capability 300 MHz input bandwidth Small 48-pin TSSOP Single +5V supply Low cost Key Specifications n n n n n Sample Rate SFDR SFDR with dither SNR Low power consumption 65 MSPS 73 dBc 85 dBFS 67 dB 615 mW Applications n n n n n n n n Cellular base-stations Digital communications Infrared/CCD imaging IF sampling Electro-optics Instrumentation Medical imaging High definition video Block Diagram DS015011-2 © 1999 National Semiconductor Corporation DS015011 www.national.com CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter June 1999 Pin Configuration Ordering Information CLC5956IMTD 48-Pin TSSOP CLC5956IMTDX 48-Pin TSSOP (Taped Reel) CLC5956PCASM Evaluation Board DS015011-1 Pin Descriptions Pin Name Pin No. Description AIN AIN 13, 14 Differential input with a common mode voltage of +2.4V. The ADC full scale input is 1.024 VPP on each of the complimentary input signals. ENCODE ENCODE 9, 10 Differential clock where ENCODE initiates a new data conversion cycle on each rising edge. Logic for these inputs are a 50% duty cycle differential PECL signal. 21 Internal common mode voltage reference. Nominally +2.4V. Can be used for the input common mode voltage. This voltage is derived from an internal bandgap reference. VCM D0–D11 GND 30–34, 39–45 1–4, 8, 11, 12, 15, 19, 20, 23–26, 35, 36, 47, 48 Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D11 is the MSB. MSB is inverted. Output coding is two’s complement. Circuit ground. +AVCC 5–7, 16–18, 22 +5V power supply for the analog section. Bypass to ground with a 0.1 µF capacitor. +DVCC 37, 38, 46 +5V power supply for the digital section. Bypass to ground with a 0.1 µF capacitor. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (VCC) Differential Voltage between any Two Grounds Analog Input Voltage Range Digital Input Voltage Range Output Short Circuit Duration (one-pin to ground) Junction Temperature (Note 6) Storage Temperature Range Lead Solder Duration (+300˚C) +5V ± 5% Positive Supply Voltage (VCC) Analog Input Voltage Range −0.5V to +6V 2.048 VPP diff. Operating Temperature Range −40˚C to +85˚C < 200 mV GND to VCC −0.5V to +VCC Package Thermal Resistance θJA 56˚C/W Package 48-Pin TSSOP Infinite 175˚C −65˚C to +150˚C 10 sec. (Note 6) θJC 16˚C/W Reliability Information Transistor Count 5000 Converter Electrical Characteristics The following specifications apply for AVCC = DVCC = +5V, 52 MSPS, 50% Encode Clock Duty Cycle, CL = 7 pF. Boldface limits apply for TA = Tmin = −40˚C to Tmax = +85˚C, all other limits TA = 25˚C (Notes 2, 3, 4). Symbol Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE BW Large-Signal Bandwidth Overvoltage Recovery Time tDS Effective Aperture Delay tAJ Aperture Jitter VIN = FS −3 dB VIN = 1.5 FS (0.01%) 300 MHz 12 ns −0.21 ns 0.4 ps(rms) NOISE AND DISTORTION SNR Signal-to-Noise Ratio (without harmonics) fIN = 20 MHz, FS −1 dB fIN = 5 MHz, FS −3 dB fIN = 25 MHz, FS −3 dB fIN = 75 MHz, FS −3 dB fIN = 150 MHz, FS −3 dB fIN = 250 MHz, FS −3 dB fIN = 20 MHz, FS −1 dB Spurious-Free Dynamic Range SFDR Spurious-Free Dynamic Range (dithered) Intermodulation Distortion IMD Intermodulation Distortion (dithered) 63 dBFS dBFS 66 dBFS 64 dBFS 62 dBFS 59 dBFS 70 dBc fIN = 5 MHz, FS −3 dB fIN = 25 MHz, FS −3 dB fIN = 75 MHz, FS −3 dB 73 dBc 70 dBc 68 dBc fIN = 150 MHz, FS −3 dB fIN = 250 MHz, FS −3 dB 58 dBc 55 dBc fIN = 19 MHz, FS −6 dB 85 dBFS 68 dBFS 58 dBFS 83 dBFS f1 = 149.84 MHz, f2 = 149.7 MHz, FS −10 dB f1 = 249.86 MHz, f2 = 249.69 MHz, FS −10 dB f1 = 74 MHz, f2 = 75 MHz, FS −12 dB 66 66 67 DC ACCURACY AND PERFORMANCE DNL Differential Non-Linearity DC; Full Scale 0.65 LSB INL Integral Non-Linearity DC; Full Scale 1.7 LSB Bipolar Offset Error −1 mV Bipolar Gain Error −0.1 % FS 2.048 VPP 500 Ω ANALOG INPUTS VIN Analog Diff Input Voltage Range RIN (SE) Analog Input Resistance (Single-Ended) 3 www.national.com Converter Electrical Characteristics (Continued) The following specifications apply for AVCC = DVCC = +5V, 52 MSPS, 50% Encode Clock Duty Cycle, CL = 7 pF. Boldface limits apply for TA = Tmin = −40˚C to Tmax = +85˚C, all other limits TA = 25˚C (Notes 2, 3, 4). Symbol Parameter Conditions Min Typ Max Units ANALOG INPUTS RIN (Diff) Analog Input Resistance (Differential) CIN Analog Input Capacitance 1000 Ω 2 pF ENCODE INPUTS VIL Logic Input Low Voltage 3.0 3.5 VIH Logic Input High Voltage 4.0 4.5 V IIL Logic Input Low Current 1 5 µA IIH Logic Input High Current 16 25 µA 0.4 V V DIGITAL OUTPUTS VOL Logic Output Low Voltage VOH Logic Output High Voltage 2.4 V TIMING Fsmax Maximum Conversion Rate 65 MSPS Fsmin Minimum Conversion Rate 10 MSPS PWH Pulse Width High 7.7 ns PWL Pulse Width Low 7.7 Pipeline Delay (Note 5) ns 3.0 Output Propagation Delay 1.6 CLK Cy ns POWER REQUIREMENTS ICC Total Operating Supply Current 65 MSPS 123 150 mA Power Consumption 65 MSPS 615 750 mW Power Supply Rejection Ratio 64 dB Note 1: “Absolute Maximum Ratings” are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Note 2: Limits are 100% tested at 25˚C. Note 3: Typical characteristics are the mean values of the distributions of deliverable converters at 25˚C. Note 4: Outgoing quality levels are determined from tested parameters. Note 5: Max pipeline delay rating is based upon product characterization and simulation. Note 6: The absolute maximum junction (TJmax) temperature for this device is 175˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax – TA)/θJA. For the 48-pin TSSOP, θJA is 56˚C/W, so PDmax = 2.68W at 25˚C and 1.6W at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this device under normal operation will typically be about 625 mW (615 mW quiescent power + 10 mW due to 1 TTL load on each digital output). The values of absolute maximum power dissipation will only be reached when the CLC5956 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Typical Performance Characteristics SNR and SFDR vs Input Frequency (AVCC = DVCC = +5V) SNR and SFDR vs Input Frequency DS015011-3 www.national.com DS015011-4 4 SNR and SFDR vs Input Frequency DS015011-5 Typical Performance Characteristics SNR and SFDR vs Sample Rate (AVCC = DVCC = +5V) (Continued) Single Tone Output Spectrum DS015011-6 Single Tone Output Spectrum (with Dither) DS015011-7 DS015011-8 Differential Non-Linearity Integral Non-Linearity DS015011-9 SNR and SFDR vs Input Amplitude DS015011-10 DS015011-11 SNR and SFDR vs Input Amplitude SNR and SFDR vs Input Amplitude DS015011-12 Two Tone Output Spectrum (with Dither) DS015011-13 Two Tone Output Spectrum DS015011-16 SNR and SFDR vs Input Amplitude DS015011-14 Two Tone Output Spectrum DS015011-17 DS015011-15 5 www.national.com Typical Performance Characteristics (AVCC = DVCC = +5V) (Continued) Spectral Response SINAD vs Input Level DS015011-21 DS015011-22 Timing Diagram DS015011-18 Full Scale Analog Input Levels DS015011-19 Single IF Down Converter DS015011-20 www.national.com 6 Evaluation Board DS015011-23 Evaluation Board Schematic 7 www.national.com Evaluation Board (Continued) DS015011-24 DS015011-26 CLC730079 Layer 1 CLC730079 Layer 2 DS015011-25 DS015011-27 CLC730079 Layer 3 CLC730079 Layer 4 www.national.com 8 U4 should be replaced with an MC10EL16D. Placing the clock source on the evaluation board reduces ground loop issues and thus improves performance. Evaluation Printed Circuit Board The Evaluation board for the CLC5956 allows for easy test and evaluation of the product. The part may be ordered with all components loaded and tested. The order number is the CLC5956PCASM. The user supplies an analog input signal, encode signal and power to the board and is able to take latched 12-bit digital data out of the board. Analog Input (AIN) The analog input is an SMA connector with a 50Ω termination. The signal is converted from single to differential by a transformer with a 5 MHz to 260 MHz bandwidth and approximately one dB loss. Full scale is approximately 11 dBm or 2.2 VPP. It is recommended that the source for the analog input signal be low jitter, low noise and low distortion to allow for proper test and evaluation of the CLC5956. ENCODE Input (ENC) The ENCODE input is an SMA connector with a 50Ω termination. The signal is converted from single to differential and its frequency is divided by four to produce a low jitter, symmetrical encode signal for the CLC5956. The user should provide a sinusoidal or square wave signal of 10 dBm to 16 dBm amplitude at four times the converter’s desired sample rate. It is recommended that the source be low jitter to maintain best performance. The transformer will pass signals in the 40 MHz to 260 MHz range which allows sample rates of 10 Msps to 65 Msps. Supply Voltages (J1 pins 31 A&B and 32 A&B) The CLC5956PCASM is powered from a single 5V supply connected from the referenced pins on the Eurocard connector. The recommended supplies are low noise linear supplies. Clock Option Digital Outputs (J1 pins 7A (MSB, D11), 8B (D10) through 18B (LSB) and 20B (Data Ready) The CLC5956 board is configured for a 4x clock input to provide optimal performance with some (i.e., HP8662) synthesizers. The HP8662 output has lower jitter above 160 MHz. Using a 208 MHz clock to sample at 52 MHz minimizes the effect of the synthesizer on the measurement. To use a 1x clock, replace the divide-by-4 sine-to-PECL converter (U4, MC10EL33D) with an MC10EL16D. The MC10EL16D sine-to-PECL converter does not divide the clock. This approach would be suitable for use with a synthesizer that has optimal jitter performance at 52 MHz (i.e., HP8643 or HP8644). The best ADC performance is obtained with a low-jitter crystal oscillator module installed at Y1 on the evaluation board. The digital outputs are provided on the Eurocard connector. The outputs are buffered by 5V CMOS latches with 50Ω series output resistors. The rising edge of Data Ready may be used to clock the output data into data collection cards or logic analyzers. The board has a location for the HP 01650-63203 termination adapter for HP 16500 logic analyzers to simplify connection to the analyzer. 9 www.national.com CLC5956 12-bit, 65 MSPS Broadband Monolithic A/D Converter Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead TSSOP (Millimeters Only) Order Number CLC5956IMTD NS Package Number MTD48 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.