ETC SL3204

TITAN TECHNOLOGY Co. Ltd.
SL3204
SL3204 Data sheet description Ver5.0
1.
Features
2.
General Description
Block Diagram
3.
Pad Description
Absolute Maximum Ratings
4.
DC Characteristic
5.
AC Characteristic
6.
Function Description
Display Memory RAM
System Oscillator
Time Base and Watchdog Timer (WDT)
Tone Output
LCD Driver
7.
Command Format
8.
Interfacing
9.
Application Circuit
10. Timing Diagram
11. Command Index
12. Pin Assignment
13. Pad Coordinates
14. Package
SSOP48、SOP32、SKDIP28、COB48、LQFP48
15. History
1
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Features
z
z
z
z
z
z
z
z
z
z
z
z
z
Operating voltage: 2.4V~5.5V
Built-in 256KHz RC oscillator
External 32.768KHz crystal or 256KHz
frequency source input
Selection of 1/2 or 1/3 bias, and selection of 1/2
or 1/3 or 1/4 duty LCD applications
Internal time base frequency sources
Two selectable buzzer frequencies
(2KHz/4KHz)
Power down command reduces power
consumption
Built-in time base generator and WDT
z
z
z
z
z
z
Time base or WDT overflow output
8 kinds of time base/WDT clock sources
32x4 LCD driver
Built-in 32x4 bit display RAM
3-wire serial interface
Internal LCD driving frequency source
Software configuration feature
Data mode and command mode instructions
R/W address auto increment
Three data accessing modes
VLCD pin for adjusting LCD operating voltage
z General Description
The SL3204 is a 128 patterns (32x4), memory mapping, and multi-function LCD driver. The S/W
configuration feature of the SL3204 makes it suitable for multiple LCD applications including LCD modules
and display subsystems. Only three or four lines are required for the interface between the host controller
and the SL3204. The SL3204 contains a power down command to reduce power consumption.
Block Diagram
Display RAM
OSCO
OSCI
CSB
RDB
WRB
Control
and
Timing
Circuit
COM0
LCD Driver /
Bias Circuit
COM3
SEG0
DATA
SEG31
VDD
VLCD
VSS
BZ
BZB
Note:
Watchdog Timer
Tone Frequency
and
Generator
Time Base Generator
IRQB
CSB: Chip selection
BZ, BZB: Tone outputs
WRB, RDB, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQB: Time base or WDT overflow output
2
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Pad Description
Pad
No.
Pad Name
I/O
Function
1
CSB
I
2
RDB
I
3
WRB
I
4
5
DATA
VSS
I/O
-
6
OSCO
O
7
OSCI
I
Chip selection input with pull high resistor When the CSB is logic high, the
data and command read from or written to the SL3204are disabled. The serial
interface circuit is also reset. But if CSB is at logic low level and is input to the
CSB pad, the data and command transmission between the host controller
and the SL3204 are all enabled.
READ clock input with pull high resistor Data in the RAM of the SL3204 are
clocked out on the falling edge of the RDB signal. The clocked out data will
appear on the DATA line. The host controller can use the next rising edge to
latch the clocked out data.
WRITE clock input with pull high resistor Data on the DATA line are latched
into the SL3204on the rising edge of the WRB signal.
Serial data input/output with pull high resistor
Negative power supply, ground
The OSCI and OSCO pads are connected to a 32.768KHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But if
an on chip RC oscillator is selected instead, the OSCI and OSCO pads can be
left open.
8
9
10
11~12
13~16
17~48
VLCD
VDD
IRQB
BZ, BZB
COM0~COM3
SEG31~SEG0
I
O
O
O
O
LCD power input
Positive power supply
Time base or WDT overflow flag, NMOS open drain output
2KHz or 4KHz tone frequency output pair
LCD common outputs
LCD segment outputs
Absolute Maximum Ratings
Supply Voltage……………………………………………... –0.3V ~ 5.5V
Input Voltage……………………………………………… VSS-0.3V ~ VDD+0.3V
Storage Temperature…………………………………….. -50°C ~ 125°C
Operating Temperature…………………………………… -25°C ~ 75°C
3
TITAN TECHNOLOGY Co. Ltd.
SL3204
z DC Characteristic
Symbol
Parameter
VDD
Istb1
Standby Current
5V
Istb2
Standby Current
3v
Idd1
Operation current
5v
Idd2
Operation current
3v
Io1
Io2
Io3
Io4
LCD Common Sink
Current
LCD Common
Source Current
LCD Segment Sink
Current
LCD Segment
Source Current
Test Conditions
Conditions
No load
Power down mode
No load
Power down mod
No load, internal RC
oscillator on
No load, internal RC
oscillator on
Min
Typical
Max
Unit.
-
5
-
uA
2
uA
120
uA
48
uA
5V
VOL=2.5V
2.36
mA
5V
VOH=2.5V
1.51
mA
5V
VOL=2.5V
1.58
mA
5V
VOH=2.5V
0.9
mA
z AC Characteristic
Symbol
Parameter
VDD
Min
Typ.
Max
Unit.
Fint3
Internal RC oscillator
3V
133
KHz
Fint5
Internal RC oscillator
5V
256
KHz
Fext5
External input clock
5V
Trdbl3
Minimum read low pulse
3V
350
ns
Trdbl5
Minimum read low pulse
5V
350
ns
Twrbl3
Minimum write low pulse
3V
350
ns
Twrbl5
Minimum write low pulse
5V
350
ns
Tcsbh5
Minimum CSB high pulse
5V
50
ns
WRB
RDB
VDD
90%
50%
10%
GND
Twrbl
Trdbl
Twrbl
Trdbl
Tcsbh
CSB
VDD
50%
GND
WRB
RDB
VDD
GND
4
3.5
MHz
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Functional Description
Display Memory RAM
he static display memory (RAM) is organized into 32x4 bits and stores the displayed data. The contents of
the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the
READ, WRITE, and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the
LCD pattern
COM3
COM2
COM1
COM0
SEG0
0
SEG1
1
SEG2
2
SEG3
3
SEG31
D3
D2
D1
D0
Address 6 bits
(A5,A4,…,A0)
31
Addr
Data
Data 4 bits
(D3,D2,D1,D0)
System Oscillator
The SL3204 system clock is used to generate the time base/Watchdog Timer (WDT) clock frequency,
LCD driving clock, and tone frequency. The source of the clock may be from an on chip RC oscillator (256
KHz), a crystal oscillator (32.768 KHz), or an external 256 KHz clock by the S/W setting. The configuration
of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop
and the LCD bias generator will turn off. That command is, however, available only for the on chip RC
oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and
the time base/WDT lose its function as well.
The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches
off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving
as a system power down command. But if the external clock source is chosen as the system clock, using
the SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal
oscillator option can be applied to connect an external frequency source of 32 KHz to the OSCI pin. In this
case, the system fails to enter the power down mode, similar to the case in the external 256 KHz clock
source operation.
At the initial system power on, the SL3204 is at the SYS DIS state.
5
TITAN TECHNOLOGY Co. Ltd.
SL3204
Time Base and Watchdog Timer (WDT)
The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate
an accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8 stage time
base generator along with a 2 stage count-up counter, and is designed to break the host controller or other
subsystems from abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT
time out will result in the setting of an internal WDT time out flag. The outputs of the time base generator
and of the WDT time out flag can be connected to the IRQB output by a command option. There are totally
eight frequency sources available for the time base generator and the WDT clock. The frequency is
calculated by the following equation.
f
WDT
=
32 KHz
Where the value of n ranges from 0 to 7 by
n
2
command options. The 32 KHz in the above equation indicates that the source of the system frequency is
derived from a crystal oscillator of 32.768 KHz, an on chip oscillator (256 KHz), or an external frequency of
256 KHz. If an on chip oscillator (256 KHz) or an external 256 KHz frequency is chosen as the source of
the system frequency, the frequency source is by default prescaled to 32 KHz by a 3 stage prescaler.
Employing both the time base generator and the WDT related commands, one should be careful since the
time base generator and WDT share the same 8-stage counter. For example, invoking the WDT DIS
command disables the time base generator whereas executing the WDT EN command not only enables
the time base generator but activates the WDT time out flag output (connect the WDT time out flag to the
IRQB pin). After the TIMER EN command is transferred, the WDT is disconnected from the IRQB pin, and
the output of the time base generator is connected to the IRQB pin. The WDT can be cleared by executing
the CLR WDT command and the contents of the time base generator is cleared by executing the CLR
WDT or the CLR TIMER command.
OSCI
Crystal Oscillator
32768Hz
OSCO
External Clock Source
256KHz
System
Clock
1/8
On-chip RC Oscillator
256KHz
System oscillator configuration
System Clock
f=32kHz
Timer/WDT
Clock Sources
/2 n
n=0~7
TIMER EN / DIS
/256
IRQB
WDT EN / DIS
VDD
WDT
/4
D
Q
CK
IRQB EN / DIS
R
Timer and WDT configuration
CLR WDT
6
TITAN TECHNOLOGY Co. Ltd.
SL3204
The CLR WDT or the CLR TIMER command should be executed prior to the WDT EN or the TIMER EN
command respectively. Before executing the IRQB EN command the CLR WDT or CLR TIMER command
should be executed first. The CLR TIMER command has to be executed before switching from the WDT
mode to the time base mode. Once the WDT time out occurs, the IRQB pin will stay at a logic low level
until the CLR WDT or the IRQB DIS command is issued. After the IRQB output is disabled the IRQB pin
will remain at the floating state. The IRQB output can be enabled or disabled by executing the IRQB EN or
the IRQB DIS command, respectively. The IRQB EN makes the output of the time base generator or of the
WDT time out flag appear on the IRQB pin. The configuration of the time base generator along with the
WDT is as shown. In the case of on chip RC oscillator or crystal oscillator, the power down mode can
reduce power consumption since the oscillator can be turned on or off by the corresponding system
commands. At the power down mode the time base/WDT loses all its functions. On the other hand, if an
external clock is selected as the source of system frequency the SYS DIS command turns out invalid and
the power down mode fails to be carried out. That is, after the external clock source is selected, the
SL3204 will continue working until system power fails or the external clock source is removed. After the
system power on, the IRQB will be disabled.
Name
Command Code
Function
LCD OFF
10000000010X
Turn off LCD outputs
LCD ON
10000000011X
Turn on LCD outputs
BIAS & COM
1000010abXcX
c=0 : 1/2 bias option
c=1 : 1/3 bias option
ab=00 : 2 commons option
ab=01 : 3 commons option
ab=10 : 4 commons option
Tone Output
A simple tone generator is implemented in the SL3204. The tone generator can output a pair of differential
driving signals on the BZ and BZB, which are used to generate a single tone. By executing the TONE4K
and TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K
commands set the tone frequency to 4 KHz and 2 KHz, respectively. The tone output can be turned on or
off by invoking the TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZB, are a
pair of differential driving outputs used to drive a buzzer.
LCD Driver
The SL3204 is a 128 (32x4) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4
commons of LCD driver by the S/W configuration. This feature makes the SL3204 suitable for multiple
LCD applications. The LCD driving clock is derived from the system clock. The value of the driving clock is
always 256Hz even when it is at a 32.768 KHz crystal oscillator frequency, an on chip RC oscillator
frequency, or an external frequency. The LCD corresponding commands are summarized in the table. The
bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been
issued, the command mode ID except for the first command will be omitted. The LCD OFF command turns
the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns
the LCD display on by enabling the LCD bias generator. The BIAS and COM are the LCD panel related
commands. Using the LCD related commands; the SL3204 can be compatible with most types of LCD
7
TITAN TECHNOLOGY Co. Ltd.
SL3204
panels.
z Command Format
The SL3204 can be configured by the S/W setting. There are two mode commands to configure the
SL3204 resources and to transfer the LCD display data. The configuration mode of the SL3204 is called
command mode, and its command mode ID is 1 0 0. The command mode consists of a system
configuration command, a system frequency selection command, a LCD configuration command, a tone
frequency selection command, a timer/WDT setting command, and an operating command. The data
mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. The following
are the data mode Ids and the command mode ID:
Operation
Mode
ID
READ
Data
110
WRITE
Data
101
READ-MODIFY-WRITE
Data
101
COMMAND
Command
100
The mode command should be issued before the data or command is transferred. If successive
commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While the system is
operating in the non-successive command or the non-successive address data mode, the CSB pin should
be set to “1” and the previous operation mode will be reset also. Once the CSB pin returns to “0” a new
operation mode ID should be issued first.
z Interfacing
Only four lines are required to interface with the SL3204. The CSB line is used to initialize the serial
interface circuit and to terminate the communication between the host controller and the SL3204. If the
CSB pin is set to “1”, the data and command issued between the host controller and the SL3204 are first
disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is
required to initialize the serial interface of the SL3204. The DATA line is the serial data input/output line.
Data to be read or written or commands to be written have to be passed through the DATA line. The RDB
line is the READ clock input. Data in the RAM are clocked out on the falling edge of the RDB signal, and
the clocked out data will then appear on the DATA line. It is recommended that the host controller read in
correct data during the interval between the rising edge and the next falling edge of the RDB signal. The
WRB line is the WRITE clock input. The data, address, and command on the DATA line are all clocked
into the SL3204 on the rising edge of the WRB signal. There is an optional IRQB line to be used as an
interface between the host controller and the SL3204. The IRQB pin can be selected as a timer output or a
WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT
function by being connected with the IRQB pin of the SL3204.
8
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Application Circuit
CSB
VLCD
RDB
WRB
MCU
DATA
VDD
SL3204
R
Clock Out
External Clock 1
External Clock 2
On-chip OSC
VR
BZ
IRQB
OSCI
OSCO
BZB
COM0~COM3
SEG0~SEG31
C1
1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty
Crystal
32768Hz
LCD Pannel
C2
Host controller with a SL3204 display system
Note: See next page for notes.
Note: The connection of IRQB and RDB pin can be selected depending on the requirement of the up
The voltage applied to VLCD pin must be lower then VDD.
Adjust VR to fit LCD display, at VDD = 5V, VLCD = 4V, VR = 15Kohm +/- 20%.
Adjust R to fit user’s time base clock.
9
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Timing Diagram
Command mode (command code : 1 0 0)
CSB
WRB
DATA
1
0
0 C8 C7 C6 C5 C4 C3 C2 C1 C0
Command 1
C8 C7 C6 C5 C4 C3 C2 C1 C0
Command ...
Command i
Command
or
Data Mode
READ mode (command code : 1 1 0)
CSB
WRB
RDB
DATA
1
1
0
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
1
1
0
Memory Address 1 (MA1) Data (MA1)
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
Memory Address 2 (MA2) Data (MA2)
READ mode (successive address reading)
CSB
WRB
RDB
DATA
1
1
0
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
Memory Address (MA) Data (MA)
Data(MA+1)
Data(MA+2)
Data(MA+3)
WRITE mode (command code : 1 0 1)
CSB
WRB
DATA
1
0
1
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
1
0
1
Memory Address 1 (MA1) Data (MA1)
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3
Memory Address 2 (MA2) Data (MA2)
WRITE mode (successive address reading)
CSB
WRB
DATA
1
0
1
A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
Memory Address (MA) Data (MA)
Data(MA+1)
10
Data(MA+2)
Data(MA+3)
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Command Index
Name
READ
WRITE
READMODIFYWRITE
SYS DIS
ID
110
101
101
Command Code
A5A4A3A2A1A0D0D1D2D3
A5A4A3A2A1A0D0D1D2D3
A5A4A3A2A1A0D0D1D2D3
D/C
D
D
D
1 0 0 0000-0000-X
C
SYS EN
LCD OFF
LCD ON
TIMER DIS
WDT DIS
TIMER EN
WDT EN
TONE OFF
TONE ON
CLR
TIMER
CLR WDT
XTAL 32K
RC 256K
EXT 256K
BIAS 1/2
100
100
100
100
100
100
100
100
100
100
0000-0001-X
0000-0010-X
0000-0011-X
0000-0100-X
0000-0101-X
0000-0110-X
0000-0111-X
0000-1000-X
0000-1001-X
0000-1101-X
C
C
C
C
C
C
C
C
C
C
100
100
100
100
100
0000-1111-X
0001-01XX-X
0001-10XX-X
0001-11XX-X
0010-abX0-X
C
C
C
C
C
BIAS 1/3
1 0 0 0010-abX1-X
C
TONE 4K
TONE 2K
IRQB DIS
IRQB EN
F1
100
100
100
100
100
C
C
C
C
C
F2
1 0 0 101X-X001-X
C
F4
1 0 0 101X-X010-X
C
F8
1 0 0 101X-X011-X
C
F16
1 0 0 101X-X100-X
C
F32
1 0 0 101X-X101-X
C
F64
1 0 0 101X-X110-X
C
F128
1 0 0 101X-X111-X
C
TEST
NORMAL
1 0 0 1110-0000-X
1 0 0 1110-0011-X
C
C
010X-XXXX-X
011X-XXXX-X
100X-0XXX-X
100X-1XXX-X
101X-X000-X
11
Function
Read data from the RAM
Write data to the RAM
READ and WRITE to the RAM
Def.
Turn off both system oscillator and LCD bias
generator
Turn on system oscillator
Turn off LCD bias generator
Turn on LCD bias generator
Disable time base output
Disable WDT time-out flag output
Enable time base output
Enable WDT time-out flag output
Turn off tone outputs
Turn on tone outputs
Clear the contents of time base generator
Yes
Clear the contents of WDT stage
System clock source, crystal oscillator
System clock source, on chip RC oscillator
System clock source, external clock source
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
Tone frequency, 4KHz
Tone frequency, 2KHz
Disable IRQB output
Enable IRQB output
Time base/WDT clock output:1Hz
The WDT time-out flag after: 4s
Time base/WDT clock output:2Hz The WDT
time-out flag after: 2s
Time base/WDT clock output:4Hz
The WDT time-out flag after: 1s
Time base/WDT clock Output: 8Hz
The WDT time-out flag after: 1/2 s
Time base/WDT clock output: 16Hz The WDT
time-out flag after: 1/4 s
Time base/WDT clock output: 32Hz
The WDT time-out flag after: 1/8 s
Time base/WDT clock output:64Hz
The WDT time-out flag after: 1/16 s
Time base/WDT clock output:128Hz
The WDT time-out flag after: 1/32 s
Test mode, user don’t use.
Normal mode
Yes
Yes
Yes
Yes
Yes
Yes
TITAN TECHNOLOGY Co. Ltd.
SL3204
Note:
X: Don’t care
A5~A0: RAM addresses
D3~D0: RAM data
D/C: Data/command mode
Def.: Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these 1 0 0 indicates the
command mode ID. If successive commands have been issued, the command mode ID except for the first
command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency
can be derived from an on chip 256KHz RC oscillator, a 32.768 KHz crystal oscillator, or an external
256KHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It
is recommended that the host controller should initialize the SL3204 after power on reset, for power on
reset may fail, which in turn leads to the malfunctioning of the SL3204.
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
z Pin Assignment
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
LOGO
BZB
COM0
COM1
COM2
COM3
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
CSB
RDB
WRB
DATA
VSS
OSCO
OSCI
VLCD
VDD
IRQB
BZ
The IC substrate should be connected to VDD in the PCB layout artwork.
12
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Pad Coordinates
No.
Name
x
y
No.
Name
x
Y
1
CSB
68.80
1499.44
25
SEG23
1820.80
218.24
2
RDB
68.80
1371.44
26
SEG22
1820.80
346.24
3
WRB
68.80
1243.44
27
SEG21
1820.80
474.24
4
DATA
68.80
1115.44
28
SEG20
1820.80
602.24
5
VSS
68.80
987.44
29
SEG19
1820.80
730.24
6
OSCO
60.80
859.44
30
SEG18
1820.80
858.24
7
OSCI
60.80
731.44
31
SEG17
1820.80
986.24
8
VLCD
60.80
603.44
32
SEG16
1820.80
1114.24
9
VDD
60.80
475.44
33
SEG15
1820.80
1242.24
10
IRQB
60.80
348.24
34
SEG14
1820.80
1370.24
11
BZ
60.80
188.80
35
SEG13
1820.80
1498.24
12
BZB
188.88
60.80
36
SEG12
1820.80
1626.24
13
COM0
324.56
60.80
37
SEG11
1604.80
1627.44
14
COM1
452.56
60.80
38
SEG10
1476.80
1627.44
15
COM2
580.56
60.80
39
SEG9
1348.80
1627.44
16
COM3
708.56
60.80
40
SEG8
1220.80
1627.44
17
SEG31
836.56
60.80
41
SEG7
1092.80
1627.44
18
SEG30
964.56
60.80
42
SEG6
964.80
1627.44
19
SEG29
1092.56
60.80
43
SEG5
836.80
1627.44
20
SEG28
1220.56
60.80
44
SEG4
708.80
1627.44
21
SEG27
1348.56
60.80
45
SEG3
580.80
1627.44
22
SEG26
1476.56
60.80
46
SEG2
452.80
1627.44
23
SEG25
1604.56
60.80
47
SEG1
324.80
1627.44
24
SEG24
1820.80
90.24
48
SEG0
196.80
1627.44
LOGO
435
1072
13
TITAN TECHNOLOGY Co. Ltd.
SL3204
z Package
SSOP 48 Pins
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
48
1
SL3204B
xxxxxxxx-xxxx
25
24
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
CSB
RDB
WRB
DATA
VSS
OSCO
OSCI
VLCD
VDD
IRQB
BZ
BZB
COM0
COM1
COM2
COM3
25
48
A
B
24
1
C
C'
G
H
D
E
F
SSOP 48pin
A
B
C
C’
D
E
F
G
H
Unit
395~420
291~299
8~12
613~637
85~99
25
4~10
25~35
4~12
mil
SL3204CS
-SOP32
7.52
1.45
COM3
COM2
COM1
COM0
VDD
VLCD
VSS
DATA
WRB
CSB
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
10.4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0.15
20.98
2.24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2.065
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG10
SEG9
SEG8
SEG7
SEG6
0.75
SOP 32 Pins
unit: mm
0.35
14
1.27
TITAN TECHNOLOGY Co. Ltd.
SL3204
SKDIP 28 Pins
A
SEG5
SEG3
SEG1
CSB
RDB
WRB
DATA
VSS
VLCD
VDD
IRQB
BZ
COM0
COM1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
COM2
28
15
1
14
B
H
C
D
I
A
B
1375~1395
C
276~299 125~135
G
F
E
HW3204D
SKDIP28
D
E
F
G
H
I
Unit
125~140
16~21
50~70
100
295~315
330~375
mil
COB48
48
1
SL3204
25
24
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
CSB
RDB
WRB
DATA
VSS
OSCO
OSCI
VLCD
VDD
IRQB
BZ
BZB
COM0
COM1
COM2
COM3
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
48
25
SL3204
B
1
24
C
C'
D
E
COB48
B
C
C’
D
E
Unit
300
15
613~637
15~17
25
mil
15
TITAN TECHNOLOGY Co. Ltd.
SL3204
LQFP48
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
C
CSB
RDB
WRB
DATA
VSS
OSCO
OSCI
VLCD
VDD
IRQB
BZ
BZB
36
1
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
4
SL3204BQ
32
6
XXXXXXXXXXXX
XXXX
31
8
30
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
G
25
SEG12
SEG13
37
SEG14
SEG15
SEG16
SEG17
B
SEG18
SEG19 A
SEG20
SEG21
48
SEG22
SEG23
33
5
7
H
D
I
24
F
E
13
K
α
J
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM3
COM2
COM1
COM0
12
1
Dimensions in mm
Symbol
Min.
Nom.
Max.
A
8.90
─
9.10
B
6.90
─
7.10
C
5.90
─
9.10
D
6.90
─
7.10
E
─
0.50
─
F
─
0.20
─
G
1.35
─
1.45
H
─
─
1.60
I
─
0.10
─
J
0.45
─
0.75
K
0.10
─
0.20
α
0
─
7
16
TITAN TECHNOLOGY Co. Ltd.
SL3204
z History
Date
Name
Version
Comment
2003/2/9
CC Kuo
1.0
2003/2/13
CC Kuo
1.1
2003/3/17
CC Kuo
1.2
2003/5/26
CC Kuo
2.0
2003/9/05
CC Kuo
3.0
2003/9/15
CC Kuo
3.1
Modify timing diagram
2003/9/20
CC Kuo
3.2
Add the AC spec
2003/9/25
CC Kuo
3.3
Modify the pin assignment
2003/11/20
CC Kuo
3.4
Add package information
2004/2/24
CC Kuo
3.5
Modify the AC spec.
2005/3/23
Rong
3.6
Add the DC Absolute Maximum Ratings
2005/4/20
Lisa
3.7
Add the D.C. spec.
2005/5/10
Lisa
3.8
Modify the Operating voltage
2005/6/8
Lisa
3.9
Modify the command code
2005/6/17
Lisa
4.0
Modify the Operating voltage
2005/7/12
Lisa
4.1
Modify the pin location
2005/11/2
Alec
4.2
Modify index
2005/11/9
Alec
4.3
Modify pin assignment and pin location
2005/12/06
Alec
4.4
Modify the pin assignment
2005/12/8
ACLin
4.5
Modify margins of document
2006/10/16
ACLin
4.6
Re-typesetting
2007/1/22
ACLin
4.7
Add package SOP32 & SKDIP28 spec.
2007/2/2
2007/4/20
ACLin
4.8
Modify application circuit graphic & Add COB48
Add: The IC substrate should be connected to VDD in the PCB
Initial
Insert the package information
layout artwork.
2007/7/25
ACLin
4.81
Modify package SSOP48 picture.
2007/8/6
Jazz
4.82
Add LQFP48 package.
2007/8/24
ACLin
5.0
Change all picture format. And modify LQFP48 information.
17