DS90CF581/DS90CF582 LVDS 24-Bit Color Flat Panel Display (FPD) Link General Description Features The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF582 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Y Y Y Y Y Y Y Y Y Up to 140 Megabyte/sec Bandwidth Narrow bus reduces cable size 345 mV swing LVDS devices for low EMI Low power CMOS design Power-down mode PLL requires no external components Low profile 56-lead TSSOP package Falling edge data strobe Compatible with TIA/EIA-644 LVDS standard Block Diagrams DS90CF581 DS90CF582 TL/F/12486 – 1 Order Number DS90CF581MTD See NS Package Number MTD56 Order Number DS90CF582MTD See NS Package Number MTD56 Application TL/F/12486 – 2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1996 National Semiconductor Corporation TL/F/12486 RRD-B30M66/Printed in U. S. A. DS90CF581/DS90CF582 LVDS 24-Bit Color Flat Panel Display (FPD) Link April 1996 Connection Diagrams DS90CF581 DS90CF582 TL/F/12486–3 http://www.national.com TL/F/12486 – 4 2 Absolute Maximum Ratings (Note 1) Maximum Package Power Dissipation If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) a 25§ C 1.63W DS90CF582 1.61W Derate Package: DS90CF581 12.5 mW/§ C above a 25§ C DS90CF582 12.4 mW/§ C above a 25§ C This device does not meet 2000V ESD rating. (Note 4) b 0.3 to a 6V CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4 sec.) @ MTD56 (TSSOP) Package: DS90CF581 b 0.3 to (VCC a 0.3V) b 0.3 to (VCC a 0.3V) b 0.3 to (VCC a 0.3V) b 0.3 to (VCC a 0.3V) Recommended Operating Conditions continuous a 150§ C b 65§ C to a 150§ C a 260§ C Supply Voltage (VCC) Min 4.5 Nom 5.0 Max 5.5 Units V Operating Free Air Temperature (TA) b 10 a 25 a 70 §C 2.4 V Receiver Input Range 0 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units V CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC VIL Low Level Input Voltage GND 0.8 VOH High Level Output Voltage IOH e b0.4 mA VOL Low Level Output Voltage IOL e 2 mA VCL Input Clamp Voltage ICL e b18 mA IIN Input Current VIN e VCC, GND, 2.5V or 0.4V IOS Output Short Circuit Current VOUT e 0V 3.8 4.9 V V 0.1 0.3 b 0.79 b 1.5 V V g 5.1 g 10 mA b 120 mA 450 mV 35 mV 1.375 V 35 mV 1.6 V b 2.9 b5 mA g1 g 10 mA a 100 mV LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage RL e 100X DVOD Change in VOD between Complimentary Output States 250 VCM Common Mode Voltage DVCM Change in VCM between Complimentary Output States VOH High Level Output Voltage VOL Low Level Output Voltage IOS Output Short Circuit Current VOUT e 0V, RL e 100X IOZ Output TRI-STATEÉ Current Power Down e 0V, VOUT e 0V or VCC 1.1 290 1.25 1.3 0.9 1.07 V LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM e a 1.2V b 100 VIN e a 2.4V VCC e 5.5V VIN e 0V mV g 10 mA g 10 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of ‘‘Electrical Characteristics’’ specify conditions for device operation. Note 2: Typical values are given for VCC e 5.0V and TA e a 25§ C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and DVOD). Note 4: ESD Rating: HBM (1.5 kX, 100 pF) PLL VCC t 1000V All other pins t 2000V EIAJ (0X, 200 pF) t 150V 3 http://www.national.com Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Typ Max Units TRANSMITTER SUPPLY CURRENT ICCTW ICCTG ICCTZ Transmitter Supply Current, Worst Case RL e 100X, CL e 5 pF, Worst Case Pattern (Figures 1, 3) f e 32.5 MHz 34 46 mA f e 37.5 MHz 36 48 mA Transmitter Supply Current, 16 Grayscale RL e 100X, CL e 5 pF, f e 32.5 MHz 27 42 mA Grayscale Pattern (Figures 2, 3) f e 37.5 MHz 28 43 mA 1 10 mA Transmitter Supply Current, Power Down Power Down e Low RECEIVER SUPPLY CURRENT ICCRW ICCRG ICCRZ Receiver Supply Current, Worst Case CL e 8 pF, Worst Case Pattern (Figures 1, 4) Receiver Supply Current, 16 Grayscale CL e 8 pF, 16 Grayscale Pattern (Figures 2, 4) Receiver Supply Current, Power Down Power Down e Low f e 32.5 MHz 55 75 mA f e 37.5 MHz 60 80 mA f e 32.5 MHz 35 55 mA f e 37.5 MHz 37 58 mA 1 10 mA Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units LLHT Symbol LVDS Low-to-High Transition Time (Figure 3) Parameter Min 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 3) 0.75 1.5 ns CLHT CMOS/TTL Low-to-High Transition Time (Figure 4) 3.5 6.5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 4) 2.7 6.5 ns TCIT TxCLK IN Transition Time (Figure 5) TCCS TxOUT Channel-to-Channel Skew (Note A) (Figure 6) TSSPW Tx Sub-Symbol Pulse Width (Figure 6) RCCS RxIN Channel-to-Channel Skew (Note B) TCIP TxCLK IN Period (Figure 7) 25 T 50 ns TCIH TxCLK IN High Time (Figure 7) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 7) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 7) 8 THTC TxIN Hold to TxCLK IN (Figure 7) 2.5 2 RCOP RxCLK OUT Period (Figure 8) 25 T f e 20 MHz Note A: This limit based on bench characterization. Note B: This limit assumes a maximum cable skew of 350 ps. http://www.national.com 4 5.5 7 8 ns 350 ps 8 ns 700 ps ns ns 50 ns Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified (Continued) Symbol RCOH RCOL Parameter Min RxCLK OUT High Time (Figure 8) RxCLK OUT Low Time (Figure 8) RSRC RxOUT Setup to RxCLK OUT (Figure 8) RHRC RxOUT Hold to RxCLK OUT (Figure 8) TCCD TxCLK IN to TxCLK OUT Delay VCC e 5.0V (Figure 9) RCCD RxCLK IN to RxCLK OUT Delay VCC e 5.0V (Figure 10) TPLLS RPLLS @ 25§ C, Typ Max Units f e 20 MHz 21.5 f e 40 MHz 10.5 ns ns f e 20 MHz 19 ns f e 40 MHz 6 ns f e 20 MHz 14 ns f e 40 MHz 4.5 ns f e 20 MHz 16 ns f e 40 MHz 6.5 ns 5 9.7 ns 7.6 11.9 ns Transmitter Phase Lock Loop Set (Figure 11) 10 ms Receiver Phase Lock Loop Set (Figure 12) 10 ms @ 25§ C, 5 http://www.national.com AC Timing Diagrams TL/F/12486 – 15 FIGURE 1. ‘‘WORST CASE’’ Test Pattern TL/F/12486 – 16 FIGURE 2. ‘‘16 GRAYSCALE’’ Test Pattern Note 1: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 2: The 16 grayscale test pattern tests device power consumption for a ‘‘typical’’ LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 3: Figure 1 and Figure 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). http://www.national.com 6 AC Timing Diagrams (Continued) TL/F/12486–8 TL/F/12486 – 9 FIGURE 3. DS90CF581 (Transmitter) LVDS Output Load and Transition Timing TL/F/12486–10 TL/F/12486 – 11 FIGURE 4. DS90CF582 (Receiver) CMOS/TTL Output Load and Transition Timing TL/F/12486 – 17 FIGURE 5. DS90CF581 (Transmitter) Input Clock Transition Time Note 1: Measurements at Vdiff e 0V Note 2: TCCS measured between earliest and latest initial LVDS edges. x Low Edge for DS90CF561 x High Edge for DS90CR561 Note 3: TxCLK OUT Differential High TxCLK OUT Differential Low TL/F/12486 – 18 FIGURE 6. DS90CF581 (Transmitter) Channel-to-Channel Skew and Pulse Width 7 http://www.national.com AC Timing Diagrams (Continued) TL/F/12486 – 12 FIGURE 7. DS90CF581 (Transmitter) Setup/Hold and High/Low Times TL/F/12486 – 13 FIGURE 8. DS90CF582 (Receiver) Setup/Hold and High/Low Times TL/F/12486 – 19 FIGURE 9. DS90CF581 (Transmitter) Clock In to Clock Out Delay TL/F/12486 – 20 FIGURE 10. DS90CF582 (Receiver) Clock In to Clock Out Delay http://www.national.com 8 AC Timing Diagrams (Continued) TL/F/12486 – 14 FIGURE 11. DS90CF581 (Transmitter) Phase Lock Loop Set Time TL/F/12486 – 21 FIGURE 12. DS90CF582 (Receiver) Phase Lock Loop Set Time 9 http://www.national.com AC Timing Diagrams (Continued) TL/F/12486 – 22 FIGURE 13. Seven Bits of LVDS in One Block Cycle TL/F/12486 – 23 FIGURE 14. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF581) http://www.national.com 10 DS90CF581 Pin DescriptionÐFPD Link Transmitter I/O No. TxIN Pin Name I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE, FPFRAME, DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE) Description TxOUT a O 4 Positive LVDS differential data output TxOUTb O 4 Negative LVDS differential data output FPSHIFT IN I 1 TTL level clock input. The falling edge acts as data strobe. TxCLK OUT a O 1 Positive LVDS differential clock output TxCLK OUTb O 1 Negative LVDS differential clock output PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATE the outputs, ensuring low current at power down. VCC I 4 Power supply pins for TTL inputs GND I 5 Ground pins for TTL inputs PLL VCC I 1 Power supply pin for PLL PLL GND I 2 Ground pins for PLL LVDS VCC I 1 Power supply pin for LVDS outputs LVDS GND I 3 Ground pins for LVDS outputs DS90CF582 Pin DescriptionÐFPD Link Receiver I/O No. RxIN a Pin Name I 4 Positive LVDS differential data inputs. Description RxINb I 4 Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE, FPFRAME, DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE) RxCLK IN a I 1 Positive LVDS differential clock input RxCLK INb I 1 Negative LVDS differential clock input FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe. PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state VCC I 4 Power supply pins for TTL outputs GND I 5 Ground pins for TTL outputs PLL VCC I 1 Power supply pin for PLL PLL GND I 2 Ground pin for PLL LVDS VCC I 1 Power supply pin for LVDS inputs LVDS GND I 3 Ground pins for LVDS inputs 11 http://www.national.com DS90CF581/DS90CF582 LVDS 24-Bit Color Flat Panel Display (FPD) Link Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90CF581MTD or DS90CF582MTD NS Package Number MTD56 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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