100351 Low Power Hex D Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors. n n n n Logic Symbol 40% power reduction of the 100151 2000V ESD protection Pin/function compatible with 100151 Voltage compensated operating range: −4.2V to −5.7V n Standard Microcircuit Drawing (SMD) 5962-9457901 Pin Names Description D0–D5 Data Inputs CPa, CPb Common Clock Inputs MR Asynchronous Master Reset Input Q0–Q5 Data Outputs Q0–Q5 Complementary Data Outputs DS100318-11 © 1998 National Semiconductor Corporation DS100318 www.national.com 100351 Low Power Hex D Flip-Flop August 1998 Connection Diagrams 24-Pin DIP 24-Pin Quad Cerpak DS100318-2 DS100318-1 Logic Diagram DS100318-4 Truth Tables Asynchronous Operation (Each Flip-flop) Inputs Synchronous Operation Inputs Outputs Dn CPa CPb MR L N L L L H N L L H L L N L L H L N L H Qn(t) X H N L N H L Qn(t) X L L L Qn(t) www.national.com CPa CPb MR Qn(t+1) X X X H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care t = Time before CP positive transition t+1 = Time after CP positive transition N = LOW-to-HIGH transition Qn(t+1) X Outputs Dn 2 Absolute Maximum Ratings (Note 1) ≥2000V ESD (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Recommended Operating Conditions Above which the useful life may be impaired −65˚C to +150˚C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic +175˚C −7.0V to +0.5V VEE Pin Potential to Ground Pin Input Voltage (DC) VEE to +0.5V Output Current (DC Output HIGH) −50 mA Case Temperature (TC) Military Supply Voltage (VEE) −55˚C to +125˚C −5.7V to −4.2V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Military Version DC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C Symbol VOH Parameter Min Max Units TC Output HIGH Voltage −1025 −870 mV 0˚C to −1085 −870 mV −55˚C −1830 −1620 mV 0˚C to −1830 −1555 mV −55˚C mV 0˚C to +125˚C VOL Output LOW Voltage Conditions Notes VIN = VIH (Max) or VIL (Min) Loading with 50Ω to −2.0V (Notes 3, 4, 5) VIN = VIH (Min) or VIL (Max) Loading with 50Ω to −2.0V (Notes 3, 4, 5) +125˚C VOHC Output HIGH Voltage −1035 +125˚C −1085 VOLC Output LOW Voltage mV −55˚C −1610 mV 0˚C to −1555 mV −55˚C −870 mV −55˚C to +125˚C VIH Input HIGH Voltage −1165 +125˚C VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C IIL Input LOW Current 0.50 µA −55˚C to +125˚C IIH IEE Input HIGH Current CP, MR 350 D0–D5 240 CP, MR 500 D0–D5 340 Power Supply Current −135 −50 µA 0˚C to Guaranteed HIGH Signal (Notes 3, 4, 5, 6) for All Inputs Guaranteed LOW Signal for All Inputs VEE = −4.2V (Notes 3, 4, 5, 6) (Notes 3, 4, 5) VIN = VIL (Min) VEE = −5.7V VIN = VIH (Max) (Notes 3, 4, 5) Inputs Open (Notes 3, 4, 5) +125˚C µA −55˚C mA −55˚C to +125˚C Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 4: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8. Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8. Note 6: Guaranteed by applying specified input condition and testing VOH/VOL. 3 www.national.com AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = −55˚C TC = +25˚C Min Max Min TC = +125˚C Max Min Units Conditions Notes (Note 10) Max fmax Toggle Frequency 375 MHz Figures 2, 3 tPLH Propagation Delay 0.40 2.40 0.50 2.20 0.50 2.60 ns Figures 1, 3 0.60 2.70 0.70 2.60 0.80 2.90 ns Figures 1, 4 0.20 1.60 0.20 1.60 0.20 1.60 ns Figures 1, 3 ns Figure 5 tPHL CPa, CPb to Output tPLH Propagation Delay tPHL MR to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% ts Setup Time th 375 375 (Notes 7, 8, 9) D0–D5 0.90 0.80 0.90 MR (Release Time) 1.60 1.80 2.60 Hold Time 1.50 1.40 1.60 ns Figure 5 2.00 2.00 2.00 ns Figures 3, 4 (Note 10) Figure 4 D0–D5 tpw(H) Pulse Width HIGH CPa, CPb, MR Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures. Note 8: Screen tested 100% on each device at +25˚C, Temperature only, Subgroup A9. Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temperature, Subgroups A10 and A11. Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data). Test Circuitry DS100318-5 Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit www.national.com 4 Test Circuitry (Continued) DS100318-6 Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Jig and stray capacitance ≤ 3 pF FIGURE 2. Toggle Frequency Test Circuit Switching Waveforms DS100318-7 FIGURE 3. Propagation Delay (Clock) and Transition Times 5 www.national.com Switching Waveforms (Continued) DS100318-8 FIGURE 4. Propagation Delay (Reset) DS100318-9 Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 5. Setup and Hold Time www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D) NS Package Number J24E 24-Lead Quad Cerpak (F) NS Package Number W24B 7 www.national.com 100351 Low Power Hex D Flip-Flop LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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