DESCRIPTION VS6961 is an LED Controller driven on a 1/7 to 1/8 duty factor. Eleven segment output lines,six grid output lines,1 segment grid output lines, one display memory, control circuit key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to VS6961 via a four-line serial interface. Housed in a 32-pin SO Package, VS6961 pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages. FEATURES Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ Ÿ CMOS Technology Low Power Consumption Multiple Display Modes(12 segment,6 Grid to 11 segment, 7 Grid) Key Scanning (10 x 3 Matrix) S-Step Dimming Circuitry Serial Interface for Clock, Data Input, Data Output, Strobe Pins Available in 32-pin, SOP Package APPLICATION Ÿ Ÿ Ÿ Micro-computer Peripheral Device VCR set Combi set 1 BLOCK DIAGRAM 2 INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below. Input Pins: CLK, STB & DIN Input Pins: K1 to K3 Output Pins: DOUT, GR1 to GR4 3 Output Pins: SG1 to SG11 Output Pins: GR5, GR6 and SG12/GR7 4 PIN CONFIGURATION 5 PIN DESCRIPTION I/O Description Pin No. Oscillator Input Pin OSC I A resistor is connected to this pin to determine the 1 oscillation frequency Data Output Pin (N-Channel, Open-Drain) DOUT O This pin outputs serial serial data at the falling edge 2 of the shift clock. Data Input Pin DIN I This pin inputs serial data at the rising edge of the 3 shift clock (starting from the lower bit) Clock Input Pin CLK I This Pin reads serial data at the rising edge and 4 outputs data at the falling edge. Serial Interface Strobe Pin STB I The data input after the STB has fallen is processed 5 as a command. When thes pin is “HIGH”, CLK is ignored. Key Data Input Pins K1 to K3 I The data sent to these pins are latched at the end of the display cycle. 6, 7, 8 (Internal Pull-Low Resistor) GND SG1/KS1 to SG10/KS10 O Ground Pin 26, 29, 32 Segment Output Pins (p-channel, open drain) 10 ~ 12 Also acts as the Key Source 14 ~ 20 SG11 O Segment Output Pins (P-Channel, open drain) 21 SG12/GR7 O Segment / Grid Output Pins 22 VDD - Power Supply 9, 25 GR6 to GR1 O Grid Output Pins NC - No Connection 6 23, 24, 27 28, 30, 31 13 FUNCTIONAL DESCRIPTION COMMANDS A command is the first byte (b0 to b7) inputted to VS6961 via the DIN Pin after STB Pin has changed from HIGH to LOW State. If for some reason the STB Pin is set to HIGH while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. Command 1: Display Mode Setting Commands VS6961 provides 2 display mode settings as shown in the diagram below : As stated earlier a command is the first one byte (b0 to b7) transmitted to VS6961 via the DIN Pin when STB is LOW. However, for these commands ,the bit 3 to bit 6 (b2 to b5) are ignored ,bit 7 & bit 8 (b6 to b7) are given a value of 0. The Display Mode Setting Commands determine the number of segments and grids to be used (12 to 11 segments, 6 to 7 grids). A display command ON must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned ON, the 7-grid ,11-segment modes is selected. 7 Command 2: Data Setting Commands The Data Setting Commands executes the Data Write or Data Read Modes for VS6961. The data Setting Command , the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of 1 while bit 8 (b7) is given the value of 0. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of 0. 8 VS6961 KEY MATRIX & KEY INPUT DATA STORAGE RAM VS6961 Key Matrix consists of 10 x 3 array as shown below: Each data entered by each key is stored as follows and read by a READ Command , starting from the last significant bit . When the most significant bit of the data (b0) has been read , the least significant bit of the next data (b7) is read . K1…………K3 K1…….……….K3 SG1/KS1 SG2/KS2 X SG3/KS3 SG4/KS4 X SG5/KS5 SG6/KS6 X SG7/KS7 SG8/KS8 X SG9/KS9 SG10/KS10 X b0….………….b2 b3……………….b5 b6……………..b7 Note: b6 and b7 do not care. 9 Command 3: Address Setting Commands Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of 00H to 0DH. If the address is set to 0EH or higher ,the data is ignored until a valid address is set. When power is turned ON, the address is set at 00H. Please refer to the diagram below. DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to VS6961 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM addresses of VS6961 are given below in 8 bits unit. SG1 SG4 SG5 SG8 SG9 SG12 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 10 Command 4: Display Control Commands The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is stopped). 11 SCANNING AND DISPLAY TIMING The Key Scanning and Display Timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the are 10 x 3 matrix is stored in the RAM. 12 SERIAL COMMUNICATION FORMAT The following diagram shows the VS6961 serial communication format. The DOUT Pin is an N-channel, opendrain output pin,therefore, it is highly recommended that an external pull-up resistor (1 KOhms to 10 KOhms) must be connected to DOUT. RECEPTION (Data/Command Write) TRANSMISSION (Data Read) where: twait (waiting time) >1µs It must be noted that when the data is read , the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1µs. 13 SWITCHING CHARACTERISTIC WAVEFORM VS6961 Switching Characteristics Waveform is given below. PWSTB (Strobe Pulse Width) > 1µs thold (Data Hold Time) >100ns tTHZ (Fall Time ) <10µs tPZL (Propagation Delay Time) < 100ns tPLZ (Propagation Delay Time) <300ns tTLZ <10µs where: PWClK (Clock Pulse Width) > 400ns tsetup (Data Setup Time) > 100ns tCLK-STB (Clock-Strobe Time) >1µs tTZH (Rise Time) < 1µs fosc = Oscillatilon Frequency tTZL < 1µs 14 Note: Test condition under tTHZ (Pull low risistor = 10k ohms, Loading capacitor = 300pf) tTLZ (Pull high risistor = 10k ohms, Loading capacitor = 300pf) APPLICATIONS Display memory is updated by incrementing addresses. Please refer to the following diagram. where: Command 1: Display Mode Setting Command Command 2: Data Setting Command Command 3: Address Setting Command Data 1 to n : Transfer Display Data (14 Bytes max. ) Command 4: Display Control Command The following diagram shows the waveforms when updating specific addresses. where: Command 2 – Data Setting Command Command 3 – Address Setting Command Data – Display Data 15 RECOMMENDED SOFTWARE FLOWCHART 16 PROGRAMMING Note: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the conents of the Display RAM is not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. SOP32 300MIL THERMAL STILLAIR AT Tj=100 17 PERFORMANCE IN ABSOUTE MAXIMUM RATINGS (Unless otherwise stated, Ta = 25 , GND = 0V) Parameter Symbol Ratings Unit Supply Voltage VDD - 0.5 to + 7 Volts Logic Input Voltage V1 -0.5 to VDD + 0.5 Volts IOLGR +250 mA IOHSG -50 mA ITOTAL 400 mA Driver Output Current Maximum Driver Output Current/Total RECOMMENDED OPERATING RANGE (Unless otherwise stated, Ta = -20 to +70 , GND = 0V) Parameter Symbol Min Typ Max Unit Logic Supply Voltage VDD 4.5 5 5.5 V Dynamic Current (see Note) IDDdyn - - 5 mA High – Level Input Voltage VIH 0.8 VDD - VDD V Low – Level Input Voltage VIL 0 - 0.3 VDD V Note: Test Condition: Set Display Control Commands = 80H (Display Turn OFF State & under no load) 18 ELECTRICAL CHARACTERISTICS (Unless otherwise stated VDD = 5V, GND = 0V, Ta = 25 Parameter Symbol Test Condition Min Typ Max Unit IOHSH1 Vo = VDD -2V SG1 to SG11, SG12/GR7 -20 -25 -40 mA IOHSG2 Vo = VDD - 3 V SG1 to SG11, SG12/GR7 -25 -30 -50 mA Low - Level Output Current IOLGR Vo = 0.3V GR1 to GR6, SG12/GR7 100 140 - mA Low - Level Output Current IOLDOUT Vo = 0.4V 4 - - mA Segment High - Level Output Current Tolerance ITOLSG Vo = VDD - 3 V SG1 to SG11, SG12/GR7 - - +5 % High - Level Input Voltage VIH - 0.8 VDD - 5 V Low LevelInput Voltage VIL - 0 - 0.3VDD V Oscillation Frequency fosc R = 51 KOhms 350 500 650 kHz K1 to K3 Pull Down Resistor RKN K1 to K3 VDD = 5V 40 - 100 kOhms High -Level Output Current 19 APPLICATION CIRCUIT 20 Note: 1. The capacitor (0.1 µF) connected between the GND and the VDD pins must be located as possible to the VS6961 chip. 2. It is strongly suggested that the NC pin (pins 10) be connected to the GND. 21 PACKAGE INFORMATION 32-Pin SOP Package (300 mil) 22 Symbols Dimensions in Millimeter Min. Nom. Max. A 2.35 2.65 A1 0.10 0.30 B 0.33 0.51 C 0.23 0.32 D 20.63 E 7.40 20.78 20.93 7.60 e 1.27bsc. H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 ? o 8o 0 JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. 23