AP8302 SRS WOW HD Audio Processor AP8302 SRS WOW HD Audio Processor Datasheet AP8302 SRS WOW HD Audio Processor Table of Contents 1. OVERVIEW......................................................................................................... 1 2. APPLICATIONS ................................................................................................. 1 3. ORDERING INFORMATION .............................................................................. 1 4. FEATURES......................................................................................................... 1 5. BLOCK DIAGRAM ............................................................................................. 2 6. PIN CONFIGURATION....................................................................................... 3 7. DEVICE PIN OUT AND PIN DESCRIPTIONS ................................................... 4 8. SWITCH CONDITIONS AND FUNCTIONS........................................................ 5 9. APPLICATION CIRCUIT .................................................................................... 6 Hardware Mode...............................................................................................................................................6 Software Mode – I2C-Bus Control ...................................................................................................................7 Software Mode – EEPROM Control ................................................................................................................8 10. ABSOLUTE MAXIMUM RATING (TA = 25OC) ................................................... 9 11. ELECTRICAL CHARACTERISTICS .................................................................. 9 12. SWITCHING ELECTRICAL CHARACTERISTICS ...........................................11 13. I2C-BUS CONCEPTS ....................................................................................... 12 14. I2C-BUS PROTOCOL ....................................................................................... 14 15. EEPROM CONTROL MODE ............................................................................ 15 16. SUB-ADDRESS BYTE ..................................................................................... 16 17. POWER ON RESET CONDITION.................................................................... 16 18. DATA BYTE SPECIFICATION.......................................................................... 17 TruBass FILTER SETTING, INPUT VOLUME (SUB-ADDRESS “XXXXB000”) ...........................................17 OUTPUT MUTE, LEFT OUTPUT ATTENUATE (SUB-ADDRESS “XXXXB001”).........................................18 BYPASS on/off, RIGHT OUTPUT ATTENUATE (SUB-ADDRESS “XXXXB010”) ........................................19 TruBass on/off, COMPRESSOR on/off, TruBass PUNCH LEVEL (SUB-ADDRESS “XXXXB011”) .............20 SRS 3D (WIDTH & CENTER) Bypass on/off, WIDTH on/off, WIDTH LEVEL (SUB-ADDRESS “XXXXB100”) 21 SRS HEADPHONE MODE on/off, CENTER on/off, CENTER LEVEL (SUB-ADDRESS “XXXXB101”) .......22 SRS FOCUS LEVEL (SUB-ADDRESS “XXXXB110”)...................................................................................23 DEFINITION LEVEL (SUB-ADDRESS “XXXXB111”) ...................................................................................23 19. PACKAGE INFORMATION .............................................................................. 24 AP8302 SRS WOW HD Audio Processor 4. FEATURES 1. OVERVIEW The AP8302 is a WOW HD audio enhancement processor based on SRS Labs’ award-winning WOW technology. WOW delivers a broadened stereo field, improved dynamics and increased bass performance over stereo headphones or a wide range of speaker sizes. WOW HD goes a step beyond WOW by delivering a new purity to sound with cleaner, livelier audio quality (definition), advanced bass enhancement for fatter low frequency bass (TruBass) and incredibly innovative “center” control to place center information in the stereo mix in the forefront or toward the back, in a delicate balance with the 3D stereo width control (SRS 3D). AP8302 operates under three different control modes, hardware, I2C and EEPROM, suitable for wide range of applications with or without external MCU. Enhanced selectable TruBass filter setting by pin settings for speaker with typical cut-off frequency between 40Hz and 400Hz minimizing external components. Apart from the integrated TruBass audio enhancement, separate subwoofer output is also available to support external connection to a subwoofer for dedicated bass reproduction. The built-in input volume control prevents signal clipping during audio enhancement while incorporating output volume control further reducing the total number of external components. 2. APPLICATIONS Portable Audio System Docking Speaker System Surround headphone LCD TV Set-Top-Box Boombox 3. ORDERING INFORMATION PART NUMBER PINS PACKAGE AP8302-LQ-L 44 LQFP Revision 0.3 SRS Audio Technologies SRS WOW HD SRS WOW SRS 3D SRS FOCUS SRS TruBass SRS Headphone Definition Center Control Other Features Hardware / Software Mode Input volume attenuator SRS 3D level adjustable Center control level adjustable TruBass on/off and level control TruBass filter selectable without external components FOCUS level control Definition level control SRS Headphone mode control (on/off) Power down mode Built-in circuit to prevent pop noise when power up/down Bypass mode Subwoofer output Built-in zero-cross detector prevents click noise No DC level shift Built-in power on reset Operating voltage: 2.7V to 5.5V Operating temperature: -20oC to 70oC Software Mode Balance output speaker attenuators Mute function SRS 3D on/off Center on/off FOCUS on/off Definition on/off TruBass compressor on/off Support I2C-bus control or EEPROM control Page 1 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 5. BLOCK DIAGRAM Software Mode Hardware Mode Revision 0.3 Page 2 of 25 September 14, 2007 Revision 0.3 38 37 36 35 34 18 19 20 21 22 SRS3DR RDEF VREF VREFB \ SDA 40 16 SRS3DL RFOCUS 41 15 LDEF 39 42 14 PUNCHIN 17 43 13 COMPO LFOCUS 44 12 COMPC Page 3 of 25 OUTPUTL SUBOUT SLP CENTERO CENTER SPACEO SPACE SRSC1 SRSC2 SRSC3 SRSC4 AP8302 SRS WOW HD Audio Processor 6. PIN CONFIGURATION September 14, 2007 AP8302 SRS WOW HD Audio Processor 7. DEVICE PIN OUT AND PIN DESCRIPTIONS LQFP PIN # PIN NAME 1 LIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RIN CB2A CB2 CB2B CB1A CB1 CB1B LPC2 LPC1 COMPC2 COMPC COMPO PUNCHIN LDEF SRS3DL LFOCUS RFOCUS SRS3DR RDEF VREF 22 SDA / VREFB 23 SCL / HPMODE SW Mode: Serial Clock Line HW Mode: SRS Headphone Mode Control Pin 24 RVOLI / BYPON SW Mode: Right Channel Volume Control Input HW Mode: Bypass Mode Control 25 RMAXO / COFCP3 SW Mode: Right Line Out HW Mode: TruBass Filter Setting Selection Bit 3 26 LVOLI / COFCP2 SW Mode: Left Channel Volume Control Input HW Mode: TruBass Filter Setting Selection Bit 2 27 LMAXO / COFCP1 SW Mode: Left Line Out HW Mode: TruBass Filter Setting Selection Bit 1 28 29 PD MB0 Powerdown Mode Selection Pin Mode Bit 0 30 31 MB1 VSA Mode Bit 1 Ground 32 33 34 35 36 37 38 39 40 41 VDA OUTPUTR OUTPUTL SUBOUT SLP CENTERO CENTER SPACEO SPACE SRSC1 42 43 SRSC2 SRSC3 SRS-3D Capacitor Output 2 SRS-3D Capacitor Output 3 44 SRSC4 SRS-3D Capacitor Output 4 Revision 0.3 DESCRIPTIONS Left Audio Input Right Audio Input TruBass Bandpass Filter 2 Input TruBass Bandpass Filter 2 Input TruBass Bandpass Filter 2 Output TruBass Bandpass Filter 1 Input TruBass Bandpass Filter 1 Input TruBass Bandpass Filter 1 Output TruBass Low-Pass Filter 2 Output TruBass Low-Pass Filter 1 Output TruBass Compressor Capacitor Output TruBass Compressor Capacitor Output TruBass Compressor Output TruBass Punch Input Left DEFINITION Input Left SRS-3D Output Left FOCUS Input Right FOCUS Input Right SRS-3D Output Right DEFINITION Input Reference Voltage Input SW Mode: Serial Data Line HW Mode: Reference Voltage Output Supply Voltage Right Speaker Output Left Speaker Output Subwoofer Output Subwoofer Low-Pass Filter Input Center Output Center Level Control Input Width Output Width Level Control Input SRS-3D Capacitor Output 1 Page 4 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 8. SWITCH CONDITIONS AND FUNCTIONS HEADPHONE MODE on/off PIN STATE OF “HPMODE” DESCRIPTION 0 Normal Mode 1 SRS Headphone Mode BYPASS MODE on/off PIN STATE OF “BYPON” DESCRIPTION 0 Normal Mode 1 Bypass Mode. Input signals will be fed to output directly without processing TruBass FILTER SETTING PIN STATE COFCP3 COFCP2 COFCP1 0 0 0 TruBass Filter Setting Selected 40Hz 0 0 1 60Hz 0 1 0 100Hz 0 1 1 150Hz 1 0 0 200Hz 1 0 1 250Hz 1 1 0 300Hz 1 1 1 400Hz POWERDOWN MODE on/off PIN STATE OF “PD” DESCRIPTION 0 Normal Mode 1 POWERDOWN Mode In this mode, all the amplifiers inside AP8302 will be shut down with a very low current consumption (<10-4A). CONTROL MODE BIT SELECTION PIN STATE DESCRIPTION MB1 MB0 0 0 Hardware Mode with TruBass OFF All functions are controlled by hardware (external variable resistors and switches) only. 0 1 Hardware Mode with TruBass ON All functions are controlled by hardware (external variable resistors and switches) only. 1 0 Software Mode Controlled By EEPROM. 1 Software Mode Controlled By I2C-Bus. Under this mode, all functions (excepting Powerdown mode) are controlled through I2C-Bus. No external variable resistor or switch is needed. 1 Revision 0.3 Page 5 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 9. APPLICATION CIRCUIT Hardware Mode AP8302 Application Notes Tolerance of all resistors = 1% Tolerance of capacitors = 5% Speaker out signal can be obtained through pin 33, 34 Revision 0.3 Page 6 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor APPLICATION CIRCUIT (continued) Software Mode – I2C-Bus Control AP8302 MCU Application Notes Tolerance of all resistors = 1% Tolerance of capacitors = 5% Speaker out signal can be obtained through pin 33, 34 Revision 0.3 Page 7 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor APPLICATION CIRCUIT (continued) Software Mode – EEPROM Control AP8302 EEPROM Application Notes Tolerance of all resistors = 1% Tolerance of capacitors = 5% Speaker out signal can be obtained through pin 33, 34 Revision 0.3 Page 8 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 10. ABSOLUTE MAXIMUM RATING (Ta = 25oC) [Under no circumstances should the absolute maximum ratings given below be violated. Stresses exceeding one or more of the limiting values may cause permanent damage to the device.] PARAMETER SYMBOL VALUE UNIT Supply Voltage Vcc 6 V mW Power Dissipation Pd 150 Operating Temperature Range Topr -20 to 70 o C -20 to 100 o C Storage Temperature Range Tstg 11. ELECTRICAL CHARACTERISTICS [Refer to the application circuit VCC=5V, Ta=25oC, f=1kHz, all controls flat unless otherwise specified] PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT POWER SUPPLY Supply Voltage Vcc Supply Current Id Supply Rejection 2.7 5 5.5 V Normal mode - 18 - mA Powerdown mode - 20 - μA - 80 - dB All flat, f=20 to 20kHz - -86 All max, f=20 to 20kHz - -63 - All flat, f=1kHz - 80 - dB -1.5 - 1.5 dB dB SVR GENERAL Output Noise Channel Separation Total Normalized Volume Set Error Nout SC ΔGa Total Tracking Error (ch. L – ch. R) ΔGt Total Harmonic Distortion + Noise THD+N G = 0 through –50dB dBV -0.2 - 0.2 Bypass - 0.02 - All max - 0.3 - Bypass, THD=3% - 1.7 - All max, THD=3% - 0.2 - - 0.5 Vcc - V - 64 - kΩ Crange - 31 - dB Maximum Attenuation Amax - 31 - dB Step Resolution Astep - 1 - dB Maximum Input Voltage Internal Reference Voltage VIM Vref % Vrms INPUT MASTER VOLUME Input Resistance Control Range Rin At pins “LIN” & “RIN” OUTPUT BALANCE AND VOLUME CONTROL Control Range Crange - 64 - dB Maximum Attenuation Amax - 62 - dB Step Resolution Astep - 1 - dB Mute Attenuation Amute - 100 - dB Revision 0.3 f=1kHz Page 9 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor ELECTRICAL CHARACTERISTICS (continued) [Refer to the application circuit VCC=3.3V, Ta=25oC, Vin = -20dBV (0.1Vrms), f=1kHz unless otherwise specified] PARAMETER SYMBOL TEST CONDITION MIN. Maximum Output Voltage Vom THD=3% at pin “OUTPUTL” & “OUTPUTR” - Output DC Voltage Level Vdc At pin “OUTPUTL” & “OUTPUTR” - Output Resistance Rout At pin “OUTPUTL” & “OUTPUTR” 250 Power Up Muting Time TPUM At pin “OUTPUTL” & “OUTPUTR” TYP. MAX. UNIT 1 Vcc - V 0.5 Vcc - V 300 400 Ω - - 1.6 s Vrst - 0.3 Vcc - V Input High Voltage for Pin “SCL" VIH 0.7 Vcc - - V Input Low Voltage for Pin “SCL” VIL - - 0.3 Vcc V Input Threshold Voltage for Pin “SDA” VTH - 0.5 Vcc - V Output-Low Current for Pin “SDA” IOL - 4 - mA Clock Frequency for Pin “SCL” fSCL - 75 - kHz AUDIO OUTPUT POWER-ON RESET Start of Reset 2 DIGITAL CIRCUIT (I C-BUS) Software mode (EEPROM control) FREQUENCY RESPONSE (WOW HD, SRS Headphone off) FREQUENCY RESPONSE (definition) FREQUENCY RESPONSE (WOW HD, SRS Headphone on) FREQUENCY RESPONSE (FOCUS) Revision 0.3 Page 10 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor FREQUENCY RESPONSE (SRS 3D, SRS headphone off) FREQUENCY RESPONSE (TRUBASS, compressor off) FREQUENCY RESPONSE (SRS 3D, SRS headphone on) FREQUENCY RESPONSE (TRUBASS, compressor on) 12. SWITCHING ELECTRICAL CHARACTERISTICS [VCC=3.3V, Ta=25oC, Software Mode (I2C-bus control), input logic 0 = 0V, input logic 1 = VCC] PARAMETER SYMBOL MIN. TYP. MAX. UNIT kHz Pin SCL Clock Frequency fscl - - 100 Bus Free Time Between Transmissions tbuf 4.7 - - Start Condition Hold Time (Prior to First Clock Pulse) thdst 4.0 - - Clock Low Time tlow 4.7 - - Clock High Time thigh 4.7 - - Setup Time for Repeated Start Condition tsust 4.7 - - Pin SDA Hold Time for Pin SCL Falling thdd 0 - - Pin SDA Setup Time to Pin SCL Rising tsud 0.25 - - Rise Time of Both SCL and Pin SDA Signal tr - - 1 Fall Time of Pin SCL and Pin SDA Signal tf - - 0.3 Setup Time for Stop Condition tsusp 4.7 - - Revision 0.3 Page 11 of 25 μs September 14, 2007 AP8302 SRS WOW HD Audio Processor stop SDA repeated start start stop tbuf thdst thigh tf tsusp SCL tlow tsud thdd tsust tr 13. I2C-BUS CONCEPTS I2C-bus is a simple bi-directional, 2-wire serial data (SDA) and serial clock (SCL) bus for inter-IC control. Both lines must be connected to a positive supply via a pull-up resistor when connected to output of device. Data Validity One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as control signals. SDA SCL SDA stable data valid change of data allowed Data Transfer Start and Stop Conditions Both data and clock remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data, while the clock is HIGH, is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Revision 0.3 Device Address After the Start condition, the address of a Slave device is sent. This address is 7 bits long followed by an 8th-bit, which is a data direction bit (R/W): 0 indicates a transmission (Write), 1 indicates a request for data (Read). Acknowledge There is no limit to the number of data byte transferred between the start and stop conditions from transmitter to receiver. Each byte of 8 bits is followed by an acknowledge bit (ACK). A slave receiver must generate an ACK after the reception of each byte. Also a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. Device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the ACK related clock pulse, set-up and hold times must be taken into consideration. A master receiver must signal an end of data to the transmitter by not generating an ACK on the last byte that has been clocked out of the slave. In this case, the transmitter must release the data line HIGH to allow the master to generate a stop condition. Page 12 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor SDA SDA SCL SCL S P START condition STOP condition Definition of START and STOP condition DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 clock pulse for acknowledge START condition Acknowledgement on I2C-bus LSB MSB 1 Start Condition 2-6 Slave Address LSB *ACK ~ ~ ~ ~ SCL ~ ~ ~ ~ MSB ~ ~ ~ SDA *NAK 7 8 9 R/W ACK 1 2-7 DATA 8 9 ACK Stop Condition * NAK – SDA line is HIGH **ACK – SDA line is pulled LOW by receiver Overall Diagram Revision 0.3 Page 13 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 14. I2C-BUS PROTOCOL The interface protocol comprises: A start condition (S) A chip address byte A sub-address byte CHIP ADDRESS MSB S 1 SUB-ADDRESS LSB 0 1 0 0 0 0 A sequence of data + acknowledge (A) A stop condition (P) 0 DATA 1 to DATA n MSB A X LSB X X X B MSB DATA A LSB DATA A P Non-Incremental Bus The user sends a start condition, the correct chip address, a sub-address with B=0 (non-incremental bus), an 8-bit data byte, a stop condition. CHIP ADDRESS SUB-ADDRESS MSB S 1 LSB 0 1 0 0 0 0 0 MSB A X 1 BYTE DATA LSB X X X 0 D2 D1 D0 MSB A LSB D7 D6 D5 D4 D3 D2 D1 D0 A P Incremental Bus The user sends a start condition, the correct chip address, a sub-address with B=1 (incremental bus), a series of 8-bit data bytes and a stop condition. Now the chip is in a loop condition with an auto increment of the sub-address. The 1st data byte will be sent to the sub-address, the 2nd data byte will be sent to the sub-address plus one, etc., and will end when the stop condition is received. CHIP ADDRESS MSB S 1 SUB-ADDRESS LSB 0 Revision 0.3 1 0 0 0 0 0 MSB A X DATA 1 to DATA n LSB X X X 1 D2 D1 D0 Page 14 of 25 MSB A LSB DATA A P September 14, 2007 AP8302 SRS WOW HD Audio Processor 15. EEPROM CONTROL MODE If “MB1” is connected to “VCC” and “MB0” is connected to “GND”, AP8302 will enter EEPROM control mode. Under this mode, all functions (excepting Powerdown mode) of AP8302 will be pre-set by an external EEPROM at power-up. The EEPROM must be I2C-compatible device such as M24CXX series and must be programmed all the data byte setting of AP8302 as below: Memory Map of EEPROM BYTE ADDRESS OF EEPROM DATA 00H 00001000 01H Data Byte With SUB-ADDRESS “XXXX1000” 02H Data Byte With SUB-ADDRESS “XXXX1001” 03H Data Byte With SUB-ADDRESS “XXXX1010” 04H Data Byte With SUB-ADDRESS “XXXX1011” 05H Data Byte With SUB-ADDRESS “XXXX1100” 06H Data Byte With SUB-ADDRESS “XXXX1101” 07H Data Byte With SUB-ADDRESS “XXXX1110” 08H Data Byte With SUB-ADDRESS “XXXX1111” EEPROM (30 ) M B 1 (29 ) M B 0 AP8302 E0 E1 E2 GND VCC WC SCL SDA M 2 4CX X SDA (22) (23 ) SCL Connection between AP8302 and EEPROM Noted: “E0”, “E1”, “E2” of EEPROM must be connected to Ground Device identifier of EEPROM must be “1010” (#) => # is pin number of AP8302 Revision 0.3 Page 15 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 16. SUB-ADDRESS BYTE MSB LSB FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 X X X X B 0 0 0 TruBass FILTER SETTING, INPUT VOLUME X X X X B 0 0 1 ZEROCROSS on/off, MUTE on/off, LEFT ATTENUATE X X X X B 0 1 0 BYPASS MODE on/off, RIGHT ATTENUATE X X X X B 0 1 1 TruBass on/off, COMPRESSOR on/off, PUNCH LEVEL X X X X B 1 0 0 SRS-3D on/off, WIDTH on/off, WIDTH LEVEL X X X X B 1 0 1 HEADPHONE MODE on/off, CENTER on/off, CENTER LEVEL X X X X B 1 1 0 FOCUS on/off, FOCUS LEVEL X X X X B 1 1 1 DEFINITION on/off, DEFINITION LEVEL 17. POWER ON RESET CONDITION SUB-ADDRESS BYTE POWER ON RESET CONDITION MSB LSB Mode Status Bit Status D7 D6 D5 D4 D3 D2 D1 D0 X X X X B 0 0 0 TruBass filter setting:100Hz Input volume: 0dB D7:D5 D4:D0 X X X X B 0 0 1 Zerocross: OFF MUTE: OFF Left output attenuates: 0dB D7 0 D6 0 D5:D0 000000 X X X X B 0 1 0 Bypass mode: ON Right output attenuates: 0dB D6 1 D5:D0 000000 X X X X B 0 1 1 TruBass: ON Compressor: ON Punch level: 0 D5 D4 D3:D0 1 1 0000 X X X X B 1 0 0 SRS-3D: ON WIDTH: ON WIDTH level: 0 D5 D4 D3:D0 1 1 0000 X X X X B 1 0 1 Headphone mode: OFF CENTER: ON CENTER level: 0 D5 D4 D3:D0 0 1 0000 X X X X B 1 1 0 FOCUS: ON FOCUS level: 0 D4 D3:D0 1 0000 X X X X B 1 1 1 DEFINITION: ON DEFINITION level: 0 D4 D3:D0 1 0000 010 00000 B = 0 non-incremental B = 1 incremental Revision 0.3 Page 16 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 18. DATA BYTE SPECIFICATION TruBass FILTER SETTING, INPUT VOLUME (SUB-ADDRESS “XXXXB000”) D7:D5 – TruBass FILTER SETTING D4:D0 – INPUT VOLUME CONTROL TruBass FILTER SETTING MSB LSB D4 D3 D2 D1 D0 TruBass FILTER SETTING D7 D6 D5 0 0 0 40Hz 0 0 1 60Hz 0 1 0 100Hz 0 1 1 150Hz 1 0 0 200Hz 1 0 1 250Hz 1 1 0 300Hz 1 1 1 400Hz INPUT VOLUME MSB D7 D6 Revision 0.3 D5 LSB INPUT VOLUME D4 D3 D2 D1 D0 1dB STEPS 1 1 1 1 1 -31dB 1 1 1 1 0 -30dB 1 1 1 0 1 -29dB • • • • • • • • • • • • • • • • • • 0 0 0 1 0 -2dB 0 0 0 0 1 -1dB 0 0 0 0 0 0dB Page 17 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor OUTPUT MUTE, LEFT OUTPUT ATTENUATE (SUB-ADDRESS “XXXXB001”) D7 – ZEROCROSS on/off D6 – LEFT & RIGHT OUTPUT MUTE on/off D5:D0 – LEFT SPEAKER OUTPUT CONTROL ZEROCROSS MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 ZEROCROSS 0 Zerocross OFF 1 Zerocross ON LEFT & RIGHT SPEAKER OUTPUT MUTE MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 SPEAKER OUTPUT MUTE 0 Speaker output ON 1 Speaker output MUTE LEFT OUTPUT ATTENUATOR CONTROL MSB D7 D6 Revision 0.3 LSB LEFT SPEAKER OUTPUT ATTENUATION D5 D4 D3 D2 D1 D0 1dB STEPS 1 1 1 1 1 1 MUTE 1 1 1 1 1 0 -62dB 1 1 1 1 0 1 -61dB • • • • • • • • • • • • • • • • • • • • • 0 0 0 0 1 0 -2dB 0 0 0 0 0 1 -1dB 0 0 0 0 0 0 0dB Page 18 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor BYPASS on/off, RIGHT OUTPUT ATTENUATE (SUB-ADDRESS “XXXXB010”) D6 – BYPASS MODE on/off D5:D0 – RIGHT SPEAKER OUTPUT CONTROL WOW HD BYPASS MSB LSB D5 D4 D3 D2 D1 D0 WOW HD D7 D6 1 0 NORMAL 1 1 BYPASS WOW HD BYPASS will bypass all functional blocks. Input signal will be fed to output directly without processing. RIGHT OUTPUT ATTENUATOR CONTROL MSB D7 D6 LSB RIGHT SPEAKER OUTPUT ATTENUATION D5 D4 D3 D2 D1 D0 1dB STEPS 1 1 1 1 1 1 1 MUTE 1 1 1 1 1 1 0 -62dB 1 1 1 1 1 0 1 -61dB 1 • • • • • • • 1 • • • • • • • 1 • • • • • • • 1 0 0 0 0 1 0 -2dB 1 0 0 0 0 0 1 -1dB 1 0 0 0 0 0 0 0dB Revision 0.3 Page 19 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor TruBass on/off, COMPRESSOR on/off, TruBass PUNCH LEVEL (SUB-ADDRESS “XXXXB011”) D5 – TruBass on/off D4 – COMPRESSOR on/off D3:D0 – PUNCH LEVEL CONTROL TruBass ON/OFF MSB LSB D4 D3 D2 D1 D0 TruBass D7 D6 D5 X X 0 OFF X X 1 ON When TruBass off is selected, the punch level will be set as “0” such that no signal from TruBass Block will be past out to the outputs. And then when TruBass is on again, the original punch level will be restored automatically. COMPRESSOR ON/OFF MSB LSB D5 D4 D3 D2 D1 D0 COMPRESSOR D7 D6 X X 0 OFF X X 1 ON PUNCH LEVEL MSB D7 D6 X D4 TruBass PUNCH LEVEL D3 D2 D1 D0 LINEAR X 1 1 1 1 15 X X 1 1 1 0 14 X X 1 1 0 1 13 X X • • • • • X X • • • • • X X • • • • • X X 0 0 1 0 2 X X 0 0 0 1 1 X X 0 0 0 0 0 Revision 0.3 D5 LSB Page 20 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor SRS 3D (WIDTH & CENTER) Bypass on/off, WIDTH on/off, WIDTH LEVEL (SUB-ADDRESS “XXXXB100”) D5 – SRS 3D Bypass on/off D4 –WIDTH on/off D3:D0 –WIDTH LEVEL CONTROL SRS 3D Bypass ON/OFF MSB LSB D4 D3 D2 D1 D0 SRS-3D D7 D6 D5 X X 0 BYPASS X X 1 NORMAL When SRS-3D off is selected, input signal will bypass the SRS 3D block and past to DEFINITION and FOCUS block directly. WIDTH ON/OFF MSB LSB D5 D4 D3 D2 D1 D0 WIDTH D7 D6 X X 0 OFF X X 1 ON When WIDTH off is selected, the WIDTH level will be set as “0” such that no signal from WIDTH module will be past out to SRS 3D outputs. And then when WIDTH is on again, the original WIDTH level will be restored automatically. WIDTH LEVEL MSB D7 D6 X X D4 WIDTH LEVEL D3 D2 D1 D0 LINEAR X 1 1 1 1 15 X 1 1 1 0 14 X X 1 1 0 1 13 X X • • • • • X X • • • • • X X • • • • • X X 0 0 1 0 2 X X 0 0 0 1 1 X X 0 0 0 0 0 Revision 0.3 D5 LSB Page 21 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor SRS HEADPHONE MODE on/off, CENTER on/off, CENTER LEVEL (SUB-ADDRESS “XXXXB101”) D5 – SRS HEADPHONE on/off D4 –CENTER on/off D3:D0 – CENTER LEVEL CONTROL SRS HEADPHONE ON/OFF MSB LSB D4 D3 D2 D1 D0 SRS HEADPHONE D7 D6 D5 X X 0 OFF X X 1 ON CENTER ON/OFF MSB LSB D5 D4 D3 D2 D1 D0 CENTER D7 D6 X X 0 OFF X X 1 ON When CENTER off is selected, the CENTER level will be set as “0” such that no signal from CENTER module will be past out to SRS 3D outputs. And then when CENTER is on again, the original CENTER level will be restored automatically. CENTER LEVEL MSB LSB CENTER LEVEL D3 D2 D1 D0 LINEAR X 1 1 1 1 15 X 1 1 1 0 14 X X 1 1 0 1 13 X X • • • • • X X • • • • • X X • • • • • X X 0 0 1 0 2 X X 0 0 0 1 1 X X 0 0 0 0 0 D7 D6 X X Revision 0.3 D5 D4 Page 22 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor SRS FOCUS LEVEL (SUB-ADDRESS “XXXXB110”) D4 – SRS FOCUS on/off D3:D0 – FOCUS LEVEL CONTROL SRS FOCUS ON/OFF MSB LSB D3 D2 D1 SRS FOCUS D7 D6 D5 D4 D0 X X X 0 OFF X X X 1 ON When SRS FOCUS off is selected, the SRS FOCUS level will be set as “0” such that no signal from FOCUS module will be past out to SRS FOCUS outputs. And then when SRS FOCUS is on again, the original FOCUS level will be restored automatically. SRS FOCUS LEVEL MSB LSB FOCUS LEVEL D3 D2 D1 D0 LINEAR X 1 1 1 1 15 X X 1 1 1 0 14 X X X • • • • • X X X • • • • • X X X • • • • • X X X 0 0 0 1 1 X X X 0 0 0 0 0 D7 D6 D5 X X X D4 DEFINITION LEVEL (SUB-ADDRESS “XXXXB111”) D4 –DEFINITION on/off D3:D0 – DEFINITION LEVEL CONTROL DEFINITION ON/OFF MSB LSB D3 D2 D1 D0 DEFINITION D7 D6 D5 D4 X X X 0 OFF X X X 1 ON When DEFINITION off is selected, the DEFINITION level will be set as “0” such that no signal from DEFINITION module will be past out. And then when DEFINITION is on again, the original DEFINITION level will be restored automatically. DEFINITION LEVEL MSB D7 D6 D5 X X X X D4 LSB DEFINITION LEVEL D3 D2 D1 D0 LINEAR X 1 1 1 1 15 X 1 1 1 0 14 • • • • X X X • X X X • • • • • X X X • • • • • X X X 0 0 0 1 1 X X X 0 0 0 0 0 Revision 0.3 Page 23 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor 11.00(0.457) NOM 8.00(0.315) REF 19. PACKAGE INFORMATION AP8302 44-Pin LQFP Revision 0.3 Page 24 of 25 September 14, 2007 AP8302 SRS WOW HD Audio Processor Valence Semiconductor Design Limited 20/F., APEC Plaza, 49 Hoi Yuen Road, Kwun Tong, Kowloon, Hong Kong Tel: (852) 2797 3288 Fax: (852) 2776 7770 Email: [email protected] Website: http://www.valencetech.com IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. ValenceTech Ltd. and its affiliates (“Valence”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF VALENCE PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY VALENCE, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Purchasers of ValenceTech products must enter into a license agreement directly with SRS Labs if the royalty for the use of the SRS technologies is not included in the ValenceTech purchase price. Neither the purchase of a ValenceTech product nor the license of SRS products conveys the right to sell commercialized recordings made with any ValenceTech or SRS technologies. ValenceTech, SRS Labs, SRS, and the SRS Labs logo designs are trademarks of SRS Labs, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Revision 0.3 Page 25 of 25 September 14, 2007