芯美电子 Preliminary EUA2101 10-W Stereo Class-D Audio Power Amplifier DESCRIPTION FEATURES The EUA2101 is a high efficiency, 10W stereo Class-D audio power amplifier for driving bridged-tied stereo speakers. The EUA2101 utilizes fully differential architecture, and comprehensive click and pop suppression. The high efficiency of the EUA2101, 87% eliminates the need for an external heat sink when playing music. The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, 36dB. The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts with an auto recovery feature and monitor output. z z z z z z z z z z z Unique Modulation Scheme Reduces EMI Emission 10-W/ch into an 8-Ω Load From a 12-V Supply 17.4-W/ch into an 4-Ω Load From a 12-V Supply Operates from 10V to 15V 87% Efficient Class-D Operation Eliminates Need for Heat Sinks Four Selectable, Gain Settings Differential Inputs Thermal and Short-Circuit Protection With Auto Recovery Feature Clock Output for Synchronization With Multiple Class-D Devices 7mm × 7mm, 48-pin TQFN Package RoHS compliant and 100% lead(Pb)-free APPLICATIONS Typical Application Circuit z Televisions Figure1. DS2101 Ver 0.1 June 2007 1 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUA2101 Pin Configurations Package Type Pin Configurations (TOP VIEW) TQFN-48 Pin Description PIN TQFN-48 I/O DESCRIPTION SHUTDOWN 44 I Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with compliance to AVCC. RINN 2 I Negative audio input for right channel. Biased at VREG/2. RINP 3 I Positive audio input for right channel. Biased at VREG/2. LINN 6 I Negative audio input for left channel. Biased at VREG/2. LINP 5 I Positive audio input for left channel. Biased at VREG/2. GAIN0 8 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 9 I Gain select most significant bit. TTL logic levels with compliance to VREG. MUTE 45 I FAULT 46 O BSLP 18 I/O Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults. Thermal faults are not reported on this terminal. Bootstrap I/O for left channel, positive high-side FET. PVCCL 26,27 LOUTP 19,20 O Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. Class-D 1/2-H-bridge positive output for left channel. PGNDL 28,29 LOUTN 21,22 O Class-D 1/2-H-bridge negative output for left channel. BSLN 23 I/O Bootstrap I/O for left channel, negative high-side FET. VCLAMPL 30 Internally generated voltage supply for left channel bootstrap capacitor. VCLAMPR 31 Internally generated voltage supply for right channel bootstrap capacitor. DS2101 Ver 0.1 June 2007 Power ground for left channel H-bridge. 2 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary Pin Description (Continued) PIN TQFN-48 I/O DESCRIPTION BSRN 38 I/O Bootstrap I/O for right channel, negative high-side FET. ROUTN 39,40 O Class-D 1/2-H-bridge negative output for right channel. PGNDR 32,33 ROUTP 41,42 PVCCR 34,35 BSRP 43 AGND 4,17 ROSC 14 I/O MSTR/ SLV 10 I SYNC 11 I/O VBYP 16 O VREG 15 O AVCC 48 NC 1,7,12, 13,24,25, 36,37,47 Power ground for right channel H-bridge. O Class-D 1/2-H-bridge positive output for right channel. Power supply for right channel H-bridge, not connected to PVCCL or AVCC. I/O Bootstrap I/O for right channel, positive high-side FET. Analog ground for digital/analog cells in core. I/O for current setting resistor of ramp generator. Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/ SLV terminal. Input signal not to exceed VREG. Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor sizing. 4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/ SLV pins only. Not specified for driving other external circuitry. High-voltage analog power supply. Not internally connected to PVCCR or PVCCL. Not internally connected. Ordering Information Order Number Package Type EUA2101JIR1 TQFN-48 EUA2101 Marking xxxxx EUA2101 Operating Temperature range -40 °C to 85°C □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: TQFN DS2101 Ver 0.1 June 2007 3 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary Absolute Maximum Ratings ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Supply Voltage, AVCC,PVCC -------------------------------------------------------------------------- -0.3 V to 15V Input Voltage, SHUTDOWN ,MUTE--------------------------------------------------------- -0.3 V to VCC +0.3V Input Voltage,GAIN0,GAIN1,RINN,RINP,LINN,LINP, MSTR/ SLV ,SYNC------- -0.3 V to VREG +0.5V Continuous Total Power Dissipation-------------------------------------------------- See Dissipation Rating Table Free-air Temperature Range, TA ---------------------------------------------------------------------- -40°C to 85°C Junction Temperature Range, TJ --------------------------------------------------------------------- -40°C to 150°C Storage Temperature Rang, Tstg ------------------------------------------------------------------- -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ----------------------------------------- 260°C Load Resistance, RLOAD ---------------------------------------------------------------------------------- 3.2Ω Minimum Typical Dissipation Ratings Package TA ≤ 25°C Derating Factor TA= 70°C TA= 85°C TQFN-48 4.39W 35.1 mW/ °C 2.81W 2.28W Recommended Operating Conditions Supply voltage, VCC PVCC,AVCC High-level input voltage, VIH Low-level input voltage, VIL SHUTDOWN ,MUTE,GAIN0,GAIN1, MSTR/SLV ,SYNC SHUTDOWN ,MUTE,GAIN0,GAIN1, MSTR/SLV ,SYNC Min Max Unit 10 15 V 2 V 0.8 SHUTDOWN ,VI=VCC,VCC=12V 125 MUTE,VI=VCC, VCC=12V 75 GAIN0,GAIN1, MSTR/SLV ,SYNC,VI=VREG, VCC=12V 2 SHUTDOWN ,VI=0V,VCC=12V 2 1 High-level output voltage, VOH SYNC,MUTE,GAIN0,GAIN1,MSTR/SLV ,VI=0V, VCC=12V FAULT, IOH=1mA Low-level output voltage, VOL FAULT, IOL= -1mA Oscillator frequency, fOSC ROSC Resistor=100 kΩ High-level input current, IIH Low-level input current, IIL Operating free-air temperature, TA V µA µA VREG-0.6 V AGND+0.4 V 200 300 kHz -40 85 °C DC Characteristics TA = 25°C ,VCC=12V, RL=8Ω (Unless otherwise noted) Symbol VOS PSRR Parameter Conditions Min EUA2101 Unit Typ Max. Class-D output offset voltage (measured differentially) VI= 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 1.30 1.39 1.49 V 4-V internal supply voltage VREG, no load, VCC= 10V to 15V 3.70 3.94 4.25 V DC Power supply rejection ratio VCC = 12 V to 15 V, inputs ac coupled to AGND, Gain = 36 dB DS2101 Ver 0.1 June 2007 5 -60 4 联系电话：１５９９９６４４５７９ ８３１５１７１５ mV dB 芯美电子 EUA2101 Preliminary DC Characteristics (Continued) Symbol ICC Parameter Conditions Quiescent supply current ICC(SD) Quiescent supply current in shutdown mode ICC(MUTE) Quiescent supply current in mute mode rDS(on) Drain-source on-state resistance EUA2101 Unit Typ Max. SHUTDOWN =2V, MUTE=0V, no load 25 30 mA SHUTDOWN =0.8V, no load 300 490 µA 6 11 mA MUTE=2V, no load VCC=12V, IO=500mA, TJ=25°C GAIN1=0.8V G Min Gain GAIN1=2V High Side 370 Low Side 370 Total 780 950 mΩ GAIN0=0.8V 19 20 21 GAIN0=2V 25 26 27 GAIN0=0.8V 31 32 33 GAIN0=2V 35 36 37 dB dB tON Turn-on time C(VBYP)=1µF, SHUTDOWN =2V 25 ms tOFF Turn-off time C(VBYP)=1µF, SHUTDOWN =0.8 V 0.1 ms AC Characteristics TA = 25°C ,VCC=12V, RL=8Ω (Unless otherwise noted) Symbol KSVR PO Parameter Conditions 200mVPP ripple from 20 Hz-1 kHz, Gain= 20dB, Inputs ac-coupled to AGND Supply ripple rejection Continuous output power THD+N Total harmonic distortion +noise Vn SNR Min EUA2101 Unit Typ Max. -50 THD+N=7%, f=1kHz 9.32 THD+N=10%, f=1kHz 10 THD+N=7%, f=1kHz, RL=4Ω 16.42 THD+N=10%, f=1kHz,RL=4Ω (thermally limited) 17.45 RL=8Ω, f=1 kHz, PO=5W (half-power) 0.258% RL=4Ω, f=1 kHz, PO=8W (half-power) 0.287% dB W Output integrated noise 20Hz to 22kHz, A-weighted filter, Gain=20dB 512 µV -65 dBV Crosstalk PO=1 W, Gain=20dB, f=1 kHz Maximum output at THD+N< 1%, f=1kHz,Gain=20dB, A-weighted -85 dB 84 dB Thermal trip point 160 ℃ Thermal hysteresis 30 ℃ Signal-to-noise ratio DS2101 Ver 0.1 June 2007 5 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUA2101 Block Diagram Figure2. DS2101 Ver 0.1 June 2007 6 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary Typical Characteristics Figure3. DS2101 Ver 0.1 June 2007 Figure4. Figure5. Figure6 Figure7. Figure8. 7 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Figure9. DS2101 Ver 0.1 June 2007 EUA2101 Preliminary Figure10. Figure11. Figure12. Figure13. Figure14. 8 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUA2101 Figure15. DS2101 Ver 0.1 June 2007 9 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary EUA2101 Application Information Figure 16. DS2101 Ver 0.1 June 2007 10 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary Application Information (continued) Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker. When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter. Gain setting via GAIN0 and GAIN1 inputs The gain of the EUA2101 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±30% due to shifts in the actual resistance of the input resistors. For design purposes, the input network should be designed assuming an input impedance of 12.8kΩ, which is the absolute minimum input impedance of the EUA2101. At the lower gain settings, the input impedance could increase as high as 41.6 kΩ. Table.1 Gain Setting Figure.17 GAIN1 GAIN0 0 0 1 1 0 1 0 1 AMPLIFIER GAIN (dB) TYP 20 26 32 36 INPUT IMPEDANCE (kΩ) TYP 32 16 16 16 Input Resistance Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ ±30%, to the largest value, 32 kΩ ±30%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Figure.18 Figure.19 Using the LC filter in Figure.17, the EUA2101 EMI EVM passed the FCC Part 15 Class B radiated emissions with 21 inch speaker wires. Quasi-peak measurements were taken for 4 configurations, and the EUA2101 EMI EVM passed with at least a 5.6dB margin. DS2101 Ver 0.1 June 2007 The -3dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1. f = 1 2 πZ C i i ---------------- (1) 11 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary Input Capacitor, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in Equation 2. EUA2101 quivalent- series-resistance (ESR) ceramic capacitor, typically 0.1µF to 1µF placed as close as possible to the device VCC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220µF or greater placed near the audio power amplifier is recommended. The 220µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220µF or larger capacitor should be placed on each PVCC terminal. A 10µF capacitor on the AVCC terminal is adequate. BSN and BSP Capacitors 1 f = c 2 πZ C i i -----------------(2) The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. 1 C = i 2 πZ f i c -----------------(3) In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47µF as this value is commonly used. If the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network (CI) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly. Power Supply Decoupling, CS The EUA2101 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low DS2101 Ver 0.1 June 2007 The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220nF ceramic capacitor, rated for at least 25V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220nF capacitor must be connected from xOUTP to BSxx, and one 220nF capacitor must be connected from xOUTN to BSxx.( See application circuit diagram in Figure 16.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. VCLAMP Capacitors To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1µF capacitors must be connected from VCLAMPL (pin 30) and VCLAMPR (pin 31) to ground and must be rated for at least 16V. The voltages at the VCLAMP terminals may vary with VCC and may not be used for powering any other circuitry. Internal Regulated 4V Supply (VREG) The VREG terminal (pin 15) is the output of an internally generated 4V supply, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10nF capacitor, placed close to the pin, to keep the regulator stable. This regulated voltage can be used to control GAIN0, GAIN1, MSTR/ SLV , and MUTE terminals, but should not be used to drive external circuitry. VBYP Capacitor Selection The internal bias generator (VBYP) nominally provides a 1.25V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode 12 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary range of the input preamplifiers. The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance. During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4ms timer. When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV is equal to VBYP. For example, a 1µF capacitor on VBYP would take 5 ms to reach the value of VBYP and begin a 16.4ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1µF capacitor on the VBYP terminal. A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25V bias generator. A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors. The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level. The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 20. Differential Input The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the EUA2101 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the EUA2101 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. SHUTDOWN Operation The EUA2101 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage. MUTE Operation The MUTE pin is an input for controlling the output state of the EUA2101. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. DS2101 Ver 0.1 June 2007 Figure.20 MSTR/SLV and SYNC Operation The MSTR/ SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching. When the MSTR/ SLV terminal is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC terminal. The SYNC terminal becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to another EUA2101, configured in the slave mode. The output switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies. When the MSTR/ SLV terminal is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square wave from another EUA2101 configured in the master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200kHz to 300kHz for proper device operation, and the maximum amplitude is 4V. 13 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 Preliminary Using Low-ESR Capacitors Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. Short-Circuit Protection and Automatic Recovery Feature The EUA2101 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates. The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 20. Thermal Protection Thermal protection on the EUA2101 prevents damage to the device when the internal die temperature exceeds 160oC. There is a 10oC tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30oC. The device begins normal operation at this point with no external system interaction. DS2101 Ver 0.1 June 2007 EUA2101 Printed-Circuit Board (PCB) Layout Because the EUA2101 is a class-D amplifier that switches at a high frequency, the layout of the printedcircuit board (PCB) should be optimized according to the following guidelines for the best possible performance. z Decoupling capacitors— The high-frequency 1µF decoupling capacitors should be placed as close to the PVCC (pins 26, 27, 34, and 35) and AVCC (pin 48) terminals as possible. The VBYP (pin 16) capacitor, VREG (pin 15) capacitor, and VCLAMP (pins 30 and 31) capacitor should also be placed as close to the device as possible. Large (220µF or greater) bulk power supply decoupling capacitors should be placed near theEUA2101 on the PVCCL, PVCCR, and AVCC terminals. z Grounding— The AVCC (pin 48) decoupling capacitor, VREG (pin 15) capacitor, VBYP (pin 16) capacitor, and ROSC (pin 14) resistor should each be grounded to analog ground (AGND, pin 17). The PVCC decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 28, 29, 32, and 33). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the EUA2101. z Output filter— The ferrite EMI filter (Figure 19) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 17 and Figure 18) should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC filter should be placed first, following the outputs. z Thermal Pad— The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 5,1 mm by 5,1 mm. Five rows of solid vias (five vias per row, 0.3302mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. 14 联系电话：１５９９９６４４５７９ ８３１５１７１５ 芯美电子 EUA2101 Preliminary Package Information TQFN-48 Detail A SYMBOLS A A1 b E1 D D1 E e L DS2101 Ver 0.1 June 2007 MILLIMETERS MIN. MAX. 0.70 0.80 0.00 0.05 0.15 0.35 5.00 6.90 7.10 5.00 6.90 7.10 0.50 0.30 0.50 INCHES MIN. 0.028 0.000 0.006 MAX. 0.031 0.002 0.014 0.200 0.272 0.279 0.200 0272 0.279 0.020 0.012 0.020 15 联系电话：１５９９９６４４５７９ ８３１５１７１５