ETC EUA6201

芯美电子
EUA6201
1.25-W Mono Fully Differential
Audio Power Amplifier
DESCRIPTION
FEATURES
The EUA6201 is a mono fully-differential audio
amplifier, capable of delivering 1.25W of continuous
average power to an 8Ω BTL load with less than 1%
distortion (THD+N) from a 5V power supply, and
650mW to a 8Ω load from a 3.6V power supply.
The EUA6201 is ideal for PDA/smart phone application
due to features such as -80-dB supply voltage rejection
from 20Ha to 2kHz, improved RF rectification immunity,
small 20mm2 PCB area, and a fast startup with minimal
pop.
The EUA6201 is available in a MSOP-8 and in the
space-saving 3mm × 3mm DFN package.
z
z
z
z
z
z
Supply Voltage 2.5V to 5.5V
1.25W into 8Ω from a 5-V Supply at THD=1% (typ)
Low Supply Current: 4mA typ at 5V
Shutdown Current: 0.01µA typ
Fast Startup with Minimal Pop
Only Three External Components
- Improved PSRR (-80dB) for Direct Battery Operation
- Full Differential Design Reduces RF Rectification
- -63dB CMRR Eliminates Two Input Coupling
Capacitors
z RoHS Compliant and 100% Lead (Pb)-Free
APPLICATIONS
z Wireless Handsets
z PDAs
z Portable Devices
Typical Application Circuit
DS6201 Ver1.2
Oct. 2006
1
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芯美电子
EUA6201
Block Diagram
Pin Configurations
Package
Pin Configurations
DFN-8
MSOP-8
Pin Description
SYMBOL
PIN
Shutdown
Bypass
IN+
INVO+
VDD
GND
VO-
1
Shutdown terminal
2
3
4
5
6
7
8
Mid-supply voltage, adding a bypass capacitor improves PSRR
Positive differential input
Negative differential input
Positive BTL output
Power supply
High-current ground
Negative BTL output
DS6201 Ver1.2
Oct. 2006
DESCRIPTION
2
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芯美电子
EUA6201
Ordering Information
Order Number
Package Type
Marking
Operating Temperature range
EUA6201JIR1
DFN-8
xxxx
A6201
-40°C to 85°C
EUA6201MIR1
MSOP-8
xxxx
A6201
-40°C to 85°C
EUA6201
□ □ □ □
Lead Free Code
1: Lead Free 0: Lead
Packing
R: Tape & Reel
Operating temperature range
I: Industry Standard
Package Type
J: DFN
M: MSOP
DS6201 Ver1.2
Oct. 2006
3
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芯美电子
EUA6201
Absolute Maximum Ratings
▓
▓
▓
▓
▓
▓
Supply voltage, VDD
Input voltage, VI
--------------------------------------------------------------------------------------------
----------------------------------------------------------------------------
-0.3 V to VDD +0.3V
Storage temperature rang, Tstg ------------------------------------------------------------------ESD Susceptibility
Junction Temperature
6V
-65°C to 150°C
--------------------------------------------------------------------------------------------
2kV
--------------------------------------------------------------------------------------
150°C
------------------------------------------------------------------------------------------------
56°C/W
Thermal Resistance
θJC (MSOP)
θJA (MSOP)
------------------------------------------------------------------------------------------------ 160°C/W
θJA (DFN)
-------------------------------------------------------------------------------------------------- 50°C/W
Recommended Operating Conditions
MIN NOM MAX UNIT
Supply Voltage, VDD
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA
2.5
1.55
5.5
0.5
85
-40
V
V
°C
Electrical Characteristics, TA=25°C
Symbol
VOS
Parameter
Conditions
VI=0V differential, Gain=1V/V,
VDD=5.5V
Output offset voltage
(measured differentially)
PSRR Power supply rejection ratio
VIC
CMRR
IQ
I(SD)
VDD=2.5V to 5.5V
2
9
mV
-85
-60
dB
VDD-0.8
V
VDD=2.5V to 5.5V
Common mode rejection
range
VDD=2.5V, VIC=0.5V to 1.7V
-63
-40
VDD=5.5V, VIC=0.5V to 4.7V
-63
-40
RL=8Ω,
VIN+=VDD,
VIN+=0V,
Gain=1V/V
VIN-=0V or
VIN-=VDD
Gain=1V/V
RL=8Ω,
VIN+=VDD, VIN-=0V or
VIN-=VDD, VIN+=0V
High-output swing
|IIL|
-9
EUA6201
Unit
Typ Max.
Common mode input range
Low-output swing
|IIH|
Min
High-level input current,
Shutdown
Low-level input current,
Shutdown
Quiescent current
Supply current
2
0.45
0.37
0.26
4.95
3.18
2.13
V
0.4
V
58
100
µA
VDD=5.5V, VI=-0.3V
3
100
µA
VDD=2.5V to 5.5V, no load
4
8
mA
V( Shutdown )≤0.5V, VDD=2.5V to 5.5V,
RL= 8Ω
0.01
1
µA
40kΩ
RI
42kΩ
RI
V/V
RL= 8Ω
Resistance from shutdown to
GND
Oct. 2006
VDD=5.5V
VDD=3.6V
VDD=2.5V
VDD=5.5V
VDD=3.6V
VDD=2.5V
dB
VDD=5.5V, VI=5.8V
Gain
DS6201 Ver1.2
0.5
38kΩ
RI
100
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kΩ
芯美电子
EUA6201
Operating Characteristics, TA=25°C, Gain=1V/V
Symbol
PO
Parameter
Output power
Total harmonic distortion
THD+N
plus noise
KSVR
Supply ripple rejection
ratio
SNR
Signal-to-noise ratio
Vn
Output voltage noise
CMRR
RF
Common mode rejection
ratio
THD+N=1%, f=1kHz,RL=8Ω
DS6201 Ver1.2
Oct. 2006
VDD=5V
VDD=3.6V
VDD=2.5V
1.25
0.65
0.30
VDD=5V, PO=1W, RL=8Ω, f=1kHz
0.15
VDD=3.6V, PO=0.5W, RL=8Ω, f=1kHz
0.1
VDD=2.5V, PO=200mW, RL=8Ω, f=1kHz
VDD=3.6V,
f = 217Hz
Inputs ac-grounded
f=20Hz
with Ci=2µF,
to 20kHz
V(Ripple)=200mVpp
VDD=5V, PO=1W, RL=8Ω
No
VDD=3.6V, f=20Hz to 20kHz,
weighting
Inputs ac-grounded with
A
Ci=2µF
weighting
VDD=3.6V
f=217Hz
VIC=1Vpp
0.1
Feedback resistance
Start-up time from
shutdown
EUA6201
Unit
Min Typ Max.
Conditions
%
-77
dB
-60
100
dB
25
µVRMS
19
-64
38
VDD=3.6V, CBYPASS=0.1µF
W
40
dB
44
27
5
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kΩ
ms
芯美电子
EUA6201
Typical Operating Characteristics
OUTPUT POWER Vs. SUPPLY VOLTAGE
3.5
Po-Output Power - W
3.0
f=1KHz
Gain=1V/V
2.5
2.0
RL=8 ohm, THD=10%
1.5
RL=8 ohm, THD=1%
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD- Supply Voltage - V
DS6201 Ver1.2
Oct. 2006
6
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芯美电子
DS6201 Ver1.2
Oct. 2006
EUA6201
7
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芯美电子
DS6201 Ver1.2
Oct. 2006
EUA6201
8
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芯美电子
EUA6201
Application Information
Application Schematics
Figure14 through Figure15 show application schematics
for differential and single-ended inputs. Typical values
are shown in Table1.
Table1. Typical Component Value
Component
RI
C(BYPASS)
CS
CI
Value
40kΩ
0.22µF
1µF
0.22µF
Power Dissipation
Power dissipation is a major concern when designing a
successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased
power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. Since the
EUA6201 has two operational amplifiers in one package,
the maximum internal power dissipation is 4 times that of
a single-ended amplifier. The maximum power dissipation
for a given application can be derived from the power
dissipation graphs of from equation1.
PDMAX = 4 * (VDD ) 2 /(2π 2 R L ) ------------(1)
It is critical that the maximum junction temperature TJMAX
of 150°C is not exceeded. TJMAX can be determine from
the power derating curves by using PDMAX and the PC
board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced,
resulting in higher PDMAX. Additional copper foil can be
added to any of the leads connected to the EUA6201. If
TJMAX still exceeds 150°C, then additional changes must
be made. These changes can include reduced supply
voltage, higher load impedance, or reduced ambient
temperature. Internal power dissipation is a function of
output power.
Proper Selection of External Components
Gain-Setting Resistor Selection
The input resistor (RI) can be selected to set the gain of
the amplifier according to equation2.
Gain=RF/RI
(2)
The internal feedback resistors (RF) are trimmed to 40kΩ.
Resistor matching is very important in fully differential
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR,
PSRR, and the cancellation of the second harmonic
distortion diminishes if resistor mismatch occurs.
Therefore, it is recommended to use 1% tolerance
resistors or better to keep the performance optimized.
Bypass Capacitor (CBYPASS) and Start-up Time
The internal voltage divider at the Bypass pin of this
device sets a mid-supply voltage for internal references
and sets the output common mode voltage to VDD/2.
Adding a capacitor to this pin filters any noise into this
pin and increases kSVR. C(BYPASS) also determines the rise
time of VO+ and VO- when the device is taken out of
shutdown. The larger the capacitor, the slower the rise
time. Show the relationship of C(BYPASS) to start-up time as
Figure10.
DS6201 Ver1.2
Oct. 2006
9
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芯美电子
EUA6201
Input Capacitor (CI)
The EUA6201 does not require input coupling
capacitors if using a differential input source that is
biased from 0.5V to VDD -0.8V. Use 1% tolerance or
better gain-setting resistors if not using input coupling
capacitors.
In the single-ended input application an input capacitor,
CI, is required to allow the amplifier to bias the input
signal to the proper dc level. In this case, CI and RI form
a high-pass filter with the corner frequency determined
in equation3.
f
C
=
1
2π R C
I I
(3)
The value of CI is important to consider as it directly
affects the bass (low frequency) performance of the
circuit.
Consider the example where RI is 10kΩ and the
specification calls for a flat bass response down to
100Hz. Equation 3 is reconfigured as equation4.
1
C =
I 2π R f
I C
DS6201 Ver1.2
Oct. 2006
In this example, CI is 0.16µF, so one would likely
choose a value in the range of 0.22µF to 0.47µF.
Ceramic capacitors should be used when possible, as
they are the best choice in preventing leakage current.
When polarized capacitors are used, the positive side of
the capacitor should face the amplifier input in most
applications, as the dc level there is held at VDD/2, which
is likely higher than the source dc level. It is important to
confirm the capacitor polarity in the application.
Decoupling Capacitor (CS)
The EUA6201 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic distortion
(THD) is as low as possible. Power supply decoupling
also prevents oscillations for long lead lengths between
the amplifier and the speaker. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series-resistance (ESR) ceramic capacitor,
typically 0.1µF to 1 µF, placed as close as possible to the
device VDD lead works best. For filtering lower
frequency noise signals, a 10-µF or greater capacitor
placed near the audio power amplifier also helps, but is
not required in most applications because of the high
PSRR of this device.
(4)
10
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芯美电子
EUA6201
Package Information
DFN-8
NOTE
1. All dimensions are in millimeters, θ is in degrees
2. M: The maximum allowable corner on the molded plastic body corner
3. Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not
exceed 0.15mm per side
4. Dimension E does not include interterminal mold protrusions or terminal protrusions. Interminal mold
protrusions and/or terminal protrusions shall not exceed 0.20mm per side
5. Dimension b applies to plated terminals. Dimension A1 is primarily Y terminal plating, but may or may
not include a small protrusion of terminal below the bottom surface of the package
6. Burr shall not exceed 0.060mm
7. JEDEC MO-229
SYMBOLS
A
A1
A3
B
D
D1
E
E1
e
L
aaa
bbb
ccc
M
θ
DS6201 Ver1.2
Oct. 2006
MIN.
0.8
0
-----0.25
2.85
-----2.85
----------0.25
---------------------12
DIMENSIONS IN MILLIMETERS
NOM.
MAX.
0.9
1.00
0.015
0.03
0.20 REF
-----0.30
0.37
3.00 BSC
3.15
2.3 BSC
-----3.00 BSC
3.15
1.5 BSC
-----0.65 BSC
----0.35
0.45
0.25
-----0.10
-----0.10
----------0.05
-----0
11
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芯美电子
EUA6201
MSOP-8
NOTE
1. Package body sizes exclude mold flash and gate burrs
2. Dimension L is measured in gage plane
3. Tolerance 0.10mm unless otherwise specified
4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
SYMBOLS
A
A1
A2
b
C
D
E
E1
e
L
y
θ
DS6201 Ver1.2
Oct. 2006
DIMENSIONS IN MILLIMETERS
MIN.
NOM.
MAX.
0.81
0.95
1.10
0.05
0.09
0.15
0.76
0.86
0.97
0.28
0.30
0.38
0.13
0.15
0.23
2.90
3.00
3.10
4.70
4.90
5.10
2.90
3.00
3.10
-----0.65
----0.40
0.53
0.66
----------0.10
0
-----6
DIMENSIONS IN INCHES
MIN.
NOM.
MAX.
0.032
0.0375
0.043
0.002
0.004
0.006
0.030
0.034
0.038
0.011
0.012
0.015
0.005
0.006
0.009
0.114
0.118
0.122
0.185
0.193
0.201
0.114
0.118
0.122
-----0.026
-----0.016
0.021
0.026
----------0.004
0
-----6
12
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