ETC CXD3172AR

CXD3172AR
Signal Processor LSI for Single CCD Color Camera
Description
The CXD3172AR is a signal processor LSI for Ye,
Cy, Mg and G single CCD color cameras. In addition
to basic camera signal processing functions, it
includes an AE/AWB detection circuit, a sync signal
generation circuit and an external sync circuit, etc.
This chip also has a built-in microcontroller to realize
basic camera functions such as AE/AWB without an
external microcomputer.
Features
• Generates timing pulses to drive the single CCD
image sensor
Built-in H/V driver for CCD image sensor
Luminance/chroma signal processing
• Supports NTSC/PAL modes
• Supports 510H/760H system CCD image sensor
• Built-in 10-bit A/D converter
• Built-in EVR (3ch)
• Analog composite output
— Built-in digital encoder
— 10-bit D/A converter output
• Digital output
— Conforms to ITU-REC656/ITU-REC601 format
• Supports external sync functions
— Sync separation circuit
— Phase comparator
• AE/AWB detector
• Block control functions with a built-in microcontroller
— AE/AWB/CLAMP/Blemish detection and
compensation
• Peripheral IC control function
— EVR/EEPROM communication control
• Serial communication function (2 mode selection)
— Microcomputer communication/start-stop
synchronous system communication (RS232C)
• Auto blemish detection and compensation function
• Mirror function
Applications
• Industrial CCD cameras
(Surveillance/FA/image input cameras)
• Multimedia CCD cameras
(Teleconferencing/personal computer cameras)
100 pin LQFP (Plastic)
Absolute Maximum Ratings
VSS – 0.5 to +4.6
V
• Supply voltage VDD
AVD
VSS – 0.5 to +4.6
V
VH
VL – 0.5 to VL + 26.0 V
VM
VL – 0.5 to VL + 26.0 V
• Input voltage
VI
VSS – 0.5 to VDD + 0.5 V
• Output voltage VO
VSS – 0.5 to VDD + 0.5 V
• Operating Temperature
Topr
–20 to +75
°C
• Storage Temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage VDD
3.0 to 3.6
AVD1, 3, 4, 5, 6
3.0 to 3.6
AVD2
3.0 to 5.5
VH
11.64 to 15.45
VL
–7.5 to –4.5
VM
0
• Operating Temperature
Topr
–20 to +75
V
V
V
V
V
V
°C
Applicable CCD Image Sensors∗
• 510H color CCDs
(Type 1/3, 1/4, NTSC/PAL)
• 760H color CCDs
(Type 1/3, 1/4, NTSC/PAL)
Supported
AGC
EVR
EEPROM
Relates LSIs
CXA2096N
MB88347 (Fujitsu Limited.)
AK6480A
(Asahi Kasei Microsystems Co.,Ltd.)
BR9080A (ROHM)
∗ Applicable CCD image sensors are applicable
products as of preparing this data sheet.
They may be changed according to the version up
and production stop of CCD image sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04643-PS
Block Diagram
CXD3172AR
PRE
CXA2096N
CDS
AGC
A/D
PG
1HDL
OB
INT
1HDL
NOSYNC_Y
ADDR
CMP
1HDL
A/D
AGCCONT
CCD
ENC
BLEMISH COMP
DL1
DL2
DL3
DEF
DET
Y
E_Y
DEF
COR
E_RY
SYNC_Y
BLK
SYNC YCMIX
LPF
YOUT
D/A
IOY
YCMIX
RY
ADDR
STOR
BST
BY MOD
E_BY
HV
CNT
COUT
D/A
IOC
DL1
DL2
DL3
DL3
DL2
DL1
MCK
CKGEN
DL13
Ypocess
SFC
HL
APC
RES
ENH
DIF
SFC
ENC
VH
APC
APC
MIX
HLAPC
GAIN
LPF
GAM
GAIN
SFC
DIF
WCLP
MSK
DADJ
DCK
D_YO
REC601 (Y) or REC656
D_CO
REC601 (C)
REC656
REC601
D_Y
D_RY
D_BY
–2–
INTERNAL BUS
OPD
Cprocess
SYS
MAN
WIND
GEN
Y_INTG
LPF
REF
GATE
RGB
MTX
WB
GAM
INIT
PORT
DR
SG
AWB
CLMP
YC
SPRS
AE
BLEMISH
COMP
LN
MTX
RGB_CNT
RGB_INTG
PERI
MCRCON
EXT-SIF
• RS232C
• MicroCOM
CAM-SIF
• EEPROM
• EVR
CSROM/CSEVR
CASI/CASO/CASCK
SG
PLL
VCO
PCK
TG
V-Dr
PHASE
COMP
ref
var
REF/VAR
SEL
SYNC
GEN
FSC
PHASE
COMP
MASTER
HD GEN
HD/VD
SEP
XCS
SI
SO
SOK
EEPROM
EVR
EX-SYNC
SYNC/BST
SEP
EX-BST
EVR
(3ch)
TGHD/TGVD
CPOUT
VCTRLIN
CCU MODE PLL
LPF
ECK
X'tal
ESCI/ESCO
EXT-VIDEO
CXD3172AR
SCOMP
PCOMP
CXD3172AR
PCK
AVS4
VCTRLIN
CPOUT
AVD4
AVD5
EXVIDEOY
EXVIDEO
AVS5
BIAS
TEST2
TEST3
EVR0
EVR1
AVS6
EVR2
IOC
VREFC
VGC
IREFC
IREFY
VGY
VREFY
AVD6
IOY
Pin Configuration
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P8 (YO8) 76
50 SVD1
P9 (YO9) 77
49 S4
P10 (YO10) 78
48 S3
P11 (YO11) 79
47 S2
P12 (YO12) 80
46 S1
VSS3 81
45 VDD2
P13 (YO13) 82
44 S0
P14 (YO14) 83
43 MCK
P15 (YO15) 84
42 PCOMP
VDD3 85
41 PBLK
ESCI 86
40 CLPOB
ESCO 87
39 CLPDM
ECK 88
38 VSS2
VSS4 89
37 VL
DCK 90
36 SUB
P0 (CO0) 91
35 V1
P1 (CO1) 92
34 VH
P2 (CO2) 93
33 V3
P3 (CO3) 94
32 V2
XRS
AVS2
H2
H1
AVD2
RG
REFC
SO (TXD)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SCK (XRTS)
8
SI (RXD)
7
XCS (XCTS)
6
VDD1
5
SIFSEL
4
XRST
3
TEST1
2
VSS1
1
CASCK
26 AVS3
CASI
27 XSHD
SVD2 100
CASO
P7 (CO7) 99
VRB
28 XSHP
CSROM
29 AVD3
P6 (CO6) 98
VIN
P5 (CO5) 97
AVS1
30 VM
VRT
31 V4
AVD1
VDD4 95
P4 (CO4) 96
Note) Symbols in parentheses are the signal names when the function is switched
by the communication parameter settings.
–3–
CXD3172AR
Pin Description
Pin
No.
Symbol
I/O
Description
1
VRT
I
2
AVD1
—
3
VIN
4
AVS1
—
5
VRB
I
A/D converter reference voltage (bottom) input.
6
CSROM
O
Chip select output for camera peripheral ICs. (to EEPROM)
7
CASI
I
Serial data input for system communication.
8
CASO
O
Serial data output for system communication.
9
CASCK
O
Serial clock output for system communication.
10
VSS1
—
GND
11
XRST
I
Reset input.
12
TEST1
I
Test
13
SIFSEL
I
Serial interface mode switching. 0: microcomputer (3 wires) 1: RS232C
14
VDD1
—
15
XCS
I
Chip select input for 3 wires serial interface. (Clear to Send)
16
SI
I
Serial data input for 3 wires serial interface. (Received Data)
17
SO
O
Serial data output for 3 wires serial interface. (Transmitted Data)
18
SCK
19
RG
O
Reset gate pulse output.
20
REFC
I
Capacitor connection.
21
AVD2
—
Power supply for horizontal driving pulse. (3.3V/5.0V)
22
H1
O
CCD horizontal register transfer pulse output.
23
H2
O
CCD horizontal register transfer pulse output.
24
AVS2
—
GND
25
XRS
O
Resampling pulse output.
26
AVS3
—
GND
27
XSHD
O
Data sample-and-hold pulse output.
28
XSHP
O
Precharge level sample-and-hold pulse output.
29
AVD3
—
Power supply for sample-and-hold pulse.
30
VM
—
V-Driver Middle level power supply.
31
V4
O
CCD vertical register transfer pulse output.
32
V2
O
CCD vertical register transfer pulse output.
33
V3
O
CCD vertical register transfer pulse output.
34
VH
—
V-Driver High level power supply.
35
V1
O
CCD vertical register transfer pulse output.
36
SUB
O
CCD electronic shutter pulse output.
37
VL
—
V-Driver Low level power supply.
I
Power supply
A/D converter reference voltage (top) input.
Power supply for A/D converter.
Analog signal input. (for A/D converter)
AVD1
AVS1
GND
VDD1
VSS1
Power supply for logic.
I (O) Serial clock input for 3 wires serial interface. (Request to Send)
–4–
AVD2
AVS2
AVD3
AVS3
VH
VL
VM
CXD3172AR
Pin
No.
Symbol
I/O
Description
38
VSS2
—
GND
39
CLPDM
O
Dummy data clamp pulse output.
40
CLPOB
O
Optical black clamp pulse output.
41
PBLK
O
Preblanking pulse output.
42
PCOMP
O
Phase comparator output.
43
MCK
I
System drive clock input.
44
S0
I/O
Sync signal input/output 0.
45
VDD2
—
Power supply for logic.
46
S1
I/O
Sync signal input/output 1.
47
S2
I/O
Sync signal input/output 2.
48
S3
I/O
Sync signal input/output 3.
49
S4
O
Sync signal output.
50
SVD1
—
Sub power supply.
51
PCK
O
PLL clock output.
52
AVS4
—
GND
53
VCTRLIN
I
Built-in VCO input.
54
CPOUT
O
Built-in charge pump output.
55
AVD4
—
Analog power supply for PLL.
56
AVD5
—
Power supply for burst separator.
57
EXVIDEOY
I
Y signal input for external synchronization.
58
EXVIDEO
I
Video signal input for external synchronization.
59
AVS5
—
60
BIAS
I
Bias current source.
61
TEST2
I
Test
62
TEST3
I
Test
63
EVR0
O
EVR0 analog output.
64
EVR1
O
EVR1 analog output.
65
AVS6
—
GND
66
EVR2
O
EVR2 analog output.
67
IOC
O
Analog chroma output.
68
VREFC
I
Reference voltage setting. (for chroma signal D/A converter)
69
VGC
I
Capacitor connection. (approx. 0.1µF) (for chroma signal D/A converter)
70
IREFC
I
Reference current setting. (for chroma signal D/A converter)
71
IREFY
I
Reference current setting. (for luminance signal D/A converter)
72
VGY
I
Capacitor connection. (approx. 0.1µF) (for luminance signal D/A converter)
73
VREFY
I
Reference voltage setting. (for luminance signal D/A converter)
74
AVD6
—
Power supply for DA converter/EVR.
75
IOY
O
Analog Y output/compostite video output.
–5–
Power supply
VDD2
VSS2
AVD4
AVS4
AVD5
AVS5
GND
AVD6
AVS6
CXD3172AR
Pin
No.
Symbol
I/O
Description
76
P8 (YO8)
I/O
Port 8 input or Y digital signal output or YUV digital signal output.
77
P9 (YO9)
I/O
Port 9 input or Y digital signal outout or YUV digital signal output.
78
P10 (YO10)
I/O
Port 10 input or Y digital signal outout or YUV digital signal output.
79
P11 (YO11)
I/O
Port 11 input or Y digital signal outout or YUV digital signal output.
80
P12 (YO12)
I/O
Port 12 input or Y digital signal outout or YUV digital signal output.
81
VSS3
—
GND
82
P13 (YO13)
I/O
Port 13 input or Y digital signal outout or YUV digital signal output.
83
P14 (YO14)
I/O
Port 14 input or Y digital signal outout or YUV digital signal output.
84
P15 (YO15)
I/O
Port 15 input or Y digital signal outout or YUV digital signal output.
85
VDD3
—
Power supply.
86
ESCI
I
Oscillation cell input.
87
ESCO
O
Oscillaton cell output.
88
ECK
I
Encoder clock input.
89
VSS4
—
GND
90
DCK
O
Clock output for digital output.
91
P0 (CO0)
I/O
Port 0 input or C digital signal output.
92
P1 (CO1)
I/O
Port 1 input or C digital signal output.
93
P2 (CO2)
I/O
Port 2 input or C digital signal output.
94
P3 (CO3)
I/O
Port 3 input or C digital siganl output
95
VDD4
—
Power supply.
96
P4 (CO4)
I/O
Port 4 input or C digital signal output or EEEPROM BUSY
signal input or OPD frame pulse output.
97
P5 (CO5)
I/O
Port 5 input or C digital signal output or VD output.
98
P6 (CO6)
I/O
Port 6 input or C digital signal output or HD output.
99
P7 (CO7)
I/O
Port 7 input or C digital signal output.
100
SVD2
—
Sub power supply.
–6–
Power supply
VDD3
VSS3
VDD4
VSS4
CXD3172AR
Electrical Characteristics
DC Characteristics
(Within recommended operating range)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
3.0
3.3
3.6
V
AVD2
3.0
—
5.5
V
AVD3, 4, 5
3.0
3.3
3.6
V
3.0
3.3
3.6
V
—
3.3
—
V
VH
11.64
—
15.45
V
VL
–7.5
—
–4.5
V
VM
—
0
—
V
VDD1, 2, 3, 4
AVD1
Supply voltage 1
AVD6
Supply voltage 2
Supply voltage 3
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output voltage 5
Input voltage
Hysteresis
Input leak current
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
∗9
D/A output amplitude = 1Vp-p
SVD1, 2
VOH1 ∗1
IOH = 1.0mA
∗1
IOL = 1.0mA
VOL1
VOH2 ∗2, ∗3
VOL2 ∗2, ∗3
VOH3 ∗4
VOL3 ∗4
VOH4 ∗5
IOH = 4.0mA
IOH = 12.0mA
IOH = 4.0mA
IOL = 5.4mA
IOH = 5.0mA
VOM62 ∗7
VOL6 ∗7
0.4
VDD – 0.4
IOH = 7.2mA
0.4
VDD/2
VDD/2
VH – 0.25
VL + 0.25
VM – 0.25
VH – 0.25
V
V
VM + 0.25
VM – 0.25
V
V
VL + 0.25
0.7VDD
V
V
0.2VDD
0.5
100
S0, S1, S2, S3, P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15
CSROM, CASO, CASCK, SO, CLPDM, CLPOB, PBLK, S4, PCK, DCK
SCK
ESCI, ESCO
SUB
V2, V4
V1, V3
CASI, XRST, SIFSEL, XCS, SI, TEST2, TEST3
TEST1
–7–
V
V
VL + 0.25
40
V
V
IOL = 10.0mA
VIN = VDD
V
V
IOL = 5.0mA
IOH = 5.0mA
V
V
IOL = 10.0mA
VT+ ∗1, ∗3, ∗8
VT– ∗1, ∗3, ∗8
VT+ – VT– ∗1, ∗3, ∗8
IIH ∗8
V
IOL = 12.0mA
VOH5 ∗6
VOL5 ∗6
VOH6 ∗7
VDD – 0.4
IOL = 4.0mA
VOL4 ∗5
VOM61 ∗7
Output voltage 6
A/D input amplitude = 1Vp-p
V
V
240
µA
CXD3172AR
I/O Pin Capacitance
Item
(VDD = VI = 0V, f = 1MHz)
Symbol
Min.
Typ.
Max.
Unit
Input pin capacitance
CIN
9
pF
Output pin capacitance
COUT
11
pF
I/O pin capacitance
CI/O
11
pF
AC Characteristics
Classification
Reset input
Digital output
SYNC block
sync output
Serial
communication
I/O
(Within recommended operating range)
Item
Symbol
Min.
Typ.
Max.
Unit
500
—
—
ns
Min. low time of reset operation of XRST pin
TwRST
P0 to P15 output delay time against DCK ↑
TpdP
5
—
20
ns
S0 output delay time against DCK ↑
TpdS0
6
—
28
ns
S1 output delay time against DCK ↑
TpdS1
6
—
30
ns
DCK output delay time against ECK ↑
TpdDCK
7
—
24
ns
HD, VD, FLD and SYNC output delay time
against ECK ↑
TpdSY
10
—
45
ns
SCK input pulse width (High period)
TwHSCK
—
580
—
ns
SCK input pulse width (Low period)
TwLSCK
—
580
—
ns
XCE input setup time against SCK ↓
TsuXCE
580
—
—
ns
XCE input hold time against SCK ↑
ThXCE
580
—
—
ns
SI input setup time against SCK ↑
TsuSI
0
—
—
ns
SI input hold time against SCK ↑
ThSI
0
—
—
ns
SO output transit time against XCE ↓
(Hi-Z → Data active)
TzdSO
0
—
—
ns
SO transit time against XCE ↑
(Data active → Hi-Z)
TdzSO
0
—
—
ns
SO output delay time against SCK ↓
TpdSO
—
—
580
ns
–8–
CXD3172AR
AC Characteristics diagram
1. Reset input
TwRST
XRST
2. DCK output
TpdDCK
DCK
ECK
TpdP
TpdS0
TpdS1
3. Digital output
P0 to P15
S0 (DHD)
S1 (DVD)
DCK
4. SYNC block output
TpdSY
HD, VD
FLD, SYNC
ECK
5. Serial communication I/O
TsuXCE
ThXCE
XCE
TwLSCK TwHSCK
SCK
TzdSO
TpdSO
TdzSO
SO
TsuSI ThSI
SI
–9–
CXD3172AR
Relationship between MODESEL and Each Clock
TV
system
CCD
type
510H
NTSC
760H
510H
PAL
760H
MODESEL
ECK
MCK
0
38.13986MHz
(ECK = MCK)
1
28.63636MHz
2
27.00000MHz
6
28.63636MHz
(ECK = MCK)
8
27.00000MHz
28.63636MHz
3
37.87500MHz
(ECK = MCK)
4
35.46895MHz
5
27.00000MHz
9
28.37500MHz
A
35.46895MHz
B
27.00000MHz
38.13986MHz
37.87500MHz
DSPCK∗1
ECK and MCK are connected internally.
MCK/4
MCK/2
ECK and MCK are connected internally.
ECK and MCK are connected internally.
MCK/4
(ECK = MCK)
28.37500MHz
Remarks
ECK and MCK are connected internally.
MCK/2
∗1 DSPCK: clock which is not output by external pins
See the above table for the relationship between encoder clock (ECK) and system drive clock (MCK).
– 10 –
Vertical Timing Chart
MODESEL 0, 1, 2 [510H NTSC]
Applicable CCD image sensor:
ICX206AK/226AK/254AK/404AK
ODD
EVEN
...
18 (280)
12 (274)
9 (271)
10 (272)
EVSUBV setting value∗2
261
0
1
2
3
4
5
6
7
8
9
ODSUBV setting value∗2
250
251
252
253
254
255
256
257
258
259
260
...
2 (264)
261
0 (262)
1 (263)
17
13
6
8
9
10
ODSUBV setting value∗2
261
262
...
250
251
252
253
254
255
256
257
258
259
260
EVSUBV setting value∗2
0
1
2
3
4
5
6
7
FLD
262 (524)
0
1
2
HD
258 (520)
VD
...
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ODSGV setting value∗2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SUB
EVSGV setting value∗2
V1
V3
CCD OUT
1 3 5 7 9 11 1 3 5
2 4 6 8 10 12 2 4 6
487
488 489
490 491
492
V4
487 488
489 490
491 492
– 11 –
V2
2 4 6 8 10 12 2 4 6
1 3 5 7 9 11 1 3 5
PBLK
CLPOB
CLPDM
CXD3172AR
The shaded area shows the position variable range of the read SG pulse. However, note that the range may over depending on the setting.
∗2 The value changes by the parameter (Category6: TG) setting.
Vertical Timing Chart
MODESEL 3, 4, 5 [510H PAL]
Applicable CCD image sensor:
ICX207AK/227AK/255AK/405AK
ODD
EVEN
...
...
22 (334)
18 (330)
13 (325)
ODSUBV setting value∗3
EVSUBV setting value∗3
311
0
1
2
3
4
5
6
7
8
9
311
312
0
1
2
3
4
5
6
7
8
ODSUBV setting value∗3
9 (321)
10 (322)
311
0 (312)
1 (313)
2 (314)
21
13
6
8
9
10
309
310
...
298
299
300
301
302
303
304
305
306
307
308
EVSUBV setting value∗3
297
298
299
300
301
302
303
304
305
306
307
308
309
310
FLD
312 (624)
0
1
2
HD
208 (520)
VD
...
ODSGV setting value∗3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SUB
EVSGV setting value∗3
V1
V3
CCD OUT
1 3 5 7 9 11 13 1 3 5
2 4 6 8 10 12 14 2 4 6
577
578 579
580 581
582
V4
577 578
579 580
581 582
– 12 –
V2
2 4 6 8 10 12 14 2 4 6
1 3 5 7 9 11 13 1 3 5
PBLK
CLPOB
CLPDM
CXD3172AR
The shaded area shows the position variable range of the read SG pulse. However, note that the range may over depending on the setting.
∗3 The value changes by the parameter (Category6: TG) setting.
Vertical Timing Chart
MODESEL 6, 8 [760H NTSC]
Applicable CCD image sensor:
ICX228AK/258AK/278AK/408AK
ODD
EVEN
17 (279)
11 (273)
12 (274)
9 (271)
2 (264)
261
0 (262)
1 (263)
16
13
8
9
10
6
262 (524)
0
1
2
HD
258 (520)
VD
FLD
ODSUBV setting value∗4
...
EVSUBV setting value∗4
261
0
1
2
3
4
5
6
7
8
9
...
250
251
252
253
254
255
256
257
258
259
260
0
1
2
3
4
5
6
7
ODSUBV setting value∗4
261
262
250
251
252
253
254
255
256
257
258
259
260
EVSUBV setting value∗4
...
...
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ODSGV setting value∗4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SUB
EVSGV setting value∗4
V1
V3
CCD OUT
1 3 5 7 9 11 1 3 5
2 4 6 8 10 12 2 4 6
487
488 489
490 491
492 493
494
V4
489 490
491 492
493 494
– 13 –
V2
2 4 6 8 10 12 2 4 6
1 3 5 7 9 11 1 3 5
PBLK
CLPOB
CLPDM
CXD3172AR
The shaded area shows the position variable range of the read SG pulse. However, note that the range may over depending on the setting.
∗4 The value changes by the parameter (Category6: TG) setting.
Vertical Timing Chart
MODESEL 9, A, B [760H PAL]
Applicable CCD image sensor:
ICX229AK/259AK/279AK/409AK
ODD
EVEN
...
...
22 (334)
16 (328)
14 (326)
12 (324)
10 (322)
6 (318)
ODSUBV setting value∗5
EVSUBV setting value∗5
311
0
1
2
3
4
5
6
7
8
9
311
312
0
1
2
3
4
5
6
7
8
ODSUBV setting value∗5
2 (314)
311
0 (312)
1 (313)
21
14
6
8
9
10
309
310
...
296
297
298
299
300
301
302
303
304
305
306
307
308
EVSUBV setting value∗5
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
FLD
312 (624)
0
1
2
HD
208 (520)
VD
...
ODSGV setting value∗5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SUB
EVSGV setting value∗5
V1
V3
CCD OUT
1 3 5 7 9 11 1 3 5
2 4 6 8 10 12 2 4 6
577
578 579
580 581
582
V4
577 578
579 580
581 582
– 14 –
V2
2 4 6 8 10 12 2 4 6
1 3 5 7 9 11 1 3 5
PBLK
CLPOB
CLPDM
CXD3172AR
The shaded area shows the position variable range of the read SG pulse. However, note that the range may over depending on the setting.
∗5 The value changes by the parameter (Category6: TG) setting.
Horizontal Timing Chart
Applicable CCD image sensor:
ICX206AK/226AK/254AK/404AK
MODESEL 0, 1, 2 [510H NTSC] DSPCK: 606fH (9.534965MHz: 104.88ns)
(606)
0
50
100
120
150
63
HD
DSPCK∗6
10
36
88
104 106
H1
H2
Back OB: 25ck
Blank: 53ck
42
V1
– 15 –
V4
66
48
78
65
SUB
82
34
PBLK
CLPDM
72
36
V3
CLPOB
60
54
V2
Dummy: 16ck
11
103
34
89
103
CXD3172AR
∗6 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
Horizontal Timing Chart
MODESEL 3, 4, 5 [510H PAL] DSPCK: 606fH (9.46875MHz: 105.60ns)
(606)
0
50
Applicable CCD image sensor:
ICX207AK/227AK/255AK/405AK
100
120
150
64
HD
DSPCK∗7
10
93
41
109
116
H1
H2
Back OB: 30ck
Blank: 53ck
47
V1
– 16 –
71
83
53
V4
70
SUB
87
108
39
PBLK
CLPDM
77
41
V3
CLPOB
65
59
V2
Dummy: 16ck
11
39
94
108
CXD3172AR
∗7 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
Horizontal Timing Chart
MODESEL 6, 8 [760H NTSC] DSPCK: 910fH (14.31818MHz: 69.84ns)
(910)
0
50
Applicable CCD image sensor:
ICX228AK/258AK/278AK/408AK
100
120
150
63
HD
DSPCK∗8
10
51
127
149
152
H1
H2
Back OB: 40ck
Blank: 77ck
60
V1
87
105
78
V2
– 17 –
96
51
V3
69
V4
114
95
SUB
121
49
PBLK
CLPOB
Dummy: 22ck
11
148
49
128
CLPDM
CXD3172AR
∗8 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
148
Horizontal Timing Chart
MODESEL 9, A, B [760H PAL] DSPCK: 908fH (14.1875MHz: 70.48ns)
(908)
0
50
100
Applicable CCD image sensor:
ICX229AK/259AK/279AK/409AK
120
150
170
63
HD
DSPCK∗9
10
51
141
163 166
H1
H2
Back OB: 40ck
Blank: 91ck
V1
60
87
V2
– 18 –
114
69
SUB
95
PBLK
CLPDM
96
51
V4
CLPOB
105
78
V3
Dummy: 22ck
121
162
49
11
49
142
CXD3172AR
∗9 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
162
Horizontal Timing Chart
Odd Field
(606)
0
MODESEL 0, 1, 2 [510H NTSC]
Applicable CCD image sensor:
ICX206AK/226AK/254AK/404AK
(606)
0
(606)
0
HD
(13)
(37)
{0}
{96}
{48}
[0]
[18]
V1
48
(0)
[12] [30]
(94)
V2
(51)
(75)
[24]
(3)
V3
[6]
[36]
V4
– 19 –
Even Field
10
(606)
0
24
14
24
19
(606)
0
(606)
0
HD
(13)
(37)
{0}
{48}
{96}
[0]
V1
(0)
[30]
V2
(51)
(75)
[24]
(3)
V3
(94)
[36]
V4
CXD3172AR
The shaded pulse area shifts while keeping the relative position relationship during shutter setting.
Horizontal Timing Chart
Odd Field
(606)
0
MODESEL 3, 4, 5 [510H PAL]
Applicable CCD image sensor:
ICX207AK/227AK/255AK/405AK
(606)
0
(606)
0
HD
(13)
{0}
(37)
{96}
{48}
[0]
[18]
V1
48
(0)
[12] [30]
(94)
V2
(51)
(75)
[24]
(3)
V3
[36]
[6]
V4
– 20 –
Even Field
10
(606)
0
24
14
24
19
(606)
0
(606)
0
HD
(13)
{0}
(37)
{48}
{96}
V1
(0)
[30]
V2
(51)
(75)
(3)
[24]
V3
(94)
[36]
V4
CXD3172AR
The shaded pulse area shifts while keeping the relative position relationship during shutter setting.
Horizontal Timing Chart
MODESEL 6, 8 [760H NTSC]
Applicable CCD image sensor:
ICX228AK/258AK/278AK/408AK
Odd Field
(910)
0
(910)
0
(910)
0
HD
(26)
{64}
[0]
{0}
(62)
{128}
[8]
[35]
V1
72
(0)
(170)
[26] [53]
V2
(98)
(134)
[44]
(3)
V3
[62]
[17]
V4
– 21 –
23
36
36
36
36
Even Field
(910)
0
(910)
0
(910)
0
HD
(26)
(62)
{0}
{64}
[0]
{128}
V1
[53]
(0)
V2
(98)
(134)
[44]
(3)
V3
V4
(170)
CXD3172AR
The shaded pulse area shifts while keeping the relative position relationship during shutter setting.
[62]
Horizontal Timing Chart
MODESEL 9, A, B [760H PAL]
Applicable CCD image sensor:
ICX229AK/259AK/279AK/409AK
Odd Field
(908)
0
(908)
0
(908)
0
HD
(25)
(62)
{64}
[0]
{0}
{128}
[8]
[35]
V1
72
(0)
[26] [53]
(173)
V2
(99)
(136)
[44]
(3)
V3
[62]
[17]
V4
– 22 –
22
37
37
37
37
Even Field
(908)
0
(908)
0
(908)
0
HD
(25)
(62)
{0}
{64}
[0]
{128}
V1
(0)
[53]
V2
(99)
(136)
(3)
[44]
V3
V4
(173)
CXD3172AR
The shaded pulse area shifts while keeping the relative position relationship during shutter setting.
[62]
High-speed waveform pulse
MODESEL 0, 1, 2, 3, 4, 5 [510H NTSC/PAL]
Applicable CCD image sensor:
ICX206AK/226AK/254AK/404AK
ICX207AK/227AK/255AK/405AK
HD
MCK
1
36/41
88/93
DSPCK∗10
H1
– 23 –
H2
RG
XSHP
XSHD
XRS
∗10 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output, a delay is added to each pulse.
∗ High-speed pulse pin setting shown above indicates the state of initial setting (delay, duty) of the parameter (Category 6: TG)
CXD3172AR
High-speed waveform pulse
MODESEL 6, 8, 9, A, B [760H NTSC/PAL]
Applicable CCD image sensor:
ICX228AK/258AK/278AK/408AK
ICX229AK/259AK/279AK/409AK
HD
MCK
1
51/51
127/141
DSPCK∗11
H1
– 24 –
H2
RG
XSHP
XSHD
XRS
∗11 DSPCK is a clock which is not output by external pins. See the previously described table (Relationship between MODESEL and Each Clock).
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output, a delay is added to each pulse.
∗ High-speed pulse pin setting shown above indicates the state of initial setting (delay, duty) of the parameter (Category 6: TG)
CXD3172AR
CXD3172AR
Package Outline
Unit: mm
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗ 14.0 ± 0.1
75
51
76
50
(15.0)
B
26
100
1
0.5 ± 0.2
A
(0.22)
25
0.5
b
0.13 M
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0.5 ± 0.2
0˚ to 10˚
0.125 ± 0.04
b = 0.18 ± 0.03
DETAIL B : PALLADIUM
NOTE: Dimension "∗" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
LQFP-100P-L01
P-LQFP100-14x14-0.5
JEDEC CODE
– 25 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
PALLADIUM PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.7g
Sony Corporation