l)CL Pro LOgic 页码 ,l/灶 ECL Logft;; ECL Pro栩 Logic ECLi"P$:蚺 Lo旬 J￠ ECL Pro 彳卩 ;Υ ;Υ Di矸 erenⅡ aI2ˉ 6V c inDut XOR/XNOR 1iqh-speed Diferenual Receiver ;Υ 10EP31VⅡ EW 5V/33V D FilDˉ FIoD W"h set and Rrset 5V`33VDF"Dˉ FloD with Rrset And DifferenfaI CIock sY10EP51VNEW sΥ 10EP52V拊 EW sΥ 10EP53VNEW sΥ 10EP58V sΥ 10EP89V衬 5V/33VD矸erentiaI Data and Clock D FilD-FIoD 5V/3.3V Di仟 erenual Data and CIock D FiID-FlOD、 Ⅳ "h set And Reset 5V/33V2H Mu"Dlexer FW sΥ 10'100EP11uN蛋 5V/3.3V3GHz CoaxiaI Cab丨 W W eD"ver 25V/3,3V/5V1∶ 2Differential PECL/LVPECL/ECL Fanout Bu仟 er sΥ 10`100EP32V肘 ε 2.5V/3.3V÷ 2Divider sΥ 10'100EP33VNEW sΥ 10`100EPT28L 2,5V/3.3V÷ 4Divider )3V/5VLVΠ L/LVCMOs-to-Differen刂 al LVPECL TranslatOr 3V LVTTLˉ toˉ Di矸 eren刂 aI LVPECL and Di矸 erenual LVPECLˉ to-LVTTL TransIator sΥ 100EP111V 25V/33V1∶ 10Di仟 eren"al LVPECL/LVECL/HsTL Clock D"Ver sY100EP140LNEW ).3V PECL/ECL Di矸 eren"al Phaseˉ Frequencv Detector ⒉5V/33V/5V1∶ 5LVPEC凵 PEC凵 ECL/HsTL2GHz Clock Driver with2∶ sV10"00EPT20V 100EP14uⅡ 臣w sΥ 100EP16VsNε W sΥ 100EP210u树 Ew sΥ 5∨ /3~3V2.5Gbps 1Di矸 erenⅡ a"nput Mux Va"abIe Output swing DmbrenuaI Receiver 25V/33V DuaI1∶ 5Di仃 erenⅡ al LVECL/LVPECL`HSTL CloCk D"Ver ;3V/5V PECL/ECL3GHz Dual Di仟 erenuaI2∶ 1M0Ⅲ pleXer 33V/5V PECL/ECL3GHz Dual Differentia14H MuⅢ oIexer 33V Diπ eren"aILVPECL-to-LVTTL TransIator sΥ 100EP56V sΥ Log∶ 5V/33V4ˉ lnout OR/NOR 5V/33Di矸 erenⅡ al AND`NAND Y10EPO8V州 Ew ⒌ 尸 Translators super300κ 1阳 ECLinPs LiteIm C 10EPO1V 10EPO5VNEW ;Υ 10EP目 superL∶ te CML LOgiC 100EPs7V村 畲W sΥ 100EPT21L sV100EPT22V sΥ 100EPT23L )3V/5V DualLVTTL/LVCMOSˉ toˉ Di仟 eren"al LVPECL TransIator 33V Dual DifferenuaI LVPEcL~to-LVTTL Translator Back ite CML L ⒌丫55851 z5V/3V,3.0GHz CML AnyGatetMAny LogiC VW50￡ 10r100‘ l outputs 55851A sY55852U sΥ DF"o-FloD EW yˇ 55854uNEw ;Υ 55855VNEw sΥ 55853U肘 sΥ 55856uN旺 sΥ 55857LⅡ ;Υ C w Ew 55858uNEW sΥ 55859LNε w D Latch 2X2ProteCtion Crosspoint sWⅡ ch DuaI CML/PECL/LVPECL-To-LVDS TransIator 25V/33V25GHz Differentia12-Channel Precision CML De丨 ay Line ;,3V,25Gbps ANY INPUTˉ to-LVPECL DUAL TRANSLATOR z.5V/3.3V30GHz Dua12X2CML Crosspoint SwⅡ ch w/lnterna丨 Terminaton ;3v,27gbps Dua12x2Crosspoint Switch Back ECLinPsTⅢ Y10`100EO16 Υ10`100E101 Υ10`100E104 Υ10'100E107 10'100E111 Υ10`100E111A`L Υ10"00E111AE`LE Υ10`100E112 Inout AND/NAND Gate 2-lnDut XOR/XNOR Gate 2ˉ ⒈9Di仟 eren犭 al Clock Driver w"h Enable /33V1∶ 9Di仟 CIOCk DHver(wⅡ hout Enable V/3.3V1∶ 9Diff CIoCk DHVer(With Enable Y10'100E116 Y10'100E122 Di仃 eren廿 aI Line ReceiveF 10`100E131 V10`100E136 ri|c∶ //F∶ \Micrcj\ECI'(炻 20L'Ogjc。 htm 20θ 2— 11-27 页码 ,2/4 ˇ10∥ 100E137 Counter ;Υ 10`100E141 )-B"shiⅡ Re¤ ister BΥ 10`100E142 )BⅡ ShiⅡ Re¤ ister )-BⅡ HoId Reqister sY10`100E143 ;ˉ B"D Latch sY10"00E151 ;ˉ BⅡ ;丫 10`100E154 5ˉ B"2" Mux-Latch 10"00E155 3ˉ Bit2∶ sΥ 10`100E刂 i|丨 i|||∴ ` ;Υ 50 D Re¤ ister 1 Muxˉ Latch sV10`100E156 3-BⅡ 4△ sΥ 10`100E157 auad2∶ 1MuI刂 p丨 exer MuX-LatCh B"2" Mu"iDIexer ;Υ 10`100E158 5ˉ ;V10`100E160 12ˉ ;Υ 10`100E163 2-BⅡ ;Υ 10'100E164 16∶ ;Υ 10`100E166 冫 BⅡ Ma¤ n"ude sΥ 10`100E167 ˉ ⒌ BⅡ sY10`100E171 -Bit4" MuⅡ ipIexer ⒊ sΥ 10`100E175 9ˉ sΥ 10`100E193 B"ParⅡ v Generato〃 Checker 8∶ 1Mu"iplexer 1 Mu"iD丨 2∶ exer ComDarator 1Mux-Reoister B"LatCh WⅡ h Pa"tv rror DeteC‖ on`Correcu。 n circuⅡ Droqrammable Delav Chip DroqrammabIe DeIaV Chip sΥ 10`100E195 sΥ 10`100E196 sY10`100E256 ˉ ⒊ B"sCannabIe Reqister ˉ B"scannable Reqister ⒊ ˉ ⒊ B"4∶ 1 Mux-LatCh ⒌Υ10`100E336 3ˉ Bit Reoistered Bus TransCeiver 3ˉ Bit sCannable Reqistered Bus Transceiver s丫 10'100E212 sΥ 10`100E24门 sY10`100E337 sY10`100E404 sY10`100E416 sΥ Duad Di仃 erenⅡ aI 10`100E431 ⒌Y1or1ooE445 sΥ 3ˉ BⅡ tˉ Bit serla〃 Para"e丨 Conveder ˉ 牛 B"Para"e卜 to-SeriaI Converter 10`100E446 ⒊Y10`100E451 5-BⅡ sΥ 10'100E452 5-BⅡ Di仃 erenⅡ al sΥ 10`100E457 Γ riDle sΥ AND/NAND erential Line ReCeiver Di矸 erentia丨 FⅡ p-Flop Duint E)i矸 Reqister Di仟 eren刂 aI Data CIock Re¤ ister 1Mu⒒ iDIexer Duint LVPECL-to-PECL or PECL-to-LVPECL Trans|ator 100E417 Di仟 erentiaI2∶ Back ECLinPs LiteTM sΨ 1o"ooELO1 ←lnput OR/NOR sΥ 10'100ELO4 2-lnput AND/NAND sˇ 10`100ELO5 2丬 nput $Υ 10`100ELO7 2-hput XOR/XNOR sˇ 10`100EL11V 5V/33V1∶ 2Differenual Fanout Buffer sΥ 10'100EL12 sΥ 10川 sΥ 00EL15 10"00EL16V ~ow丬 DifferenuaI AND/NAND mpedance D"ver ⒈4Clock Dist"buuon 5V/3.3V Di仟 eren"aI Receiver sΥ 10"00EL16VAˉ VF 三nhanced Differential Receiver s丫 10'100EL3日 DF"pˉ Flop vvith Set and Reset ;Y10'100EL32V sΥ 10`100EL33`L 5V/3.3V÷ 2Divider V`33V÷ -4Divider ⒌ Y10'100EL34`L ⒌ 3V/33V÷ Υ10`100EL35 ⒌ 2,÷ 4,÷ 8CloCk Generaton Chiρ K FⅡ p-FIop sΥ 10`100EL38`L 5V/33V÷ 2,÷ 4`6Clock Generau。 n0hip ;Υ 10`100EL51 Di矸 eren1aI sΥ 10'100EL52 DifferenⅡ a丨 Data and Clock D FIipˉ sY10`100EL57 sΥ 10`100EL58 sY10`100ELT20V f,ilc∶ //lr∶ Clock D F"p-FIop FIOp 1Di仃 erenⅡ aI MuItipIexer 1 MuⅡ ipIexer 5V/3.3V TTL-tJ-Di仃 eren"aI PECL TransIator \Micrel\ECl'%201'Ogic。 htm ・ 2002-11-27 页码 ,3/4 )rO l冫 Osyi c 丨 :CI' 丨 Υ10`100ELT21 ;Υ 矸erential PECL-to-TTL Translator ;3V Di矸 erential LVPECLˉ to:L~VTTL Translator 10'100ELT21L DuaI TTL-toˉ Di矸 erenual PEcL Translator ;Y10`100ELT22 冫 |丨 i∫ , ;Υ 10'100ELT22L ⒊.3V DualTTL-toˉ Di矸 eren"al s丫 10/100ELT23 Dual DifferenJaI PECL-toˉ PECL TransIator TTL TransIator TTL Trans|ator sY10H OOELT23L ).3V DuaI Di仟 erential PECLˉ sY100EL勹 001 ~aser Diode DHver w"h Input D Flip¨ Flop sY100EL1003 sΥ 100EL14V ~aser Diode Driver wⅡ h output Enable sΥ toˉ 5V/33Vr1∶ 5CloCk Dist"bu刂 on ⒊3V⒈ 4CIock Dist"bution|C 100EL日 5L sY100EL16VON母 W 33ˇ /5V800MHz Precision PECL AmpⅡ Ⅱer w"h Low Gain Feedback sΥ 100EL16Vs 5V/33V Va"able Output Swing Di仟 er0nuaI Receiver sΥ 100EL17V 5V/3.3V Quad Di矸 erenual Receiver sΥ 100EL29V ;Υ 100EL56V 9V/3,3V DuaI Di仃 erenuaI Data and CIOck D Flipˉ Flop w"h setand Reset ˉ V/3~3V Dual DifferenⅡ aI2"MuⅡ iplexer sΥ 100EL57L )3V4"Di仟 erenual sΥ 100EL90V 5V/33VT"ple ECL/LVECLˉ to-PECL/LVPECL Translator Γ rlp丨 e PECLoto-ECL Trans丨 ator sY100EL91 sΥ MuⅡ ipIexer 33VT"ple LVPECLˉ 100EL91L toˉ ECL orLVPECLˉ to1LVEcL TransletⅡ sY100EL92 ΓHpIe LVPECL-toˉ PECL0r PECL-to-LVPECL Translator SV100ELt24 sV100ELT25 ;Υ 100ELT982 Γ TLˉ to-DifferenⅡ al ECL TransIator sΥ 10EL日 sΥ Differen"aI ECL△ o-TTL Translator ’ECL-tO-CML Translator w"h output Enable 189 =ibre ChanneI COaxiaI Cable DHver and LOop Res"iency CircuⅡ 10EL89 3oaxial Cable D"ver Back 300κ Tm 「 lnDut OR/NOR Gate sY100s302 "o|e5ˉ Duint2-丨 nDut OR/NOR Gate sΥ 100s304 Duint AND/NAND Gate sΥ 100s307 Duint Exclusive OR/NOR Gate sΥ 100s313 Duad D"ver sΥ 100s314 Duint E)ifferenJaI Line Receiver sY100s317 sY100s318 「 Hde2ˉWide OA/OAl Gate ;V100s321 Υ100s322 ⒌ sΥ 100s324 sΥ 100s325 sΥ 100s331 sΥ 100s336 ~oWˉ PoWer9-Bit Inve吐 er ⒌Y100s336A 三 nhanCed4ˉ staoe Counte〃 Shi伍 Register sY100s341 sΥ 100s350 sΥ 100s351 sΥ 100s355 sY100s360 sΥ 100s363 ;-BⅡ sΥ 100s301 sY100s364 100s366 sY100s370 ;Υ 100s371 ;Υ 100s391 sΥ 100s811 ;Υ 100s815 ;Υ 100s834`L sΥ 100s838`L sΥ ;Υ Γilc∶ C 100s839V 5-Wide5,4,4,20AlOAl Gate -B"Buffer 冫 ow-PoWer Hex TTL-toˉ ECL Translator ow¨ PoWer Hex ECL-toˉ TTL TransIator 「 riDle D F"p-Flop 卜Sta¤ e Counter/ShiR Reqister 丬ex shift Reqister D-Latch 丬ex D F"Dˉ FlOD Duad Mu"iDlexer`Latch Dua丨 Paritv Checker/Generator DuaI8ˉ InDut Mu"ioIexer 6丬 nDut 9ˉ Mu"iplexer B"ComDarator Jniversal DemuⅡ iDlexer/Decoder riDle4-Inout Mu"ipIexer vvith EnabIe Γ ~oW-PoWer Hex TTL-toˉ PECL Translator 3in¤ Ie suDDIv1∶ 9PECL厅 TLˉ toˉ PECL toˉ PECL sinqle SuDo丨 V Quad PECLlTTLˉ (÷ 日,÷ 2,÷ 4)or(÷ ÷1,÷ 2/3)or〈 ÷2/4,÷ //Γ ∶ \Micrel\ECl'%201'ogic。 2,÷ 4,÷ 8)Clock Gen Chip 艹2,÷ 4/6)C丨 °ck Gen Chip 4`5/6CLOCK GENERAT丨 oN CHlP htm 2002一 ll-27 页码 ,‘ /4 PECL DifferenuaI MuX、 呐th TTL SeleCts 亻卩 :￠ 2002— 11-27 页码 ,1/l 格磊科技产 品数据光盘 V3.2 憾 溺 翮 耐 鼹躐 槲巍翻 鼹忿 涠 CloCkWorksTⅢ 爿 。 sˇ nthesizers =requencˇ ;3V32ˉ 175Mbps AnyRateTM CIOCk And Data Recovery ;V/33V32ˉ 175MbDs AnvRateTM Clock and Data Recovery ;3V32-1250Mbρ s AnVRateTM CIock And Data RecOvery ⒌ Υ877001 87700V 3Υ 87701L sΥ B丫 87701V ;V/33V32-1250Mbps AnvRatetM Clock and Data Recovery ;3V28MbDs-25GbDs AnvRatetm Clock and Data Recoverv 87702L sΥ 87724L ;Υ sΥ ;3V AnvRatetM MUX`DEMUX Upto27GHz DrOqrammabIe Frequency synthesizer(25MHzt° 400MHz) 5V/3,3V Pro¤ rammab丨 e FrequencV SVnthesizer(25MHzto400MHz) 荪乃E∶ 5ˇ 冖ro¤ rammable Frequency synthes泛 er(50MHzt。 950MHz) 89429A ;Y89429V ⒌Y89430V 0loCk Generators 3Υ 5V/3,3V÷ 2Divider 10`100EL32V 5V/33V÷ 5V/33V÷ 5V`33V÷ 5V/33V÷ 5V/33V÷ 10`100EL33`L sΥ 10`100EL34`1 sΥ 10`100EL38`L sΥ 2DiVider 4DiVider 5V`3.3V(÷ 1,÷ 2,÷ 4)or(÷ 2,÷ 4,÷ 8)CloCk Gen Chip 5V/33V(÷ 1,÷ 2/3)。 r← ÷2,÷ 4/6)CIOck Gρ n∶ chip 10`100EP32V 0`100EP33V ;Υ 100s834`L ;丫 100s838`L ;Υ ;V日 ÷2/4,÷ 4`5/6C丨 oCk Generauon chip ;Y100s839V ’ro¤ raⅡ able Delaˇ Lines`t Iming Verniers DroqrammabIe DeIav Chip "η sΥ 10`100E195 ’ro¤ rammable Delav Chio wⅡ h AnaIOq Inpu1 ;Υ 10`100E196 25MHz T"¤ qer Proqrammable Tinninq Edqe Vernier 25MHz W"te ProqrammabIe Timing Edge Vernier ;Υ 604 605 Phase Locked Loops sΥ 89420V s丫 9V/33V Dua|Phase Locked Loop 9V/33V Hiqh Performance PLL sY89421V )∶ 4Divider 2,÷ 4,÷ 8C丨 ock Generaton Chip 2,÷ 4/6Clock Genera刂 on chip oCk D∶ stribution and D"ˇers sΥ 10`日 sΥ 00ε 111 10HOOE111A'L 10`100E111AE`LE 3Y10`100EL11V 5V10'100EL15 sΥ sΥ 10"00ELT20V 0`100ELT21 10`100ELT21L PECLotoˉ TTL TransIator ⒊3V Di矸 erential LVPECL-to-L∨ TTL Translator Di矸 eren刂 aI sΥ 日 sΥ ∶ 9Di矸 erenuaI cl。 ck D"ver(w"h EnabIe) 5V/33V1∶ 9Di仟 CloCk D"ver(w/o Enable) 5V/33V lmoroved1∶ 9Di矸 erentia丨 Clock D"Ver(w/Enab|e) 5V/33V1∶ 2Di仃 eren臼 aI Fanout Bu矸 er 彳 CIoCk Dist"buJon 5V/33V TTL-to-Di仟 erenuaI PECL Translator TTL sΥ 日0`闸 00ELT23 DuaI Differential PECLˉ sY10`100ELT23L 33V Dual Di矸 erenual PECL-toˉ sΥ 10'100EP11uN琶 W sΥ 日0`100H641 sY10`100H641A sΥ 10`mOH641L sΥ 10`100H646L l^「 L 25V/33V/5V1∶ 2Di钌 erentiaI PECL/LVPECL/ECL Fanout Buffer sin¤ le suoDlV1∶ 9PECLˉ toˉ TTL(135MHz) e suDpIV1∶ 9PECL-to-丁 TL(80MHz) sinΩ 丨 33V sinΩ le supply1∶ 9PECLˉ toˉ TTL ;3V Single SuppIy OCTAL PECL/1TLˉ toˉ l^rL V Quad PECL-to-TTL W/output EnabIe 33V sinoIe Supplv Quad PECL-toˉ l「 LW/Output Enao壁 3inqle supplV Quad PECLˉ to-TTL wLatched output Enable Ⅰ3V sin¤ le s山 。°lv Quad PECL-toˉ TTL w/LatChed output Enable sΥ 10`100H841 sin¤ le suDo丨 sY10`100H841L sY10`100H842 sΥ 日0'100H842L sΥ toˉ 100EL14V 5V/33V1∶ 5C丨 ock Distobution sΥ 100EL15L ⒊3V1⒕ CIock DistHbution lC sY100EL29V DuaI Di矸 erenuaI Data and Clock D F"pˉ FIop with Set and Reset sY100EP111u~苫 w sΥ 89809L 25V/33V1H O Differen刂 alLVPECL/LVECL/HSTL CIoCk DHVer ∶ ,5V/33V/5V1∶ 5LVPEC凵 PEC凵 EC凵 HSTL2GHz CIoCk D"ver wⅡ 旧ux 25V/33V DuaI1∶ 5Differen"a丨 LVECL/LVPECL/HSTL CIock Dover ;3V DuaI Di仃 erential LVPECLˉ to-LVTTL Translator Dual suoDIV0CTAL ECL-toˉ l^「 L ;ino|e SuoplV1∶ 9PECL厅 TLˉ toˉ PECL・ ;in¤ le SuDDlV Quad PEC凵 TTLˉ toˉ PECL ;3V1∶ 9Hiqh-Peror1η ance、 Low-Vo"aqe Bus CIock DHver sΥ 89824L 1iqhˉ Performanco‘ sΥ 100EP14U 100EP210u 100EPT23L SΥ 100HA643 ;Υ ;ˇ sV100s811 sΥ 100s815 ilc∶ 〃 lr∶ \index。 htm a丨 lnput LoW-Vo"age Bus Clock D"ver D【 ρ : 0"o'′ l、 h2"Di矸 erenⅡ I⌒ ^tr nr∶ ˇ⌒、ρ tr勹 nCl0◆ ^o",t△ 2002-ll-27 页码 ,1/I 格磊科 技产 品数据 光盘 V3.2 躅 蹋 翮 阿 撼黥 槲蚰氓 鑫 弼公涠 TransIators 舛 l 10H OOELT20V ;Y10`100ELT21 ;Υ 10`100ELT21L ;Υ 10`100ELT22 ;Υ 10`100ELT22L ;Υ 日 0'100ELT23 sΥ 10`100ELT23L ;Υ 5V`33V TTL-toˉ DifferenⅡ aI PECL Translator Di仃 erent∶ al PECLˉ toˉ TTL TΓ anslator 33V DifferenⅡ al LVPECL-to-LVTTL Translator Dual TTLˉ to-Differen刂 al PECL TransIator ;3V DuaITTL-to-DⅢ ℃ren【 aI PECL TransIator DuaI DifferentiaI PECLˉ )3V Dual Di矸 erent∶ al toˉ TTL Translator PECL-toˉ 1TL TransIator 3Υ 10`日 00ELT28N￠ W 5V TTLˉ toˉ Di矸 eren刂 al PECLˉ toˉ 1TL Translator sΥ 10`目 00EPT20V )3V`5V LVTTL/LVCMOs-to-Di仟 erenuaI LVPECL Translator ⒊ V LVTTL-to-Differen刂 alLVPECL and Di矸 erenⅡ al LVPECLˉ toˉ LVTTL ˉ 冫 BⅡ TTL-to-ECL with tTL、 ECL Enable sΥ 10'100EPT28LN琵 w sΥ 10`100H600 ˉ BⅡ ECL-toˉ 1TL wⅡ h3ˉ state Enab丨 e 冫 ˉ 冫 Bit Latched TTLˉ toˉ ECL 10`100"601 10`100H602 s丫 10`100H603 sΥ sΥ ˉB"Latched 冫 ECL-toˉ TTL sΥ 10`100H606 Reqistered Hex TTLˉ to-PECL sΥ 10`100H607 Re¤ istered ⒌Υ10`100H641 sΥ 10川 sin¤ Ie 00H641A 9PECL-to-1TL(135MHz) sinqIe suDD丨 V1∶ 9PECLˉ toˉ TTL(80MHz) 1.3V Sinqle supp|V1∶ 9PECL-toˉ TTL ⒊Υ10`100H641L sΥ Hex PECL-to-TTL suDDlV1∶ 10'100H646L ;3V sinoIe SuDDIv OCtal PECL/TTL-to-l^TL sinqle SuDDIv Quad PECLˉ to-TTL w/outDut Enable ;3V sinΩ le supp丨 v Quad PECLˉ toˉ TTL wⅡ h output Enable ;in¤ Ie SuDo丨 V Quad PECL-to-TTL W/LatChed outout Enable ;3V Sinq丨 e supolv Quad PECL-toˉ 1TL W/Latched outDut Enable Duint PECLˉ to-LVPECL Translator sΥ 10`100H841 10`100H841L sV10`100H842 sΥ 10`100H842L sΥ 100E417 sΥ sΥ 100EL90V 5V/33VT"DIe ECL`LVECL-to-PECL/LVPECLTranslator ;Υ 100EL91 ;V TriD丨 e ;V100EL91L PECL¨ toˉ ECL Translator ;3VT"ple LVPECL-to-ECL TransIator ;Y100EL92 「 oD|e LVPECLˉ to-PECL or PECLˉ toˉ LVPECL Translator 100ELT24 ;Υ 100ELT25 ;丫 100ELT982 sΥ 100EPT21L s丫 100EPT22V sΥ 100EPT23L s丫 日 00HA643 Π L-to-Di仃 erential ECL Translator ;Υ sΥ Di矸 erenⅡ al 100s324 3Y100s325 sY100s391 sY100s811 sΥ 100s815 ~oWˉ POwer Hex TTL-toˉ PECL Trans丨 ator 3inqle SuDDlv1∶ 9PECL冂 TL-to-PECL l^rL~t。 ~PECL sinqle supp|v Quad PECLlˉ ’ECL-toˉ 1tL Translator sY10H350 ;Υ ECL-toˉ tTL Translator DECL-to-CML Translator wⅡ h outρ ut Enable 33V Di矸 erentiaI LVPECLˉ toˉ LVTTL TransIator )3V/5V DualLVTTL/LVCMOSˉ to-D渊 ℃ren刂 al LVPECL TransIator ⒊3V DuaI Differen"aI LVPECLˉ toˉ LVTTL Translator DuaI SuDDIv OCtaI ECLˉ to-TTL ~oWˉ PoWer Hex TTLˉ toˉ ECL TransIator ~oWˉ PoWer Hex ECLˉ toˉ TTL Trans丨 ator 10H351 DUAD TTL/NMOs-toˉ PECL Translator MOSˉ toˉ PECL TransIator 3Y10冂 352 Back ￠ ’ Γilc∶ //r∶ \indcx。 htm 2002-11-27 页码 ,l/l 格磊科技产 品数据光盘 V3.2 muxrDemuxes 彳 , sΥ 10`100E445 -Bit seria卜 toˉ ParaⅡ el ConveHer Ⅱ 扭 sY10'100E446 Iˉ 3Y87724LN旺 弼 ;3V AnyRateTM MUX/DEMUX Upto2,7GHz 卩〓 「 B"Para"el-to-seriaI Converter 氵 ￠ 2002— ll-27 页 码 ,〃 l 丘 辶 噶溅翮耐 膺 涠 ∵ 卜 衤 诲弼 《 审 蘩 群 甄 博 醇 蛰闸 再 彳 : rransceiˇ ers sΥ 69952 DCˉ 3/sTS-3Clock ReCovering Transceiver sΥ 69952A DCˉ 3`sTS-3C丨 oCk RecOve"nq Transceˇ er sY87700L sΥ 87700V sΥ 8770日 L sΥ 87701V sΥ 87702L ;3V32ˉ 175Mbos AnvRateTM Clock And Data RecOvery 9V/33V32-175Mbps AnVRateTMClock and Data Recovery ;3V32-1250Mbps AnyRatetM Clock And Data Recovery ˉ V/33V32-1250Mbps AnvRate了 M cI。 ck and Data RecOvery ;3V28Mbps~2.5Gbps AnvRateTm Clock and Data Recovery :Jl 2002— ll-27 页码 ,1/l 格磊科技产 品数 据光盘 V3.2 F鼹 躐辍蚰妯弼公涠 Module lCs 〃 . ~aser D:ode D"ˇ ers sΥ 10`100EL16V 5V/33V Di仟 erenuaI Receiver sΥ 10EP16VNε w 丬i¤ hˉ Soeed Differential Receiver 5V/332.5Gbps Va"abl己 0utput swing Di仟 erenⅡ a!Receiver ¨ aser Diode Driver wⅡ h lnput D FIipˉ Flop 00EP16Vs斜 茁W ;Υ 日 ;Υ 100E△ 1001 sΥ 100EL1003 sΥ 100EL16Vs sΥ 88902 ~aser Diode D"ver w"h output Enable 5V/33V VaHabIe Output Swing DifferenⅡ al Receiy￡ ⊥ ~aser Diode Driver wⅡ h output EnabIe W s丫 88922 sΥ 88922V ;3V32Gbos sONET/SDH Laser Dovode Drlver V sDH/sONET25Gb/s Laser Diode D"ver ⒌ sDH/sONET25Gb/s Laser Diode D"ver sΥ 88927V 5V/33V2,5Gbos Hiqh-Speed Di矸 erential Receiver 3Υ 88912LN￡ ’ ost Amos 125Gbps High Speed Lim"ing Post^唑 sΥ 88903 sΥ 5V/33V125Gb/s Highˉ Speeα 88903V ;Υ 88θ LimⅡ ing Post AmpImg三 Speed Lim"ing Post Amp丨 rier ;V/33V125Gbps High-Speed LimⅡ in且 P。 st AmpImer 250Gbps Hiqh-speed Lim"∶ ng PostAmp丨 fier 125G0Ds HiΩ 13 hˉ sΥ 88913V 88923 3Υ 88923AV sΥ 88923V 5V/33V32GbDs Hiqh-Speed LimⅡ ing Post AmpIⅡ 咋Ⅰ 5V/33V25Gbps Hiqh-Speed Lim"ing PosL仝 mpIfier ;Υ 88943V V/33V25Gbps Lim"ing Post A 予 sΥ sΥ 889θ 3AV 5V/33V32GbDs HIqh-speed Lim"ing POst AmpI"i￡ E 5V/33V32Gbps Hlqh-Speed Lim"ing PQ螂 ;Y88993V ⒋utomat∶ c PoWer ControlfAPC er wⅡ h APC ~aser Diode Contro丨 丨 sΥ 88θ 05 Back 氵 ￠ Γilc∶ //Γ ∶ \indcx。 htm 2θ 02-11-27