NSC MM74HCT193

MM54HCT193/MM74HCT193
Synchronous Binary Up/Down Counters
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of CMOS technology,
along with the speeds of low power Schottky TTL. The
MM54HCT193/MM74HCT193 is a binary counter having
two separate clock inputs, an UP COUNT input and a
DOWN COUNT input. All outputs of the flip-flops are simultaneously triggered on the low-to-high transition of either
clock while the other input is held high. The direction of
counting is determined by which input is clocked.
This device has TTL compatible inputs. It can drive 15 LSTTL loads.
This counter may be preset by entering the desired data on
the DATA A, DATA B, DATA C, and DATA D inputs. When
the LOAD input is taken low, the data is loaded independently of either clock input. This feature allows the counter
to be used as a divide-by-n counter by modifying the count
length with the preset inputs.
In addition, the HCT193 can also be cleared. This is accomplished by inputting a high on the CLEAR input. All 4 internal
stages are set to a low level independently of either COUNT
input.
Connection Diagram
Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions. The
BORROW output produces a negative-going pulse when
the counter underflows and the CARRY outputs a pulse
when the counter overflows. The counter can be cascaded
by connecting the CARRY and BORROW outputs of one
device to the COUNT UP and COUNT DOWN inputs, respectively, of the next device.
All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
Y
Y
Y
Low quiescent supply current: 80 mA maximum (74HCT
Series)
Low input current: 1 mA maximum
TTL compatible inputs
Truth Table
Dual-In-Line Package
Count
Up
Clear
Load
Function
L
L
H
L
H
H
X
L
Count Up
Count Down
Clear
Load
Down
u
H
H
X
X
u
X
X
H e high level
L e low level
ue transition from low-to-high
X e don’t care
TL/F/5742 – 1
Order Number MM54HCT193 or MM74HCT193
C1995 National Semiconductor Corporation
TL/F/5742
RRD-B30M105/Printed in U. S. A.
MM54HCT193/MM74HCT193 Synchronous Binary Up/Down Counters
January 1988
Absolute Maximum Ratings
Operating Conditions
(Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temp. Range (TA)
MM74HCT
MM54HCT
Input Rise or Fall Times
(tr, tf)
b 0.5V to a 7.0V
Supply Voltage (VCC)
b 1.5V to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5V to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per Pin (IOUT)
g 50 mA
DC VCC or GND Current, per Pin(ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
260§ C
Min
4.5
Max
5.5
Units
V
0
VCC
V
b 40
b 55
a 85
a 125
§C
§C
500
ns
DC Electrical Characteristics VCC e 5V g 10% unless otherwise specified
Symbol
Parameter
Conditions
TA e 25§ C
74HCT
54HCT
TA eb40§ C to 85§ C TA eb55§ C to 125§ C Units
Typ
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
0.8
0.8
0.8
V
VOH
Minimum High Level VIN e VIH or VIL
Output Voltage
VCC VCCb0.1
lIOUTl e 20 mA
lIOUTl e 4.0 mA, VCC e 4.5V 4.2 3.98
lIOUTl e 4.8 mA, VCC e 5.5V 5.2 4.98
VCCb0.1
3.84
4.84
VCCb0.1
3.7
4.7
V
V
V
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
g 0.1
g 1.0
g 1.0
mA
8.0
80
160
mA
1.0
1.2
1.3
mA
VOL
Maximum Low Level VIN e VIH or VIL
Voltage
lIOUTl e 20 mA
lIOUTl e 4.0 mA, VCC e 4.5V
lIOUTl e 4.8 mA, VCC e 5.5V
IIN
Maximum Input
Current
ICC
Maximum Quiescent VIN e VCC or GND
Supply Current
IOUT e 0 mA
0
0.2
0.2
VIN e VCC or GND,
VIH or VIL
VIN e 2.4V or 0.5V (Note 4)
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power dissipation temperature deratingÐplastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: Measured per pin, all other inputs held at VCC or GND.
2
AC Electrical Characteristics
(Note 6) VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
From
(Input)
fMAX
Maximum Clock
Frequency
tPLH, PHL
Maximum Propagation
Delay Time
Load
tPLH, PHL
Maximum Propagation
Delay Time
tPLH, PHL
To
(Output)
Conditions
Typ
Guaranteed
Limit
Units
35
MHz
QA, QB,
QC, QD
26
ns
Data A,
B, C, D,
QA, QB,
QC, QD
25
ns
Maximum Propagation
Delay Time
Count-Up
or -Down
QA, QB,
QC, QD
26
ns
tPLH, PHL
Maximum Propagation
Delay Time
Count-Up
Carry
22
ns
tPLH, PHL
Maximum Propagation
Delay Time
Count-Dn
Borrow
22
ns
tPLH, PHL
Maximum Propagation
Delay Time
Clear
QA, QB,
QC, QD
25
ns
AC Electrical Characteristics (Note 6)
VCC e 5V, g 10%, CL e 50 pF (unless otherwise specified)
Symbol
fMAX
Parameter
From
(Input)
74HC
54HC
To
T e 25§ C T e 25§ C
T eb40§ to 85§ C T eb55§ to 125§ C Units
(Output)
Typ
Guaranteed Limits
32
20
16
13
MHz
tPLH, PHL Maximum Propagation
Delay Time
Maximum Clock Frequency
Load
QA, QB,
QC, QD
29
44
55
66
ns
tPLH, PHL Maximum Propagation
Delay Time
Data A
QA, QB,
QC, QD
28
40
50
60
ns
tPLH, PHL Maximum Propagation
Delay Time
Count-Up
or -Down
QA, QB
QC, QD
30
43
54
65
ns
tPLH, PHL Maximum Propagation
Delay Time
Count-Up
Carry
25
30
38
45
ns
tPLH, PHL Maximum Propagation
Delay Time
CountDown
Borrow
25
30
38
45
ns
tPLH, PHL Maximum Propagation
Delay Time
Clear
QA, QB
QC, QD
28
35
44
53
ns
16
25
31
38
ns
20
25
30
ns
tW
Minimum Clock
Pulse Width
tS
Minimum Setup Time Data
before Load-LH
tH
Minimum Hold Time Data
after Load-LH
b3
5
6
8
ns
tREM
Minimum Removal Time
Load to Count
b2
5
6
8
ns
tREM
Minimum Removal Time
Clear to Count
2
5
6
8
ns
tW
Minimum Load
Pulse Width
18
20
25
30
ns
tW
Minimum Clear
Pulse Width
8
20
25
30
ns
tTLH, THL Output Rise or Fall Time
10
15
19
22
CPD
Power Dissipation
Capacitance
40
CIN
Maximum Input Capacitance
5
ns
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, Is e CPD VCC f a ICC.
Note 6: Refer to Section 1 for Typical MM54/74HCT AC Switchforms and Test Circuits.
3
4
MM54HCT193/MM74HCT193 Synchronous 4-Bit Up/Down Binary Counter
TL/F/5742 – 2
Logic Waveforms
’HCT193 Synchronous Binary Counters
Typical Clear, Load, and Count Sequences
TL/F/5742 – 3
Sequence:
(1) Clear outputs to zero.
(2) Load (preset) to binary thirteen
(3) Count up to fourteen, fifteen, carry, zero, one, and two.
(4) Count down to one, zero, borrow, fifteen, fourteen, and thirteen.
Note A: Clear overrides load data, and count inputs.
Note B: When counting up, count-down input must be high; when counting down, count-up input must be high.
5
6
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54HCT193J or MM74HCT193J
NS Package J16A
7
MM54HCT193/MM74HCT193 Synchronous Binary Up/Down Counters
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM74HCT193N
NS Package N16E
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