Genesys Logic, Inc. GL850G USB 2.0 Hub Controller Datasheet Revision 1.23 Jul. 15, 2011 GL850G Datasheet Copyright Copyright © 2011 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc. Ownership and Title Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder. Disclaimer All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice. Genesys Logic, Inc. 12F., No. 205, Sec. 3, Beixin Rd., Xindian Dist. 231, New Taipei City, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http://www.genesyslogic.com ©2011 Genesys Logic, Inc. - All rights reserved. Page 2 GL850G Datasheet Revision History Revision Date Description 1.00 05/10/2006 First formal release 1.01 08/30/2006 Update DC supply current, table6.6, P.23 1.02 11/03/2006 Modify 93C46 configuration, table 5.1, P.19 1.03 01/17/2007 Modify table 6.1-maximum ratings, P.21 1.04 08/08/2007 Modify table 6.6-DC Supply Current, P.23 1.07 Add SSOP 28 package assignment ,Ch3, P.11~14 Add –low/high-enabled power switches, Ch5.2.7, P.23 03/10/2008 Add built-in 5V to 3.3V power regulator, Ch5.2.5, P.21 Modify power on reset description, Ch5.2.1, P.18 Add description of port configuration, Ch5.2.8 and Ch5.2.9, P.23 Add QFN 28pin: pinout, p.12 pin List, p.13 01/07/2008 pin descriptions, p.14 ~15 package dimension, p.30 ordering information, p.32 02/19/2009 Modify SSOP 28 pin, QFN 28 pinout, pin list, pin description, p.11~15 1.08 03/18/2009 Modify electrical characteristics, Ch6, p.26~27 1.09 04//15/2009 Modify table 6.6-DC supply current, p.27 1.10 1.17 04/27/2009 Modify part number of QFN 28, table8.1- ordering information, p.31 Modify pin name SEL48/SEL27 pinout / pin list/ description, p.10, p.13, p.15 04/29/2009 Modify Fosc 12 MHz 0.05% to 12 MHz 50ppm, maximum ratings, table-6.1, p.26 Modify Fosc 12 MHz 50ppm to 12 MHz 0.05%, maximum ratings, table 06/12/2009 6.1, p.26 Modify power on reset diagram, figure 5.3, p.21 08/12/2009 Modify Ch6.4 power consumption, table 6.6 – DC supply current , p.28 Update table 3.4 – pin description, p.16 Update table 6.2 – operating ranges, p.29 09/02/2009 Update table 6.3 – power dissipation, p.29 Update Ch8 order information, p.35 Update Ch2 features, p.9 Add note to table 3.2, p.14 09/22/2009 Add note to table 3.4, p.15 Add note to table 5.2, p.27 Update table 6.3 – power dissipation, p.30 Modify description of reference clock configuration, Ch5.2.10, p.28 03/15/2010 Modify Ch7 Package Dimension, p.32-33 Modify Ch8 Ordering Information, p.35 10/05/2010 Modify table 6.2 – operating ranges, p.29 1.18 10/25/2010 Modify Figure 7.3, p.34 1.05 1.06 1.11 1.12 1.13 1.14 1.15 1.16 ©2011 Genesys Logic, Inc. - All rights reserved. Page 3 GL850G Datasheet 1.19 Modify Ch2 features, p.9 Modify 5.2.5 EEPROM Setting, p.25 12/24/2010 Add 6.5 AC Characteristics, p.31~32 Add 6.6 On-Chip Power Regulator, p.33 1.20 03/02/2011 1.21 04/26/2011 Modify 5.2.1 RESET Setting, p.23~24. 1.22 05/11/2011 Modify SSOP28 package dimension information, p.36 1.23 07/15/2011 Update Table 3.1, 3.2, 3.3, 3.4 RREF I/O type, p.15, 16 Update table 6.2 – operating ranges, p.28 Update table 6.3 – DC characteristics except USB signals, p.29 ©2011 Genesys Logic, Inc. - All rights reserved. Page 4 GL850G Datasheet Table of Contents CHAPTER 1 GENERAL DESCRIPTION ......................................................................... 9 CHAPTER 2 FEATURES................................................................................................... 10 CHAPTER 3 PIN ASSIGNMENT ..................................................................................... 12 3.1 Pinouts .......................................................................................................................... 12 3.2 Pin List.......................................................................................................................... 15 3.3 Pin Descriptions ........................................................................................................... 16 CHAPTER 4 BLOCK DIAGRAM .................................................................................... 19 CHAPTER 5 FUNCTION DESCRIPTION...................................................................... 20 5.1 General Description..................................................................................................... 20 5.1.1 USPORT Transceiver.......................................................................................... 20 5.1.2 PLL (Phase Lock Loop) ...................................................................................... 20 5.1.3 FRTIMER ............................................................................................................ 20 5.1.4 μC .......................................................................................................................... 20 5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface)............................................ 20 5.1.6 USPORT Logic .................................................................................................... 20 5.1.7 SIE (Serial Interface Engine).............................................................................. 20 5.1.8 Control/Status Register ....................................................................................... 20 5.1.9 REPEATER ......................................................................................................... 21 5.1.10 TT (Transaction Translator) ............................................................................ 21 5.1.11 REPEATER/TT Routing Logic........................................................................ 21 5.1.12 DSPORT Logic .................................................................................................. 22 5.1.13 DSPORT Transceiver........................................................................................ 22 5.2 Configuration and I/O Settings .................................................................................. 23 5.2.1 RESET Setting ..................................................................................................... 23 5.2.2 PGANG/SUSPND Setting ................................................................................... 24 5.2.3 SELF/BUS Power Setting ................................................................................... 26 5.2.4 LED Connections ................................................................................................. 26 5.2.5 EEPROM Setting................................................................................................. 26 5.2.6 Power Switch Enable Polarity (Only Available in LQFP48 Package)............ 27 5.2.7 Port Number Configuration (Only Available in LQFP48 Package)............... 27 5.2.8 Non-removable Port Configuration (Only Available in LQFP48 Package)... 28 5.2.9 Reference Clock Configuration (Only Available in LQFP48 Package) ......... 28 CHAPTER 6 ELECTRICAL CHARACTERISTICS...................................................... 29 6.1 Maximum Ratings ....................................................................................................... 29 ©2011 Genesys Logic, Inc. - All rights reserved. Page 5 GL850G Datasheet 6.2 Operating Ranges ........................................................................................................ 29 6.3 DC Characteristics ...................................................................................................... 30 6.4 Power Consumption .................................................................................................... 31 6.5 AC Characteristics ...................................................................................................... 32 6.5.1 93C46 EEPROM IF............................................................................................. 32 6.5.2 24C02 EEPROM Interface ................................................................................. 33 6.6 On-Chip Power Regulator .......................................................................................... 34 CHAPTER 7 PACKAGE DIMENSION ........................................................................... 35 CHAPTER 8 ORDERING INFORMATION ................................................................... 38 ©2011 Genesys Logic, Inc. - All rights reserved. Page 6 GL850G Datasheet List of Figures Figure 3.1 - GL850G LQFP 48 Pin Pinout Diagram .......................................................... 12 Figure 3.2 - GL850G SSOP 28 Pin Pinout Diagram ........................................................... 13 Figure 3.3 - GL850G QFN 28 Pin Pinout Diagram............................................................. 14 Figure 4.1 - GL850G Block Diagram (Single TT) ............................................................... 19 Figure 5.1 - Operating in USB 1.1 Scheme .......................................................................... 21 Figure 5.2 - Operating in USB 2.0 Scheme .......................................................................... 22 Figure 5.3 - Power on Reset Diagram................................................................................... 23 Figure 5.4 - Power on Sequence of GL850G........................................................................ 23 Figure 5.5 - Timing of PGANG/SUSPEND Strapping........................................................ 24 Figure 5.6 - Individual/GANG Mode Setting....................................................................... 25 Figure 5.7 - SELF/BUS Power Setting ................................................................................. 26 Figure 5.8 - LED Connection ................................................................................................ 26 Figure 5.9 - Schematics between GL850G and 93C46........................................................ 27 Figure 6.1 - Vin(V5) vs Vout(V33)*...................................................................................... 34 Figure 7.1 - GL850G 48 Pin LQFP Package........................................................................ 35 Figure 7.2 - GL850G 28 Pin SSOP Package ........................................................................ 36 Figure 7.3 - GL850G 28 Pin QFN Package.......................................................................... 37 ©2011 Genesys Logic, Inc. - All rights reserved. Page 7 GL850G Datasheet List of Tables Table 3.1 - GL850G LQFP 48 Pin List................................................................................. 15 Table 3.2 - GL850G SSOP 28 Pin List ................................................................................. 15 Table 3.3 - GL850G QFN 28 Pin List ................................................................................... 15 Table 3.4 - Pin Descriptions................................................................................................... 16 Table 5.1 - Reset Timing ........................................................................................................ 24 Table 5.2 - Configuration by Power Switch Type ............................................................... 27 Table 5.3 - Port Number Configuration............................................................................... 27 Table 5.4 - Ref. Clock Configuration.................................................................................... 28 Table 6.1 - Maximum Ratings............................................................................................... 29 Table 6.2 - Operating Ranges................................................................................................ 29 Table 6.3 - DC Characteristics except USB Signals ............................................................ 30 Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode .................................. 30 Table 6.5 - DC Characteristics of USB Signals under HS Mode ....................................... 30 Table 6.6 - DC Supply Current ............................................................................................. 31 Table 6.7 - AC Characteristics of EEPROM Interface (93C46) ........................................ 32 Table 6.8 - AC Characteristics of EEPROM Interface (24C02) ........................................ 33 Table 8.1 - Ordering Information......................................................................................... 38 ©2011 Genesys Logic, Inc. - All rights reserved. Page 8 GL850G Datasheet CHAPTER 1 GENERAL DESCRIPTION GL850G is Genesys Logic’s advanced version hub solutions which fully comply with Universal Serial Bus Specification Revision 2.0. GL850 inherits Genesys Logic’s cutting edge technology on cost and power efficient serial interface design. GL850G has proven compatibility, lower power consumption figure and better cost structure above all USB2.0 hub solutions worldwide. GL850G provides multiple advantages to simplify board level design that help achieve lowest BOM (Bill of Material) for system integrator. GL850G integrated both 5V to 3.3V and 3.3V to 1.8V voltage drop regulator into single chip, therefore no external LDO required. Also, GL850G’s power enable pin supports both high-enable and low-enable power switch that provides better flexibility on component selection. GL850G embeds an 8-bit RISC processor to manipulate the control/status registers and respond to the requests from USB host. Firmware of GL850G will control its general purpose I/O (GPIO) to access the external EEPROM and then respond to the host the customized PID and VID configured in the external EEPROM. Default settings in the internal mask ROM is responded to the host without having external EEPROM. GL850G is designed for customers with much flexibility. The more complicated settings such as PID, VID, and number of downstream ports settings are easily achieved by programming the external EEPROM (Ref. to Chapter 5). Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850G also support both Individual and Gang modes (4 ports as a group) for power management. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs. Please refer the table in the end of this chapter for more detail. Number of downstream ports setting can be configured by IO setting in absence of EEPROM. (Ref. to Chapter 5) To fully meet the cost/performance requirement, GL850G is a single TT hub solution for the cost requirement. Genesys Logic also provides GL852G for multiple TT hub solution to target on systems which require higher performance for full/low-speed devices, like docking station, embedded system … etc.. Please refer to GL852G datasheet for more detailed information. *TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports. ©2011 Genesys Logic, Inc. - All rights reserved. Page 9 GL850G Datasheet CHAPTER 2 Compliant to USB Specification Revision 2.0 Support 4/3/2 downstream ports by I/O pin configuration Upstream port supports both high-speed (HS) and full-speed (FS) traffic Downstream ports support HS, FS, and low-speed (LS) traffic FEATURES 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) Backward compatible to USB specification Revision 1.1 On-chip 8-bit micro-processor RISC-like architecture USB optimized instruction set Performance: 6 MIPS @ 12MHz With 64-byte RAM and 2K mask ROM Support customized PID, VID by reading external EEPROM Support downstream port configuration by reading external EEPROM Single Transaction Translator (STT) Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT. Multiple TT provides individual TT control logics for each downstream port. This is a performance better choice for USB 2.0 hub. Please refer to GL852G datasheet for more detailed information. Integrate USB 2.0 transceiver Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down Embed serial resister for USB signals Conform to bus power requirements Automatic switching between self-powered and bus-powered modes Support compound-device (non-removable in downstream ports) by I/O pin configuration Configurable non-removable device support Built-in PLL supports external 12 MHz crystal / Oscillator clock input Built-in 5V to 3.3V regulator Low power consumption Improve output drivers with slew-rate control for EMI reduction Internal power-fail detection for ESD recovery Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 (Not available for SSOP 28 package) Support both individual and gang modes of power management and over-current detection for downstream ports (Individual mode is not supported by SSOP 28 package) Power enable pin supports both low/high-enabled power switches. (Power switch is not supported by GL850G-22 SSOP28 package) Optional 27/48 MHz Oscillator clock input (Not available for QFN28 / SSOP28 package) Number of Downstream port can be configured by GPIO without external EEPROM Available package type: 48 pin LQFP, 28 pin QFN and 28 pin SSOP (Full Function only available in 48 pin) ©2011 Genesys Logic, Inc. - All rights reserved. Page 10 GL850G Datasheet Applications: Stand-alone USB hub PC motherboard USB hub, Docking of notebook Gaming console LCD monitor hub Any compound device to support USB hub function ©2011 Genesys Logic, Inc. - All rights reserved. Page 11 1 2 3 4 5 6 7 8 9 10 11 12 AGND DM0 DP0 DM1 ©2011 Genesys Logic, Inc. - All rights reserved. DP1 AVDD AGND DM2 DP2 RREF AVDD 25 26 27 28 29 30 31 32 33 34 35 36 SEL48 RESET# TEST OVCUR4# PWREN4# OVCUR3# PWREN3# PGREEN3 PAMBER3 DVDD PGREEN2 PAMBER2 CHAPTER 3 AVDD GL850G Datasheet PIN ASSIGNMENT 3.1 Pinouts Figure 3.1 - GL850G LQFP 48 Pin Pinout Diagram Page 12 GL850G Datasheet AVDD 1 28 DP1 DM2 2 27 DM1 DP2 3 26 DP0 RREF 4 25 DM0 AVDD 5 24 V33 X1 6 23 V5 X2 7 22 PWREN1# DM3 8 21 OVCUR1# DP3 9 20 PWREN2# AVDD 10 19 OVCUR2# DM4 11 SSOP - 28 18 PGANG DP4 12 17 PSELF RESET# 13 16 DVDD TEST/SCL 14 15 GND Figure 3.2 - GL850G SSOP 28 Pin Pinout Diagram ©2011 Genesys Logic, Inc. - All rights reserved. Page 13 DM4 15 7 DP2 DP4 16 6 DM2 RESET# 17 5 AVDD TEST/SCL 18 4 DP1 OVCUR4# 19 3 DM1 OVCUR3# 20 2 DP0 21 1 DM0 DVDD GL850G Datasheet Figure 3.3 - GL850G QFN 28 Pin Pinout Diagram ©2011 Genesys Logic, Inc. - All rights reserved. Page 14 GL850G Datasheet 3.2 Pin List Table 3.1 - GL850G LQFP 48 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# I Pin Name Type 1 AVDD P 13 AGND P 25 SEL48 37 PSELF 2 AGND P 14 X1 I 26 RESET# 3 DM0 B 15 X2 O 27 TEST 4 DP0 B 16 AVDD P 28 OVCUR4# 5 DM1 B 17 DM3 B 29 PWREN4# 6 DP1 B 18 DP3 B 30 OVCUR3# 7 AVDD P 19 AVDD P 31 PWREN3# O 43 PWREN1# O 8 AGND P 20 AGND P 32 PGREEN3 O 44 SEL27 I 9 DM2 B 21 DM4 B 33 PAMBER3 O 45 PGREEN1 O 10 DP2 B 22 DP4 B 34 DVDD P 46 PAMBER1 O 11 RREF A 23 PGREEN4 O 35 PGREEN2 O 47 V5 P 12 AVDD P 24 PAMBER4 O 36 PAMBER2 O 48 V33 P I_5V 38 DVDD I 39 PGANG I_5V 40 OVCUR2# O 41 PWREN2# I_5V 42 OVCUR1# I_5V P B I_5V O I_5V Table 3.2 - GL850G SSOP 28 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 AVDD P 8 DM3 B 15 GND P 22 PWREN1# O 2 DM2 B 9 DP3 B 16 DVDD P 23 V5 P 3 DP2 B 10 AVDD P 17 PSELF 4 RREF A 11 DM4 B 18 PGANG 5 AVDD P 12 DP4 B 19 OVCUR2# 6 X1 I 13 RESET# 7 X2 O 14 TEST/SCL I_5V 20 PWREN2#* I/B I_5V 24 V33 B 25 DM0 I_5V 26 DP0 O 27 DM1 21 OVCUR1#* I_5V 28 DP1 P B B B B * Power switch is not supported in GL850G-22 version. Table 3.3 - GL850G QFN 28 Pin List Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 DM0 B 8 RREF A 15 DM4 B 22 PSELF I_5V 2 DP0 B 9 AVDD P 16 DP4 B 23 PGANG B 3 DM1 B 10 X1 I 17 RESET# 4 DP1 B 11 X2 I 18 TEST/SCL 5 AVDD P 12 DM3 B 19 OVCUR4# I_5V 26 SDA B 6 DM2 B 13 DP3 B 20 OVCUR3# I_5V 27 V5 P 7 DP2 B 14 AVDD P 21 DVDD ©2011 Genesys Logic, Inc. - All rights reserved. I_5V 24 OVCUR2# I/B P 25 OVCUR1# 28 V33 I_5V I_5V P Page 15 GL850G Datasheet 3.3 Pin Descriptions Table 3.4 - Pin Descriptions USB Interface DM0,DP0 LQFP 48 Pin 3,4 GL850G SSOP 28 Pin 25,26 QFN 28 Pin 1,2 DM1,DP1 5,6 27,28 DM2,DP2 9,10 DM3,DP3 Pin Name I/O Type Description B USB signals for USPORT 3,4 B USB signals for DSPORT1 2,3 6,7 B USB signals for DSPORT2 17,18 8,9 12,13 B USB signals for DSPORT3 DM4,DP4 21,22 11,12 15,16 B RREF 11 4 8 A USB signals for DSPORT4 A 680Ω resister must be connected between RREF and analog ground (AGND) Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850G Design Guideline. Hub Interface Pin Name LQFP 48 Pin GL850G SSOP 28 Pin QFN 28 Pin OVCUR1~4# 42,40, 30,28 21,19 25,24, 20,19 PWREN1~4# 43,41, 31,29 22,20 -- PGREEN1~4 45,35, 32,23 -- -- PAMBER1~4 46,36, 33,24 -- -- PSELF 37 17 22 PGANG 39 18 23 ©2011 Genesys Logic, Inc. - All rights reserved. I/O Type Description Active low. Over current indicator for DSPORT1~4. I_5V *Over current flag On when OVCUR= low over 3ms. (pu) OVCUR1# is the only over current flag for GANG mode Active low. Power enable output for DSPORT1~4 PWREN1# is the only power-enable output for GANG O mode * Power switch is not supported in GL850G-22 version. Green LED indicator for DSPORT1~4 1,3,4:O *GREEN[1~2] are also used to access the external 2:B EEPROM (pd) For detailed information, please refer to Chapter 5 Amber LED indicator for DSPORT1~4 *Amber[1~2] are also used to access the external O (pd) EEPROM For detailed information, please refer to Chapter 5 0: GL850G is bus-powered I_5V 1: GL850G is self-powered This pin is default put in input mode after power-on reset. Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. B When GL850G is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend Individual input:0, output: 1@normal, 0@suspend Page 16 GL850G Datasheet Clock and Reset Interface GL850G SSOP 28 Pin Pin Name LQFP 48 Pin X1 14 6 10 X2 15 7 11 RESET# 26 13 17 -- -- SEL48/SEL27 25,44 I/O Type QFN 28 Pin Description 12MHz crystal clock input, or 12/27/48MHz clock input O 12MHz crystal clock output Active low. External reset input, default pull high 10KΩ I_5V When RESET# = low, whole chip is reset to the initial state SEL48/SEL27: 0 1: 48MHz OSC-in I 1 0: 27MHz OSC-in 1 1: 12MHz X’tal/OSC-in I System Interface GL850G SSOP 28 Pin Pin Name LQFP 48 Pin TEST/SCL 27 14 18 SDA -- -- 26 QFN 28 Pin I/O Type Description I (pd) B B TEST: 0: Normal operation. (Internal pull down) 1: Chip will be put in test mode. I2C:clock output pin (SSOP 28pin/QFN 28pin only) I2C: data pin Power / Ground Pin Name LQFP 48 Pin GL850G SSOP 28 Pin QFN 28 Pin I/O Type Description AVDD 1,7,12, 16,19 1,5,10 5,9,14 P 3.3V analog power input for analog circuits AGND 2,8,13, 20 -- -- P Analog ground input for analog circuits DVDD 34,38 16 21 P 3.3V digital power input for digital circuitsLL GND -- 15 -- V5 47 23 27 P V33 48 24 28 P Ground 5V Power input. It need be NC if using external regulator 5V-to-3.3V regulator Vout (LQFP48) 5V-to-3.3V regulator Vout & 3.3 input (SSOP28/QFN28) It can be NC or connect to 3.3V power if using external regulator (LQFP48 only) Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850G Design Guideline. ©2011 Genesys Logic, Inc. - All rights reserved. Page 17 GL850G Datasheet Notation: Type O I I_5V B B/I B/O P A SO pu pd odpu Output Input 5V tolerant input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up ©2011 Genesys Logic, Inc. - All rights reserved. Page 18 GL850G Datasheet CHAPTER 4 BLOCK DIAGRAM Figure 4.1 - GL850G Block Diagram (Single TT) ©2011 Genesys Logic, Inc. - All rights reserved. Page 19 GL850G Datasheet CHAPTER 5 FUNCTION DESCRIPTION 5.1 General Description 5.1.1 USPORT Transceiver USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and high-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. USPORT transceiver will operate in full-speed electrical signaling when GL850G is plugged into a 1.1 host/hub. USPORT transceiver will operate in high-speed electrical signaling when GL850G is plugged into a 2.0 host/hub. 5.1.2 PLL (Phase Lock Loop) GL850G contains a 40x PLL. PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help in generating high speed signal without jitter. 5.1.3 FRTIMER This module implements hub (micro) frame timer. The (micro) frame timer is derived from the hub’s local clock and is synchronized to the host (micro)frame period by the host generated Start of (micro)frame (SOF). FRTIMER keeps tracking the host’s SOF such that GL850G is always safely synchronized to the host. The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 μC μC is the micro-processor unit of GL850G. It is an 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, μC can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub. These configurations include self/bus power mode setting, individual/gang mode setting, downstream port number setting, device removable/non-removable setting, and PID/VID setting. 5.1.5 UTMI (USB 2.0 Transceiver Microcell Interface) UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion. 5.1.6 USPORT Logic USPORT implements the upstream port logic defined in section 11.6 of USB specification Revision 2.0. It mainly manipulates traffics in the upstream direction. The main functions include the state machines of Receiver and Transmitter, interfaces between UTMI and SIE, and traffic control to/from the REPEATER and TT. 5.1.7 SIE (Serial Interface Engine) SIE handles the USB protocol defined in chapter 8 of USB specification Revision 2.0. It co-works with Μc to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow, CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in UTMI, not in SIE. 5.1.8 Control/Status Register Control/Status register is the interface register between hardware and firmware. This register contains the information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based architecture, GL850G possesses higher flexibility to control the USB protocol easily and correctly. ©2011 Genesys Logic, Inc. - All rights reserved. Page 20 GL850G Datasheet 5.1.9 REPEATER Repeater logic implements the control logic defined in section 11.4 and section 11.7 of USB specification Revision 2.0. REPEATER controls the traffic flow when upstream port and downstream port are signaling in the same speed. In addition, REPEATER will generate internal resume signal whenever a wakeup event is issued under the situation that hub is globally suspended. 5.1.10 TT (Transaction Translator) TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850G adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852G adopts multiple TT architecture to provide the most performance effective solution. Multiple TT provides control logics for each downstream port respectively. Please refer to GL852G datasheet for more detailed information. 5.1.11 REPEATER/TT Routing Logic REPEATER and TT are the major traffic control machines in the USB 2.0 hub. Under situation that USPORT and DSPORT are signaling in the same speed, REPEATER/TT routing logic switches the traffic channel to the REPEATER. Under situation that USPORT is in the high speed signaling and DSPORT is in the full/low speed signaling, REPEATER/TT routing logic switches the traffic channel to the TT. 5.1.11.1 Connected to USB 1.1 Host/Hub If an USB 2.0 hub is connected to the downstream port of an USB 1.1 host/hub, it will operate in USB 1.1 mode. For an USB 1.1 hub, both upstream direction traffic and downstream direction traffic are passing through REPEATER. That is, the REPEATER/TT routing logic will route the traffic channel to the REPEATER. USB 1.1 HOST/HUB USPORToperating in FS signaling Traffic channel is routed to REPEATER REPEATER TT DSPORT operating in FS/LS signaling Figure 5.1 - Operating in USB 1.1 Scheme ©2011 Genesys Logic, Inc. - All rights reserved. Page 21 GL850G Datasheet 5.1.11.2 Connected to USB 2.0 Host/Hub If an USB 2.0 hub is connected to an USB 2.0 host/hub, it will operate in USB 2.0 mode. The upstream port signaling is in high speed with bandwidth of 480 Mbps under this environment. The traffic channel will then be routed to the REPEATER when the device connected to the downstream port is signaling also in high speed. On the other hand, the traffic channel will then be routed to TT when the device connected to the downstream port is signaling in full/low speed. USB 2.0 HOST/HUB USPORToperating in HS signaling HS vs. HS: Traffic channel is routed to REPEATER REPEATER TT DSPORT operating in HS signaling HS vs. FS/LS: Traffic channel is routed to TT DSPORT operating in FS/LS signaling Figure 5.2 - Operating in USB 2.0 Scheme 5.1.12 DSPORT Logic DSPORT (downstream port) logic implements the control logic defined in section 11.5 of USB specification Revision 2.0. It mainly manipulates the state machine, the connection/disconnection detection, over current detection and power enable control, and the status LED control of the downstream port. Besides, it also output the control signals to the DSPORT transceiver. 5.1.13 DSPORT Transceiver DSPORT transceiver is the analog circuit that supports high-speed, full-speed, and low-speed electrical characteristics defined in chapter 7 of USB specification Revision 2.0. In addition, each DSPORT transceiver accurately controls its own squelch level to detect the detachment and attachment of devices. ©2011 Genesys Logic, Inc. - All rights reserved. Page 22 GL850G Datasheet 5.2 Configuration and I/O Settings 5.2.1 RESET Setting GL850G’s power on reset can either be triggered by external reset or internal power good reset circuit. The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or 5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested value refers to schematics) GL850G’s internal reset is designed to monitor silicon’s internal core power (3.3V) and initiate reset when unstable power event occurs. The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 2.7 uS after power good. GL850G internally contains a power on reset circuit as depicted in the picture above Figure 5.3 - Power on Reset Diagram Figure 5.4 - Power on Sequence of GL850G ©2011 Genesys Logic, Inc. - All rights reserved. Page 23 GL850G Datasheet Table 5.1 - Reset Timing Symbol TPG T1 T2 Parameter Min. Max. VDD power up to internal reset (power good) assert (12MHz) - VDD power up to internal reset (power good) assert (24MHz) - 2.7 1.3 VDD power up to internal reset (power good) assert (27MHz) - 1.2 VDD power up to internal reset (power good) assert (48MHz) - 0.7 VDD power up to external reset (RESETJ) assert 3 - μs 70 - ms RESET assert to respond USB command ready Unit μs To fully control the reset process of GL850G, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. 5.2.2 PGANG/SUSPND Setting To save pin count, GL850G uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL850G outputs the suspend flag once it is globally suspended. For individual mode, a pull low resister greater than 100KΩ should be placed. For gang mode, a pull high resister greater than 100KΩ should be placed. In figure 5.5, we also depict the suspend LED indicator schematics. It should be noticed that the polarity of LED must be followed, otherwise the suspend current will be over spec limitation (2.5mA). Figure 5.5 - Timing of PGANG/SUSPEND Strapping ©2011 Genesys Logic, Inc. - All rights reserved. Page 24 GL850G Datasheet GANG Mode DVDD(3.3V) "0": Individual Mode "1": GANG Mode DVDD(3.3V) 100K ohm Suspend LED Indicator SUSPNDO GANG_CTL 100K ohm Suspend LED Indicator Inside GL850G On PCB Individual Mode Figure 5.6 - Individual/GANG Mode Setting ©2011 Genesys Logic, Inc. - All rights reserved. Page 25 GL850G Datasheet 5.2.3 SELF/BUS Power Setting GL850G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850G can be configured as a bus-power or a self-power hub. 1: Power Self PSELF 0: Power Bus Inside GL850G On PCB Figure 5.7 - SELF/BUS Power Setting 5.2.4 LED Connections GL850G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0. Both manual mode and Automatic mode are supported in GL850G. When GL850G is globally suspended, GL850G will turn off the LED to save power. AMBER/GREEN LED DGND Inside GL850G On PCB Figure 5.8 - LED Connection 5.2.5 EEPROM Setting GL850G replies to host commands by the default settings in the internal ROM. GL850G also offers the ability to reply to the host according to the settings in the external EEPROM (LQFP48 supports 93C46 and QFN28/SSOP28 only supports 24C02). The detail setting information please refers to the GL850G AP Note_EEPROM Info document. The schematics between GL850G and 93C46 are depicted in the following figures: ©2011 Genesys Logic, Inc. - All rights reserved. Page 26 GL850G Datasheet DVDD EE_CS CS VCC EE_SK SK NC EE_DI DI NC EE_DO DO GND 93C46 Figure 5.9 - Schematics between GL850G and 93C46 GL850G firstly verifies the check sum after power on reset. If the check sum is correct, GL850G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. 5.2.6 Power Switch Enable Polarity (Only Available in LQFP48 Package) Both low/high-enabled power switches are supported. It is determined by jumper setting, based on the state of pin AMBER2, as the following table: Table 5.2 - Configuration by Power Switch Type AMBER2 Power Switch Enable Polarity 0 Low-active 1 High-active Note: When AMBER2=1, the external resistor of PWREN1~4 need pull down. 5.2.7 Port Number Configuration (Only Available in LQFP48 Package) Number of downstream port can be configured as 2/3/4 ports by pin strapping in addition to EEPROM, based on the state of pin AMBER 3, AMBER 4, as the following table: Table 5.3 - Port Number Configuration AMBER3 AMBER 4 Port Number 1 0 2 0 1 3 0 0 4 ©2011 Genesys Logic, Inc. - All rights reserved. Page 27 GL850G Datasheet 5.2.8 Non-removable Port Configuration (Only Available in LQFP48 Package) For compound application or embedded system, downstream ports that always connected inside the system can be set as non-removable based on the state of corresponding status LED, pin GREEN 1~4. If the pin is pull high in the initial stage (POR reset), the corresponding port will be set as non-removable. 5.2.9 Reference Clock Configuration (Only Available in LQFP48 Package) GL850G can support optional 27/48MHz clock source, which is selectable through GPIO configurations. For some on-board design that 27/48MHz clock source is available, such as motherboard or Monitor built-in applications, system integrator can leverage this feature to further reduce BOM cost by removing external crystal. Table 5.4 - Ref. Clock Configuration SEL48 SEL27 Clock Source 0 1 48MHz OSC-in 1 0 27MHz OSC-in 1 1 12MHz X’tal/OSC-in ©2011 Genesys Logic, Inc. - All rights reserved. Page 28 GL850G Datasheet CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Maximum Ratings Table 6.1 - Maximum Ratings Symbol Min. Max. Unit 5V Power Supply -0.5 +6.0 V VDD 3.3V Power Supply -0.5 +3.6 V VIN Input Voltage for digital I/O pins -0.5 +3.6 V VINOD Open-drain input pins(Ovcur1~4#,Pself,Reset) -0.5 +5.5 V VINUSB Input Voltage for USB signal (DP, DM) pins -0.5 +3.6 V +100 o V5 TS FOSC Parameter Storage Temperature under bias -55 C 12 MHz 0.05% Frequency 6.2 Operating Ranges Table 6.2 - Operating Ranges Symbol Min. Typ. Max. Unit 5V Power Supply 4.75 5.0 5.25 V VDD 3.3V Power Supply 3.0 3.3 3.6 V VIN Input Voltage for digital I/O pins -0.5 - 3.6 V VINOD Open-drain input pins(Ovcur1~4#,Pself,Reset) -0.5 - 5.0 V VINUSB Input Voltage for USB signal (DP, DM) pins 0.5 - 3.6 V 85 o 125 o V5 TA TJ Parameter Ambient Temperature Absolute maximum junction temperature Thermal Characteristics 48 LQFP θJA Thermal Characteristics 28 SSOP Thermal Characteristics 28 QFN ©2011 Genesys Logic, Inc. - All rights reserved. 0 0 - 83.5 63.3 34.5 C C - o - o - o C/W C/W C/W Page 29 GL850G Datasheet 6.3 DC Characteristics Table 6.3 - DC Characteristics except USB Signals Symbol Parameter Min. Typ. Max. Unit 366.5 - 426.5 mW PD Power Dissipation VIL LOW level input voltage - - 0.8 V VIH HIGH level input voltage 2.0 - - V VTLH LOW to HIGH threshold voltage 1.4 1.5 1.6 V VTHL HIGH to LOW threshold voltage 0.87 0.94 0.99 V VOL LOW level output voltage when IOL=8mA - - 0.4 V VOH RDN RUP HIGH level output voltage when IOH=8mA Pad internal pull down resister Pad internal pull up resister 2.4 29 80 59 108 135 140 V KΩ KΩ Table 6.4 - DC Characteristics of USB Signals under FS/LS Mode Symbol Parameter Min. Typ. Max. Unit VOL DP/DM FS static output LOW(RL of 1.5K to 3.6V ) 0 - 0.3 V VOH DP/DM FS static output HIGH (RL of 15K to GND ) 2.8 - 3.6 V VDI Differential input sensitivity 0.2 - - V VCM Differential common mode range 0.8 - 2.5 V VSE Single-ended receiver threshold 0.2 - - V CIN Transceiver capacitance - - 20 Pf ILO Hi-Z state data line leakage -10 - +10 A Driver output resistance 28 - 44 Ω ZDRV Table 6.5 - DC Characteristics of USB Signals under HS Mode Symbol Parameter Min. Typ. Max. Unit VOL DP/DM HS static output LOW(RL of 1.5K to 3.6V ) - - 0.1 V CIN Transceiver capacitance 4 4.5 5 Pf ILO Hi-Z state data line leakage -5 0 +5 A Driver output resistance for USB 2.0 HS 42 45 48 Ω ZDRV ©2011 Genesys Logic, Inc. - All rights reserved. Page 30 GL850G Datasheet 6.4 Power Consumption Table 6.6 - DC Supply Current Symbol Condition Active ports ISUSP Host Suspend 4 3 2 1 USPORT Config. Typ. Unit 753 uA * F 85.3 mA * H 70.3 mA H F 82.2 mA F F 83.4 mA H H 71 mA H F 80.3 mA F F 80.9 mA H H 71.9 mA H F 78.2 mA F F 78.3 mA H H 72.6 mA H F 75.7 mA F N/A 75.6 mA H N/A 73.3 mA F ICC Device H *: F: Full-Speed, H: High-Speed Note: Test result represents silicon level operating current, without considering additional power consumption contributed by external over-current protection circuit such as power switch or polyfuse. ©2011 Genesys Logic, Inc. - All rights reserved. Page 31 GL850G Datasheet 6.5 AC Characteristics GL850G LQFP48 package supports 93C46 EEPROM for customized VID/PID. GL850G QFN28 and SSOP28 package supports 24C02 type EEPROM. AC characteristics of these two types of EEPROM summarized as below figures and tables. 6.5.1 93C46 EEPROM IF Table 6.7 - AC Characteristics of EEPROM Interface (93C46) Symbol Parameter Min. Typ. Max. tCSS CS Setup Time 3.0 tCSH CS Hold Time 3.0 tSKH SK High Time 1.0 tSKL SK Low Time 2.2 tDIS DI Setup Time 1.8 tDIH DI Hold Time 2.4 tPD1 Output Delay to “1” 1.8 tPD0 Output Delay to “0” 1.8 ©2011 Genesys Logic, Inc. - All rights reserved. Units us Page 32 GL850G Datasheet 6.5.2 24C02 EEPROM Interface Table 6.8 - AC Characteristics of EEPROM Interface (24C02) ©2011 Genesys Logic, Inc. - All rights reserved. Page 33 GL850G Datasheet 6.6 On-Chip Power Regulator GL850G requires 3.3V source power for normal operation of internal core logic and USB physical layer (PHY). The integrated low-drop power regulator converts 5V power input from USB cable (Vbus) to 3.3V voltage for silicon power source. The 3.3V power output is guaranteed by an internal voltage reference circuit to prevent unstable 5V power compromise USB data integrity. The regulator’s maximum current loading is 200mA, which provides enough tolerance for normal GL850G operation (below 100mA). On-chip Power Regulator Features: 5V to 3.3V low-drop power regulator 200mA maximum output driving capability Provide stable 3.3V output when Vin = 4.4V~5.5V Max. suspend current:266uA; typical suspend current 187uA Figure 6.1 - Vin(V5) vs Vout(V33)* *Note: Measured environment: Ambient temperature = 25℃ / Current Loading = 200mA ©2011 Genesys Logic, Inc. - All rights reserved. Page 34 GL850G Datasheet CHAPTER 7 Internal No. PACKAGE DIMENSION Green Package + AU Wire Version No. GL850G AAAAAAAGAA YWWXXXXXXXX Date Code Lot Code Figure 7.1 - GL850G 48 Pin LQFP Package ©2011 Genesys Logic, Inc. - All rights reserved. Page 35 GL850G Datasheet Package GL850G Green + AU Wire AAAAAAAGAA Version No. YWWXXXXXXXX Internal No. Date Code Lot Code Figure 7.2 - GL850G 28 Pin SSOP Package ©2011 Genesys Logic, Inc. - All rights reserved. Page 36 GL850G Datasheet Internal No. Version GL850G No. AAAAAAA YWWXXXX Date Code Lot Code Figure 7.3 - GL850G 28 Pin QFN Package ©2011 Genesys Logic, Inc. - All rights reserved. Page 37 GL850G Datasheet CHAPTER 8 ORDERING INFORMATION Table 8.1 - Ordering Information Part Number Package Green/Wire Material Version Status GL850G-MNGXX LQFP 48 Green Package + AU Wire XX Available GL850G-HHGXX SSOP 28 Green Package + AU Wire XX Available GL850G-OHG*XX QFN 28 Green Package + AU Wire XX Available *The marking of "OHG" will not be shown on the IC due to QFN 28 package size limitation. ©2011 Genesys Logic, Inc. - All rights reserved. Page 38