反激式开关电源 新 型控 制器 lCE1Qso1 工作原 理及应用 王 守志 东临沂师范学院工程 学院 山 摘要 :ICE1Qs01是 英飞凌公 司新推 出的支持低功率待机和功率因数校正 (PFC)的 开关型电源 (sMPs) 准谐振控制器单片 IC。文中介绍了 ICE1Qs01的 基本结构 、功能原理及由其控制的 TV回 扫式 sMPs电 路。 关键 词 :IcE1Qs01 反 激变换器 数 字处理 待 机突发模式 Tv电 源 1概 述 ICE1Qso1是 英飞凌公司推出的一种新型带有 或不带功率因数校正 (PFC)的 反激式变换器控制 器 。该控制器 IC适 合于输 出功率范围从 1W到 3OW的 TV、 VCR、 DV播 放 机 、 卫 星 接 收 机 和突发模式控制 电路 以及折 回 (fold back)点 校正 及振铃 (ringing)抑 制 电路 。 ˉˉˉ冖■ NC ˉ VCC 、 笔记本 电脑适配器及其它 消费类 电子产 品中应用 。 ICE1Qso1为 在轻载 下提供低功率消耗 ,开 关 频率 随负载减 小数 字式地逐步减 小到 20KIIZ。 同 时 ,随 频率 降低保持准揩振模式 。在从满载到空载 范 围 内 ,能 够平稳 工 作 。一 个数字抗抖动 电路 ,可 以消除随定期脉动 负载产生 的任何颤动 。为在轻载 PCs UT ○ lC E1QsOl Rz丨 GND sRC 0FC 图 1 引 脚排例 下提供非常低 的功耗 ,IC可 以转换进入 待机突发模 式 。对于在适配器 中应用 ,可 以没有待机控 制信 号 。 ICE1QSo1的 启动 电流仅约 ⒛ uA° 为减 小乃至消除 外部功率 MOsFET的 开关应力 ,功 率 晶体管总是 在最低 的 电压上接通 。IC的 保护功 能包括 Vcc过 电 压与欠 电压 、AC线 路欠 电压和 电流 限制等 。利用 内部误差放大器或利用 光耦合器反馈 ,来 执行 电压 调节 。在整个适用功率范 围内,待 机输入功率远低 于 1W。 2基 本 结 构 及 主 要 功 能 与 特 点 2.1基 本结构 与引脚功 能 ICE1QS01采 用 8引 脚 PDIP封 装 ,引 脚排列 1所 。 如图 示 ICE1QS01芯 片 电路组成框 图如 图 2所 示 。 与传 统 反激 式 变 换 器 初 级 控 制 器 IC比 较 , ICE1QSo1的 芯片 电路主要特 点是设置 了数字处理 2004年 第 3期 (总 第 40期 )《 中@昀 塬博 宽》 1″ ∞ 图 2 ICE1Qs01的 C∞ "σ 加 减 计 放 番 芯 片电路组成框 图 Chlnc .Fourr Snpplg Surrrg C ICE1Qso1的 引脚 I 各引脚功能如 附表所列。 附表 引脚功能 功能简述 符号 N・ C 未连接 PCs 的存储器与 IC脚 RZI上 过零电流数相比较,如 果 过零 电流数 与加/减计数器 的寄存数相 等 ,功 率 MOSFET则 。 在 低 载 下 导 通 ,若 VsRc(3.5ˇ RzI 初级 电流模拟 (simulation)输 入 过 零信 号输入与 (初 级 )调 整端 sRC 调整与软启动 电容连接端 每隔 sOms加 1。 其结果使 MOSmT的 长和 占空 比减小 。当 VsRc>4,4V时 ⒛ms减 1。 在此情况下,MOSFET关 oFC 过 电压 故障 比较器 (同 相 )输 入 端 开 关 抖 动 可 被 消 除 6 GND 地 7 oUT 驱动器 输 出 VCC 电源 电压施加端 4 截止时间延 ,计 数器每隔 断时间缩短, 3.5V(VsRc(4.4Ⅴ 时 ,计 供低功率待机 操作 ,并 允许 以 PFC电 荷泵 电路为特 AC输 入 电流 的正弦控 制 。为保证在 征 的 sMPS的 时提供满功 率 。由 VsRc提 供 的信息被 存储在两个独 立 的触发器 中,一 个 内部定时器 产 生 一 个触发脉冲 并带 50ms的 周期 。每 当脉冲发生 时 ,加 /减 计数器 检查状态触发器 。在该脉冲之后 ,触 发器被复 位 。 图 4说 明 了加/减 计数器 的特性 。 过增加 被 省略 的过零信 号数 目随负载减 轻而逐步 降低 开关频率 。 在变压器退磁 结束 与下 一 个 开关周期开始之 间,发 生 中止 ,保 证 从最大 负载到空载整 个 范 围与 sMPs 的频率之 间有 一 个最佳 的一 致性 。图 3示 出了负 载 (输 出功率 )与 开关频率之 间的关系 曲线 。在 图 3 中,⑴ 表示满载 下第 — 个过零信 号 出现 时负载 开始 减 小 ,频 率相应开始 降低 。 dl表 示省略六个过 零信 号 ,在 第七次过零 时负载和频 率变化情况 。在无载 情况下 ,频 率 降至 20KHz的 图 4 力 口/减 可逆计数 器特性 最小值 。 图 5 突 发模 式相 关波 形 Vpcs市 'il」宀 `| 图 3 负 载依 从 的频 率 曲线 在 ICE1QSo1中 的抗抖动 电路保证 一 定程度 的 滞后 ,以 避免在周 期长度之 间迅速 开关 ,并 保证在 恒定负载或 平稳定期变化 负载下动 行 时,被 省略的 过零数相 同 。在轻载下通过 省略变压器退 磁之后 的 过零信 号来降低频 率 。IC脚 SRC上 的电压 VsRc决 定 4位 加/减 (可 逆 )计 数器 的动作 。加/减计数器 Chfnc Pouar Sqp1lly Snrrng 数 器停止计数 。假如发生页 载跳跃并且 VsRc)4.8V, 加/减 计数器迅速 置位 到 1(000D,以 保 证 能在瞬 2.2主 要功 能与特 点 2.2.1数 字频率 降低 一 重要 ICE1QS01的 个 特 性是 自由振 荡 (】cc mnning)SMPs的 负载依赖于频 率 响应 。该功 能提 轻载下仍保持 高效率 ,ICE1QSo1通 。 在 计 数 器 ˉ ˉ H>l ~ˉ ◆ ˇ mdn` 图 6 带 折 回`点校 正与不带时电压 VPcs和 最 大功率 PMAx比较 ⒛ ∝ 年 第 3期 (总 第 们 期 )《 中0咆 塬 博 览》 四 lC02sFH617A-2 l0n`0tXlˇ 男 华 图 7由 器 △ ICE1QS01控 制 的 120W TV电 源 电路 El a ff ppc ri zoowrv svrpstr& 2.2.2突 发模式 Vcc(。 为使轻载下的功耗减小到最低,ICE1QS01可 以被置于待机突发模式 。突发模式 由 IC脚 SRC上 的 (初 级 )调 整电压或次级反馈 电压 ⅤsRc控 制 。只 要 VsRc降 至 2V以 下,IC就 进入突发模式。在激活 突发模式比较器之后,栅 极驱动器输出低 电平,功 率 MOS∏ 是 15V,关 比 较 m ⒛ r载 器 止 闭 启 动 门 ,Vcc(。 ∝ 年 第 3期 。在 限 常 态 下 Vcc(。 FF)是 FF)将 由 ,Vcc导 通 9Ⅴ 9V增 。 加 门 一 到 旦 限 突 Vcc(。 发 14.5V,而 (总 第 00期 )《 中国 咆 塬 博 览》 bl〉 模 式 进 为 N)仍 入 启 动 模 式 15V。 。 如 一 旦 果 Vcc达 Vcc达 到 到 Vcc(。 Vcc(。 N)门 FF),IC将 限 ,IC再 次开始接通 。IC在 突发期间,接 通时间至少为最大 接通时间的 1″。图 5为 IC突 发模式下的相关波形。 2,2.3折回点校正 (Fdd bⅡk0o吨 ∞rrection) 随主电源 (m缸ns)电 压升高,开 关接通时间变短, 频率升高,致 使最大输出功率增大,功 率 MOS田 T 损坏的可能性增加。为避免这种情况发生,IC内 置 折回点校正电路,经 Vcc偏 置绕组和连接到 RZI脚 Chlna .PtorPr Sqpplgt Sut.gtgr Fec九 屁 o饣oσ u ReseGrc九 &垒 凼 姒 ∞ 磁 o⒏ 上 的一 支 电阴来感测主 线 电压 。在 MOsFET导 刂 通 接 ,开 PzI被 。 间 期 关 电流 从脚 抽 取 当该 电流 大于 可 的 电阻 R22和 脚 2上 的接地 电容 C” ,固 定最大 能输 出功率 ,并 且 R22决 定 AC主 线欠 电压锁定 ⒛ 0uA时 限 。 ,高 出 500uA这 部 份 电 流 的 Ⅳ5通 过 IC 门 脚 PCs该 脚外部电容充电,使 PCS脚 上电压 VPcs 的斜率升高,结 果是 MOsFET的 导通时间减小, 最大可能输出功率不再随主电压升高而增大,而 保 持在一个不变的功率电平上,如 图 6所 示 。 3应 用 电路 实例 31120W TV s"Ps电 用 ICE1QS01作 路 控制器 的 12W TV sMPS电 3 2 荦 者 PFC自 勺 200W TV sⅢ 带 PFC的 。 O/V 、 A ∞ ” .O/V04 、 A 绣 .O/V41 和 A 路 波 。 A24.0/V7 极 IC1(ICE1QSo1)内 部集成的突发待机模式电路 , 保证待机输入功率远低于 1W。 当开关 S1和 s2闭 入待机突发模式 。待机输出电流能 合时,SMPs进 够从 14W输 出 V4上 汲取,该 电流使 V1从 正常模 式的 137V降 低到 7V左 右 (即 约减小到 Ⅳ20),Ⅴ 4 降低值 由齐纳二极管 D62决 定 。当开关 s1闭 合但 S2断 开时,齐 纳 二 极管 D61提 供过 电压保护 。 IC1脚 2与 脚 7之 间连接 的电容 C⒛ 与脚 2上 电容 C21组 成 电压分压器 ,用 作减短功率 MOs田 T (TQ1)在 突发模式下 的导通 时间 。这种方法可 提 高 sMPs频 率 ,减 小变压器磁化 强度 ,避 免变压器 可 扣 见 的噪声产 生 。 为提 高 突 发 频 率 ,在 输 入 端 EMI滤 波器扼流 圈 L01之 后与 二 极管 D⒛ 和 DzT 连接 点之 间连接 的电容 C21,充 当一 个容性启动 电 流源 。为整流通过 C21的 AC电 流 ,二 极管 D冗 和 D” 是必须加入 的 。在 IC1脚 2和 DC干 线之 间连 200W TV SMPs电 路 如 图 8所 示 。 在 TQ1漏 极与 L08和 D08之 间连接的电容 C08E 及 L08、 D08组 成 电荷泵 PFC电 路 。电荷泵 电路加 在 电容 COT之 前 ,加 大 了桥式整流 二 极管 的导通角 , 使 AC输 入 电流不再是尖峰脉 冲 ,而 十分接近 正弦 如 图 7所 示 。 该 电源 AC线 路 输 入 电压 范 围为 18仁 976V,次 边五路 DC输 出分别为 :137W0.5A、 出 ” Ps ,故 系统功率 因数达 0,9以 上 。 当开关 Sl断 开时 ,参 考 二 极管 D60导 通 ,输 电压 V2被 调节 ,并 全其 数值 由齐纳 (稳 压 )二 管 时 出 发 被 输 设 16D 定 。 当 脚 1CI 上 4 的 反 馈 电 压 低 于 V2 ,IC1中 的突发模式电路被激活 。当 s1闭 合但输 V1无 载时,二 极管 D62决 定正常模式与待机突 模式之间的过渡状态。当输出 V2降 低时,D60 关断 。IC1内 部低功率待机突发模式电路,保 证 入待机功率小于 1W。 在页载降低时,随 集成数 字 处理电路,开 关频率逐步降低 。随负载变化,在 TV应 用 中 电电路不会产生 任何抖动 ,从 而 防止 了 图 像 失真 。 4结 束 语 ICE1QSo1在 带或不带 PFC电 荷泵 电路的反激 式变换器中应用,具 有低于 1W的 空载待机功耗 。 这种准谐振控制器被用作设计直达 ⒛0W的 TV等 消费类视听电子产品 SMPs,被 业 界认为是一种优 选器件,并 得到用户认可。◆ D a t a s he et , V 1 . 4 , 2 7 A p ri l 2 00 4 ICE 1QS01 Controller for Quasiresonant Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction Pow er Mana geme nt & Sup ply N e v e r s t o p t h i n k i n g . ICE1QS01 Revision History: Current Version: 200404-27 Previous Version: 200311-28 Page13 (in Page 13 (in previous version) current version) Diagram mains undervoltage lockout curent added Page 16-18 (in Page 16-18 (in previous version) current version) Min.- max.- values added, typ. values adapted, according to measuring results. Page 20 (in Page 20 (in previous version) current version) Application circuit changed to new 250 W demo board with PFC current pump. Edition 2004-04-27 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München © Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons ICE1QS01 Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction (PFC) P-DIP-8-4 Features P-DIP-8-4 • • • • • • • • • • • • • • Quasiresonant Operation Primary and Secondary Regulation Primary Current Simulation Standby Input Power < 1 W Low Power Consumption Very Low Start-up Current Soft-Start for noiseless Start-up Standby Burst Mode with and without Control Signal for lowered Output Voltages Digital Frequency Reduction in small Steps at Decreasing Load Over- and Undervoltage Lockout Switch Off at Mains Undervoltage Mains Voltage Dependent Fold Back Point Correction Ringing Suppression Time Controlled from Output Voltage Free usable Fault Comparator P-DSO-8-3 P-DSO-8-3 Functional Description The ICE1QS01 is optimized to control free running flyback converters with and without Power Factor Correction (with PFC Charge Pump). The switching frequency is reduced in small steps with decreasing load towards a minimum of 20 kHz in standby mode. This function is performed by a digital circuit to avoid any jitter also with periodically pulsed loads. To provide extremely low power consumption at light loads, this device can be switched into Standby Burst Mode. This is also possible without standby control signal (for adapter application). Additionally, the start up current is very low. To avoid switching stresses of the power devices, the power transistor is always switched on at minimum voltage. The device has several protection functions: VCC overand undervoltage, mains undervoltage and current limiting. Regulation can be done by using the internal error amplifier or an opto coupler feedback. The output driver is ideally suited for driving a power MOSFET. The ICE1QS01 is suited for TV-sets, DVD- sets, SAT- receivers and other consumer applications in the power range from 0 to app. 300 W. Type ICE1QS01 ICE1QS01G Version 1.4 Ordering Code Q67040-S4558 Q67040-S4559 3 Package P-DIP-8 P-DSO-8 27 Apr 2004 ICE1QS01 Block Diagram VCC Overvoltage 20V - Foldback Point Corr. Protection + PCS UVLO + - - + SRC + Burst-Mode 1.5V Reference Voltage and Current + 5V - - 2V + 1V Ringing Suppression Time + 4.8V 5V - 20k + 4.5V Start 5V + 3.5V - 50µs Timer 50ms Timer 50mV Latch Primary Regulation + RZI Digital Processing - ZC-Counter UP/DO-Counter 5.7V Power Driver S SET OUT Q 1V OFC R CLR Q + + D 1V SET Q - L CLR Q GND Version 1.4 4 27 Apr 2004 ICE1QS01 Pinning Pin Symbol Function 1 N.C. 2 PCS Primary Current Simulation 3 RZI Regulation and Zero Crossing Input 4 SRC Soft-Start and Regulation Capacitor 5 OFC Overvoltage Fault Comparator 6 GND Ground 7 OUT Output 8 VCC Supply Voltage Pin Configuration (top view) 1 N.C. VCC 8 1 2 PCS OUT 7 2 3 RZI GND 6 4 SRC OFC 5 Version 1.4 5 VCC 8 PCS OUT 7 3 RZI GND 6 4 SRC OFC 5 27 Apr 2004 ICE1QS01 Functional Description Start up An internal start up diode is connected between pin PCS and pin VCC. Start up current is provided via this diode if VPCS is higher than VCC + VBE (VBE = Base-Emitter-Voltage). During start up the internal reference of the IC is shut off and current consumption is about 60 µA. There is only the start up circuitry working which determines the VCCon threshold. Gate driver OUT is switched to low. An active shut down circuitry ensures that OUT is held below the MOS gate threshold when the IC is in start up mode. Block Diagram: Start Up VCC PCS UVLO OUT ICE1QS01 Version 1.4 6 27 Apr 2004 ICE1QS01 Soft start The internal reference of the IC is switched on when VCC exceeds the VCCon threshold. The IC begins to work with soft start mode. Soft start is realized with an internal soft start resistor, an internal current sink, a current source and the external feedback capacitor connected at pin SRC. The internal resistor is connected between the internal voltage reference and pin SRC. The current sink is connected between pin SRC and GND. The value of the current is set with a timer. Immediately after the IC is switched on the capacitor CSRC is charged with a current source up to 2.5V. This current source is switched off 12 µsec after beginning of soft start. The current value of the current sink is set with a timer. Every three msec the current of the current sink is reduced and so VSRC can increase stepwise. The soft start is finished 24 msec after the IC is switched on. At the end of the soft start the current sink is switched off. Figure: Soft Start VCC 2.5V ICE1QS01 5V 500 VCCon timer t=12us t timer tp=3ms timer t=24ms up down counter D/A 20k current sink VSRC pin SRC VSRC2 VSRC1 ton tp1 tp2 t PCS (primary current simulation) A voltage proportional to the current of the power transistor is generated at Pin PCS by the RC-combination R2, C2. The voltage at Pin PCS is forced to 1.5V when the power transistor is switched off and during its switch on time C2 is charged by R2 from the rectified mains. The relation of VPCS and Version 1.4 7 27 Apr 2004 ICE1QS01 the current in the power transistor (Iprimary) is: × IprimaryVPCS = 1, 5V + Lprimary ------------------------------------------------------R2 × C2 Lprimary: Primary inductance of the transformer The advantage of primary current simulation is the elimination of the leading edge spike, which is generated when the power transistor is switched on. RZI (zero crossing input and primary regulation) Zero current counter Every time when the falling voltage ramp of VRZI crosses the 50 mV threshold a pulse is sent to the zero-current-counter and increases the counter by one. If zero-current-counter and up-down-counter are equal the gate drive OUT is switched to high. Up-down counter is influenced via SRC voltage as described below. If VRZI is greater than 50 mV gate drive OUT is always switched low. Figure: Zero Crossing Switching Behaviour V VSRC VPCS 1.5V t VRZI OUT Version 1.4 status up-down counter = 0001: switch on at first zero crossing status up-down counter = 0010: switch on at second zero crossing t ton ton t toff 8 toff 27 Apr 2004 ICE1QS01 Ringing suppression When VPCS reaches the feedback voltage VSRC the gate drive OUT is set to low and the ringing suppression timer is started. This timer ensures that the gate drive cannot be switched on until this ringing suppression time is passed. Duration of ringing suppression time depends on the VRZI voltage. Suppression time is 3 µsec if VRZI > 1V and it is 30 µsec if VRZI < 1V. Figure: Ringing Suppression up-down-counter =1 up-down-counter =1 VRZI 1V VSRC 1.5V VPCS OUT ringing suppression time 3 µs Version 1.4 30 us 9 27 Apr 2004 ICE1QS01 Primary regulation Primary regulation is achieved by activating the internal current sink. The current sink is connected between pin SRC and ground. If VRZI exceeds the 5V threshold the current sink is switched on. It is switched off when VRZI falls below 5V. The current sink discharges the CSRC capacitor. CSRC is charged via the internal 20k resistor. If VRZI exceeds the 4.4V threshold a flip-flop is set and the resistor is switched off when VRZI falls below 50 mV. The resistor is switched on again with the falling slope of gate drive OUT. Diagram Primary Regulation VRZI zero current counter = 0010 5V 4.5V OUT OUT 5V start R Q stop S Q 0.05 V R Q S Q + 20k - 20K resistor R Q on 4.5 V RZI + - SRC S Q off + 5V current sink - ICE1QS01 on current sink off VSRC t Version 1.4 10 27 Apr 2004 ICE1QS01 SRC (Regulation and soft start capacitor) The feedback capacitor is connected to pin SRC. The feedback voltage VSRC has two main functions. Function I (MOS FET on time): VSRC provides the switch off reference voltage. If VPCS (which contains the primary current information) exceeds the VSRC voltage the external MOS transistor is switched off. Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by ignoring zero crossing signals after the transformer demagnetization. VSRC determines the action of the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content of the up-down-counter is compared with the number of zero-current crossings of VRZI. If the number of zero-current crossings in each period after the transformer demagnetization is equal to the up-down-counter content the MOS is switched on. At low load conditions when VSRC is below 3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time increases and duty cycle decreases. At high load conditions when VSRC is higher than 4.4V the counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With this off-time regulation switching jitter can be eliminated. The up-down-counter is immediately set to 0001 if a load jump occurs and VSRC exceeds 4.8 V. This ensures that full power can be provided instantaneously. The following table shows the SRC voltage range and the corresponding up-down counter action. SRC voltage range up-down-counter action 1: VSRC< 3.5V count forward 2: 3.5<VSRC<4.4 stop count 3: VSRC>4.4 count backward 4: VSRC> 4.8 set up-down-counter to1 The information provided by VSRC is stored in two independent flip flops. An internal timer creates a trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the diagram below the behaviour of the up-down counter is depicted in more detail. D ia g r a m 1 tim e r p u ls e tp VSRC tp tp 50 m sec tp tp tp tp tp tp tp n + 1 n + 1 n + 1 n n - 1 n - 2 n - 3 4 .5 V 3 .5 V s ta tu s o f u p -d o w n c o u n te r Version 1.4 n n + 1 n + 1 11 27 Apr 2004 ICE1QS01 Burst mode 12 µsec after beginning of softstart the burst mode comparator is activated. If VSRC falls below 2V after activating the comparator the gate drive OUT is switched to low and the VCCoff threshold is changed to 14.5 V. VCC decreases because gate drive is held low. If VCC reaches the VCCoff threshold the IC is going into start-up mode. At VCCon threshold the IC is switched on again starting with soft start modus. VCCoff threshold is set to the normal 9V. Figure: Burst Mode Secondary load high low VSRC 2V OUT Vcc 15V 14.5V VCCOFF 9V Vsec normal mode Version 1.4 burst mode 12 soft start t 27 Apr 2004 ICE1QS01 Restart timer If voltage VRZI is lower than 50 mV and gate drive OUT is low an internally created restart pulse will switch gate drive OUT high every 50 µs and the minimum switching frequency is about 20 kHz. Restart pulse is inhibited if VRZI is higher than 50 mV. So the MOS transistor cannot be switched on until the transformer is discharged. VCC overvoltage protection If VCC exceeds the VCCD threshold a latch is set and the gate is disabled. Reset of latch occurs when VCC is falling below VCCon- VCCBHY. Overvoltage fault comparator (OFC) With an external sense resistor connected to pin OFC primary current can be sensed directly. If the sensed current exceeds the internal VOFC threshold a latch is set and gate is disabled. Reset of latch occurs when VCC is falling below VCCon- VCCBHY. Notice: If this comparator is not used pin OFC has to be connected to ground. Mains undervoltage Power supplies must be shut down when mains voltage is below a certain limit to avoid too long ontime of MOS-FET switch, which would lead to a switching frequency in audible spheres. Mains undervoltage is sensed during the off-time of the MOS-FET switch. If the current flowing into pin PCS is smaller than 100 uA, then the output is latched and cannot be switched to high state. Diagram Mains Undervoltage Lockout Current 130 120 Ipcs/µA 110 100 90 80 70 60 50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Temp./°C Version 1.4 13 27 Apr 2004 ICE1QS01 Fold back point correction With increasing mains voltage the switch on time becomes shorter and so the frequency becomes higher. With higher frequency also the maximal possible output power becomes higher. With higher power the danger in case of failure increases. To avoid this, the foldback point correction circuit senses main voltage to reduce the on-time of the switch. Mains voltage is sensed at the supply coil of VCC voltage via a resistor connected to pin RZI. During on-time of the MOS-FET switch current is pulled out from pin RZI. When this current is higher than 500 µA, one fifth of the current higher than this threshold is driven into pin PCS to increase the voltage slope charging the capacitor connected to this pin. IRZI – 0, 5mA IPCSFO = --------------------------------- ,( IRZI > 500uA ) 5 Figure: Fold Back Point Correction Vpcs with fold back point correction Pmax without fold back point correction Vpcs at high mains voltage 5V Vpcs Pmax Vpcs at low mains voltage t0 t1 t2 Pmax with fold back point correction t3 Vmains t Version 1.4 14 27 Apr 2004 ICE1QS01 Absolute Maximum Ratings Parameter Symbol Min Max Unit Remark Charge Current into Pin2 IPCS 500 uA During start up Voltage at Pin 2 VPCS -0.3 21 V Current into Pin 3 IRZI IRZI -10 10 mA mA VRZI>VRZICH VRZI<VRZICL Voltage at Pin 4 VSRC -0.3 VSRCCL V ISRC=100 µA Voltage at Pin 5 VOFC -0.3 6 V Current into Pin 7 IOUT -500 500 mA Voltage at Pin 8 VCC -0.3 21 V 4000 V ESD Protection Storage Temperature Tstg -50 150 °C Operating Junction Temperature TJ -25 150 °C Thermal Resistance Junction-Ambient RthJA 100 K/W Version 1.4 15 t<1ms MIL STD 883C method 3015.6, 100pF,1500Ω P-DIP-8 27 Apr 2004 ICE1QS01 Characteristics (Unless otherwise stated, -25°C<Tj <150 °C, VCC = 16V) Parameter Symbol min. typ. max. Unit Test Condition VCC start-up circuit Start-up supply current ICCL 60 100 µA VCC=VCCon-0.5V Operating supply current ICCH 8 11 12.5 mA Output low VCC Turn-On threshold VCC ON 14.1 15 15.5 V VCC Turn-Off threshold VCC OFF 8.5 9 9.5 V VCC Hysteresis VCCHY 5.4 6 6.5 V VCC Burst Hysteresis VCCBHY 0.2 0.4 0.6 V VCC Overvoltage VCCD 19 20 21 V 2.40 2.65 2.85 V Ioptocoupler=0 µA Ioptocoupler=0 µA SRC soft start mode Start Voltage VSRC1 Digital voltage step VSRCST 360 mV Step pulse rate tSRCSTR 3 ms Soft start time tST Current source rise time tSTRT 14 µs Current source on time tSTOT 12 µs 19 24 32 ms VSRC=0.2V to 2.0V CSRC=10nF SRC normal mode Source resistor RSRC 17 21 28 kOhm Clamping threshold voltage VSRCCL 4.95 5.1 5.25 V Reset counter to one VSRCR 4.75 4.9 5.05 V Distance clamping to reset VSRCH 150 200 250 mV Threshold downward count VSRCD 4.3 4.5 4.7 V Threshold upward count VSRCSU 3.4 3.5 3.7 V Burst mode latch threshold voltage VSRCB 1.9 2.05 2.2 V Counter time 1) tCOUNT Sink current prim reg mode ISRCS 50 400 500 VPCS=VSRC, OUT switches to Low, ISRC=100µA VSRC <VSRCB: OUT=Low msec 550 µA VRZI > 5V 1) The parameter is not subject to production test - verified by design/characterization Version 1.4 16 27 Apr 2004 ICE1QS01 Parameter Symbol min. typ. max. Unit Test Condition VRZI<VRZIT1: Out=High RZI (regulation and zero crossing input) Zero crossing threshold voltage VRZIT1 25 50 80 mV Time delay switch on tdon 350 440 550 nsec Leakage current IRZIB -1 25 110 µA VRZI=5V Clamping voltage low state VRZICL -0.5 -0.3 -0.2 V IRZI = -1mA Clamping voltage high state VRZICH 5.5 6.0 6.4 V IRZI= 5mA Primary regulation threshold for discharge current VRZIDC 4.95 5.1 5.25 V Primary regulation threshold for charge current VRZICC 4.2 4.4 4.65 V Ringing suppression threshold voltage VRZIT2 0.9 1.0 1.1 V Ringing suppression time tRZIPS tRZIPL 1.5 20 2.5 29 3.2 37 µsec µsec VRZI > VRZIT2 VRZI < VRZIT2 Foldback point correction current threshold IPCSF 250 400 600 µA -25°C<Tj<120°C PCS (primary current simulation) Gate enable threshold voltage VPCSE 0.9 1.0 1.1 V VPCS<VPCSE: Out=Low Basic voltage VPCSB 1.45 1.55 1.65 V gate low Shut down delay tPCS 150 230 nsec Mains undervoltage lockout current 2) IPCS 100 160 µA Voltage drop startup diode VPCSD Discharge current IPCSD 40 0.85 1.6 2.6 3.6 V IPCS=300µA mA VPCS=3V OFC (overcurrent fault comparator) Bias Current IOFCB -1 µA Gate drive disabled threshold voltage VOFC 0.93 Shut Down Delay tOFC 1.0 1.05 V 180 240 ns 2) See diagram mains undervolt. lockout current Version 1.4 17 27 Apr 2004 ICE1QS01 Parameter Symbol min. typ. max. Unit Test Condition tRES 33 42 55 µs VRZI<25mV 0.7 0.8 1.1 1.4 V V IOUT=20mA IOUT=200mA 10.6 10.5 11.0 11.0 V V IOUT=-20mA IOUT=-180mA Output voltage active shut down 1.0 1.35 V VCC=7V IOUT=20mA Rise time 40 100 ns COUT=1nF Fall time 60 120 ns COUT=1nF Restart Timer Restart time Gate Drive Output voltage low Output voltage high Version 1.4 9.5 9.5 18 27 Apr 2004 ICE1QS01 Figure: Circuit Diagram for Standard Application with PFC Version 1.4 19 27 Apr 2004 ICE1QS01 Figure: Circuit Diagram for Application with PFC and Low Voltage Standby Mode Version 1.4 20 27 Apr 2004 ICE1QS01 GPS05121 Plastic Package, P-DSO-8-3 (Plastic Dual Small Outline Package) GPD05025 Plastic Package, P-DIP-8-4 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Version 1.4 21 Dimensions in mm 27 Apr 2004