July 09, 2008 IRS2530D(S) DIM8 DIMMING BALLAST CONTROL IC Product Summary IC Features • • • • • • • • • • • TM Dimming ballast control plus half-bridge driver Closed-loop lamp current dimming control Internal non-ZVS protection Internal crest factor protection Programmable preheat time Fixed dead-time (2.0μs typ.) Lamp insert auto-restart Internal bootstrap MOSFET Internal 15.6V zener clamp diode on Vcc Micropower startup (250μA) Latch immunity and ESD protection Topology Half-Bridge VOFFSET 600 V VOUT VCC IO+ & IO- (typical) 180mA & 260mA Deadtime (typical) 2.0μs Package Types Ballast System Features • • • • • • • • • Single chip dimming solution Simple lamp current dimming control method Single lamp current sensing resistor required No half-bridge current-sensing resistor required No external protection circuits required (fully PDIP8 SO8 internal) Flash-free lamp start at all dimming levels Large reduction in component count Typical applications Easy to use for fast design cycle time • Linear dimming ballast (down to 10%) Increased manufacturability and reliability • 3-way dimming ballast • Multi-level switch dimming ballast Typical Connection Diagram L AC LINE INPUT F1 LF BR1 RVCC1 N RVCC2 RLIM1 CF CBUS VCC CVCC2 COM VB 1 8 IRS2530D CVCC1 RLIM2 2 CDIM DIM CVCO VCO 3 4 7 6 5 RHO MHS HO VS LO LRES:A CDC CBS LRES:B CSNUB RLO CRES MLS SPIRAL CFL LAMP CH1 DCP2 RDIM1 1-10V DIM INPUT RLMP2 CPH RVCO (+) RLMP1 CH2 CFB RFB DCP1 LRES:C RDIM2 (-) RCS www.irf.com © 2008 International Rectifier 1 IRS2530D(S) Table of Contents Page Description 3 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Electrical Characteristics 7 Input/Output Pin Equivalent Circuit Diagram 9 Lead Definitions 10 Lead Assignments 10 State Diagram 11 Application Information and Additional Details 12 Package Details 20 Tape and Reel Details 21 Part Marking Information 22 Ordering Information 23 www.irf.com © 2008 International Rectifier 2 IRS2530D(S) Description This IC takes full advantage of IR’s patented ballast and high-voltage technologies to realize a simple, highperformance dimming ballast solution. A single high-voltage pin senses the half-bridge current and voltage to perform necessary ballast protection functions. The DC dim input voltage reference and the AC lamp current feedback have been coupled together allowing a single pin to be used for dimming. Combining these high-voltage control algorithms together with a simple dimming method in a single 8-pin IC results in a large reduction in component count, an increase in manufacturability and reliability, a reduced design cycle time, while maintaining high dimming ballast system performance Block Diagram Bootstrap MOSFET VCC 1 Driver Logic UVLO COM 2 High-Side Half-bridge Driver 8 VB 7 HO 6 VS 5 LO 1uA Voltage Controlled Oscillator VCO 4 Fault Logic Crest Factor Protection Non-ZVS Protection Dimming Control DIM Half-bridge Voltage Sensing Low-Side Half-bridge Driver 3 Restart Logic www.irf.com © 2008 International Rectifier 3 IRS2530D(S) † Qualification Information Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial†† Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. MSL2††† SOIC8 (per IPC/JEDEC J-STD-020C) Not applicable PDIP8 (non-surface mount package style) Class C (per JEDEC standard EIA/JESD22-A115) Class 3A (per EIA/JEDEC standard JESD22-A114) Class I, Level A (per JESD78A) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com © 2008 International Rectifier 4 IRS2530D(S) Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. VB High-Side Floating Supply Voltage -0.3 625 VS High-Side Floating Supply Offset Voltage VB - 25 VB + 0.3 VHO High-Side Floating Output Voltage VS - 0.3 VB + 0.3 VLO Low-Side Output Voltage -0.3 VCC + 0.3 VVCO VCO Input Voltage -0.3 6 VDIM DIM Input Voltage -0.3 VCC + 0.3 †† † ICC --- 20 -500 500 dVS/dt Supply Current Maximum allowable current at LO, HO and PFC due to external power transistor Miller effect. Allowable VS Pin Voltage Slew Rate -50 50 PD Maximum Power Dissipation @ TA ≤ +25ºC, 8-Pin DIP --- 1.0 PD Maximum Power Dissipation @ TA ≤ +25ºC, 8-Pin SOIC --- 0.625 RθJA Thermal Resistance, Junction to Ambient, 8-Pin DIP --- 85 RθJA Thermal Resistance, Junction to Ambient, 8-Pin SOIC --- 128 TJ Junction Temperature -55 150 TS Storage Temperature -55 150 TL Lead Temperature (Soldering, 10 seconds) --- 300 IOMAX Units V mA V/ns W ºC/W ºC † This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. †† This IC contains a zener clamp structure between the chip VCO and COM which has a nominal breakdown voltage of 7.25V. This pin should not be driven by a DC, low impedance power source greater than the VVCOMAX specified in the Electrical Characteristics section. www.irf.com © 2008 International Rectifier 5 IRS2530D(S) Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBS Definition Min. Max. Units VCC - 0.7 VCLAMP V 600 V VCCUV+ + 0.1V VCLAMP V VCC High-Side Floating Supply Voltage Steady State High-Side Floating Supply Offset Voltage Supply Voltage ICC Supply Current --- 5 mA VVCO VCO Pin Voltage 0 6 V TJ Junction Temperature -40 125 ºC VS ††† -3.0 ††† Care should be taken to avoid output switching conditions where the VS node decreases below COM by more than 5V. www.irf.com © 2008 International Rectifier 6 IRS2530D(S) Electrical Characteristics VCC=VBS=14V, VS=0V, CVCC=CBS=0.1μF, CVCO=CDIM=10nF, CLO=CHO=1nF, and TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective HO and LO output leads. Symbol Definition Min Typ Max Units Test Conditions Low Voltage Supply Characteristics VCLAMP VCC Zener Clamp Voltage 14.6 15.6 16.6 VCCUV+ Rising VCC UVLO+ Threshold 11.5 12.5 13.5 VCCUV- Falling VCC UVLO- Threshold 9.5 10.5 11.5 VCC Undervoltage Lockout Hysteresis 1.5 2.0 3.0 IQCCUV Micropower Startup VCC Supply Current --- 250 --- µA VCC = 8V ICCDIM DIM Mode VCC Supply Current --- 4.5 --- mA MODE = DIM IQCCFLT Fault Mode VCC Supply Current VCO Pin Zener Clamp Voltage --- 375 --- µA MODE = FAULT --- 7.25 --- V MODE = DIM VBS Supply Current --- 2 3 mA MODE = DIM IQBSUV UVLO Mode VBS Quiescent Current --- --- 50 µA VBS = 7V VBSUV+ Rising VBS Supply Undervoltage Threshold Falling VBS Supply Undervoltage Threshold Offset Supply Leakage Current 8.0 9.0 10.0 7.0 8.0 9.0 --- --- 50 VCCUVHY VVCOMAX ICC = 10mA V Floating Supply Characteristics IBS VBSUVILK V μA VB = VS = 600V Ballast Control Characteristics fMIN Minimum Output Frequency 32.0 34.2 36.4 fMAX Maximum Output Frequency --- 115 --- Duty Cycle --- 50 --- % Output Deadtime (HO or LO) --- 2.0 --- µs MODE = ALL VCO Pin Charging Current --- 1 --- µA MODE = PH/IGN VLOSD+ LO Pin Shutdown Threshold --- 8.75 --- VLOSD- LO Pin Re-start Threshold --- 8.5 --- VZVSTH VS Non-ZVS Detection Threshold --- 4.5 --- VCO Fault Rising Threshold --- 4.0 --- Crest factor peak-to-average fault factor --- 5.5 --- d DT IVCO VVCOFLT+ CSCF www.irf.com kHz VCO = 6V VCO = 0V MODE = FAULT V MODE = FAULT MODE = DIM, LO = HIGH V MODE = PH/IGN N/A MODE = DIM VS offset = 0.5V © 2008 International Rectifier 7 IRS2530D(S) Electrical Characteristics VCC=VBS=14V, VS=0V, CVCC=CBS=0.1µF, CVCO=CDIM=10nF, CLO=CHO=1nF, and TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to COM and are applicable to the respective HO and LO output leads. Symbol Definition Min Typ Max Units --- 0.0 --- V Test Conditions Dimming Control Characteristics VDIMREG DIM Regulation Threshold MODE = DIM Gate Driver Output Characteristics (HO and LO) VOH High-Level Output Voltage --- VCC --- IO = 0A VOL Low-Level Output Voltage --- COM --- IO = 0A --- IO = 0A, VCC ≤ VCCUV- VOL_UV --- UV-Mode Output Voltage COM tr Output Rise Time --- 120 220 tf Output Fall Time --- 50 80 tSD Shutdown Propagation Delay --- 350 --- IO+ Output source current --- 180 --- IO- Output sink current --- 260 --- ns mA Bootstrap FET Characteristics VB_ON VB when the bootstrap FET is on --- 13.3 --- IB_CAP VB source current when FET is on 30 55 --- IB_10V VB source current when FET is on 8 12 --- www.irf.com V mA CBS = 0.1µF VB = 10V © 2008 International Rectifier 8 IRS2530D(S) I/O Pin Equivalent Circuit Diagrams www.irf.com © 2008 International Rectifier 9 IRS2530D(S) Lead Definitions Pin # Symbol Description 1 VCC Logic and internal gate drive supply voltage 2 COM IC power and signal ground 3 DIM Dimming DC reference and AC lamp current feedback input 4 VCO Voltage-controlled oscillator (VCO) input 5 LO Half-bridge low-side gate driver output 6 VS High voltage floating supply return and half-bridge sensing input 7 HO High-side gate driver output 8 VB High-side gate driver floating supply Lead Assignments 1 COM 2 DIM 3 VCO 4 8 IRS2530D VCC www.irf.com VB 7 HO 6 VS 5 LO © 2008 International Rectifier 10 IRS2530D(S) State Diagram Power Off VCC > 0V UVLO Mode Half-Bridge Off VCC < 10.5V (VCCUV-) or LO > 8.75V (VLOSD+) (Lamp Removed) IQCCUV ≅ 250μA VCO = 0V HO Off LO Open Circuit VCC > 12.5V (VCCUV+) and LO < 8.5V (VLOSD-) (Lamp Inserted) VCC < 10.5V (VCCUV-) FAULT Mode Fault Latch Set Half-Bridge Off IQCCUV ≅ 250μA HO Off LO Open Circuit VCO > 4.0V (VVCOFLT+) (Lamp non-strike) PH/IGN Mode Half-Bridge Oscillating Freq ramps from fMAX to fMIN VCO Charging (1μA) non-ZVS Disabled Crest Factor Disabled Lamp Ignites CF > 5.5 (lamp removal) DIM Mode non-ZVS ZVS freq = freq + df ZVS OK Half-Bridge Oscillating @fDIM Dimming Loop Enabled non-ZVS Enabled Crest Factor Enabled www.irf.com © 2008 International Rectifier 11 IRS2530D(S) Application Information and Additional Details Information regarding the following topics is included as subsections within this section of the datasheet: • • • • • • • • UVLO Mode and IC Supply Circuitry Preheat/Ignition (PH/IGN) Mode Dim Mode Non Zero-Voltage Switching (ZVS) Protection Crest Factor Over-current Protection Fault Mode and Lamp Reset Component Selection PCB Layout Guidelines UVLO Mode and IC Supply Circuitry The Under-Voltage Lock-Out Mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC, VCCUV+ (12.5 V, typical), and LO is above the shutdown threshold, VLOSD+ (8.75 V, typical). The UVLO circuit is designed to maintain an ultra-low supply current IQCCUV (<250 μA), and to guarantee that the IC is fully functional before the high- and low-side output gate drivers are activated. The VCC capacitor, CVCC, is charged up from the DC bus voltage through supply resistors RVCC1 and RVCC2 (Figure 1). The values of these resistors are chosen such that VCC reaches the UVLO+ turn-on threshold voltage at the desired DC bus voltage level. Once the capacitor voltage on VCC reaches the start-up threshold, VCCUV+, the IC turns on and the HO and LO gate drive outputs start oscillating. The capacitor CVCC should be large enough to hold the voltage at VCC above the VCCUV- threshold until the external auxiliary supply can take over and supply the required voltage and current to the IC. DCBUS(+) RVCC1 RVCC2 DCP2 RLIM1 MHS RLIM2 VCC 1 CVCC1 CVCC2 COM 2 CDIM 15.6V CLAMP DIM 3 DIM REF and FB VCO 4 VB Bootstrap FET Driver VCC UVLO 8 Highand Lowside Driver RHO TO LOAD HO 7 VS CBS CSNUB 6 LO RLO 5 CVCO MLS CPH RVCO DCP1 DCBUS(-) LOAD RETURN Figure 1, UVLO and supply circuitry. An external charge pump circuit consisting of capacitor CSNUB and diodes DCP1 and DCP2, comprises the auxiliary supply voltage for the low-side circuitry (Figure 1). To limit high peak currents that can flow from the external charge pump to VCC, a zener diode (18 V, typical) should be used for the lower charge pump diode, DCP1. Also, two low-ohmic resistors (RLIM1 and RLIM2, 10 Ω each, typical) should be used together with CVCC1 and CVCC2 to further limit and filter fast current spikes to minimize resulting voltage spikes that can occur at VCC. An internal bootstrap MOSFET between VCC and VB and external supply capacitor, CBS, determine the supply voltage for the high-side driver circuitry (Figure 1). The bootstrap MOSFET is turned on when LO is ‘high’ and charges CBS from VCC each cycle to maintain the VB-to-VS voltage above the VBSUVthreshold (8 V, typical). The value of CBS should be chosen such that the VB-to-VS voltage and ripple stays above VBSUV- at all times. When VCC exceeds VCCUV+ for the first time, LO will first oscillate for several cycles www.irf.com © 2008 International Rectifier 12 IRS2530D(S) until the VB-to-VS voltage exceeds the high-side UVLO rising threshold, VBSUV+ (9 V, typical), and the highside driver is enabled. The capacitor CVCC should be large enough such that VCC does not reach UVLObefore HO is enabled and the charge pump supply takes over. External gate drive resistors, RHO and RLO, are also recommended as standard design practice to limit high peak currents that can flow into or out of the HO and LO gate drive outputs. During UVLO Mode, the high-side gate driver output, HO, is ‘low’ and the VCO pin is pulled down internally to COM. The low-side gate driver output, LO, is open circuit and is used as a shutdown/reset input function for automatically restarting the IC when a lamp has been removed and re-inserted. The IC includes an internal shutdown threshold, VLOSD+ (8.75 V, typical), and re-start logic circuit at the LO pin that is only active during UVLO mode. If VCC is above VCCUV+, but the lamp is removed, the external pull-up network (RLMP1 and RLMP2) will pull LO above VLOSD+ and the IC will remain in UVLO mode. When the lamp is reinserted, the lower filament of the lamp will pull LO down below VLOSD- (8.5 V, typical) and the IC will exit UVLO Mode and enter Preheat/Ignition Mode. Preheat/Ignition (PH/IGN) Mode When VCC exceeds VCCUV+ and the LO pin is below VLOSD-, the IC enters Preheat/Ignition Mode. An internal current source, IVCO (1 μA, typical), (Figure 2) charges the external capacitor on pin VCO causing the voltage on pin VCO to start ramping up linearly. An additional quick-start current, IVCOQS (50 μA, typical), is also connected to the VCO pin and charges the VCO pin initially to 0.85 V. The quick-start current charges the VCO voltage up quickly to the internal 1 to 5 V range of the internal VCO. When the VCO voltage exceeds 0.85 V the quick-start current is then disconnected internally and the VCO voltage continues to charge up with the normal frequency sweep current source, IVCO (1 μA, typical) (Figure 3). DCBUS(+) RVCC1 RVCC2 DCP2 MHS RLIM1 RLIM2 VCC CVCC1 CVCC2 CDIM COM 2 8 Highand Lowside Driver 15.6V CLAMP DIM 3 DIM REF and FB VB Bootstrap FET Driver 1 1uA RHO HO VS LO RLO 5 VCO CVCO CPH RVCO CSNUB CBS 6 VCO 4 TO LOAD 7 MLS 4.6V + _ Fault Logic DCP1 DCBUS(-) LOAD RETURN Figure 2, Preheat/Ignition Mode circuitry. The frequency ramps down from the maximum frequency towards the resonance frequency of the high-Q ballast output stage. The lamp filaments are preheated as the lamp voltage and load current increase. The voltage on pin VCO continues to increase and the frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the IC will then enter DIM Mode (Figure 3). www.irf.com © 2008 International Rectifier 13 IRS2530D(S) VVCO 4.0V VVCOFLT+ 0.85V Preheat/Ignition Mode Dim Mode Freq fmax fmin Lamp Ignites VLAMP AC lamp current VDIM DC dim reference Figure 3, Preheat/Ignition/Dim Mode timing diagram. The resonant output stage transitions to a series-L, parallel-RC circuit with the Q-value and operating point determined by the user dim level (Figure 4). If the lamp does not ignite, the voltage on pin VCO continues to increase and the frequency continues to decrease until the VCO voltage exceeds VVCOFLT+ (4.0V, typical) and the IC enters Fault Mode and shuts down. The minimum frequency should be set below the high-Q resonance frequency of the ballast output stage to ensure that the frequency ramps through resonance for lamp ignition (Figure 4). The desired preheat time can be set by adjusting the slope of the VCO ramp with the external capacitor, CPH. www.irf.com © 2008 International Rectifier 14 IRS2530D(S) High-Q Vout Vin Ignition 10% ea eh Pr 50% t Start 100% Low-Q fmin f100% f50% f10% fmax Frequency Figure 4, Resonant tank Bode plot with lamp dimming operating points. Dim Mode When the lamp ignites, the ballast output stage becomes a series-L, parallel-RC circuit and the AC lamp current flows through the current sensing resistor, RCS. The resulting AC voltage across resistor RCS is coupled to the DIM pin through feedback resistor, RFB (1 kΩ, typical), and feedback capacitor, CFB (0.1 μF, typical). The DIM pin voltage is a combination of the DC offset voltage provided by the user dim setting and the AC voltage that is capacitively coupled through capacitor CFB from the lamp current sensing resistor to the DIM pin. The IC enters Dim Mode when the lamp ignites and the dimming control loop becomes active. The DC+AC voltage at the DIM pin is regulated by the control loop such that the valley of the AC voltage always stays at COM. By offsetting the AC voltage with a DC reference and holding the valley of the AC voltage at COM, the amplitude of the AC voltage, and therefore the AC lamp current, is accurately controlled. When the DC reference voltage at the DIM pin is decreased for dimming, the valleys of the AC voltage are pushed below COM. The dimming control circuit increases the frequency to decrease the AC lamp current until the AC valleys at the DIM pin are at COM again. When the DC reference is increased to increase the brightness level, the valleys of the AC voltage increase above COM. The dimming control circuit decreases the frequency to increase the AC lamp current until the AC valleys at the DIM pin are at COM again. In this way, the dimming control circuit keeps the AC lamp current peak-to-peak amplitude regulated to the desired value at all DC dim level settings. Capacitor CVCO programs the speed of the dimming loop and is typically set to a low value (2.2 nF, typical) for cycle-by-cycle lamp current control. An additional compensation network is formed by RVCO (1.5 kΩ, typical) and CPH to prevent the VCO voltage from changing too much from one cycle to the next for maintaining smooth and stable dimming. A capacitor, CDIM (10 nF, typical) is also necessary from the DIM pin to COM for filtering high-frequency switching noise. During Dim Mode, the VS-sensing circuit and non-ZVS and crest factor protection circuits are also enabled (see State Diagram, Page 11). Non Zero-Voltage Switching (ZVS) Protection During Dim Mode, if the voltage at the VS pin has not slewed entirely to COM during the dead-time such that there is voltage between the drain and source of the external low-side half-bridge MOSFET when LO turnson, then the system is operating too close to, or, on the capacitive side of resonance. The result is non-ZVS capacitive-mode switching that causes high peak currents to flow in the half-bridge MOSFETs that can damage or destroy them (Figure 5). This can typically occur during a decrease of the DC bus during an AC mains interrupt or brown-out condition, lamp variations over time, driving an incorrect lamp type, or component and temperature variations. To protect against this, an internal high-voltage MOSFET is turned on at each turn-off of HO and the VS-sensing circuit measures the VS voltage at each rising edge of LO. If the VS voltage is greater than VZVSTH (4.5 V, typical), the non-ZVS control circuit will increase the frequency until ZVS is reached again. Increasing the frequency due to non-ZVS during a brown-out also ensures that www.irf.com © 2008 International Rectifier 15 IRS2530D(S) that the ignition/preheat ramp will be reset to re-ignite the lamp reliably in case the DC bus decreases too far and the lamp extinguishes. LO HO ! VS I L I I ! MLS MHS ! Too close to resonance. Hard-switching and high peak MOSFET currents! Frequency shifted higher to maintain ZVS. Figure 5, Non-ZVS protection timing diagram. Crest Factor Over-current Protection The IRS2530D uses the VS-sensing circuitry to also measure the low-side half-bridge MOSFET current for detecting an over-current fault. By using the RDSon of the external low-side MOSFET for current sensing, the IC eliminates the need for an external current sensing resistor. To cancel changes in the RDSon value due to temperature and MOSFET variations, the IC performs a crest factor measurement that detects when the peak current exceeds the average current by a factor of 5.5 (CSCF). Measuring the crest factor is ideal for detecting when the inductor saturates due to excessive current that occurs in the resonant tank when the frequency is too close to resonance. During Dim Mode, the crest factor over-current protection is used to detect if the filaments fail, the lamp is removed, or the lamp becomes deactivated. During each of these fault conditions, the output stage will transition to a series-LC configuration. The resonant inductor, LRES, and resonant capacitor, CRES, remain connected together to form a complete circuit due to the voltage-mode heating configuration to the lamp (see Typical Application Diagram, Page 1). The frequency will move towards resonance until the inductor saturates. The crest factor protection circuit will then detect the saturation and the IC will enter Fault Mode and shut down. Fault Mode and Lamp Reset During Fault Mode the internal fault latch is set, HO is off, LO is open circuit, and the IC consumes an ultralow micro-power current (see State Diagram, Page 11). The IC can be reset with a lamp exchange (as detected by the LO pin) or a recycling of VCC below and back above the UVLO thresholds. During Fault Mode, the LO pin is open circuit and is used as an input pin for resetting the IC. If the lamp is removed, the external pull-up network at the lower lamp filament, RLMP1 and RLMP2 (see Typical Application Diagram, Page 1), will pull LO above VLOSD+ (8.75V, typical) and the IC will exit Fault Mode and enter UVLO mode. When the lamp is re-inserted, the lower filament of the lamp will pull LO down below VLOSD- (8.5V, typical) and the IC will exit UVLO Mode and enter Preheat/Ignition Mode and restart the lamp. www.irf.com © 2008 International Rectifier 16 IRS2530D(S) Component Selection Proper design of the circuit schematic (see Typical Application Diagram, Page 1) and component selection is important for achieving proper ballast functionality and preventing problems. The following design procedure should be followed for determining the various programming and filtering component values: 1) Capacitor CPH programs the desired preheat/ignition time. CPH is charged up by an internal 1 μA current source at the VCO pin. The value of CPH is determined by: CPH = IVCO ⋅ t PH / IGN 1μA ⋅ t PH / IGN = VVCOFLT 4V 2) Capacitor CVCO programs the speed of the dimming feedback loop. To ensure smooth and stable dimming, CVCO should be small enough such that the dimming loop reacts to lamp current changes each switching cycle. The value of CVCO is typically fixed for most lamp types and is given as: CVCO = 2.2nF 3) Resistor RVCO and capacitor CPH provide additional compensation of the dimming loop to prevent the VCO voltage from changing too much over a given switching cycle. The value of RVCO is typically fixed for most lamp types and is given as: RVCO = 1.5kΩ 4) Resistor RCS measures the lamp current for dimming. RCS should be kept small to minimize power losses but the peak voltage across RCS at the lowest lamp current dimming level should be above a minimum level to avoid noise problems. Using the minimum rms lamp current during dimming, a minimum allowable peak voltage level across RCS of 100 mV, and an additional factor of 5 (signal attenuation due to RFB and CDIM), the value of RCS is determined by: RCS = 100mV I LAMP _ RMS _ MIN ⋅ 2 ×5 Using the maximum rms lamp current, the power loss in resistor RCS is then determined by: PLOSS _ RCS = ( I LAMP _ RMS _ MAX ) 2 × RCS 5) The additional feedback components include RFB for current limiting and noise filtering, CFB for DC blocking, and CDIM for noise filtering. The value of these components are typically fixed for most lamp types and are given as: R FB = 1kΩ C FB = 0.1μF C DIM = 10nF 6) Capacitors CVCC2 and CBS are the low-side and high-side supply capacitors for maintaining their respective supply voltages and providing high-frequency noise filtering. These capacitors are typically fixed and are given as: CVCC 2 = C BS = 0.1μF www.irf.com © 2008 International Rectifier 17 IRS2530D(S) Component Selection (continued) 7) Resistors RVCC1 and RVCC2 provide the micro-power supply current to VCC and therefore determine the AC line input voltage where the ballast first turns on. The value of these resistors is determined by: RVCC1 + RVCC 2 = VAC ON ⋅ 2 − VCCUV + 250uA 8) The additional supply components include capacitor CVCC1 for holding up VCC until the charge pump takes over, charge pump capacitor CSNUB for providing VCC supply current, charge pump diodes DCP1 and DCP2, and limiting resistors RLIM1 and RLIM2 for preventing high currents from flowing into VCC. These components are typically fixed for most design and are given as: CVCC1 = 1μF C SNUB = 1nF / 1KV DCP1 = 18V / 500mW DCP 2 = 1N 4148 R LIM 1 = RLIM 2 = 10Ω 9) Resistors RLMP1 and RLMP2 provide the necessary pull-up signal to the LO pin for detecting the removal and insertion of the lower lamp filament. Both of these resistor should be high-ohmic to minimize current flow from VCC and to minimize current flow from the low-side filament to the LO pin. These resistor values are typically fixed and are given as: RLMP1 = 470 KΩ R LMP 2 = 1MΩ www.irf.com © 2008 International Rectifier 18 IRS2530D(S) PCB Layout Guidelines Proper care should be taken when laying out a PCB board to minimize noise effects due to high-frequency switching and to ensure proper functionality of the IRS2530D. IC and programming components CPH IC COM connects to Power GND at single point Dim Input (+) (-) RVCO CVCO 1 RLIM2 RLO DCP2 CBS CFB RVCC2 CVCC2 CVCC1 RLIM1 VCC charge pump circuitry CDIM Lamp current sensing and feedback RHO RFB Power Ground RCS RLMP2 Lamp Return Filament Sensing RLMP1 RVCC1 Adjacent COM trace for additional noise filtering of feedback signal. DCP1 (+) DC Bus Half-Bridge Output (VS) CSNUB MLS High-side GND (VS) connects to half-bridge mid-point at single point (-) DC Bus MHS High-voltage, high-current and high-frequency half-bridge output Figure 9, Typical through-hole and SMD single-layer PCB layout for Application Diagram, Page 1 (bottom copper layer shown from top view). The programming components for the IC should be connected to the IC COM pin and then connected to power ground at a single point (Figure 9). The lamp current sensing feedback components (RFB, CFB) should be kept as far away as possible from the high-voltage/high-frequency half-bridge components to prevent switching noise from distorting the lamp current feedback signal. Adjacent ground traces to the feedback signals can also help reduce switching noise. In general, the following guidelines should be followed during PCB board layout: 1) Place all IC supply capacitors (CVCC2, CBS) and as close as possible to their respective supply and return pins (CVCC, CBS). 2) Place all IC programming and filter components as close as possible between their respective pins and COM (CVCO, RVCO, CPH, CDIM, CFB, RFB). 3) Connect IC COM to power GND at one connection only. Do not route power GND through the programming components or IC COM! 4) Connect high-side gate-drive ground (VS) to half-bridge mid-point at one connection only. Do not route high-side power ground through the VS components or VS pin. 5) Connect the anode of charge pump diode DCP1 to power ground. Do not connect to IC COM. 6) Use gate resistors (RLO, RHO) between all gate driver outputs and the gate of their respective power MOSFETs. 7) Use zener diode (18 V, typical) for lower charge pump diode (DCP1) and limiting resistors and capacitors (RLIM1, CVCC1, RLIM2, CVCC2) to filter high current spikes that can cause large voltage spikes to occur on VCC. www.irf.com © 2008 International Rectifier 19 IRS2530D(S) Package Details www.irf.com © 2008 International Rectifier 20 IRS2530D(S) Tape and Reel Details: SOIC8N LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 © 2008 International Rectifier 21 IRS2530D(S) Part Marking Information Part number IRSxxxxx Date code YWW ? Pin 1 Identifier ? MARKING CODE P Lead Free Released IR logo ? XXXX Lot Code (Prod mode – 4 digit SPN code) Assembly site code Per SCOP 200-002 Non-Lead Free Released www.irf.com © 2008 International Rectifier 22 IRS2530D(S) Ordering Information Standard Pack Base Part Number Package Type PDIP8 IRS2530D SOIC8N Complete Part Number Form Quantity Tube/Bulk 50 IRS2530DPBF Tube/Bulk 95 IRS2530DSPBF Tape and Reel 2500 IRS2530DSTRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com © 2008 International Rectifier 23 Application Note AN-1153 Low Cost Triac Dimmable CFL Ballast Using IRS2530D DIM8TM By Andre Tjokrorahardjo Table of Contents Page Introduction ................................................................................................... 2 Circuit Schematic ......................................................................................... 5 Electrical and Fault Protection Characteristics ............................................. 6 Functional Description ................................................................................. 7 Fault Conditions .......................................................................................... 14 Ballast Design ............................................................................................. 17 Bill of Materials ............................................................................................ 19 PCB Information and Layout ....................................................................... 21 Conclusion .................................................................................................. 23 www.irf.com AN-1153 1/23 INTRODUCTION It has often been a disadvantage with electronic ballasts that they have been unable to be dimmed with a standard (phase cut) type of dimmer, particularly in the case of small integral ballast-lamp combinations commonly used in the home to save energy. This is due to the fact that, where there is no power factor correction, the ballast circuit input consists of a rectification stage followed by a large storage capacitor connected to the AC mains supply that provides the DC bus from which the high frequency half bridge and output section is supplied. In such a system current is drawn from the mains only near the peak of the mains voltage where the storage capacitor charges and not during the remainder of the mains half-cycle. Virtually all domestic and professional dimming systems are based on triacs. These devices will conduct once they have been fired, only while current flows in excess of the holding current of the device. These dimmers work very well with a resistive load such as an ordinary Tungsten filament light bulb as the triac can be fired at any point during the mains half-cycle and will continue to conduct until very close to the end of the half-cycle as current is drawn continuously over this period. In this way the lamp current can be adjusted from maximum to zero. A basic 120VAC dimmer circuit When a compact ballast is connected to a circuit containing such a dimmer, the triac will only conduct if it is fired at a point during the mains half-cycle where the rectified mains voltage is greater than the storage capacitor voltage. In this instance the capacitor will be charged to the same voltage and the triac will then switch off. In this way it would be possible to adjust the DC bus voltage of the ballast to some extent by adjusting the triac firing point from 90º to 180º however this will not provide a satisfactory means of controlling the light output. There is also an additional problem encountered due to the fact that a dimmer of this kind requires an inductor in series with the triac (Figure 1) to limit the rise time of the current when the device is fired. Without this inductor, mains current harmonics would be produced at frequencies high enough to cause considerable radiated and conducted interference problems. Since the load presented by a ballast circuit is effectively capacitive, when the triac is fired there will be ringing caused by the resonance of the suppression inductor of the dimmer and the capacitive load. This can cause the triac to fire and then switch off as the ringing output voltage swings above and then below the input voltage causing the current to fall below the holding current. This can occur several times during each half cycle, resulting in severe lamp flicker and loss of control of the output. www.irf.com AN-1153 2/23 AC INPUT 16uH 100nF 15K TRIAC 500K 47nF 33nF AC OUTPUT Figure 1: Triac Dimmer Circuit Triac dimmable CFL ballast A system has now been developed, based around the 8-pin dimming ballast control IC IRS2530D, where the ballast is able to operate with minimal flicker over a considerable portion of the adjustment range of a dimmer. The light output may be controlled over this range from maximum output down to close to 10%. In this system, the front end of the ballast has been designed so that when the triac in the dimmer has fired, it will remain on continuously until almost the end of the mains half-cycle. In addition to this there is circuitry that detects the firing angle of the triac and adjusts the lamp current by adjusting the switching frequency hence the controlling light output depending on the level set by the dimmer. It should be noted that if the dimmer is set too low the triac will never fire when a capacitive load is connected. Also when the ballast is running and the dimmer is turned too low, there will be insufficient bus voltage for the ballast to be able to operate. Because of these factors, it is impossible for the ballast to operate over the complete range of adjustment of the dimmer. There will also be some hysteresis so when the ballast is being dimmed down and reaches the point where the lamp goes out, the dimmer has to be turned back up some way before the lamp will strike again. www.irf.com AN-1153 3/23 This application note is about a dimming CFL ballast, dimmable with phase-cut dimmer, driving a single 15W spiral CFL lamp. The design contains an EMI filter and a dimming ballast control circuit using the IRS2530D. This demo board is intended to help with the evaluation of the IRS2530D dimming ballast control IC, and serve as an aid in the development of production ballasts using the IRS2530D. www.irf.com AN-1153 4/23 www.irf.com N 120V Triac Input L VR R1 AN-1153 R3 D5 R2 C1 C3 C2 L1 D6 C6 R4 D3 D1 D4 D2 R6 R5 CBUS C4 CPH RVCO CVCO CDIM CVCC 3 2 1 4 VCO DIM COM VCC RVCC2 RVCC1 CFB IC1 C5 RFB 5 6 7 8 LO VS HO VB RLMP1 RLO CBS RHO RCF MLS MHS DCP1 DCP2 CVS LRES CRES CDC LRES:C CH2 CH1 LRES:B RCS CFL LAMP CIRCUIT SCHEMATIC IRS2530D Figure 2: Circuit Schematic 5/23 ELECTRICAL AND FAULT PROTECTION CHARACTERISTICS Parameter Lamp Type Units Input Power [W] Input Current [mArms] Lamp Running Voltage [Vpp] Lamp Running Current [mArms] Start Frequency [kHz] Run Frequency [kHz] Preheat Time Input AC Voltage Range Dimming Level 100% Minimum 100% Minimum 100% Minimum 100% Minimum 100% Minimum [s] [VACrms] Value 15W Spiral CFL 14 6.5 233 240 240 450 160 20 115 54 54.5 1.3 80 – 135 Table 1: Electrical Parameter Fault Brown-out Protection Non-ZVS Open filament Failure to ignite End of life Crest Factor Over Current VVCOFLT+ Crest Factor Over Current Ballast Increase frequency Deactivates Deactivates Deactivates Restart Operation Line voltage increase Lamp exchange Lamp exchange Lamp exchange Table 2: Fault Protection Characteristic www.irf.com AN-1153 6/23 FUNCTIONAL DESCRIPTION IRS2530D DIM8TM Dimming Ballast Control IC The IRS2530D is an application specific solution for dimming CFL and TL lamps in CFL or matchbox (small size ballasts) applications. It integrates all of the necessary functions for preheat, ignition and dimming control of the lamp, plus lamp fault protection, low AC-line protection, lamp exchange auto-restart, and a 600V half-bridge driver into a standard SO8 or DIP8 package. The IRS2530D includes adaptive zero-voltage switching, non-zero voltage switching (ZVS) protection, as well as an integrated 600V bootstrap MOSFET. The heart of this IC is a voltage-controlled oscillator (VCO) with a dimming reference/feedback input. One of the biggest advantages of the IRS2530D is that it uses the VS pin (the mid-point of the half-bridge) for over-current protection and to detect non-ZVS conditions. The IRS2530D uses the RDSon of the lowside half-bridge MOSFET for current sensing each cycle when the low-side MOSFET is on. An internal 600V MOSFET connects the VS pin to the VSsensing circuitry and allows for the VS pin to be accurately measured during the time when pin LO is high, while withstanding the high DC bus voltage during the other portion of the switching cycle when the high-side MOSFET is turned on. This eliminates the need for an external, precision current sensing resistor that is typically used to detect over-current. Please refer to the IRS2530D datasheet for further information including electrical parameters, a state diagram and a complete functional description. When power is turned on, the IRS2530D first starts in Under Voltage Lockout (UVLO) mode. The UVLO mode is designed to maintain an ultra-low (<250µA) supply current, and to guarantee that the IC is fully functional before the highand low-side output (HO and LO) gate drivers are activated. During UVLO, HO is ‘low’, and VCO is pulled down to COM for resetting the starting frequency to the maximum. LO is open circuit, and is used as a shutdown/reset input function for automatically restarting the IC when a lamp has been removed and re-inserted. In this CFL ballast application, however, this protection is not necessary and is disabled by pulling LO ‘low’ using resistor RLMP1. Once VCC reaches the startup threshold (VCCUV+), the half-bridge FETs start to oscillate and the IC enters Preheat/Ignition Mode. At startup, VCO is 0V and the frequency starts at fMAX. The frequency ramps down towards the resonant frequency of the high-Q ballast output stage, causing the lamp voltage to increase. During this time, the filaments of the lamp are pre-heated to their emission temperature to minimize the necessary ignition voltage and to increase lamp life. The voltage on pin VCO continues to increase and the frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the IRS2530D enters the DIM mode. The resonant output stage transitions to a series-L, parallel RC circuit with the Q-value and operating point determined by www.irf.com AN-1153 7/23 the user dim level (Figure 3). Figure 3: Resonant tank Bode plot showing lamp operating points Figure 4 shows the VCO voltage, the voltage across the lamp and the current through the lamp during Preheat, Ignition, and Run mode. Figure 4: Preheat, Ignition, and Run mode: CH1 is the VCO voltage, CH3 is the voltage across the lamp, and CH4 is the lamp current www.irf.com AN-1153 8/23 IRS2530D-based solution for triac dimmable CFL ballast When the dimmer triac is fired the current that flows must remain above the holding current until a point close to the end of the mains half cycle at which the voltage is very low. This is achieved by ensuring that the ballast draws current exceeding the holding current of a standard power triac as used in most dimmers with a capacitor network consisting of C2, C3, C4 and C5. When the ballast is operating, the point between LRES and CDC swings low when MLS is on. This charges C2 and C5 during the positive half-cycle of the mains voltage. When MLS switches off and MHS switches on, the voltage between LRES and CDC swings high causing C5 to be discharged through the capacitor C3. During the negative half-cycle of the mains voltage, the opposite happens between C2 and C3. The result is that a continuous series of current pulses are drawn from the input during the period when the triac has been fired until close to the end of the mains half-cycle. The inductor L1 ensures that a continuous current is drawn from the input and that the triac does not switch off between pulses. In order to do this the inductor must store energy when current is being drawn to charge C5, and release this energy during the period when C5 is discharging. Voltage at Ballast Input Current at Ballast Input Figure 5: Voltage and current at ballast input The voltage waveform at the junction of D1 and D3, ignoring high frequency components is equivalent to the output voltage of the dimmer. With respect to the negative rail of the bus this will be a phase cut approximate sine wave with a DC offset such that the negative peak is at 0V. This is reduced by the voltage divider network of R2 and R3 which is then fed into D5 and D6. Only the signal representing the positive half-cycle of the mains is left at the anode of D6 which is then converted to a DC level via the filter of R4 and C6. Because the minimum dimming level occurs at a point where the dimmer is still capable of providing enough output for the ballast to operate, this voltage will never actually be zero. The DC level is further reduced with the voltage divider network of R5 and R6, and used as the dimming reference. www.irf.com AN-1153 9/23 The AC lamp current is sensed by the resistor RCS, and the resulting AC voltage is coupled with the DC dimming level reference through feedback resistor (RFB) and feedback capacitor (CFB), and then fed into the DIM pin (pin #3) of IRS2530D (Figure 6). The DC + AC voltage at the DIM pin is regulated by the control loop such that the valley of the AC voltage always stays at COM. When the DC reference voltage at the DIM pin is decreased for dimming, the valleys of the AC voltage are pushed below COM. The dimming control circuit increases the frequency to decrease the AC lamp current until the AC valleys at the DIM pin are at COM again. When the DC reference in increased to increase the brightness level, the valleys of the AC voltage increase above COM. The control loop decreases the frequency to increase the AC lamp current until the AC valleys at the DIM pin are at COM again. In this way, the dimming control circuit keeps the AC lamp current peak-to-peak amplitude regulated to the desired value at all DC dim level settings. Figure 6: IRS2530D AC+DC Dimming Control Method www.irf.com AN-1153 10/23 Figure 7 shows the voltage at the DIM pin (pin 3 of IRS2530D), the VCO pin (pin 4 of the IC) and the VS pin (half-bridge) voltage during DIM Mode for maximum dimming level. Figure 8 shows these voltages at the minimum dimming level, just before the lamp turn off. The frequency does not change significantly between the maximum and minimum dimming level since the bus voltage is decreased as the lamp is dimmed. Figure 7: Maximum dimming level waveforms: CH1 is the DIM pin (pin 3 of IC1), CH2 is the VCO pin (pin 4 of IC1) and CH3 is the voltage at VS pin Figure 8: Minimum dimming level waveforms: CH1 is the DIM pin (pin 3 of IC1), CH2 is the VCO pin (pin 4 of IC1) and CH3 is the voltage at VS pin www.irf.com AN-1153 11/23 Figure 9 shows the voltage across, the current through and the power delivered to the lamp during DIM Mode for maximum dimming level. Figure 10 shows these waveforms for the minimum dimming level. Figure 9: Maximum dimming level waveforms: CH3 is the voltage across the lamp, CH4 is the current through the lamp and CHA is the power of the lamp (voltage x current) Figure 10: Minimum dimming level waveforms: CH3 is the voltage across the lamp, CH4 is the current through the lamp and CHA is the power of the lamp (voltage x current) www.irf.com AN-1153 12/23 Figure 11 shows the dimming characteristic of the ballast. The light output cannot go down below 10% of dimming level since the bus voltage becomes too low for the ballast to operate. The ballast also possesses a hysteresis behavior where the ballast is turned on at certain angle about midway between the turn-off point and the maximum point. This is necessary to ensure that the bus voltage is high enough to ignite the lamp and allows the ballast to operate sufficiently. Dimming Characteristic Figure 11: Dimming Characteristics www.irf.com AN-1153 13/23 FAULT CONDITIONS In case of fault conditions such as open filaments, or failure to strike, the IR2530D will go into Fault Mode. In this mode, the internal fault latch is set, HO and LO are low, and the IRS2530D consumes an ultra-low micro-power current. The IR2530D can be reset with a recycling of VCC below and back above the VCCUV thresholds. Failure to Strike At initial turn-on of the ballast, the frequency will ramp down from fMAX toward the resonance frequency. When the lamp fails to strike, the VCO voltage continues to increase and the frequency continues to decrease until the VCO voltage exceeds VVCOFLT+ (4.0V, typical), and the IRS2530D enters Fault Mode and shuts down (Figure 12). It should be noted that in case of failure to strike, the system will operate in capacitive side of resonance, but only for short period of time. Figure 12: Failure to strike: CH1 is the VCO voltage and CH3 is the voltage across lamp AC Mains Interrupt / Brown-Out Conditions This protection relies on the non-ZVS circuit of IRS2530D, enabled in the DIM Mode. During an AC mains interrupt or brown-out condition, the DC bus can decrease and cause the system to operate too close to, or, on the capacitive side of resonance. The result is non-ZVS switching that causes high peak currents to flow in the half-bridge MOSFETs that can damage or destroy them. www.irf.com AN-1153 14/23 To protect against this, the IRS2530D will detect non-ZVS by measuring the VS voltage at each rising edge of LO. If the voltage is greater than VZVSTH (4.5V, typical), the IC will reduce the voltage at VCO pin, and thus increase the frequency until ZVS is reached again. In case the DC bus decreases too far and the lamp extinguishes, the VCC voltage will go below VCCUV- and the ignition/preheat ramp will be reset to reignite the lamp reliably (Figure 13). Figure 13: DC Bus decreases too far: CH1 is the VCO voltage, CH2 is the VS voltage, CH3 is the voltage across the lamp, CH4 is the lamp current Open Filament The open filament protection relies on the non-ZVS and the Crest Factor Overcurrent protection, enabled in the DIM mode. When the open filament occurs, the output stage will transition to a series-LC configuration, and hard-switching will occur at the half-bridge because the system operates on the capacitive side of resonance. The non-ZVS circuit of the IRS2530D will detect this condition, increasing the frequency each cycle toward resonant frequency until the inductor saturates. The IRS2530D uses the VS-sensing circuitry and the RDSon of the low-side half-bridge MOSFET to measure the MOSFET current for detecting an over-current fault. Should the peak current exceed the average current by a factor of 5.5 (CF>5.5) during the on-time of LO, the IRS2530D will enter Fault Mode, where the half-bridge is off. Performing crest factor measurement provides a relative current measurement that cancels temperature and/or tolerance variations of the RDSon of the low-side half-bridge MOSFET. www.irf.com AN-1153 15/23 Figure 14 shows the LO pin voltage, the VS voltage, voltage at lamp terminal and inductor current when the inductor saturates and the ballast shuts down. Figure 14: Open Filament: CH1 is the LO voltage, CH2 is the VS voltage, CH3 is the voltage at lamp terminal and CH4 is the current through the inductor www.irf.com AN-1153 16/23 BALLAST DESIGN Output Inductor Design The output inductor LRES should be designed to allow a high peak ignition current without saturating. This is important as the IRS2530D shutdown will be triggered if the inductor saturates. The ignition current depends on the type of lamp being used and must be kept to a minimum by ensuring the preheat is sufficient. To minimize losses in the inductor multi-stranded wire should be used in combination with Ferrite cores of adequate quality. The best approach to design is to wind as many turns as possible of multi-stranded wire and have the largest gap possible to achieve the correct inductance. This will produce the highest available peak current before saturating the inductor. It is important to be aware that when the cores are hot, the saturation point and hence the peak current for the inductor will be lower therefore a poorly designed inductor may result in the ballast shutting down during an attempted hot re-strike. Lamp Preheating The lamp must be sufficiently preheated before ignition. The correct preheat current can be determined from published data or from International Rectifiers Ballast Designer software. The preheat time can be set by adjusting the value of CPH. As a general rule the lamp filament should glow red before ignition. If preheat is insufficient the ballast is likely to shutdown during ignition because the output inductor will be unable to operate at the high current required. The number of turns in the auxiliary cathode windings of the output inductor LRES should be chosen to provide sufficient preheat. The lamp filament (Cathode) resistance over the range of dimming levels should be between 3 and 5.5 times the resistance when cold. A simple method for determining the hot resistance is to first connect one cathode to a DC power supply via an ammeter and slowly increase the voltage from zero, noting the current at 1V intervals. This should be done until the cathode can be seen to be glowing red. When this occurs the voltage should not be increased further in order to prevent possible cathode damage. The resistance can then be calculated for each voltage and hence the acceptable voltage range can be found to comply with the 3 to 5.5 times cold resistance, which can be easily measured with a digital multi-meter (DMM). Then when the ballast is being run a true RMS digital voltmeter can be connected across one cathode and the voltage can be observed at maximum and minimum brightness. The cathode voltage increases as the ballast is dimmed. The values of CH1 and CH2 will control how much it increases by; www.irf.com AN-1153 17/23 reducing the capacitance will reduce the amount by which the voltage rises. The values should be chosen to prevent the voltage exceeding the upper limit at minimum output. It is important to consider that using additional windings on the inductor to provide cathode heating means that power is now being transferred through the core and consequently the core losses will increase and hence the core operating temperature. The core will reach its highest operating temperature when the ballast is running at minimum brightness. The following component values have been selected for a 15W spiral CFL. The circuit will need to be optimized for the particular lamp used to obtain best performance. Demo Board Connections The demo board has two test points for connection to the 120VAC mains supply. The board must not be connected to a supply greater than 120V. There are four output connections to be connected to a compact lamp. The two upper connections go to one lamp cathode and the two lower connections go to the other lamp cathode. www.irf.com AN-1153 18/23 BILL OF MATERIALS Item # Qty Manufacturer Part Number Description Reference 1 4 Diodes, Inc. 1N4007DICT-ND Diode, 1000V, 1A D1, D2, D3, D4 2 1 Renco RL-5480-3-2700 Filter inductor L1 3 1 Panasonic ERZ-V05D221 Varistor / Surge Absorber VR 4 3 Panasonic-ECG ECQ-E2333KB Capacitor, 33nF, 250V C1, C2, C3 5 1 EPCOS B32671L0682J Capacitor, 6.8nF, 1kV, LS=10mm C4 6 1 EPCOS B32620A472J Capacitor, 4.7nF, 1kV, LS=7.5mm C5 7 1 Panasonic ECJ-2FB1E105K Capacitor 1.0uF, 25V, 0805 C6 8 1 Wima MKS2 Series Capacitor, 47nF, 400V CDC CBUS 9 1 Panasonic EEU-EB2D220 Capacitor, 22µF, 200VDC, 105C 10 2 Panasonic ECJ-2FB1H104K Capacitor, 0.1µF, 50V, 0805 CBS, CFB 11 2 Panasonic ECJ-3VB1E104K Capacitor, 0.10µF, 25V, 1206 CH1, CH2 12 1 Panasonic ECJ-2VB1H222K Capacitor, 2.2nF, 50V, 0805 CVCO 13 1 AVX 08053D684KAT2A Capacitor, 0.68µF, 25V, 0805 CPH 14 1 Panasonic ECJ-3YB1C105K Capacitor, 1µF, 16V, 1206 CVCC 15 1 Panasonic ECJ-2VB1H103K Capacitor, 10nF, 50V, 0805 CDIM 16 1 Panasonic ECK-A3A102KBP CVS 17 1 Wima MKP 472K1K6 18 1 IR IRS2530D Capacitor, 1nF, 1KV, Ceramic disk Polypropylene Capacitor, 4.7nF/1.6KV, 10%, LS=10mm Dimming Ballast Control IC IC1 19 1 Vogt Ballast Resonant Inductor 1.25mH LRES 20 2 Digikey/Vishay IRFU320 Transistor, MOSFET, 400V MHS, MLS 21 1 Vishay PPC.47BCT-ND Resistor, 0.47R, 1/2W R1 22 2 Panasonic ERJ-6GEYJ153V Resistor, 15K, 0805 R3, R6 23 2 Panasonic ERJ-8GEYJ104V Resistor, 100K, 1206 RVCC1, R2 24 3 Panasonic ERJ-6GEYJ104V Resistor, 100K, 0805 RVCC2, R4, R5 25 1 Panasonic ERJ-6GEYJ224V Resistor, 220K, 0805 RLMP1 26 1 Panasonic ERJ-P08J102V Resistor, 1K, 1206 RFB 27 1 Panasonic ERJ-6GEYJ152V Resistor, 1.5K, 0805 RVCO 28 3 Panasonic ERJ-6GEYJ100V Resistor, 10 Ohm, 0805 RHO, RLO, RLIM 29 1 Panasonic PPC7.5W-1CT-ND Resistor, 7.5 Ohm, 5%, 1 W, Axial RCS 30 1 Panasonic PPC1.0W-1CT-ND Resistor, 1.0 Ohm, 5%, 1 W, Axial 31 2 Diodes, Inc. LL4148DICT-ND Diode, 1N4148 SMT DL35 RCF* (please note below) DCP2, D5 32 1 Diodes, Inc. ZMM5248BDICT-ND Zener Diode, 18V, 500mV, SMT DCP1 33 1 Diodes, Inc. ZMM5240BDICT-ND Zener Diode, 10V, 500mV, SMT D6 Total 48 CRES Table 3: Bill of Materials. Lamp type: 15W Spiral CFL * Some lamp type, when is cold and dimmed down, can trigger the Crest-Factor Over-Current Protection of the IRS2530D. If this is the case, please use the 1.0 Ohm resistor for RCF. Otherwise, put a jumper across RCF. www.irf.com AN-1153 19/23 see Resonant Inductor Specification INDUCTOR SPECIFICATION E16/ 8 / 8 CORE SIZE GAP LENGTH 1.0 mm CORE MATERIAL Philips3C85 , Siemens N27 or equivalent mH NOMINAL INDUCTANCE 1.25 TEST TEMPERATURE C 100 WINDING START PIN FINISH PIN TURNS WIRE DIAMETER ( mm) 1 4 130* 8 strands of 40 awg CATHODE 2 3 5 32 awg insulated CATHODE 5 6 5 32 awg insulated MAIN PHYSICAL LAYOUT 0.4" ( Vertical6- Pin Bobbin) Pin View TEST 6 1 5 2 4 3 TEST TEMPERATURE MAIN WINDING INDUCTANCE * C 100 MIN 1.2 Adjust turns for specified Inductance www.irf.com 0.3" AN-1153 mH MAX 1.3 mH 20/23 PCB INFORMATION AND LAYOUT Board Information Diameter: 1.87inches (475mm) Number of copper layer: 1 (bottom layer) Through hole components: 21 Surface Mount components: 27 Top Assembly www.irf.com AN-1153 21/23 Bottom Assembly Bottom Copper www.irf.com AN-1153 22/23 CONCLUSIONS A CFL ballast without PFC is effectively capacitive and by itself, cannot work with a phase-cut (triac) dimmer. This application note suggests a ballast circuit that is dimmable with such dimmer. The design contains an EMI filter and a dimming ballast control circuit using the revolutionary 8-pin dimming ballast IC IRS2530D DIM8TM. Because of the simplicity of the dimming method of IRS2530D, this board uses few components counts to realize the minimum dimming level close to 10%. The ballast is also fully protected from fault conditions, such as nonstrike, brown-out and open filament. Disclaimer This application note is intended for evaluation purposes only and has not been submitted or approved by any external test house for conformance with UL or international safety or performance standards. International Rectifier does not guarantee that this reference design will conform to any such standards. www.irf.com AN-1153 23/23 IR's Control ICs for Energy-Efficient Fluorescent Ballasts Slash Component Count - Increase Reliability and Performance How to Buy Products Part Search IR’s Control ICs for Energy-Efficient Fluorescent Ballasts Slash Component Reference Count;Cross Increase Reliability and Performance Product Change Notices EL SEGUNDO, Calif. — International Rectifier, Manufacturing Facilities IR® (NYSE: IRF), a world leader in power management technology, today introduced the IRS2530D and IRS2158D 600V control ICs for Sales Reps energy-efficient dimming fluorescent lighting ballast applications. Distributors The IRS2530D DIM8™ is a unique linear dimming ballast control IC with half-bridge driver in a compact 8-pin form factor. The new device provides a competitive solution to replace inefficient incandescent bulbs in multi-level and three-way compact fluorescent lighting (CFL) applications. Requiring only several small external components, the IRS2530D significantly simplifies and shrinks circuit design and delivers a dimming system performance of up to 10 percent for compact fluorescent lamps as well as linear ballasts. Part Search Site Search AC-DC Appliances Automotive DC-DC Lighting NetCom A&D/HiRel Audio Desktop/Server Enterprise Power Motor Control Portables The IRS2158D 16-pin fluorescent dimming ballast control IC with half-bridge driver is designed for applications requiring dimming performance below 10 percent. Comprehensive protection features About IR such as protection from failure of a lamp to strike, filament failures and end-of-life protection are Contact Us offered making the device well suited for thin lamps including the increasingly popular T5 lamp. Press Room Careers Investor Relations Site Index Corporate Social Responsibility Awards Featured Articles Print Advertising Request Literature Trade Show Calendar Editorial Contacts All News Releases New Product Releases New Catalog Additions Investor News E-Mail News RSS Feeds “These innovative new devices add to IR’s rich portfolio of energy-efficient products. With the opportunity to save up to 30 percent of energy compared to non-dimming lighting, designers are seeking to create new dimming product lines using several different control methods. With a high level of integration and protection features, the new control ICs provide the small form factor, functionality and performance required while reducing part count and simplifying design,” said Tom Ribarich, IR’s director, Lighting Systems and Applications. IRS2530D DIM8™ Technical Data The IRS2530D DIM8™ control IC features IR’s patented ballast and high-voltage technologies. A single high-voltage pin senses the half-bridge current and voltage to perform necessary ballast protection functions. The DC dim input voltage reference and AC lamp current feedback are combined allowing a single pin to be used for dimming. These high-voltage control algorithms coupled with a simple dimming method in a single 8-pin IC result in a significantly reduced component count, increased reliability and reduced design cycle time, while maintaining high dimming ballast system performance. The IRS2530D also features an internal non-ZVS protection and internal crest factor protection to prevent lamp failure damaging the ballast. IRS2158D Technical Data The IRS2158D is a fully integrated, fully protected 600V ballast control IC designed to drive a wide variety of fluorescent lamps. The device’s features include programmable half-bridge over-current protection, programmable pre-heat and run frequencies, programmable preheat time and deadtime, closed-loop half-bridge ignition current regulation, programmable end-of-life protection, brownout protection and low input offset operational amplifier for dimming, current or power control. In addition, the new device features end-of-life window comparator pin and internal 60-event current sense up/down fault counter to accommodate T5 lamp and multi-lamp ballasts. http://www.irf.com/whats-new/nr081111.html[2012-06-27 11:20:38] IR's Control ICs for Energy-Efficient Fluorescent Ballasts Slash Component Count - Increase Reliability and Performance Specifications Programmability Preheat Time IRS2530D IRS2158D Yes Yes Preheat Frequency - Yes Closed Loop Ignition Current - Yes Run Frequency Yes Yes Deadtime - Yes Features IRS2530D IRS2158D Fixed Deadtime 2.0 µs Programmable Failure to Strike On Over Current Yes Open Filament On Over Current Yes Brownout Protection with non-ZVS Yes Shutdown Pin - Yes Fault Counter - Yes End-of-Life Protection - Integration Bootstrap Diode Yes IRS2530D IRS2158D Yes Yes Crest Factor Over Current Protection Yes - Adaptive Non-ZVS Protection Yes - Dimming Minimum Dimming Level IRS2530D Package DIP & SOIC IRS2158D 10% < 10% IRS2530D IRS2158D 8 pin 16 pin The IRPLDIM4E, IRPLDIM5E, IRPLCFL8U reference designs, featuring the IRS2530D are available in addition to the IRPLDIM3 reference design which features the IRS2158D. Availability and Pricing Available in an 8-lead DIP or 8-lead SOIC package, pricing for the IRS2530D begins at US $1.09 in 10,000-unit quantities. The IRS2158D is available in16-pin PDIP and 16-pin narrow body SOIC packages with pricing beginning at US $1.29 each in 10,000-unit quantities. Pricing for the IRPLDIM4E, IRPLDIM5E and IRPLCFL8U reference designs is US $99 per kit, and pricing for the IRPLDIM3 is US $150 per kit. Production orders are available immediately. The devices are RoHS compliant and prices are subject to change. International Sites: | Chinese ???? | Korean ??? | Japanese ??? | http://www.irf.com/whats-new/nr081111.html[2012-06-27 11:20:38] About International Rectifier | Contact Us | Privacy ©1995- 2012 International Rectifier