整ι lS27C512 65.536 ISS/@ x 8 CMOS EPROM FEATURES DESCRIPTION • Fast access time: 90 ns The ISSI IS27C512 is an 512K-bit CMOS (64K-word by 8-bit) Ultraviolet Erasable CMOS Programmable Read-Only Memory. It requires only a single 5V power supply in normal read mode operation. Any byte can be access in less than 90 ns. The IS27毛主12 offers separate Output Enable (δE)and Chip Enable (CE) controls , thus eliminating bus contention in a multiple bus microprocessor system. • JEDEC-approved pinout • High-speed write programming 一 Typically ·士 10% less than eight seconds power supply tolerance available • 80th CMOS and TTL compatible input and output AII signals are TIL levels , including programming signals. Bit locations may be programmed singly , in blocks , or at random. • Two line control functions • Versions available in industrial and commercial temperature ranges The IS27C512 supports [SSI 与 write programming algorithm. Programming time is typically only 100μs per byte. This product is available in ceramic windowed DIP as well as One-Time Programmable (OTP) PDIP , PLCC , and TSOP 叫…∞ mm川r川 FUNCTIONAL BLOCK DIAGRAM 。 ~vcc 。 'GND 0凹PP 二二1 CE ~I 000-007 』' CHIP ENABLE AND PROG LOGIC 什 ' OUTPUT BUFFERS Y GATING .. …吟| • I 524 ,288-BIT X DECOßER ' I CELL MATRIX 1881 reserves Ihe righl 10 make changes 10 ils products al any lime without nolice in order 10 improve design and supply Ihe besl possible proQuct. We assume no responsibility for any errors whi由 appear in Ihis publicalion. @ Copyrighl 1995 , Inlegraled 8ili∞ n SoI ution , 1时 π旧y Integrated Silicon Solution, Inc. Rev. C 0595 EP81995D803 乒 .. 5-21 IS27C512 5于/ ""1 黯器;二 PIN CONFIGURATIONS 28-Pin DIP PIN DESCRIPTIONS Address Inputs CE (E) Chip Enable Input DQO-DQ7 Data Inputs/Outputs OE (G)/Vpp Output Enable Input / program Voltage Input A15 vcc A12 A14 A7 A13 A6 A8 A5 A9 A4 A11 Vcc Power Supply Voltage A3 OE (G)NPP GND Ground A2 A10 NC No Internal Connection A1 CE (E) AO OQ7 OQO OQ6 OQ1 OQ5 OQ2 OQ4 GNO OQ3 32-Pin PlCC ‘ INDEX < h , 28-Pin TSOP NU F < F O Z 8 > j1 寸凹 < F < F 曰曰t:l日J::J....J::l巳 4 3 2 • 32 31 30 29 A8 28 A9 25 OE (G)IVPP OE(G)NPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 " , 21 OQO[] 13 16 17 A5 OQ6 A4 18 19 20 TgFROQ2r王 O1E三3σoQ3 5-22 AO-A15 、orQ A3 ug3 F 22 23 24 25 26 27 28 1 • 2 3 4 5 6 7 A10 CE (E) DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 OQ1 OQO AO A1 A2 IS27C512 Standard Pinout Integratéd Silicon Solution, Inc. . Rev. C 0595 EP81995DS03 ....... 一 监豆二二二二一一一一一IU立 IS27C512 FUNCTIONAL DESCRIPTION Erasing the IS27C512 In orderto clear alllocations of their programmed contents , it is necessary to expose the IS27C512 to an ultraviolet light source. A dosage of 15W sec!cm 2 is required to completely erase the IS27C512. This dosage can be obtained by exposure to an ultraviolet lamp-wavelength of 2537 Angstroms (À)-with intensity of 12 ， 000μW!cm 2 for 15 to 20 minutes. The IS27C512 should be directly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the IS27C512 , and similar devices , will erase with light sources having wavelengths shorter than 4000À. The exposure to fluorescent light and sunlight will eventually erase the IS27C512 and exposure to them should be prevented to realize maximum system reliability. If used in such an environme时， the package window should be covered by an opaque label or substance. Programming the IS27C512 Upon delivery , or after each erasure , the IS27C512 has 524 ,288 bits in the "ONE" , or HIGH state. "ZEROs" are loaded into the IS27C512 through the procedure of programmlng. The programming mode is entered when 12.75 士 0.25Vis applied to the O El Vpp pin , Vcc =6.25V and CE is at VIL. For programming , the data to be programmed is applied eight bits in parallel to the data output pins. The write programming algorithm reduces programming time by using 100μs programming pulses followed by a byte verification to determine whether the byte has been successfully programmed. If the data does not verify , an additional pulse ìS applied for a maximum of 25 pulses. This process is repeated while sequencing through each .address of the EPROM. The write programming algorithm programs and verifies at Vcc =6.25Vand O El Vpp =12.75V. Afterthe final address is completed , all b调e are compared to the original data with Vcc 5.25V. = program Inhibit Programming of multiple IS27C512s in pa刚 lel with different data is also easily accomplished. Except for CE , alllike inputs of the paralle门 S27C512 may be common. A TTL low-Ievel program pulse applied to an IS27C512 CE input with OEl Vpp = 12.75 土 0.25V will program that IS27C512. A high-Ievel CE input inhibits the other IS27C512 from being programmed. Integrated Silicon Solution, Inc. Rev.cm到5 EP819950Sω 乒 Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with CE at VIL and OEl Vpp at VIL. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25 C :t 5 C ambient temperature range that is required when programming the IS27C512. 0 0 To activate this mode , the programming equipment must force 12.0 :t 0.5Von address lineA90fthe IS27C512. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. AII other address lines must be held at VIL during auto select mode. Byte 0 (AO =VIL) represents the manufacturer code , and byte 1 (AO = VI时， the device identifier code. For the IS27C512 , these two identifier bytes are given in the Mode Select table. AII identifiers manufacturer and device codes will possess odd parity , with the MSB (OQ7) defined as the parity bi t. Read Mode The IS27C512 has two control functions , btth of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Assuming that addresses are stable , address access time (tACC) is equal to the delay from CE to output (tCE). Output Enable (OE) is the output control and should be used to get data to the output pins , independent of device selection. Oata is available at the outputs tOE after the falling edge of OE assuming that CE has been LOW and addresses havebeen stable for at least tA cc - to巳 Stalldby Mode The IS27C512 hasa standby mode which reduces the maximum Vcc active curren t. It is placed in standby mode when CE is at VIH. The amount of current drawn in standby mode depends on the frequency and the number of address pins s,<< itching. The IS27C512 is specified with 50% of the address lines toggling at 5 MHz. A reduction of the frequency or quantity of address lines toggling will significantly reduce the actual standby curren t. . 5-23 .一 ~ IS27C512 。 ABSOLUTE MAXIMUM λ 隆 ISSI RATINGS仰 Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND AII pins except A9 and VPP VPP A9 Vcc 一0.6 to Vcc + 0.5(2) Vcc - 0.3 to 13.5(2.3) 一0.6 to 13.5(2, 3) 一0.6 to 7.0(2) V V V V TA Ambient Temperature with Power Applied 一65 to +125 。C TSTG Storage Temperature (OTP) -65 to +125 。C - Storage Temperature (AII others) 一65 to +150 。C TSTG Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Minimum DC input voltage is .5V. During transitions , inputs may undershoot to -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 10 ns. 3. Maximum DC voltage on A9 or VPP may overshoot to + 13.5V for periods less than 10 ns. -o 因 OPERATING RANGE 一。 ι' 0 J 一40 C to +85 C -。 to +70 o C 0 MA 叫圃， -E·-d 唱 E- E-u-EU -f。 -r。 V 一+二± 0。 C Commercial Industrial(l) :-nu-nU -v-V AmbientTemperature Range Note: 1. Operating ranges define those limits between which the functionally of the device is guaranteed. ' DC ELECTRICAL CHARACTERISTICS(1 ,2,3) .. (Over Operating Range) Symbol Parameter Test Conditions Min. VOH Output HIGH Voltage Vcc 2 .4 VOL Output LOW Voltage =Min. , IOH =-400μA Vcc = Min. , IOL =2.1 mA VIH Input HIGH Voltage(4) VIL Input LOW Voltage(4) Input Load Current ILO ‘' Output Leakage Current Max. Unit V 0 .45 V 2.0 Vcc + 0.5 V -0.3 0.8 V 5.0 μA 10 μA =OV to +Vcc VOUT = 0飞机o+Vc。 VIN Notes: 1. Vcc must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below Vcc. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27C512 must not be removed from (or inserted into) a socket when Vcc or VPP is applied. 3. Minimum DC input voltage is 甲O.5V. During transitions , the inputs may undershoofto -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is Vcc + 0.5V whic~ may overshoot to Vcc + 2.0V for periods less than 10 ns. 4. Tested under static DC conditions. Integrated Silicon Solution, Inc. Rev.C0595 EP81995DS03 a P . 5-25 黯 IS27C512 1 System Applications During the switch between active and standby conditions , transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device at a minimum , a 0.1μFceramic capacitor (high-frequency , low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition , to overcome the voltage drop caused by the inductive effects of the printed circuìt board traces on EPROM arrays , a 4.7μF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. Output OR-Tieing To accommodate multiple memo叩 connections ， a twoline control function is provided to allow for: 1. 2. 1 Low memory power dissipation , and Assurance that output bus contention will not occu r. It is recommended that CE be decoded and used as the primary device-selecting function , while O El Vpp be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. TRUTH TABLE(1 ,2,4) Mode CE O El Vpp AO A9 Outputs Read Output Disable Standby Program Program Verify program Inhibit Auto Select(3 .5) Manufacturer Code Device Code VIL VIL VIH X X X X X X X X X X X X DOUT Hi-Z Hi-Z DIN DOUT Hi-Z VIL VIH VH VH D5H 91H X VIH VIL VIL VIH VIL VIL X VPP VIL VPP VIL VIL ' Notes: 1. VH = 12.0V :t O.5V. 2. X = Either VIH or VI L. 3. A1-A8 = A10-A15 = VI L. 4. 8ee DC Programming Characteristics for VPP voltage during programming. 5. The 1827C512 can use the same write algorithm during program as other 1827C512 or 1827512 devices. ~ LOGIC SYMBOL AO-A15 000-007 CE (E) OE (G)!V PP 5-24 F Integrated Silicon SOlut;on, Inc. Rev. C 0595 EP81995DS03 露黯 IS27C512 ISSI POWER SUPPLY CHARACTERISTICS(1 ,2 ,4) (Over Operating Range) Symbol Parameter Test Conditions ICC1 Vcc Operating Supply Current(3) VCC Max. , CE VIL 10UT 0 mA , f 5 MHz (Open outputs) ICCQO Vcc CMOS Standby Quiescent Current ICCSBO IcCSB1 Vcc CMOS Standby Current Vcc TTL Standby Current = = Min. = = Max. Unit 30 30 mA Commercial Industrial CE 三 Vcc-0.3V 100μA AII pins 2: Vcc 一 0.3V or ~二 0.3V (AII inputs fixed , no switching) CE~三 VCC 一 0.3V 1 mA 2 mA AII pins 三 VCC 一 0.3V or 三 0.3V toggling f::; 5 MHz CE 二 VIH AII pins =VIH or VIL (TTL level) toggling f 三 5MHz Notes: 1. Vcc must be applied simultaneously or before VPP and removed simultaneously or after VPP. Never try to force VPP LOW to 1V below Vcc. Manufacturer suggests to tie VPP and Vcc together during the READ operation. 2. Caution: the IS27C512 must not be removed from (or inserted into) a socket when Vcc or VPP is applied. 3. Icc1 is tested with O El Vpp = VIH to simulate open outputs. 4. Minimum DC input voltage is -G .5V. During transitions , the inputs may undershoot to -2.0V for periods less than 10 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than 10 ns. CAPACITANCE(1 ,2 ,3) DIP Symbol Parameter CIN Input Capacitance COUT Output Capacitance CIN O E/ VPp O E/ VPp Capacitance PLCCITSOP Typ. Max. Conditions Typ. Max. =OV VOUT =OV O E/ VPp = OV 6 10 6 9 8 12 6 9 pF 12 15 12 15 pF VIN Unit ' pF Notes: 1. Typìcal values are for nominal supply voltage. 2. This parameteris only sampled , but not 100% tested. 3. Test conditions: TA =25 0 C, f = 1 MHz. e SWITCHING TEST CIRCUIT 4，，-、『 HU 0.8V INPUT HVMV nueo -HU E、一，， - -兴 u 一忡 0.45V 一一...;/-一~ nu 2.7 Kn ， 2句-一、 --f- 2.0V 、→ J'O 5.0V 句ι ， • SWITCHING TEST WAVEFORM F-ST Notes: AC Testing: 1. Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". 2. Input pulse rise and fall times are < 20ns. 5-26 重 Integrated Silicon SOfut;on, Inc. .. Rev. C0595 EP81995DS03 黯霹黠 IS27C512 ISSI SWITCHING CHARACTERISTICS(1 ,2,3,4) (Over Operating Range) JEDEC Symb01 Std. Symbol -90 ÌAVOA tACC Address to Output Delay CE OE CL = CL1 90 tELOV tcE Chip Enable to Output Delay OE = VIL CL = CL1 tGLQV tOE Output Enable to Output Delay CE = VIL CL = CL1 tEHOZ, tGHOZ tOF(21 Chip Enable HIGH or Output Enable HIGH, whichever comes first, toOutput Float CL = CL2 ÌAvox tOH Output Hold from Address , CE orOE whicheveroccured first P a r a m e t e T,est Conditions Min. = =VIL 0 0 -12 Max. -15 Max. Unit 120 150 ns 90 120 150 ns 45 50 65 ns 35 ns 30 Min. 0 Max. 35 0 Min. 0 0 ns 圈 Notes: 1. Vcc must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled , not 100% tested. 3. Caution: The IS27C512 must not be removed from (or inserted into) a socket or board when VPP or Vcc applied. 4. Output Load: 1 TIL gate and CL = 100 pF. Input Rise and Fall times: 20 ns. Input Pulse Levels: 0 .4 5 to 2 .4V. Timing Measurement Reference Level: 0.8V to 2.0V for inputs and outputs. ' SWITCHING WAVEFORMS 2.4 V ADDRESS O.4 V 〉皮 2.0V O.6V ADDRESS VA Ll D CE tCE OE/Vpp \i , |唱 •• OUTPUT tA Cc (1) Hi-Z VA Ll D OUTPUT Notes: 1. OE may be delayed 旦旦to 吧cc - tOE after the falling edge of CE without impact on tACC. 2. tDF is specified from OE or CE , ~hichever occurs firs t. Integrated Silicon Solution, Inc. C0595 EP81995DS03 Rev. 乒 . 5-27 ""1 露黎注I二 IS27C512 DC PROGRAMMING CHARACTERISTICS(1 ,2 ,3) (TA =+25 0 C :t 5 0 C) Symbol Parameter Test Conditions Min. VOH Output HIGH Voltage During Verify 2 .4 VOL Output LOW Voltage During Verify =--400μA IOL =2.1 mA VIH Input HIGH Voltage VIL IOH Max. Unit V 0 .4 5 V 2.0 Vcc + 0.5 V Input LOW Voltage (Alllnputs) -0.3 0.8 V VH A9 Auto Select Voltage 11.5 12.5 V lu Input Current (Alllnputs) 10.0 μA Icc Vcc Supply Current (program & Verify) 50 mA Ipp VPP Supply Current 30 mA Vcc Supply Voltage 6.0 6.5 V VPP Programming Voltage 12.5 13.0 V VIN CE = VIL or VIH = VIL , OE =VIH SWITCH PROGRAMMING CHARACTERISTICS(1 ,2,3) (TA =+25 0 C :t 50 C) JEDEC Symbol Std. Symbol tAVEL tA s Address Setup Time 2 μs tEHGL tOEH O El Vpp Hold Time 2 μs tOVEL tos Data Setup Time 2 μs tGHAX tAH Address Hold Time O μs tEHOX tOH Data Hold Time 2 μs tEHOZ tOFP CE HIGH to Output Float Delay O tvps tvps VPP Setup Time 2 tELEH1 tpw CE Program Pulse Width 95 tvcs tvcs Vcc Setup Time 2 μs tGLEL tVR O El Vpp Recovery Time 2 μs .. tELOV -Notes: tov Data Valid from CE Min. Parameter Max. Unit ' 130 ns μs 105 μs 150 ns 1. Vcc must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. When programming IS27C512, a 0.1μF capacitor is required across VPP and ground to suppress spurious voltage transients which may damage~he device. 3. Programming characteristics are sampled but not 100% teste <f at worst-case conditions. 5-28 F Integrated Silicon Solution, Inc. . Rev. C0595 EP81995DS03 ............- 黯意I巳二 IS27C512 IS立I PROGRAMMING ALGORITHM WAVEFORM(1 ,2) PROGRAM 4喝一一一一一一 PROGRAM VERIFY 一一一.. ADDRESS DATA tDV CE OEIVpp tvcs 一" Vcc Notes: 1. The timing reference level is O.8V to 2V for inputs and outputs 2. tOE and tOFP are characteristics of the device but must be accommodated by the programme r. ' " , Integrated Silicon Solution, Inc. Rev. C0595 EPB19950S03 F . 5-29 / 黯器 IS27C512 ISSI PROGRAMMING FLOW CHART 本 Address = First Location Interactive programmmg Section Program One 100 IJs Pulse Yes Fail Increment Address , 臼 |lli窗' 印1 ve c on Pass iD例iωPassed 陷 . am咽创 g z'con so,..UauE iC ‘ "叫四川阳 ,,,nategr aazed -WM 山民 乒 ·@n问 m 5-30 I ~ 隘在二二川 IS27C512 1551I ORDERING INFORMATION o Commercial Rangle: OOC to +70 C Speed (ns) Order Part Number Package 90 90 90 90 IS27C512-90W IS27C512-90PL IS27C512-90CW IS27C512-90T 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window 了SOP 120 120 120 120 IS27C512-12W IS27C512-12PL IS27C512-12CW IS27C512-12T 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window TSOP 150 150 150 150 IS27C512-15W IS27C512-15PL IS27C512-15CW IS27C512-15T 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window TSOP 圈 ORDERING INFORMATION Industrial Range: Sp回d (ns) o 0 -40 C to +85 C Order Part Number Package 90 90 90 90 IS27C512-90WI IS27C512-90PLI IS27C512-90CWI IS27C512-90TI 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window TSOP 120 120 120 120 IS27C512-12WI IS27C512-12PLI IS27C512-12CWI IS27C512-12TI 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window TSOP 150 150 150 150 IS27C512-15WI IS27C512-15PLI IS27C512-15CWI IS27C512-15TI 600-mil Plastic DIP PLCC - Plastic Leaded Chip Carrier 600-mil Ceramic DIP with window TSOP ' 合 , Integrated Silicon Solution, Inc. Rev. C0595 EPBl995DS03 j . 5-31