ETC MAX7049

19-5867; Rev 0; 6/11
备有评估板
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
概述
MAX7049高性能、单芯片、超低功耗ASK/FSK UHF发送
器工作在288MHz至945MHz工业、科学和医学(ISM)载波
频段。IC还包括一个低相位噪声N分频合成器，支持高精
度调谐、快速变频，并可有效降低带外功率。为支持窄带
应用，该IC还具有幅度整形和频率整形功能，方便用户优
化频谱效率。IC提供高达+15dBm的Tx功率，非常适合远
距离通信应用。
这款IC的其它系统级功能包括：内置数字温度传感器和多
个灵活的GPO，可方便监测射频通信状态、控制外部功能。
该IC配合一个低成本的微处理器控制单元(MCU)、一个晶
体和少数无源元件，即可构成完整的发送器系统。
IC采用小尺寸5mm x 5mm、28引脚、带有裸焊盘的TQFN
封装，工作在-40℃至+125℃汽车级温度范围。
应用
优势和特性
S发送器(Tx)
功率高达+15dBm，支持远距离传输
Tx功率为+10dBm时，Tx电流为21mA*
Tx功率为+15dBm时，Tx电流为41mA*
ASK、FSK调制
S通用特性
延长电池寿命
关断电流< 50nA
休眠电流< 350nA
减少了IC与MCU串行外设接口(SPITM)之间所需的I/O
数量
满足以下规范
FCC Part 15跳频
ETSI EN300-220
内置温度传感器
带有用户自定义外部环路滤波器的快速N分频合成器
自动抄表(AMR)
RF模块
远程、单向遥控钥匙(RKE)
*VDD = 3.0V，包括匹配网络和谐波滤波器的功耗。
无线传感器网络
TPMS
家庭安全监控
定购信息在数据资料的最后给出。
家庭自动化
RFID
相关型号以及配合该器件使用的推荐产品，请参见：china.maxim-ic.com/
MAX7049.related。
远端控制
SPI是Motorola, Inc.的商标。
�� Maxim Integrated Products 1
本文是英文数据资料的译文，文中可能存在翻译上的不准确或错误。如需进一步确认，请在您的设计中参考英文资料。
有关价格、供货及订购信息，请联络Maxim亚洲销售中心：10800 852 1249 (北中国区)，10800 152 1249 (南中国区)，
或访问Maxim的中文网站：china.maxim-ic.com。
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
目录
Absolute Maximum Ratings................................................................................................................................................. 5
DC Electrical Characteristics................................................................................................................................................ 5
AC Electrical Characteristics................................................................................................................................................. 6
典型工作特性........................................................................................................................................................................ 9
引脚配置............................................................................................................................................................................. 13
引脚说明............................................................................................................................................................................. 13
功能框图............................................................................................................................................................................. 15
详细说明............................................................................................................................................................................. 15
架构概述和应用电路...................................................................................................................................................... 15
数字输入和输出............................................................................................................................................................. 17
数字输入................................................................................................................................................................... 17
数字输出................................................................................................................................................................... 17
串行外设接口(SPI).................................................................................................................................................... 19
SPI命令..................................................................................................................................................................... 20
工作模式概述............................................................................................................................................................ 21
休眠模式................................................................................................................................................................... 22
温度检测模式............................................................................................................................................................ 23
Tx模式...................................................................................................................................................................... 23
跳频扩谱(FHSS)工作原理......................................................................................................................................... 24
功能说明........................................................................................................................................................................ 24
晶振.......................................................................................................................................................................... 24
N分频合成器............................................................................................................................................................. 26
Tx ASK模式.............................................................................................................................................................. 26
频率整形Tx FSK模式................................................................................................................................................ 27
Tx脉冲FSK模式......................................................................................................................................................... 29
环路带宽................................................................................................................................................................... 29
锁定检测器............................................................................................................................................................... 30
功率放大器............................................................................................................................................................... 31
幅度整形Tx ASK模式................................................................................................................................................ 33
Tx FSK模式下的幅度缓变控制.................................................................................................................................. 34
寄存器详细说明.................................................................................................................................................................. 35
寄存器详细说明............................................................................................................................................................. 37
布局考虑............................................................................................................................................................................. 49
定购信息............................................................................................................................................................................. 50
芯片信息............................................................................................................................................................................. 50
封装信息............................................................................................................................................................................. 50
修订历史............................................................................................................................................................................. 51
�� Maxim Integrated Products 2
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
图目录
图1. SPI时序图...................................................................................................................................................................... 8
图2. 典型工作电路.............................................................................................................................................................. 16
图3. 数字输入..................................................................................................................................................................... 17
图4. 数字输出..................................................................................................................................................................... 18
图5. 数字输出选项.............................................................................................................................................................. 18
图6. SPI格式....................................................................................................................................................................... 20
图7. SPI写命令格式............................................................................................................................................................ 20
图8. SPI读命令格式............................................................................................................................................................ 21
图9. SPI全读命令格式.........................................................................................................................................................21
图10. SPI复位命令格式.......................................................................................................................................................21
图11. 工作模式................................................................................................................................................................... 21
图12. Tx预热时序图............................................................................................................................................................23
图13. 跳频扩谱(FHSS)流程图..............................................................................................................................................24
图14. 推荐的晶振与IC连接..................................................................................................................................................25
图15. N分频合成器配置Tx ASK模式................................................................................................................................... 27
图16. Tx FSK模式设置........................................................................................................................................................ 28
图17. Tx FSK频率整形时序图............................................................................................................................................. 28
图18. 合成器环路滤波器拓扑..............................................................................................................................................30
图19. 锁定检测器延迟功能.................................................................................................................................................30
图20. 功率放大器拓扑和信号摆幅优化...............................................................................................................................31
图21. Tx ASK模式设置........................................................................................................................................................ 32
图22. ASK整形时序图.........................................................................................................................................................33
图23. Tx FSK幅度缓变控制................................................................................................................................................. 34
图24. Tx FSK幅度缓变控制时序图...................................................................................................................................... 35
表目录
表1. 数字输入控制选项.......................................................................................................................................................17
表2. 模式控制逻辑.............................................................................................................................................................. 22
表3. 模式选项逻辑.............................................................................................................................................................. 22
表4. 休眠模式汇总.............................................................................................................................................................. 22
表5. 温度检测模式汇总.......................................................................................................................................................23
表6. 晶振分频器设置...........................................................................................................................................................25
表7. LO分频器模式............................................................................................................................................................. 26
表8. Tx FSK脉冲模式下的倍频器....................................................................................................................................... 29
表9. PA设计示例................................................................................................................................................................. 32
�� Maxim Integrated Products 3
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表目录(续)
表10. 配置寄存器映射.........................................................................................................................................................35
表11. 第0组：标识寄存器(Ident).........................................................................................................................................37
表12. Ident寄存器(0x00).....................................................................................................................................................37
表13. 第1组：通用配置寄存器(Conf0、Conf1)...................................................................................................................37
表14. Conf0寄存器(0x01)....................................................................................................................................................37
表15. Conf1寄存器(0x02)....................................................................................................................................................38
表16. 第2组：GPO、数据输出和时钟输出寄存器(IOConf0、IOConf1、IOConf2)............................................................. 38
表17. IOConf0寄存器(0x03)................................................................................................................................................39
表18. IOConf1寄存器(0x04)................................................................................................................................................40
表19. IOConf2寄存器(0x05)................................................................................................................................................41
表20. 第3组：合成器频率设置(FBase0、FBase1、FBase2、FLoad)................................................................................. 41
表21. 合成器分频器设置.....................................................................................................................................................41
表22. 合成器设置................................................................................................................................................................ 42
表23. 频率范围................................................................................................................................................................... 42
表24. FBase0寄存器(0x08).................................................................................................................................................42
表25. FBase1寄存器(0x09).................................................................................................................................................42
表26. FBase2寄存器(0x0A).................................................................................................................................................42
表27. FLoad (0x0B)............................................................................................................................................................. 42
表28. 第4组：发送器幅度和定时参数(TxConf0、TxConf1、TxTstep)................................................................................ 43
表29. TxConf0寄存器(0x0C)...............................................................................................................................................43
表30. TxConf1寄存器(0x0D)...............................................................................................................................................43
表31. TxTstep寄存器(0x0E)................................................................................................................................................43
表32. 第5组：发送器整形寄存器(Shape00-Shape18)........................................................................................................44
表33. Shape00寄存器(0x0F)...............................................................................................................................................44
表34. Shape01-Shape18寄存器(0x10-0x21).....................................................................................................................45
表35. 第6组：控制寄存器(TestMux、Datain、EnableReg)................................................................................................ 45
表36. TestMux寄存器(0x3C)...............................................................................................................................................45
表37. Datain寄存器(0x3D)..................................................................................................................................................46
表38. EnableReg寄存器(0x3E)............................................................................................................................................46
表39. 第7组：只读状态寄存器(TestBus0、TestBus1、Status0、Status1)........................................................................ 46
表40. TestBus0寄存器(0x40)..............................................................................................................................................46
表41. 测试总线信号(tbus[15:8])..........................................................................................................................................47
表42. TestBus1寄存器(0x41)..............................................................................................................................................47
表43. 测试总线信号(tbus[7:0])............................................................................................................................................48
表44. Status0寄存器(0x42).................................................................................................................................................49
表45. Status1寄存器(0x43).................................................................................................................................................49
�� Maxim Integrated Products 4
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
ABSOLUTE MAXIMUM RATINGS
PAVDD, LOVDD, VCOVDD, CPVDD, PLLVDD,
XOVDD, DVDD, and AVDD to EP.....................-0.3V to +3.6V
ENABLE, DATAIN, SDI, SDO, CS, SCLK,
GPO1, GPO2, HOP, and SHDN to EP.. -0.3V to (VDD + 0.3V)
All Other Pins to EP................................... -0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70NC)
TQFN (single-layer board)
(derate 21.3mW/NC above +70NC)..........................1702.1mW
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
Supply Voltage
SYMBOL
VDD
CONDITIONS
PAVDD, LOVDD, VCOVDD, CPVDD,
PLLVDD, XOVDD, DVDD, and AVDD
connected to power supply
PA off
Operating Current
IDD
Shutdown Current
Input Low Voltage
VIL
Input High Voltage
VIH
PA off,
PA predriver at
high current
setting
MIN
TYP
MAX
UNITS
2.1
3.0
3.6
V
fRF = 315MHz
11.2
fRF = 434MHz
10.4
fRF = 863MHz to 945MHz
10.2
fRF = 315MHz
13.2
fRF = 434MHz
12.4
fRF = 863MHz to 945MHz
12.2
868MHz +15dBm
POUT = +15dBm matching network with
harmonic filter
41
868MHz +10dBm
POUT = +10dBm matching network with
harmonic filter
21
TA = +25NC, Sleep mode
350
TA = +85NC, Sleep mode
600
TA = +125NC, Sleep mode
1700
TA = +25NC, Shutdown mode (registers reset)
50
TA = +85NC, Shutdown mode (registers reset)
200
TA = +125NC, Shutdown mode
(registers reset)
1300
mA
4000
nA
3500
0.2 x VDD
0.8 x VDD
V
�� Maxim Integrated Products 5
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
DC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Pulldown Sink Current
12.5
Pullup Source Current
12.5
Output Low Voltage
Output High Voltage
VOL
In buffer mode, GPO1 250FA sink current,
SDO 1mA sink current, and GPO2 4mA
sink current
VOH
In buffer mode, GPO1 250FA source current,
SDO 1mA source current, and GPO2 4mA
source current
MAX
UNITS
FA
0.225
V
VDD - 0.225
AC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Operating Frequency
Maximum Data Rate
Maximum Frequency Deviation
Frequency Settling Time
Divide-by-1 LO divider setting
863
945
Divide-by-2 LO divider setting
431.5
472.5
Divide-by-3 LO divider setting
287.7
315
Manchester encoded
100
NRZ encoded
200
100kHz synthesizer loop bandwidth
tON
From Enable low-to-high transition to LO
within 5kHz of final value, 100kHz synthesizer
loop bandwidth
Q150
MHz
kbps
kHz
330
Fs
From Enable low-to-high transition to LO
within 1kHz of final value, 100kHz synthesizer
loop bandwidth
400
Match to 50I, including harmonic filter
+15
dBm
Programmable PA Bias Current
Step
With Q1% 56.2kI external PA reference
current setting resistor
0.5
mA
Programmable PA Power
Dynamic Range
Power range from decimal 1 to decimal 63
on digital PA bias current
36
dB
Modulation Depth
With respect to +10dBm output power
57
dB
Maximum Carrier Harmonics
With output matching network
-50
dBc
POWER AMPLIFIER
Maximum Output Power
PMAX
�� Maxim Integrated Products 6
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FRACTIONAL-N SYNTHESIZER
VCO Gain
KVCO
Referenced to 863MHz to 945MHz LO
108
MHz/V
Close-In Phase Noise
10kHz offset, 100kHz loop BW
-101
dBc/Hz
VCO Phase Noise
1MHz offset, 863MHz to 945MHz
-126
dBc/Hz
VOUT = VCPVDD/2, low setting (icont bit = 0)
204
FA
VOUT = VCPVDD/2, high setting (icont bit = 1)
407
FA
Charge-Pump Current
ICP
1
LO Divider Settings
2
3
Minimum Synthesizer Frequency
Step
Referenced to 863MHz to 945MHz LO or
carrier frequency band
fXTAL/216
Hz
-71
dBc
48
Fs
1
VP-P
7
Bits
7.25
mV
16 to 22.4
MHz
Frequency Pulling by VDD
0.5
ppm/V
Recommended Crystal Load
Capacitance
10
Maximum Crystal Load
Capacitance
20
Reference Spur
26MHz frequency step, 902MHz to 928MHz
band, 100kHz synthesizer loop bandwidth
Frequency Switching Time
Reference Frequency Input
Level
ADC
Resolution
LSB Bit Width
CRYSTAL OSCILLATOR
Crystal Frequency
fXTAL
pF
TEMPERATURE SENSOR
Range
Digital Code Slope
-40 to +125
NC
2
NC/LSB
SPI TIMING CHARACTERISTICS (Figure 1)
Minimum SCLK Low to Falling
Edge of CS Setup Time
tSC
20
ns
Minimum CS Low to Rising Edge
of SCLK Setup Time
tCSS
30
ns
�� Maxim Integrated Products 7
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
Minimum SCLK Low to Rising
Edge of CS Setup Time
CONDITIONS
MIN
TYP
MAX
UNITS
tHCS
30
ns
Minimum SCLK Low after Rising
Edge of CS Hold Time
tHS
20
ns
Minimum Data Valid to SCLK
Rising-Edge Setup Time
tDS
15
ns
Minimum Data Valid to SCLK
Rising-Edge Hold Time
tDH
10
ns
Minimum SCLK High Pulse
Width
tCH
30
ns
tCL
30
ns
Minimum CS High Pulse Width
tCSH
30
ns
Maximum Transition Time from
Falling Edge of CS to Valid SDO
tCSG
CL = 10pF load capacitance from
SDO to GND
20
ns
Maximum Transition Time from
Falling Edge of SCLK to
Valid SDO
tCG
CL = 10pF load capacitance from
SDO to GND
20
ns
Minimum SCLK Low Pulse Width
CS
tCSH
tCSS
tHCS
tSC
tCH
SCLK
tCL
tDH
tHS
tDS
SDI
tCSG
tCG
SDO
图1. SPI时序图
�� Maxim Integrated Products 8
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
典型工作特性
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
1.0
VDD = 3.6V
0.8
VDD = 3.0V
0.6
VDD = 2.7V
0.4
VDD = 2.1V
0.2
0
-50
-25
0
25
50
75
100
125
VDD = 3.6V
1.6
1.4
1.2
1.0
0.8
VDD = 3.0V
VDD = 2.7V
VDD = 2.1V
0.6
0.4
0.2
0
-25
940
0
25
50
75
100
MAX7049 toc03
-50
-25
0
TA = +85˚C
25
50
75
100
125
CHARGE-PUMP CURRENT
vs. CONTROL VOLTAGE
(LOW CURRENT SETTING, 2.1V SUPPLY)
FREQUENCY SETTLING
AFTER POWER-UP
MAX7049 toc05
868.62MHz
868.60MHz
880
860
20
TEMPERATURE (°C)
920
900
40
125
TA = +25˚C
TA = +125˚C
840
250
-40˚C
200
+25˚C
+85˚C
150
100
-40˚C
+125˚C
DOWN
UP
50
820
868.58MHz
800
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
TRANSMIT FREQUENCY (MHz)
960
MAX7049 toc04
TA = -40˚C
60
TEMPERATURE (°C)
VCO TUNING CHARACTERISTIC
(IN 900MHz BAND) vs. CONTROL VOLTAGE
980
80
0
-50
TEMPERATURE (°C)
1000
100
MAX7049 toc06
1.2
1.8
120
TEMPERATURE SENSOR CODE (DECIMAL)
1.4
2.2
2.0
CHARGE-PUMP CURRENT (µA)
1.6
MAX7049 toc02
SHUTDOWN MODE CURRENT (µA)
1.8
2.4
SLEEP MODE CURRENT (µA)
MAX7049 toc01
2.0
TEMPERATURE SENSOR CODE
vs. TEMPERATURE
SLEEP MODE CURRENT
vs. TEMPERATURE
SHUTDOWN MODE CURRENT
vs. TEMPERATURE
CONTROL VOLTAGE WITH RESPECT TO SUPPLY (V)
0.00s
500.0µs
100.0µs/div
1.000ms
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CONTROL VOLTAGE WITH RESPECT TO GROUND (V)
�� Maxim Integrated Products 9
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
典型工作特性(续)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
927MHz, ibsel = 1
-130
-140
10
100
1000
10,000
OFFSET FREQUENCY (kHz)
-30
-40
-50
-80
-80
-90
-90
868.590 868.594 868.598 868.602 868.606 868.610
926.990 926.994 926.998 927.002 927.006 927.010
868.592 868.596 868.600 868.604 868.608
FREQUENCY (MHz)
926.992 926.996 927.000 927.004 927.008
FREQUENCY (MHz)
0
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+10dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
0
-20
-10
-20
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
926.990 926.994 926.998 927.002 927.006 927.010
926.992 926.996 927.000 927.004 927.008
FREQUENCY (MHz)
POWER (dBc)
-40
-50
-70
-30
-30
-40
-60
-10
POWER (dBc)
POWER (dBc)
-20
-30
-70
UNMODULATED SPECTRUM
(palopwr = 0, 100% DUTY CYCLE,
+10dBm, 868MHz,
WITH +10dBm AT 3V MATCH)
MAX7049 toc10
-10
-20
-60
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
16MHz CRYSTAL, ibsel = 0, icont = 0)
0
-10
MAX7049 toc12
-110
MAX7049 toc08
-20
POWER (dBc)
927MHz, ibsel = 0
-120
-10
POWER (dBc)
868MHz, ibsel = 0
-100
0
MAX7049 toc11
-80
PHASE NOISE (dBc/Hz)
0
MAX7049 toc07
-70
-90
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
MAX7049 toc09
PHASE NOISE (VCO DOMINATED)
vs. OFFSET FREQUENCY
(CL = 0.1µF, CS = 0.01µF,
R = 200I, RP = CP = 0)
UNSHAPED
-30
-40
-50
-60
GAUSSIAN
-70
848 853 858 863 868 873 878 883 888
FREQUENCY (MHz)
-80
867.75
867.85
867.80
867.95
868.05
868.15
867.90 868.00 868.10
FREQUENCY (MHz)
868.25
868.20
�� Maxim Integrated Products 10
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
典型工作特性(续)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
-10
-40
-50
-60
-70
GAUSSIAN
-80
867.85
867.80
867.95
-20
-20
-30
-30
-40
-50
868.15
867.90 868.00 868.10
FREQUENCY (MHz)
868.25
-70
-70
867.95
868.20
867.97
867.96
867.99
868.01
868.03
867.98 868.00 868.02
FREQUENCY (MHz)
-10
GAUSSIAN
-20
-40
-50
-10
868.05
UNSHAPED
-50
-80
-80
FREQUENCY (MHz)
868.03
-40
-70
868.6
868.01
-30
-60
868.2 868.4
867.99
FREQUENCY (MHz)
-20
-70
867.8 868.0
867.97
0
-60
-90
867.4 867.6
-80
867.95
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
POWER (dBc)
-30
868.05
868.04
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
0
-50
-60
-80
868.05
UNSHAPED
-40
-60
MAX7049 toc16
867.75
-10
MAX7049 toc17
-30
POWER (dBc)
UNSHAPED
POWER (dBc)
POWER (dBc)
-20
GAUSSIAN
POWER (dBc)
-10
0
MAX7049 toc14
0
MAX7049 toc13
0
FSK MODULATION SPECTRUM
(1kHz RBW, 4kHz SQUARE-WAVEMODULATION,
±4kHz DEVIATION, +10dBm OUTPUT POWER,
WITH +10dBm AT 3V MATCH)
FSK MODULATION SPECTRUM (1kHz RBW,
4kHz SQUARE-WAVE MODULATION,
±4kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
MAX7049 toc15
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+9dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
-90
867.4 867.6
867.8 868.0
868.2 868.4
868.6
FREQUENCY (MHz)
�� Maxim Integrated Products 11
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
典型工作特性(续)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 915MHz,
WITH +15dBm AT 3V MATCH)
15
VDD = 3.0V
10
POUT (dBm)
VDD = 3.6V
3.6V
10.30
10.20
10.10
VDD = 2.1V
10
3.0V
2.1V
5
3.6V
15
POUT (dBm)
10.40
20
MAX7049 toc19
10.50
9.90
0
-5
-5
0
25
50
75
100
-10
125
0
TEMPERATURE (°C)
8
16
24
32
40
48
56
64
0
10
12
POUT (dBm)
0
40
48
56
64
PA CODE 39
8
6
4
PA CODE 19
2
-5
32
14
10
2.4V 2.7V 3.0V 3.3V 3.6V
24
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc21
15
2.1V
16
PA CODE (DECIMAL)
PA POWER vs. PA CODE
(palopwr = 1, 100% DUTY CYCLE, 868MHz,
WITH +10dBm AT 3V MATCH)
5
8
PA CODE (DECIMAL)
MAX7049 toc22
-25
5
0
-10
-50
3.0V
2.1V
VDD = 2.7V
10.00
POUT (dBm)
Tx CURRENT (mA)
20
MAX7049 toc18
10.60
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc20
Tx CURRENT vs. TEMPERATURE
(PA OFF, 900MHz BAND, palopwr = 1)
PA CODE 10
0
-2
-10
0
8
16
24
32
40
PA CODE (DECIMAL)
48
56
64
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
�� Maxim Integrated Products 12
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
CS
SDI
SCLK
ENABLE
DATAIN
SDO
TOP VIEW
GPO2
引脚配置
21
20
19
18
17
16
15
DVDD 22
14
N.C.
HOP 23
13
XTALB
GPO1 24
12
XTALC
SHDN 25
11
XOVDD
10
N.C.
9
PLLVDD
8
CPOUT
MAX7049
AVDD 26
PA+ 27
EP
4
5
6
7
CTRL
CPVDD
PAVDD
REXTPA
3
VCOVDD
2
N.C.
1
LOVDD
+
PA- 28
TQFN
(5mm x 5mm)
引脚说明
引脚
名称
1
PAVDD
2
REXTPA
3, 10,
14
N.C.
4
LOVDD
5
6
功能
功率放大器电源输入。利用33pF电容旁路至地，电容尽量靠近引脚放置。
外部PA偏置电流设置电阻的连接端。通过±1%容限、低温度系数电阻耦合至地。建议采用56.2kΩ电阻，将PA偏
置电流DAC的LSB标称值设置在0.5mA。
无连接，保持浮空。
本地振荡器(LO)电源输入。利用33pF电容旁路至地，电容尽量靠近引脚放置。
VCOVDD 压控振荡器(VCO)电源。利用1μF电容旁路至地，电容尽量靠近引脚放置。
CTRL
VCO输入控制(调谐)电压，以VCOVDD引脚为参考。通过无源环路滤波器连接至CPOUT。
7
CPVDD
电荷泵电源输入。利用0.01μF电容旁路至地，电容尽量靠近引脚放置。
8
CPOUT
电荷泵输出。通过无源环路滤波器连接至CTRL。
9
PLLVDD
合成器电源输入。利用33pF电容旁路至地，电容尽量靠近引脚放置。
11
XOVDD
晶振电源输入。利用0.1μF电容旁路至地，电容尽量靠近引脚放置。
�� Maxim Integrated Products 13
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
引脚说明(续)
引脚
名称
功能
12
XTALC
集电极晶振输入，直接或通过交流耦合电容连接到晶体。该引脚可能需要与地之间连接电容，具体取决于晶振负
载电容和PCB杂散电容。也可以由信号摆幅为0.8VP-P至1.2VP-P、交流耦合的外部参考时钟驱动。
13
XTALB
基极晶振输入，直接或通过交流耦合电容连接到晶体。该引脚可能需要与地之间连接电容，具体取决于晶振负载
电容和PCB杂散电容。如果XTALC由外部参考时钟驱动，该引脚必须直流短路至地。
15
SDO
16
DATAIN
发送器数据输入，也可由SPI控制数据输入功能。内部下拉至地。
17
ENABLE
使能控制。驱动为高电平时正常工作；驱动为低电平或浮空时，器件置于休眠模式。使能控制也可以由SPI控制，
内部下拉至地。
18
SCLK
19
SDI
20
SPI低电平有效片选，内部上拉至电源。
21
CS
GPO2
22
DVDD
数字电源输入，利用0.1μF电容旁路至地，电容尽量靠近引脚放置。
23
HOP
24
GPO1
通用输出1，低驱动数字通用输出。
25
SHDN
关断控制数字输入。驱动为高电平时，关断内部上电复位(POR)电路，寄存器内容保持在初始状态。正常工作时
必须将该引脚驱动至低电平。内部没有拉至电源或地。
26
AVDD
模拟电源输入，利用1μF电容旁路至地，电容尽量靠近引脚放置。
27
PA+
功率放大器(PA)输出正端。需要通过电感通路提供直流供电回路，直流电流通路也是输出阻抗匹配和谐波滤波器
网络的一部分。
28
PA-
功率放大器(PA)输出负端。需要通过电感通路提供直流供电回路，直流电流通路也是输出阻抗匹配和谐波滤波器
网络的一部分。
—
EP
裸焊盘，这是唯一的接地点。为了保证器件正常工作，将该焊盘牢固地焊接到PCB的接地区域。建议在焊盘与
PCB接地区域之间采用多个过孔。
串行外设接口(SPI)数据输出，也可配置为通用数字输出。
SPI时钟，内部下拉至地。
SPI数据输入，内部下拉至地。
通用输出2，具有高驱动能力的数字通用输出。
跳频引脚，将base[20:0]位传送到N分频器，参见N分频合成器部分。跳频功能也可由SPI控制，内部下拉至地。
�� Maxim Integrated Products 14
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
功能框图
27
28
PA+ PASHDN* 25
MAX7049
2 REXTPA
6
PA
GPO1* 24
ADC
7
HOP* 23
TEMPERATURE
SENSOR
GPO2* 21
/1, /2, OR /3
8 CPOUT
CS 20
DIGITAL
CONTROL
AND MCU
INTERFACE
CHARGE
PUMP
SDI 19
SCLK 18
6 CTRL
FRACTIONAL-N
DIVIDER
PFD
ENABLE* 17
VCO
21
GROUNDED
PAD (EP)
DATAIN* 16
SDO* 15
XTAL OSCILLATOR
XTALC
XTALB
12
13
详细说明
架构概述和应用电路
MAX7049内部集成了一个高精度本振N分频合成器，包括
VCO、N分频器、鉴相/鉴频器、电荷泵、LO驱动器和锁
定检测器。环路滤波器位于片外，允许用户针对具体应用
优化合成器的噪声和瞬态特性。FSK发送模式下，合成器
根据DATAIN引脚或datain位(Datain寄存器，0x3D，第6位)
的状态发送高电平信号(mark)频率和低电平信号(space)频
率。用户可编程的频率整形功能帮助用户精确定义从高电
平信号频率到低电平信号频率(或反方向)的转换，使得调
制后的Tx波形占用最小带宽。
* OPTIONAL I/Os FROM/TO MCU.
IC采用差分发射极耦合、双集电极开路功率放大器发送输
出信号。输出级偏置电流由外部电阻和内部幅度整形电路
共同设置。可编程整形功能使得用户能够根据DATAIN引
脚或datain位的状态精确定义载波信号的开、启(或反方向)
转换过程，从而将调制后的Tx信号占用带宽降至最小。当
PA开启突发数据或结束突发数据关闭时，FSK模式采用线
性调节幅度缓变功能，以限制频谱范围。
IC配合低端MCU、晶振和少数用于电源旁路、射频匹配的
无源元件即可构成完整的发送器，如图2所示。
MCU与IC之间的通信通过4引脚SPI总线和可以选择的数字
输入、输出实现。
�� Maxim Integrated Products 15
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
C13
L1
DASHED LINES DENOTE OPTIONAL CONNECTIONS
C20
J1
C14
L3
L4
C12
L2
C11
50I
+
VDD
PAVDD
28
27
26
25
24
23
DVDD
HOP
GPO1
SHDN
AVDD
PA-
C15
PA+
C16
C17
22
1
21
2
20
3
19
4
18
C1
REXTPA
R1
N.C.
LOVDD
C2
C3
VCOVDD
CTRL
CPVDD
R2
MAX7049
5
17
GROUNDED
PAD (EP)
6
16
7
15
GPO2
CS
SDI
µP
SCLK
ENABLE
DATAIN
SDO
C4
C7
C8
14
N.C.
13
XTALB
12
11
XTALC
10
XOVDD
9
N.C.
8
PLLVDD
C5
CPOUT
C6
Y1
C9
C10
图2. 典型工作电路
�� Maxim Integrated Products 16
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
数字输入和输出
数字输入
IC的SPI输入包括：CS、SCLK和SDI引脚。CS引脚为低电
平有效，该引脚带有内部上拉；SCLK和SDI引脚带有内部
下拉。除SPI输入外，还提供多个IC数字输入选项，包括：
DATAIN、ENABLE和HOP。这些可选输入在内部下拉至
地电位，用户在控制内部信号时，可以选择把引脚驱动到
相应的逻辑电平或将控制位设置到相应状态，如图3所示。
数字输出
IC具有两路专用的通用输出(GPO1和GPO2)、一路SPI输
出(SDO)，CS为高电平时，SPI输出还可作为通用输出。
GPO1、GPO2和SDO引脚可配置输出不同的内部状态信号
和时钟，如图4所示。
输出(GPO1和GPO2)引脚既可作为数字缓冲器，也可作为
源出/吸入的限流输出，如图5所示。
SPI控制将IC和MCU之间所需的I/O数量降至最少，引脚控
制位可以节省与SPI通信有关的配置任务。
22 DVDD
22 DVDD
22 DVDD
INTERNAL
CSB
SIGNAL
20 CS
INTERNAL
INPUT
SIGNAL
INPUT
‘OR’
INPUT
INPUT
GROUNDED
PAD (EP)
GROUNDED
PAD (EP)
INTERNAL
INPUT
SIGNAL
PROGRAMMABLE
CONTROL BIT
GROUNDED
PAD (EP)
INPUT = SCLK AND SDI
INPUT = DATAIN, ENABLE, AND HOP
SPI INPUTS
图3. 数字输入
表1. 数字输入控制选项
PIN
BIT NAME
REGISTER
NAME
REGISTER
ADDRESS (hex)
BIT LOCATION
(7:0)
DATAIN
datain
Datain
0x3D
6
Data input to transmitter.
ENABLE
enable
EnableReg
0x3E
0
Enable input for transmitter.
HOP
hop
FLoad
0x0B
0
Initiates the transition to the next
frequency as defined by base[20:0].
FUNCTION
�� Maxim Integrated Products 17
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
sdos[3:0]
SPI READ-ONLY REGISTERS
TestBus0 AND TestBus1 (0x40 AND 0x41)
tmux[3:0]
INTERNAL SIGNALS
MUX
SDO 15
MUX
gp1s[3:0]
tbus[15:0]
gp1md[1:0]
GPO1 24
MUX
gp2s[3:0]
gp1isht
[15:4]
MAX7049
plllock
xtal
/16
ckdiv[1:0]
/1, /2,
/4, OR /8
gp2md[2:0]
GPO2 21
MUX
/1, /2,
/4, OR /8
gp2isht
/5, /6, mclk /1, /2,
/7, OR /8
/4, OR /8
clksht
XTALC
12
XTALB
xtal[1:0]
13
图4. 数字输出
BUFFER MODE
CURRENT MODE
DVDD 22
DVDD 22
ISOURCE
INTERNAL
SIGNAL
OUTPUT
GROUNDED
PAD (EP)
OUTPUT
INTERNAL
SIGNAL
ISINK
GROUNDED
PAD (EP)
图5. 数字输出选项
�� Maxim Integrated Products 18
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
电流工作模式能够降低与电源电流尖峰相关的数字噪声，
GPO1引脚的电流驱动能力相对较弱(80μA或160μA)，由
IOConf2寄存器(0x05) (gp1md[1:0]位)控制电流设置：
xtal为晶振频率，mclk为主控制器数字时钟。主控制器数
字时钟是由xtal[1:0]位(Conf0寄存器，0x01)设置分频的晶
振频率，设置如下：
gp1md[1:0]
模式
xtal[1:0]
分频比
0x
缓冲模式
00
5
10
80μA吸入/源出电流
01
6
11
160μA吸入/源出电流
10
7
11
8
GPO2具有较大的电流驱动(高达4mA)，该GPO可用作输出
时钟信号源。IOConf2寄存器(0x05) (gp2md[2:0]位)控制电
流设置：
gp2md[2:0] 模式
0xx
缓冲模式
100
1.0mA吸入/源出电流
101 2.0mA吸入/源出电流
110 3.0mA吸入/源出电流
111 4.0mA吸入/源出电流
如果在IC处于休眠模式(ENABLE引脚和使能位复位至0)时
仍需保持有效的GPO2时钟输出，则将SHDN引脚复位至0，
clksht位(IOConf2寄存器，0x05，第3位)必须置1。
GPO非常有用的一个功能是输出状态指示，可及时反映特
定条件下的发送器状态。关于TestBus0和TestBus1寄存器
的状态信号说明，请参考寄存器详细说明部分。
串行外设接口(SPI)
IC按照4线SPI协议设置寄存器，配置、控制整个发送器的
工作。
其它2位也用于控制GPO1和GPO2，IOConf0寄存器(0x03)
(gp1isht和gp2isht位)允许继续工作在电流模式，即使关闭
IC (休眠模式)。
以下数字引脚控制SPI工作：
CS:
低电平有效的SPI片选
GPO2引脚设计用于时钟驱动的主输出，具有最强的缓冲
能力，可输出最大电流。
SDI:
SPI数据输入
GPO2时钟信号可由gp2s[3:0]和ckdiv[1:0]位(IOConf0寄存
器，0x03)选择。
SDO:
gp2s[3:0]
GPO2输出
0000
plllock
0001
mclk/(ckdiv分频器)
在一个CS低电平周期内，可发送任意数量的8位数据(Data 1、
Data 2、... Data N)，允许进行突发写操作和突发读操作。
CS引脚为高电平时，SDO引脚用作通用输出(GPO)。
0010
xtal/(ckdiv分频器)
0011
xtal/16/(ckdiv分频器)
SCLK: SPI串行时钟
SPI数据输出
SPI采用字节格式通信，如图6所示。
其中ckdiv分频器为：
ckdiv[1:0]
分频比
00
1
01
2
10
4
11
8
�� Maxim Integrated Products 19
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
CS
SCLK
SDI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SDO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DATA 1
DATA N
图6. SPI格式
SPI命令
IC支持以下命令：
Write：在同一CS周期内，写命令操作如下：
SDI： <0x01> <Initial Address> <Data 1> <Data 2> ... <Data N>
利用该命令，将Data 1写入<Initial Address>指定的地址，Data 2写入<Initial Address + 1>指定的地址，依此类推。
Read：在同一CS周期内，读命令操作如下：
SDI： <0x02> <Address 1> <Address 2> <Address 3> ... <Address N>
SDO：<0xXX>
<0xXX>
<Data 1>
<Data 2>
<0x00>
... <Data N - 1> <Data N>
利用该命令，可在同一CS周期内读取所有寄存器。能够以任意顺序指定地址。
Read All：需要两个CS周期，Read All命令操作如下：
CS周期1 SDI： <0x03> <Address N>
SDO：
<0x00>
CS周期2
<0x00>
<0x00>
...
<0x00>
<Data N> <Data N + 1> <Data N + 2> ... <Data N + n>
Reset：SPI复位命令操作如下：
SDI： <0x04>
内部产生一个低电平有效的主控制器复位信号，从上一个SCLK信号的下降沿到下一个CS信号的下降沿(tHCS + tCSH)。
CS
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE COMMAND (0x01)
INITIAL ADDRESS (A[7:0])
DATA 1
D7
D0
DATA N
图7. SPI写命令格式
�� Maxim Integrated Products 20
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
CS
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7
READ COMMAND (0x02)
ADDRESS 1
ADDRESS 2
SDO
ADDRESS N
D7 D6 D5 D4 D3 D2 D1 D0 D7
DATA 1
A0
0x00
D0 D7
DATA 2
D0
DATA N
图8. SPI读命令格式
CS
SCLK
A7 A6 A5 A4 A3 A2 A1 A0
SDI
READ-ALL COMMAND (0x03)
ADDRESS N
SDO
D7 D6 D5 D4 D3 D2 D1 D0 D7
DATA N
D0 D7
D0
DATA N + 1 DATA N + n
图9. SPI全读命令格式
INITIAL
CS
SHUTDOWN
SCLK
SLEEP
SLEEP
XTAL ON
SDI
SPI
CONFIGURATION
TEMPERATURE
SENSOR
RESET COMMAND (0x04)
resetb
Tx
FSK
ASK
图10. SPI复位命令格式
图11. 工作模式
工作模式概述
IC提供多种工作模式，用户可根据具体应用将发送器的功
耗降至最小。主要工作模式包括：初始化、休眠、温度检
测和Tx模式，如图11所示。
SHDN引脚为高电平时，IC处于关断模式。关断模式下，
IC内部的POR电路禁用，不消耗电流。关断模式下，所有
内部数据寄存器复位到初始状态，只有在SHDN引脚驱动
至低电平后，重新配置寄存器才能进入相应的发送器工作
状态。
�� Maxim Integrated Products 21
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
SHDN引脚为低电平时，POR电路有效，内部数据寄存器
保持在初始状态，直到电源高于2.1V，IC进入初始化模式。
在初始化模式下，IC可以配置进入休眠模式、温度检测
模式或Tx模式。休眠模式下提供两个选择：休眠和XTAL
ON。休眠状态下，消耗电流的典型值为350nA，保留所有
寄存器状态；XTAL ON模式下，由clksht位(IOConf2寄存
器，0x05，第3位)控制，使能晶振，晶振信号经过分频(/1、
/2、/4、/8，由ckdiv[1:0]位(IOConf0寄存器，0x03，[5:4]位)
设置)后通过GPO2输出。设计XTAL ON模式的目的是保证
始终提供一路精确的高速时钟输出，供MCU使用。
温度检测模式下，可使用内部温度传感器。
Tx模式下，发送器配置为发送ASK数据或FSK数据。
引脚驱动为低电平，ENABLE引脚驱动为高电平或使能位
置位，则开启发送器模式，参见表2逻辑汇总。
模式选项由SPI模式控制位(Conf0寄存器，0x01，第4位)选
择，参见表3选项汇总。
休眠模式
从初始化模式，发送器直接进入休眠模式。XTAL ON模式
下，晶振保持有效，晶振时钟经过分频后通过GPO2输出。
禁用RF功能且clksht位置位时，进入该模式。该模式下，
电流消耗与输出信号的频率、GPO2引脚的负载电容有关。
输出信号为3.2MHz、负载电容为10pF时，电流损耗典型
值为750μA。详细信息请参考数字输出部分，表4汇总了
休眠模式功能。
Tx模式由SHDN引脚、ENABLE引脚和使能位(EnableReg
寄存器，0x3E，第0位)的逻辑状态共同确定。如果SHDN
表2. 模式控制逻辑
表4. 休眠模式汇总
SHDN PIN
ENABLE PIN
enable BIT
TRANSMITTER
MODE
0
0
0
Sleep
0
0
1
Tx
0
1
0
Tx
0
1
1
Tx
1
0
0
Shutdown
1
0
1
Shutdown
1
1
0
Shutdown
1
1
1
Shutdown
SLEEP
MODE
SETTINGS
TYPICAL
CURRENT
DRAIN
Sleep
Enable = 0
350nA
All register contents
are retained.
XTAL
ON
clksht = 1
750FA*
Divided XTAL
oscillator signal can
be directed to GPO2.
COMMENTS
*与GPO2负载电容和输出时钟频率有关。
表3. 模式选项逻辑
mode BIT
MODE OPTION
0
ASK
1
FSK
�� Maxim Integrated Products 22
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
温度检测模式
用户必须从休眠模式启动温度检测模式，而且，发送器完
成温度测量后自动返回休眠模式。
当tsensor位(EnableReg寄存器，0x3E，第3位)置位时，
使能片上温度传感器。一旦内部温度传感器电路达到
稳定，A/D转换器进行温度转换，ADC转换结果储存在
tsadc[6:0]，当数字测试复用位tmux[3:0] (TestMux寄存器，
0x3C，3:0位)置0时，可通过TestBus1寄存器(0x41，6:0位)
访问温度测试结果。tsensor位为自复位，完成温度测量后
自动返回至零状态。完成测量后，tsdone状态位(Status1
寄存器，0x43，第4位)也会复位。温度检测模式下，电流
损耗小于1mA，传感器稳定建立时间和ADC转换时间共计
小于2ms。温度检测模式相关特性汇总于表5。
Tx模式
2) ASK模式下，内部txready信号转变到高电平之后，功
率放大器在DATAIN引脚的上升沿或datain置位时开始
缓慢升高；FSK模式下，功率放大器则在txready信号
的上升沿开始缓慢上升的过程。
图12所示为预热过程。
ASK应用中，合成器输出固定在载频。输出功率在完全关
闭(DATAIN引脚为逻辑0或datain位清零时)和所设置的输出
功率电平(DATAIN引脚为逻辑1或datain置位时)之间交替切
换。可以对输出信号幅度整形，以降低占用的传输频宽。
关于幅度整形的详细信息，请参考功率放大器部分。PA
输出功率由线性控制PA输出偏置电流的6位幅值字决定，
LSB电流幅值由REXTPA引脚与地之间的片外电阻设置。
电阻为56.2kΩ时，LSB电流标称值为0.5mA，利用低温度
系数、±1%容限的电阻可以严格控制发送器功率。
Tx模式包含两个子单元：FSK和ASK。
发送器输出信号由N分频合成器产生，经过缓冲后，由功
率放大器(PA)放大到所设置的输出功率电平。发送器需要
有限的预热时间，从休眠模式进入Tx模式后，按照以下过
程工作：
1) 使能晶振，并建立到稳定状态。内部ckalive状态信号
的上升沿表示晶振已经稳定工作，提供精确的时基。
除PA外，使能其它所有Tx模块。在其它模块稳定到相
应的工作点的同时，合成器也稳定到相应的LO频率。
lockdet状态信号的上升沿表示合成器已锁定频率。有
些窄带应用中，lockdet信号可利用plldl[2:0]位(Conf1寄
存器，0x02，5:3位)设置有效延时，确保合成器稳定在
规定的精度内，延迟信号称为plllock。txready状态信
号的上升沿与plllock信号的上升沿一致。
tsensor
EXECUTION
TIME (ms)
<2
105µs
(typ)
ckalive
95µs
(typ)
lockdet
plldel
INTERVAL
plllock
txready
datain
‘OR’
DATAIN
表5. 温度检测模式汇总
BIT
enable
‘OR’
ENABLE
TYPICAL
CURRENT
DRAIN (mA)
COMMENTS
<1
The tsdone status
bit is set when the
measurement is
completed. The
results are stored in
tsadc[6:0].
PAQ*
USER-DEFINED PA RAMP
(*PA RAMP BEGINS ON THE RISING EDGE OF DATAIN IN ASK MODE
AND ON THE RISING EDGE OF txready IN FSK MODE.)
图12. Tx预热时序图
�� Maxim Integrated Products 23
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
FSK应用中，合成器输出在低电平信号(DATAIN引脚为逻
辑0、datain清零时)频率和高电平信号(DATAIN引脚为逻辑
1、datain置位时)频率之间交替切换。可以对输出信号进
行频率整形，以降低发送信号占用的频宽。关于频率整形
的更多信息，请参见N分频合成器部分。PA功率由6位幅
值字决定，发送器使能或禁用时，PA输出功率在完全关闭
和所设置的功率之间缓慢变化，还可以设置变化斜率。为
了以所要求的功率发送信息，用户需等待PA完成缓变过程，
然后发送数据序列。
Tx模式下，典型电流损耗为10.2mA (低功率缓冲模式)或
12.2mA (大功率缓冲模式)加上所设置的PA输出电流。缓
冲器功率模式由palopwr位(TxConf0寄存器，0x0C，第7位)
控制，置位时处于低功率模式。
INITIAL STATE
CONFIGURE
SET fska
TO ZERO
HOP
LOAD FIRST
CHANNEL
(FBase)
ENABLE
**CAN BE COMPLETED IN A SINGLE SPI BURST**
NO
跳频扩谱(FHSS)工作原理
IC支持FHSS工作模式，快速建立N分频合成器和幅度整形
PA协同工作，能够在低端MCU的控制下实现严谨、高效、
便捷的跳频工作。
图13所示为工作在FHSS模式下的推荐流程。
初始配置期间，首选使用hop位配置；发送器工作期间，
最好使用HOP引脚配置(优于hop位控制)，有助于避免发送
器工作期间激活SPI的可能，以严格控制发送器时序。
LOAD SECOND
CHANNEL
(FBase)
SET fska TO
DESIRED VALUE
IF FSK MODE
DISABLE
SLEEP STATE
ENABLE
HOP
TRANSMITTER
ACTIVITY
WARMUP
SYNTHESIZER
FORCED OUT
OF LOCK
FSK MODE
ckalive
TRANSITIONS
HIGH
YES
YES
PA
RAMPED
DOWN
NO
YES
END
TRANSMITTER
ACTIVITY
SYNTHESIZER
FREQUENCY
CHANGED
LOAD NEXT
CHANNEL
(FBase)
NO
YES
SYNTHESIZER
ACQUIRES LOCK
HOP PIN
HELD
LOGIC 1
NO
FSK
TRANSMITTER
MODE
YES
PA RAMPED
UP
NO
图13. 跳频扩谱(FHSS)流程图
�� Maxim Integrated Products 24
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
功能说明
式中：
晶振
IC的晶振电路设计用于配合并联谐振晶体，为数字控制模
块产生N分频合成器参考时钟频率和信号。通常只需在引
脚XTALB和XTALC之间连接晶体，以及两个可选择的负载
调整电容。
fP为牵引晶体频率总量，单位为ppm。
考虑到PCB的杂散电容，振荡器通常在晶体连接引脚之间
存在大约8pF的等效负载电容。必须在XTALC与地之间、
XTALB与地之间增加相同的电容，使晶振工作在规定的晶
体负载电容下。如果晶体的负载电容不符合规定的负载电
容，振荡器频率会偏离规定的工作频率，在N分频合成器
时钟上引入误差。晶振规定的负载电容高于实际作用的负
载电容时，振荡频率高于规定频率。
CLOAD为负载电容。
已知晶体的电气参数，可计算出相对于规定工作频率的频
率牵引。频率牵引由下式给出：
fP
CM
2

1

+
C
 CASE C LOAD
−

1
6
 × 10
C CASE + C SPEC 
OPTIONAL
BLOCKING
CAPACITORS
SHORT IF NOT
REQUIRED
XTALB
12
13
CBLOCK
CBLOCK
CLOAD
CLOAD
CCASE为外壳电容(包括封装电容和晶体外壳电容)。
CSPEC为规定的负载电容。
当晶体负载电容符合技术指标时(即CLOAD = CSPEC)，频率
牵引为零。
振荡器电路设计的晶振负载电容介于8pF和20pF之间。建
议工作在10pF负载电容，以优化启动时间。当施加的负载
电容大于20pF时，振荡器不能启动。
晶振工作频率范围为16.0MHz至22.4MHz。为了维持内
部3.2MHz时基mclk，xtal[1:0] (Conf0寄存器，0x01，1:0
位)必须按照表6所示设置。对于80kbps (曼彻斯特码)或
160kbps (NRZ码)以下的所有数据率，推荐使用3.2MHz内
部时基。对于更高的数据率(高达100kbps (曼彻斯特码)或
200kbps (NRZ码))，需采用4MHz内部时基，如表6所示。
晶体的初始误差、温度系数和老化必须满足要求，从而使
发送器和接收器的频率累积误差保持在规定的范围内。发
射信号必须由配套的接收器进行下变频，使整个必要的调
制边带位于预解调滤波器的通带内，确保正常工作。对于
信道化工作，发射信号(包括调制边带)必须包含在给定的
频率范围内，由此限制了晶体的初始误差、温度系数和老
化指标。
MAX7049
XTALC
CM为晶体动态电容。
LOADING CAPACITORS
(USED ALONG WITH THE IC INTERNAL CAPACITANCE AND PCB STRAY
CAPACITANCE TO APPLY SPECIFIED LOAD CAPACITANCE TO THE CRYSTAL.)
图14. 推荐的晶振与IC连接
表6. 晶振分频器设置
CRYSTAL FREQUENCY
(MHz)
CRYSTAL DIVIDER RATIO
xtal[1:0] Conf0 REGISTER,
ADDRESS 0x01, BITS 1:0
mclk (MHz)
16.0
5
00
3.2
19.2
6
01
3.2
22.4
7
10
3.2
20.0
5
00
4.0
注：本表中晶振频率和分频比的组合为推荐设置，并未包括全部设置。
�� Maxim Integrated Products 25
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
IC提供温度传感器和小步进N分频合成器，以改善晶振频
率的稳定度。系统MCU可利用传感器及晶振温度系数计算
必要的频率修正，并可按照fXTAL/216Hz步长调节N分频合
成器。
电荷泵工作在0.4V至电源电压以下0.4V的范围。icont位
(Conf1寄存器，0x02，第7位)复位时，电荷泵电流典型值
为204μA，icont置位时，几乎倍增到407μA。CPOUT引脚
为电荷泵输出。
IC允许采用外部参考时钟信号代替晶振。外部参考时钟应
通过交流耦合电容连接到引脚XTALC，幅度介于0.8VP-P
和1.2VP-P之间，引脚XTALB DC接地。
Tx ASK模式
N分频器可通过21位分频字设置，分频字由5为整数部分和
16位小数部分组成，如图15所示。
N分频合成器
除外部无源环路滤波器外，IC包含了完全集成的N分频合
成器，用于产生发射信号频率。器件包括：压控振荡器
(VCO)、电荷泵、鉴相鉴频器(PFD)、N分频器、LO分频器
及所有必要的支持电路。片上晶振为N分频合成器产生参
考时钟。
参数D为N分频比：
N分频合成器的工作频率为：863MHz至945MHz。LO分
频器具有三种模式：1分频、2分频和3分频。从而允许分
别工作在863MHz至945MHz、431.5MHz至472.5MHz和
287.7MHz至315MHz。863MHz至945MHz范围内，频率
分辨率为fXTAL/216，LO分频后，LO分频器输出的分辨率更
小。LO分频器的分频比由fsel[1:0]位(Conf0寄存器，0x01，
3:2位)设置，分频比如表7所示。
21位分频字由FBase0、FBase1和FBase2寄存器定义，在
Hop信号的上升沿锁存至N分频器，Hop信号是IC使能时
HOP输入引脚电平与hop位(FLoad寄存器，0x0B，第0位)
的逻辑或。
D = 32 + base[20:0]/216
因此，合成器输出频率由下式给出：
fSYNTH = D x fXTAL
式中，fXTAL为晶振产生的参考时钟频率。
VCO工作于整个规定的频率范围，无需校准。典型的
VCO增益为108MHz/V，1MHz频偏下的典型相位噪声
为-126dBc/Hz。工作在2分频LO分频器时，相位噪声
改善20 x log10(2)；工作在3分频LO分频器时，改善20 x
log10(3)。VCO控制电压作用在CTRL引脚，以VCOVDD引
脚为参考。ibsel位(Conf1寄存器，0x02，第6位)设置VCO
偏置电流，ibsel位置位时，VCO电流增大1mA。1MHz时，
VCO相位噪声可以达到-128dBc/Hz，电流损耗增大。
表7. LO分频器模式
fsel[1:0] Conf0 REGISTER, ADDRESS
0x01, BITS 3:2
LO DIVISION RATIO
TRANSMITTER OPERATING
FREQUENCIES (MHz)
00
3
287.7 to 315
01
2
431.5 to 472.5
10
Not used
N/A
11
1
863 to 945
�� Maxim Integrated Products 26
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
图15所示合成器工作在Tx ASK模式，Tx载频为静态。对
于Tx FSK应用，载波频率根据Datain输入在高电平信号频
率和低电平信号频率之间交替切换，IC具有频率整形功能，
允许用户限制发送信号的频宽。
频率整形Tx FSK模式
整形功能的输入如图16所示。该模式下，wsoff位(TxConf0
寄存器，0x0C，第6位)清零，wsmlt[1:0]位(TxConf1寄存器，
0x0D，7:6位)清零。base[20:0]位设置最低频率(对应于
低电平)的分频比，base1[20:0]设置最高频率(对应于高电
平)的分频比。在Datain信号的上升沿，N分频器输入按照
tstep[7:0]位(TxTstep寄存器，0x0E，7:0位)和shpnn[7:0]
位(Shape00-Shape18寄存器，0x0F-0x21，7:0位，其中
nn = 00至18)的定义，在base[20:0]和base1[20:0]之间以
20级步长转换，如图17所示。
icont = 0 → CP CURRENT = 204µA
icont = 1 → CP CURRENT = 407µA
MAX7049
fTX
icont
REGISTER
Conf1,
ADDRESS
0x02, BIT 7
fsel[1:0]
REGISTER
Conf0,
ADDRESS
0x01,
BITS 3:2
/1, /2, OR /3
fsel[1:0] = 00 → /3
fsel[1:0] = 01 → /2
fsel[1:0] = 11 → /1
fSYNTH
CHARGE
PUMP
8 CPOUT
PROGRAMMABLE
CONTROL BITS
hop
REGISTER
FLoad,
ADDRESS
0x0B,
BIT 0
FRACTIONAL-N DIVIDER D
/(32 + base[20:0]/216)
PFD
VCO
108MHz/V
6 CTRL
Hop
21-BIT LATCH
ibsel
REGISTER
Conf1,
ADDRESS
0x02,
BIT 6
base[20:16]
REGISTER
FBase0,
ADDRESS
0x08,
BITS 4:0
base[15:8]
REGISTER
FBase1,
ADDRESS
0x09,
BITS 7:0
HOP 23
base[7:0]
REGISTER
FBase2,
ADDRESS
0x0A,
BITS 7:0
XTAL OSCILLATOR
fXTAL
XTALC
12
XTALB
13
图15. N分频合成器配置Tx ASK模式
�� Maxim Integrated Products 27
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
PROGRAMMABLE
CONTROL BITS
FROM VCO
TO PFD
21
datain
16 DATAIN
FRACTIONAL-N
DIVIDER D
MAX7049
Datain
FREQUENCY
WAVESHAPING
FUNCTION
wsoff
shpnn[7:0] : nn = 00:18
wsmlt[1:0]
tstep[7:0]
base[20:0] → SPACE FREQUENCY
base1[20:0] → MARK FREQUENCY
base[20:0]
图16. Tx FSK模式设置
Datain
base1[20:0]
base[20:0]
shp05[7:0]
shp04[7:0]
tSTEP
tSTEP
图17. Tx FSK频率整形时序图
�� Maxim Integrated Products 28
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
21位分频字以tstep[7:0]规定的速率更新，步长更新时间有
下式给出：
tSTEP = tstep[7:0]/mclk
用shpnn[7:0]表示，base1[20:0]为：
base1[20:0]
= base[20:0] +
nn = 18
∑
shpnn[7:0]
nn = 00
如图17所示，频率缓降波形与频率缓升波形反相，而非镜
像。频率偏差，即高电平信号频率和低电平信号频率之差，
也可以用shpnn[7:0]表示：
frequency =
deviation
频率偏差 = fXTAL /2 16 ×
nn = 18
∑
shpnn[7:0]
nn = 00
整形功能可以逼近任何单调波形特性。作为整形功能
的一个例子，我们利用持续时间为1/2位间隔、频偏为
50kHz的线性缓变波形逼近2kbps NRZ。缓变持续时间为
250μs，采用3.2MHz mclk，由于每个步长时间为12.5μs，
而40 x 0.3125μs得到12.5μs，所以tstep[7:0] SPI位需要
设置为十进制40 (0x28)。如果采用16MHz晶振，则要求
shpnn[7:0]位的值为十进制值11 (0xB)。本例中，频偏为
19 (频率步长数) x 11 (每步频率变化) x 16,000,000/216
或51.03kHz。如果以牺牲线性度为代价，得到更接近于
50kHz的数值，Shape00-Shape18四个寄存器可以设置为
十进制10 (0xA)。这样得到的频偏为205 x 16,000,000/216
或50.05kHz。该模式下，采用16.0MHz晶振时，最大可设
置频偏为(并非配套接收器考虑到带宽限制而使用的典型
值)：19 x 255 x 16,000,000/216或1.18MHz。
Tx脉冲FSK模式
该模式下，wsoff位(TxConf0寄存器，0x0C，第6位)置
位，wsmlt[1:0]位(TxConf1寄存器，0x0D，7:6位)用于配
置从低电平频率直接转换到高电平频率，不采用整形功能。
base1[20:0]表示为：
base1[20:0]
=
base[20:0] + wsm × shp00[7:0]
式中，wsm为表8给出的倍频器
脉冲FSK模式相对于整形FSK而言工作范围略宽，占用的
频带也更宽。Tx ASK模式下同样可以使用整形功能，功率
放大器部分介绍这一功能。
环路带宽
N分频合成器的环路带宽取决于对发射载波信号的相位噪
声、频率建立时间、FSK调制率以及电流损耗的要求。
N分频合成器输出相位噪声的三个主要来源是：近载波相
位噪声、VCO相位噪声和分频量化相位噪声。可以设置环
路带宽和滤波器阶数，来满足不同应用对低载波相位噪声
(为了在较宽的环路带宽下获得优异性能)和低VCO相位噪
声(为了在窄带环路带宽下获得优异性能)的要求。必要时，
可增大环路滤波器阶数，以减小分频量化相位噪声的影响，
支持更宽的环路频带要求。
表8. Tx FSK脉冲模式下的倍频器
wsmlt[1:0] TxConf1 REGISTER, ADDRESS 0x0D, BITS 7:6
wsm
00
1
01
2
10
4
11
8
�� Maxim Integrated Products 29
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
通常情况下，100kHz环路带宽即可适用于大多数应用，
提供较快的建立时间。在902MHz至928MHz ISM频带，
26MHz步长，频偏小于5kHz时，建立时间典型值在48μs
以内。该环路带宽优化于最小载波相位噪声和VCO噪
声。此外，这种设置下，能够支持大多数FSK调制率高达
160kbps的NRZ和80kbps的曼彻斯特编码应用。如果在更
高的频偏下需要进一步降低相位噪声，可适当降低环路带
宽，此时VCO噪声将占相位噪声的主导地位。
环路滤波元件计算如下：
R = (2 x G x D x BW)/(ICP x KVCO)I
其中：
R为环路滤波器电阻，单位为Ω。
D为N分频合成器的反馈分频比。
BW为相应的N分频合成器环路带宽，单位为Hz。
ICP为电荷泵电流，单位为A。
KVCO为合成器输出频率(863MHz至945MHz)下的VCO
增益，单位为Hz/V。
CS = 1/(2 x G x R x BW x (√10) )，单位为F
其中：
CS为与R和CL串联组合相并联的小环路滤波电容。
R为环路滤波器电阻，单位为Ω。
BW为所要求的N分频合成器环路带宽，单位为Hz。
10为近似值。
可向环路滤波器增加一个RC极点，以消除宽环路带宽内
更多的分频量化相位噪声。该极点增加在CPOUT引脚和
CTRL引脚之间。RC极点的阻抗值应为环路滤波电阻的1.5
倍，从而在限制负载的同时限制热噪声对相位噪声的影响。
极点频率应大于环路带宽的10倍，图18所示为环路滤波器
配置。
锁定检测器
N分频合成器的主要支持电路为锁定检测器，内部锁定检
测信号为发送器工作的一个门控信号，如工作模式概述部
分所示。锁定检测信号本身满足大多数工作条件，但是如
果该信号触发太快则会增加额外的延迟，使得合成器不能
够稳定建立在对应的频率精度内，如图19所示。
CL = (√10)/(2 x G x R x BW)，单位为F
其中，
CL为与R串联的大环路滤波电容。
R为环路滤波器电阻，单位为Ω。
BW为所要求的N分频合成器环路带宽，单位为Hz。
10为近似值。
VDD
5
CP
6
CL
RP
R
CTRL
MAX7049
lockdet
VDD
7
CS
VCOVDD
CPVDD
plldel INTERVAL
CPOUT
8
plllock
SHORT RP AND CP IF EXTRA POLE IS NOT USED.
BYPASS VCOVDD AND CPVDD TO GROUND.
图18. 合成器环路滤波器拓扑
图19. 锁定检测器延迟功能
�� Maxim Integrated Products 30
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
附加延迟间隔由plldl[2:0]位(Conf1寄存器，0x02，5:3位)设
置，该延迟由下式给出：
REXTPA引脚和地之间有一个外部电阻(REXT)。该电阻与片
上1.13V基准电压共同设置参考电流(IR)。电阻应尽量靠近
IC放置，以降低该节点的电容。建议采用具有稳定温度特
性的±1%高精度电阻，使输出功率波动降至最小。片上电
流放大器25 x IR决定PA偏置DAC的LSB。例如，56.2kΩ
电阻将LSB设置为0.5mA。palopwr位(TxConf0寄存器，
0x0C，第7位)控制PA缓冲放大器的偏置电流。该位置1时，
将缓冲偏置电流降低2mA，用于低功率应用。缓冲放大器
设置基底电压(VP)，提供足够的PA偏置DAC裕量。
plldel 间隔 = plldl[2:0] x (64/mclk)s
式中，plldl[2:0]为十进制等效值，产生的标称(3.2MHz
mclk) plldel间隔为0至140μs。SDO、GPO1和GPO2可指
示lockdet和plllock的状态，参见寄存器详细说明部分的
TestBus0和TestBus1寄存器。
功率放大器
IC提供可编程电流损耗和高效率功率放大器(PA)。PA为差
分输出级，能够为50Ω负载提供大于+15dBm的功率驱动，
包括匹配网络和谐波滤波器损耗。PA偏置电流(IPA)能够以
64级步长线性配置，如图20所示。
匹配网络的功能是将负载电阻(RL)转换为最佳的PA差分负
载电阻(ROPT)。ROPT由相应的输出功率(PD)、匹配网络损
耗(Lm)、电源电压(VDD)和基底电压(VP)决定。表9所示为
确定ROPT和IPA_peak的设计示例，其中IPA_peak为直流
电流的峰值。
VDD
L
J
INSERTION LOSS
= Lm
SIGNAL SWINGS FOR
OPTIMAL LOAD
IMPEDANCE
MATCHING
NETWORK
FROM FREQUENCY
SYNTHESIZER
BUFFER
AMP
vi
RL
27
28
PA-
1.13V
REXT
2 REXTPA
IR
25x
I_lsb = 25 x IR
0
PA+
ROPT
MAX7049
PA+
VDD
VP
VP
palopwr
CURRENT MIRROR
vi
PA-
VP
PA BIAS DAC
IPA = (0:63) DIGITAL
CONTROL
x I_lsb
6
VDD
2 x (VDD - VP)
(PA+) - (PA-)
0
图20. 功率放大器拓扑和信号摆幅优化
�� Maxim Integrated Products 31
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
理想的差分输出级最大效率为2/π，必需通过(VDD - VP)/
VDD调节，以满足PA偏置DAC电流源所要求的裕量。注意，
非平衡差分阻抗，PA输出端等效阻抗，会造成PA+引脚和
PA-引脚钳位电平不一致，从而影响效率。此外，如果匹
配网络不能将负载电阻转换成严格等于ROPT + j0的差分阻
抗，失配损耗会进一步降低效率。在这里的PA设计示例中，
如果在ASK模式下PA偏置电流从零切换至IPA_peak，调制
信号占用较宽频带。IC的幅度整形功能可以减小ASK调制
占用的带宽。
表9. PA设计示例
PARAMETER
SYMBOL AND/OR EQUATION
EXAMPLE VALUE
VDD
3V
VP
0.5V
REXT
56.2kI
I_lsb = 25 x 1.13/REXT
0.5mA
Desired Peak RF Output Power
PD
14dBm
Harmonic Filter and Composite
Matching/Combiner Network Loss
Lm
2dB
Supply Voltage
Pedestal Voltage
External PA Bias Resistance
PA Bias DAC LSB
Actual PA RF Output Power
PPA = PL + Lm
Actual PA RF Output Power
PPA_mW =
10(P
16dBm
/10)
40mW
PA
Required PA DC Power
PDC = PPA_mW x G/2 x VDD/(VDD -VP)
75mW
Maximum PA Efficiency
Maximum efficiency = 100 x 2/G x (VDD - VP)/VDD
53%
Efficiency = 100 x 10(PD/10)/PDC
33%
Required Peak DC Current
IPA_peak = PDC/VDD
25mA
PA Code for Desired Power
idac_peak[5:0]
50 decimal (0x32)
Composite PA Efficiency (includes
Matching Network Loss)
FROM FREQUENCY
SYNTHESIZER
28
27
PA-
PA+
BUFFER
AMP
vi
idac[5:0]
datain
16 DATAIN
MAX7049
Datain
PROGRAMMABLE
CONTROL BITS
IPA = idac[5:0] x I_lsb
6
wsoff
AMPLITUDE
WAVESHAPING
FUNCTION
shpnn[7:0] : nn = 00:18
wsmlt[1:0]
tstep[7:0]
图21. Tx ASK模式设置
�� Maxim Integrated Products 32
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
幅度整形Tx ASK模式
ASK整形功能如图21所示。
该模式下，wsoff位(TxConf0寄存器，0x0C，第6位)清
零，wsmlt[1:0]位(TxConf1寄存器，0x0D，7:6位)清零。
txready为高电平后，PA在Datain信号的上升沿从零偏置电
流转换到IPA_peak。这种转换经过20个步长变化实现，由
tstep[7:0]位(TxTstep寄存器、0x0E，7:0位)和shpnn[7:0]
位(Shape00-Shape18寄存器，0x0F-0x21，7:0位，其中
nn = 00至18)确定，如图22所示。
PA DAC字按照tstep[7:0]位规定的速率更新，更新时间步
长由下式给出：
tSTEP = tstep[7:0]/mclk
用shpnn[7:0]位表示，idac_peak[5:0]值为：
.
idac_peak[5:0] =
nn = 18
∑
ASK模式下，shpnn[7:0]的两个最高有效位始终为零。如
图22所示，缓降波形与缓升波形的变化规律为反方向。整
形功能能够逼近任何单调波形。由于shpnn寄存器为8位字
宽，必要时，PA可一次从零增大到最大偏置电流。
我们可以考虑一个设计示例，利用持续时间为1/2位间
隔、PA偏置电流峰值为10mA (REXT = 56.2kΩ)的线性缓
变波形逼近4kbps NRZ。缓变时间为125μs，采用3.2MHz
mclk，由于20个步长均为6.25μs，20 x 0.3125μs得到
6.25μs，所以tstep[7:0]的十进制值设置为20 (0x14)。这要
求Shape00-Shape18中每个寄存器为十进制值1 (0x1)。此
时，PA峰值偏置电流为19 x 25 x 1.13/56,200或9.55mA。
如果以牺牲线性度为的情况下得到更接近于10mA的值，
Shape00-Shape18其中一个寄存器的值可设置为十进制
2 (0x2)。得到峰值PA偏置电流为20 x 25 x 1.13/56,200或
10.05mA。
shpnn[7:0]
nn = 00
Datain
idac_peak[5:0]
0
shp05[7:0]
shp04[7:0]
tSTEP
tSTEP
图22. ASK整形时序图
�� Maxim Integrated Products 33
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
Tx FSK模式下的幅度缓变控制
Tx FSK模式下，载频信号由整形函数调制，参见N分频合
成器部分。频率整形的作用是将Tx FSK模式下发射信号占
用的带宽降至最小。然而，如果PA在突发数据开始、结束
时被瞬间打开或关闭，所占用的带宽将展宽。Tx FSK模式
下可以采用PA幅度缓变控制功能，避免占用更宽频带，功
能介绍如图23所示。
类似地，PA偏置电流在使能信号的下降沿线性缓降。注意，
从某个信道跳至另一信道时，也自动激活PA缓变过程，参
见N分频合成器部分。
IC使能、txready信号变为高电平后，PA偏置电流线性缓
升至fska[5:0] (TxConf0寄存器，0x0C，5:0位) x I_lsb，增
量为fskas[5:0] (TxConf1寄存器，0x0D，5:0位) x I_lsb，
如图24所示。
为了按照所要求的功率发送整个消息，用户应等待PA完成
缓变过程，然后再启动数据序列。
PA DAC字以tstep[7:0]位规定的速率更新，步长更新时间
由下式给出：
tSTEP = tstep[7:0]/mclk
FROM FREQUENCY
SYNTHESIZER
28
27
PA-
PA+
BUFFER
AMP
vi
idac[5:0]
enable
17 ENABLE
MAX7049
Enable
PROGRAMMABLE
CONTROL BITS
IPA = idac[5:0] x I_lsb
6
fska[5:0]
AMPLITUDE
RAMP
FUNCTION
fskas[5:0]
tstep[7:0]
图23. Tx FSK幅度缓变控制
�� Maxim Integrated Products 34
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
enable AND
txready
fska[5:0]
0
fskas[5:0]
fskas[5:0]
tSTEP
tSTEP
图24. Tx FSK幅度缓变控制时序图
寄存器详细说明
表10. 配置寄存器映射
GROUP/FUNCTION
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Ident
0x00
1
0
1
0
0
1
1
1
Conf0
0x01
—
—
—
mode
fsel_1
fsel_0
xtal_1
xtal_0
Conf1
0x02
icont
ibsel
plldl_2
plldl_1
plldl_0
—
—
—
IOConf0
0x03
gp1isht
gp2isht
ckdiv_1
ckdiv_0
gp2s_3
gp2s_2
gp2s_1
gp2s_0
IOConf1
0x04
sdos_3
sdos_2
sdos_1
sdos_0
gp1s_3
gp1s_2
gp1s_1
gp1s_0
IOConf2
0x05
—
—
gp1md_1
gp1md_0
clksht
gp2md_2
gp2md_1
gp2md_0
FBase0
0x08
—
—
—
base_20
base_19
base_18
base_17
base_16
FBase1
0x09
base_15
base_14
base_13
base_12
base_11
base_10
base_9
base_8
FBase2
0x0A
base_7
base_6
base_5
base_4
base_3
base_2
base_1
base_0
1
2
3
4
FLoad
0x0B
—
—
—
—
—
—
—
hop
TxConf0
0x0C
palopwr
wsoff
fska_5
fska_4
fska_3
fska_2
fska_1
fska_0
TxConf1
0x0D
wsmlt_1
wsmlt_0
fskas_5
fskas_4
fskas_3
fskas_2
fskas_1
fskas_0
TxTstep
0x0E
tstep_7
tstep_6
tstep_5
tstep_4
tstep_3
tstep_2
tstep_1
tstep_0
�� Maxim Integrated Products 35
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表10. 配置寄存器映射(续)
GROUP/FUNCTION
5
6
7
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Shape00
0x0F
shp00_7
shp00_6
shp00_5
shp00_4
shp00_3
shp00_2
shp00_1
shp00_0
Shape01
0x10
shp01_7
shp01_6
shp01_5
shp01_4
shp01_3
shp01_2
shp01_1
shp01_0
Shape02
0x11
shp02_7
shp02_6
shp02_5
shp02_4
shp02_3
shp02_2
shp02_1
shp02_0
Shape03
0x12
shp03_7
shp03_6
shp03_5
shp03_4
shp03_3
shp03_2
shp03_1
shp03_0
Shape04
0x13
shp04_7
shp04_6
shp04_5
shp04_4
shp04_3
shp04_2
shp04_1
shp04_0
Shape05
0x14
shp05_7
shp05_6
shp05_5
shp05_4
shp05_3
shp05_2
shp05_1
shp05_0
Shape06
0x15
shp06_7
shp06_6
shp06_5
shp06_4
shp06_3
shp06_2
shp06_1
shp06_0
Shape07
0x16
shp07_7
shp07_6
shp07_5
shp07_4
shp07_3
shp07_2
shp07_1
shp07_0
Shape08
0x17
shp08_7
shp08_6
shp08_5
shp08_4
shp08_3
shp08_2
shp08_1
shp08_0
Shape09
0x18
shp09_7
shp09_6
shp09_5
shp09_4
shp09_3
shp09_2
shp09_1
shp09_0
Shape10
0x19
shp10_7
shp10_6
shp10_5
shp10_4
shp10_3
shp10_2
shp10_1
shp10_0
Shape11
0x1A
shp11_7
shp11_6
shp11_5
shp11_4
shp11_3
shp11_2
shp11_1
shp11_0
Shape12
0x1B
shp12_7
shp12_6
shp12_5
shp12_4
shp12_3
shp12_2
shp12_1
shp12_0
Shape13
0x1C
shp13_7
shp13_6
shp13_5
shp13_4
shp13_3
shp13_2
shp13_1
shp13_0
Shape14
0x1D
shp14_7
shp14_6
shp14_5
shp14_4
shp14_3
shp14_2
shp14_1
shp14_0
Shape15
0x1E
shp15_7
shp15_6
shp15_5
shp15_4
shp15_3
shp15_2
shp15_1
shp15_0
Shape16
0x1F
shp16_7
shp16_6
shp16_5
shp16_4
shp16_3
shp16_2
shp16_1
shp16_0
Shape17
0x20
shp17_7
shp17_6
shp17_5
shp17_4
shp17_3
shp17_2
shp17_1
shp17_0
Shape18
0x21
shp18_7
shp18_6
shp18_5
shp18_4
shp18_3
shp18_2
shp18_1
shp18_0
TestMux
0x3C
—
—
—
—
tmux_3
tmux_2
tmux_1
tmux_0
Datain
0x3D
—
datain
—
—
—
—
—
—
EnableReg
0x3E
—
—
—
—
tsensor
—
—
enable
TestBus0
0x40
tbus_15
tbus_14
tbus_13
tbus_12
tbus_11
tbus_10
tbus_9
tbus_8
TestBus1
0x41
tbus_7
tbus_6
tbus_5
tbus_4
tbus_3
tbus_2
tbus_1
tbus_0
Status0
0x42
txready
—
adcrdy
—
gpo1out
plllock
lockdet
ckalive
Status1
0x43
—
—
—
tsdone
—
—
—
—
“—”表示保留位。如果寄存器含有保留位，写0至保留位。
寄存器0x00始终为0xA7，可用于识别SPI总线上的IC。
寄存器0x40至0x43为只读寄存器，包含各种状态，可通过SPI读取状态。
�� Maxim Integrated Products 36
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
寄存器详细说明
表11. 第0组：标识寄存器(Ident)
GROUP/FUNCTION
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0x00
1
0
1
0
0
1
1
1
Ident
表12. Ident寄存器(0x00)
BIT
NAME
7:0
ident[7:0]
FUNCTION
Read-only register used for identification purposes. The content of this register is always 0xA7.
表13. 第1组：通用配置寄存器(Conf0、Conf1)
GROUP/FUNCTION
1
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Conf0
0x01
—
—
—
mode
fsel_1
fsel_0
xtal_1
xtal_0
Conf1
0x02
icont
ibsel
plldl_2
plldl_1
plldl_0
—
—
—
表14. Conf0寄存器(0x01)
BIT
NAME
4
mode
FUNCTION
1-bit configuration for transmit mode:
0 = ASK
1 = FSK
2-bit configuration for LO division ratio:
3:2
fsel[1:0]
003
012
10
Not used
111
2-bit crystal divider configuration. Based on a typical crystal selection of 16.0MHz, 19.2MHz, or
22.4MHz, these bits are usually configured to yield a constant 3.2MHz mclk frequency for timing
control and driving characteristics of the digital section of the IC. For data rates up to 200kbps,
an mclk frequency of up to 4.0MHz is needed. The typical settings are:
1:0
xtal[1:0]
Crystal 16.0MHz
19.2MHz
22.4MHz
20.0MHz
xtal[1:0]
00 01 10 00 11 Divide
Divide
Divide
Divide
Divide
by
by
by
by
by
5
6
7
5
8
(16.0/5
(19.2/6
(22.4/7
(20.0/5
=
=
=
=
3.2MHz)
3.2MHz)
3.2MHz)
4.0MHz)
�� Maxim Integrated Products 37
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表15. Conf1寄存器(0x02)
BIT
NAME
FUNCTION
7
icont
Selects between low current (0 = 204FA) and high current (1 = 407FA) modes for the synthesizer
charge pump, allowing for lower noise operation with the expense of extra current.
6
ibsel
Selects between low VCO core current and high VCO core current (1 = additional 1mA) in the
synthesizer.
3-bit configuration for extra delay after lock-detect flag (lockdet) from the synthesizer is asserted
(assuming mclk = 3.2MHz):
5-3
plldl[2:0]
plldl[2:0] delay(Fs)
000 0
001 20
010 40
011 60
100 80
101 100
110 120
111 140
After this delay, an internal signal called plllock is asserted high to determine the digital lock flag
for the synthesizer.
表16. 第2组：GPO、数据输出和时钟输出寄存器(IOConf0、IOConf1、IOConf2)
GROUP/FUNCTION
2
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IOConf0
0x03
gp1isht
gp2isht
ckdiv_1
ckdiv_0
gp2s_3
gp2s_2
gps2_1
gps2_0
IOConf1
0x04
sdos_3
sdos_2
sdos_1
sdos_0
gp1s_3
gp1s_2
gp1s_1
gp1s_0
IOConf2
0x05
—
—
gp1md_1
gp1md_0
clksht
gp2md_2
gp2md_1
gp2md_0
�� Maxim Integrated Products 38
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表17. IOConf0寄存器(0x03)
BIT
NAME
FUNCTION
7
gp1isht
GPO1 current mode during sleep. If the IC GPO1 is configured to current drive mode (IOConf2
register, 0x05), writing 1 to this bit allows for the current mode operation even if the IC is in Sleep
mode or disabled. If this bit is 0, current mode operation is only active when the IC is enabled.
6
gp2isht
GPO2 current mode during sleep. If the IC GPO2 is configured to current drive mode (IOConf2
register, 0x05), writing 1 to this bit allows for the current mode operation even if the IC is in Sleep
mode or disabled. If this bit is 0, current mode operation is only active when the IC is enabled.
2-bit configuration for clock output divider setting. A clock source selected by gp2s[3:0] is divided by
the settings in these bits, according to the following:
5:4
ckdiv[1:0]
ckdiv[1:0] 00 01 10 11 Divide by
1
2
4
8
4-bit configuration for GPO2 signal selection:
3:0
gp2s[3:0]
gp2s[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011 1100 1101 1110 1111 Output
plllock
mclk/(ckdiv divider)
xtal/(ckdiv divider)
xtal/16/(ckdiv divider)
tbus[4]
tbus[5]
tbus[6]
tbus[7]
tbus[8]
tbus[9]
tbus[10]
tbus[11]
tbus[12]
tbus[14]
tbus[15]
where:
mclk is the master digital clock generated from the crystal divider block (xtal[1:0]);
xtal is the crystal oscillator output clock;
xtal/16 is a divided-by-16 version of the crystal oscillator frequency;
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 39
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表18. IOConf1寄存器(0x04)
BIT
NAME
FUNCTION
4-bit SPI data output GPO mode selection. When CS is low, the SDO pin outputs the SPI data output,
as described in the Serial Peripheral Interface (SPI) section. When CS is high, the SDO acts as a third
GPO, according to:
7:4
sdos[3:0]
CS sdos[3] sdos[2] sdos[1] sdos[0] output
0
x
x
x
x
SPI_Dout
1
0
0
0
0
tbus[ 0]
1
0
0
0
1
tbus[ 1]
1
0
0
1
0
tbus[ 2]
1
0
0
1
1
tbus[ 3]
1
0
1
0
0
tbus[ 4]
1
0
1
0
1
tbus[ 5]
1
0
1
1
0
tbus[ 6]
1
0
1
1
1
tbus[ 7]
1
1
0
0
0
tbus[ 8]
1
1
0
0
1
tbus[ 9]
11 0 1 0tbus[10]
11 0 1 1tbus[11]
11 1 0 0tbus[12]
11 1 0 1tbus[13]
11 1 1 0tbus[14]
11 1 1 1tbus[15]
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
4-bit configuration for GPO1 signal selection:
3:0
gp1s[3:0]
gp1s[3] gp1s[2] gp1s[1] gp1s[0] output
0
0
0
0
tbus[ 0]
0
0
0
1
tbus[ 1]
0
0
1
0
tbus[ 2]
0
0
1
1
tbus[ 3]
0
1
0
0
tbus[ 4]
0
1
0
1
tbus[ 5]
0
1
1
0
tbus[ 6]
0
1
1
1
tbus[ 7]
1
0
0
0
tbus[ 8]
1
0
0
1
tbus[ 9]
1 0
1 0tbus[10]
1 0
1 1tbus[11]
1 1
0 0tbus[12]
1 1
0 1tbus[13]
1 1
1 0tbus[14]
1 1
1 1tbus[15]
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 40
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表19. IOConf2寄存器(0x05)
BIT
NAME
FUNCTION
2-bit
5:4
gp1md[1:0]
3
clksht
GPO1 mode selection:
0x
buffer mode
1080FA current mode
11160FA current mode
Enable (1) or disable (0) clock output on GPO2 during sleep.
3-bit GPO2 mode selection. The GPO2 can provide a high-frequency clock output, and therefore its
current capability is higher.
2:0
gp2md[2:0]
0xx
100
101 110
111
buffer mode
1.0mA
2.0mA
3.0mA
4.0mA
表20. 第3组：合成器频率设置(FBase0、FBase1、FBase2、FLoad)
GROUP/FUNCTION
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x08
—
—
—
base_20
base_19
base_18
base_17
base_16
FBase1
0x09
base_15
base_14
base_13
base_12
base_11
base_10
base_9
base_8
FBase2
0x0A
base_7
base_6
base_5
base_4
base_3
base_2
base_1
base_0
FLoad
0x0B
—
—
—
—
—
—
—
hop
FBase0
3
寄存器0x08、0x09和0x0A设置21位base值，用于控制合成器频率。20:16位为5位整数部分(base[20:16])，15:0位为16位
小数部分(base[15:0])。
所以，合成器频率可由下式给出：
fSYNTH = fXTAL x (32 + base[20:0]/65,536)
式中，fXTAL为晶振频率，单位为MHz。然后按照fsel[1:0]设置(Conf0寄存器，0x01，3:2位)对合成器频率分频，产生LO频率。
表21. 合成器分频器设置
fsel[1:0]
LO DIVIDER
00
3
01
2
11
1
�� Maxim Integrated Products 41
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
合成器频率范围从863MHz至945MHz，转换至base[20:0]，如表22所示。
表22. 合成器设置
CRYSTAL (MHz)
SYNTHF (MHz)
MULTIPLIER FACTOR (dec)
863
21.9375
0x15F000
945
27.0625
0x1B1000
863
12.9479
0x0CF2AB
945
17.2188
0x113800
863
6.5268
0x0686DB
945
10.1875
0x0A3000
863
11.1500
0x0B2666
945
15.2500
0x0F4000
16.0
19.2
22.4
20
base[20:0]
每个频带的最低和最高工作频率列于表23。
表23. 频率范围
SYNTHF (MHz)
300MHz (fsel = 00)
450MHz (fsel = 01)
900MHz (fsel = 11)
863
287.70
431.50
863.00
945
315.00
472.50
945.00
hop位允许三个FBase寄存器设置的并联负载，操作完成后自复位返回0。该功能也可使用外部HOP引脚实现，关于跳频操
作的详细说明，请参考发送器详细工作原理部分。
表24. FBase0寄存器(0x08)
BIT
NAME
4:0
base[20:16]
FUNCTION
5-bit integer value for synthesizer.
表25. FBase1寄存器(0x09)
BIT
NAME
7:0
base[15:8]
FUNCTION
8 MSBs of fractional value for synthesizer.
表26. FBase2寄存器(0x0A)
BIT
NAME
7:0
base[7:0]
FUNCTION
8 LSBs of fractional value for synthesizer.
表27. FLoad (0x0B)
BIT
NAME
0
hop
FUNCTION
Hop bit. Loads the synthesizer fractional-N divider base value to base[20:0] written in registers
8 through 10. This is a self-reset bit, and is reset to zero after the operation is completed.
�� Maxim Integrated Products 42
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表28. 第4组：发送器幅度和定时参数(TxConf0、TxConf1、TxTstep)
GROUP/FUNCTION
4
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxConf0
0x0C
palopwr
wsoff
fska_5
fska_4
fska_3
fska_2
fska_1
fska_0
TxConf1
0x0D
wsmlt_1
wsmlt_0
fskas_5
fskas_4
fskas_3
fskas_2
fskas_1
fskas_0
TxTstep
0x0E
tstep_7
tstep_6
tstep_5
tstep_4
tstep_3
tstep_2
tstep_1
tstep_0
这些寄存器设置通用FSK/ASK参数，用于PA幅度和速率控制(FSK)、整形控制，以及调幅或频移键控整形的步进控制。
表29. TxConf0寄存器(0x0C)
BIT
NAME
7
palopwr
6
wsoff
5:0
fska[5:0]
FUNCTION
Reduces the PA input buffer current by 2mA when set to 1. Useful at low output power levels.
Disables (1) or enables (0) waveshaping. If waveshaping is disabled, only shp00[7:0] (Shape00
register, 0x0F) and wsmlt[1:0] (TxConf1 register, 0x0D) are used to set the amplitude (ASK) or
frequency (FSK) deviation.
6-bit final value for FSK PA amplitude (bias current) control.
表30. TxConf1寄存器(0x0D)
BIT
NAME
FUNCTION
2-bit scaler for shp00[7:0] (Shape00 register, 0x0F), effectively multiplying the value of Shape00 by:
7:6
wsmlt[1:0]
5:0
fskas[5:0]
wsmlt[1:0] multiplier
00
1
01
2
10
4
11
8
6-bit FSK amplitude (bias current) step for ramp-up and ramp-down operations. The PA amplitude
increases/decreases by this amount for every 1/20th of the data rate time elapsed (TxTstep register,
0x0E), until it reaches the final fska[5:0] value when ramping up, or reaches 0 when ramping down.
表31. TxTstep寄存器(0x0E)
BIT
NAME
FUNCTION
8-bit update value for waveshaping. This setting corresponds to 1/20th of the data rate, given in
periods of the master digital clock (312.5ns for 3.2 MHz).
tstep[7:0] = INT (mclk/(20 x DataRate))
7:0
tstep[7:0]
For 80kbps < DataRate P 160kbps, tstep[7:0] = 1, mclk = 3.2MHz
For 40kbps < DataRate P 80kbps, tstep[7:0] = 2, mclk = 3.2MHz
For 160kbps < DataRate P 200kbps, tstep[7:0] = 1, mclk = 4.0MHz
For 4kbps, tstep = INT (3.2 x106/(20 x 4000)) = 40 (0x28), mclk = 3.2MHz
The maximum value for tstep[7:0] is 255, which allows for a minimum shaped data rate of 627bps.
These values assume shaping during the entire bit interval. The tstep value can be set lower if
possible for shaping during a portion of the bit interval.
该设置允许每个发送数据符号按照20级顺序步进，完成调幅(ASK)或频移键控(FSK)整形。
�� Maxim Integrated Products 43
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表32. 第5组：发送器整形寄存器(Shape00-Shape18)
GROUP/FUNCTION
5
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Shape00
0x0F
shp00_7
shp00_6
shp00_5
shp00_4
shp00_3
shp00_2
shp00_1
shp00_0
Shape01
0x10
shp01_7
shp01_6
shp01_5
shp01_4
shp01_3
shp01_2
shp01_1
shp01_0
Shape02
0x11
shp02_7
shp02_6
shp02_5
shp02_4
shp02_3
shp02_2
shp02_1
shp02_0
Shape03
0x12
shp03_7
shp03_6
shp03_5
shp03_4
shp03_3
shp03_2
shp03_1
shp03_0
Shape04
0x13
shp04_7
shp04_6
shp04_5
shp04_4
shp04_3
shp04_2
shp04_1
shp04_0
Shape05
0x14
shp05_7
shp05_6
shp05_5
shp05_4
shp05_3
shp05_2
shp05_1
shp05_0
Shape06
0x15
shp06_7
shp06_6
shp06_5
shp06_4
shp06_3
shp06_2
shp06_1
shp06_0
Shape07
0x16
shp07_7
shp07_6
shp07_5
shp07_4
shp07_3
shp07_2
shp07_1
shp07_0
Shape08
0x17
shp08_7
shp08_6
shp08_5
shp08_4
shp08_3
shp08_2
shp08_1
shp08_0
Shape09
0x18
shp09_7
shp09_6
shp09_5
shp09_4
shp09_3
shp09_2
shp09_1
shp09_0
Shape10
0x19
shp10_7
shp10_6
shp10_5
shp10_4
shp10_3
shp10_2
shp10_1
shp10_0
Shape11
0x1A
shp11_7
shp11_6
shp11_5
shp11_4
shp11_3
shp11_2
shp11_1
shp11_0
Shape12
0x1B
shp12_7
shp12_6
shp12_5
shp12_4
shp12_3
shp12_2
shp12_1
shp12_0
Shape13
0x1C
shp13_7
shp13_6
shp13_5
shp13_4
shp13_3
shp13_2
shp13_1
shp13_0
Shape14
0x1D
shp14_7
shp14_6
shp14_5
shp14_4
shp14_3
shp14_2
shp14_1
shp14_0
Shape15
0x1E
shp15_7
shp15_6
shp15_5
shp15_4
shp15_3
shp15_2
shp15_1
shp15_0
Shape16
0x1F
shp16_7
shp16_6
shp16_5
shp16_4
shp16_3
shp16_2
shp16_1
shp16_0
Shape17
0x20
shp17_7
shp17_6
shp17_5
shp17_4
shp17_3
shp17_2
shp17_1
shp17_0
Shape18
0x21
shp18_7
shp18_6
shp18_5
shp18_4
shp18_3
shp18_2
shp18_1
shp18_0
这些寄存器设置发送数据的幅度调制(ASK)或频移键控(FSK)调制。tstep[7:0]定义1/20码率，在之前的累积结果上增加波形
整形值。所有整形值为差值，最终ASK幅度或FSK频偏由所有整形寄存器累加和决定。
ASK模式下，初始值为0；FSK模式时，初始值由base[20:0]给出。通过20级间隔(所以有19个波形成形寄存器)建立发送数
据从0至1所需的频率转换，或从1至0所需的频率转换。
表33. Shape00寄存器(0x0F)
BIT
7:0
NAME
shp00[7:0]
FUNCTION
First 8-bit value for waveshaping. This value is effectively multiplied by the wsmlt[1:0] setting
(TxConf1 register, 0x0D). If the wsoff bit is high, this is the only value that is added or subtracted to
perform either amplitude (ASK) or frequency (FSK) modulation.
�� Maxim Integrated Products 44
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表34. Shape01-Shape18寄存器(0x10-0x21)
BIT
NAME
7:0
shp01[7:0]
shp02[7:0]
shp03[7:0]
shp04[7:0]
shp05[7:0]
shp06[7:0]
shp07[7:0]
shp08[7:0]
shp09[7:0]
shp10[7:0]
shp11[7:0]
shp12[7:0]
shp13[7:0]
shp14[7:0]
shp15[7:0]
shp16[7:0]
shp17[7:0]
shp18[7:0]
FUNCTION
18 8-bit values for waveshaping. These values, along with shp00[7:0], yield the 19 different values
(20 intervals) used for waveshaping, one for each of the 20 updates occurring during each 0-1 or
1-0 transmitted data transition.
表35. 第6组：控制寄存器(TestMux、Datain、EnableReg)
GROUP/FUNCTION
6
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TestMux
0x3C
—
—
—
—
tmux_3
tmux_2
tmux_1
tmux_0
Datain
0x3D
—
datain
—
—
—
—
—
—
EnableReg
0x3E
—
—
—
—
tsensor
—
—
enable
该寄存器组组合了状态总线控制(tbus[15:0])、GPO控制、温度传感器控制、引脚功能(txdata)寄存器控制，以及使能控制。
表36. TestMux寄存器(0x3C)
BIT
NAME
3:0
tmux[3:0]
FUNCTION
4-bit selection of tbus[15:0] (TestBus0 and TestBus1 registers, 0x40 and 0x41) contents. See the
TestBus0 and TestBus1 register descriptions for a complete description of what can be observed
through this 16-bit bus.
�� Maxim Integrated Products 45
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表37. Datain寄存器(0x3D)
BIT
NAME
6
datain
FUNCTION
Transmit datain bit. This is a register equivalent of the DATAIN pin. When either the DATAIN pin or datain bit
is 1, the transmit data is 1. Only when both are 0 the transmit data is 0 (logical OR function). Keep 0 if only the
external DATAIN pin is used, and keep DATAIN pin 0 if the internal datain bit is used.
表38. EnableReg寄存器(0x3E)
BIT
3
0
NAME
FUNCTION
tsensor
Writing a 1 to this bit starts the temperature sensor A/D conversion. This is a self-reset bit, where the
bit is automatically reset when the conversion is finished. The result can then be read through the
TestBus1 register (0x41). This function is available only in Sleep mode.
enable
Enables (1) or disables (0) the IC’s transmitter operations. To enable the IC, SHDN must be driven low. This is a
register equivalent of the ENABLE pin. When either the ENABLE pin or enable bit is 1, the IC transmit operation
is enabled. Only when both are 0 the transmitter is disabled (logical-OR function). Keep 0 if only the external
ENABLE pin is used, and keep ENABLE pin 0 if the internal enable is used.
表39. 第7组：只读状态寄存器(TestBus0、TestBus1、Status0、Status1)
GROUP/FUNCTION
7
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TestBus0
0x40
tbus_15
tbus_14
tbus_13
tbus_12
tbus_11
tbus_10
tbus_9
tbus_8
TestBus1
0x41
tbus_7
tbus_6
tbus_5
tbus_4
tbus_3
tbus_2
tbus_1
tbus_0
Status0
0x42
txready
—
adcrdy
—
gpo1out
plllock
lockdet
ckalive
Status1
0x43
—
—
—
tsdone
—
—
—
—
寄存器0x3F-0x43为只读寄存器，用于存储A/D转换结果、状态和测试。
表40. TestBus0寄存器(0x40)
BIT
NAME
FUNCTION
7:0
tbus[15:8]
8 MSBs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (TextMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 46
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表41. 测试总线信号(tbus[15:8])
tmux[3:0]
tbus[15]
tbus[14]
tbus[13]
tbus[12]
tbus[11]
tbus[10]
tbus[9]
tbus[8]
0x0
—
—
—
—
—
—
—
—
0x1
—
—
—
—
—
—
—
—
0x2
—
—
—
—
—
—
—
—
0x3
—
—
—
—
—
—
—
—
0x4
—
—
—
—
—
—
—
—
0x5
—
—
pabia[5]
pabia[4]
pabia[3]
pabia[2]
pabia[1]
pabia[0]
0x6
frac[15]
frac[14]
frac[13]
frac[12]
frac[11]
frac[10]
frac[9]
frac[8]
0x7
—
—
—
—
—
—
—
—
0x8
—
—
—
—
—
—
—
—
0x9
—
—
—
—
—
—
—
—
0xA
—
—
—
—
—
—
—
—
0xB
—
—
—
—
—
—
—
mclk
0xC
—
—
—
—
—
—
—
plllock
0xD
—
—
—
—
—
—
—
—
0xE
—
—
—
—
—
—
—
—
0xF
—
—
—
—
—
—
—
—
其中：
tmux[3:0]
信号
说明
0x0–0x4
—
保留信号，用于测试
0x5
pabia[5:0] PA幅值控制总线
0x6
frac[15:8]
发送至频率合成器的小数MSB
0x7–0xA — 保留信号，用于测试
0xB
mclk
主控制器数字时钟
0xC
plllock
合成器锁定信号
0xD–0xF — 保留信号，用于测试
表42. TestBus1寄存器(0x41)
BIT
NAME
FUNCTION
7:0
tbus[7:0]
8 LSBs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 47
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表43. 测试总线信号(tbus[7:0])
tmux[3:0]
tbus[7]
tbus[6]
tbus[5]
tbus[4]
tbus[3]
tbus[2]
tbus[1]
tbus[0]
0x0
tsdonef
tsadc[6]
tsadc[5]
tsadc[4]
tsadc[3]
tsadc[2]
tsadc[1]
tsadc[0]
0x1
—
—
—
—
—
—
—
—
0x2
—
—
—
—
—
—
—
—
0x3
—
—
—
—
—
—
—
—
0x4
—
—
—
—
—
—
—
—
0x5
palopwr
—
—
integ[4]
integ[3]
integ[2]
integ[1]
integ[0]
0x6
frac[7]
frac[6]
frac[5]
frac[4]
frac[3]
frac[2]
frac[1]
frac[0]
—
0x7
—
—
—
—
—
—
—
0x8
—
—
—
—
—
—
—
—
0x9
—
—
—
ents
—
—
—
tsdonef
0xA
—
—
—
—
—
—
—
—
0xB
—
—
—
—
—
—
—
—
0xC
—
lockdet
ckalive
—
—
—
txready
—
0xD
—
—
—
—
—
—
—
—
0xE
—
—
—
—
—
—
—
—
0xF
—
—
—
—
mclk
—
—
—
其中：
tmux[3:0]
信号
说明
0x0
tsdonef
温度传感器转换完成标志。
tsadc[6:0]
温度传感器A/D结果
0x1–0x4
—
保留信号，用于测试
0x5
palopwr
PA低功率模式标记
integ[4:0]发送至频率合成器的整数值
0x6
frac[7:0]
发送至频率合成器的小数LSB
0x7, 0x8
—
保留信号，用于测试
0x9
ents
使能温度传感器转换信号。
tsdonef温度传感器完成标志
0xA, 0xB
—
保留信号，用于测试
0xC
lockdet
合成器锁定检测信号
ckalive晶振时钟有效标志
txreadyTx就绪标志
0xD, 0xE
—
保留信号，用于测试
0xF
mclk
主控制器数字时钟
注意，数字测试总线的每个信号均可在GPO1、GPO2或SDO观察到，如数字输出部分所述。
�� Maxim Integrated Products 48
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
表44. Status0寄存器(0x42)
BIT
NAME
FUNCTION
7
txready
Transmit ready flag. After this bit goes to 1, the IC is ready to accept transitions on the DATAIN pin
or on the datain bit inputs. Both these bits should be 0 before the txready flag is 1.
5
adcrdy
Internal test flag that signals the end of the A/D warmup time.
3
gpo1out
Register copy of the GPO1 pin logical state.
2
plllock
Synthesizer lock flag, after programmable plldl[2:0] expires.
1
lockdet
Synthesizer lock detect flag.
0
ckalive
Crystal oscillator clock alive flag, indicating clock activity from the crystal oscillator.
表45. Status1寄存器(0x43)
BIT
4
NAME
tsdone
FUNCTION
Temperature sensor conversion done flag. When 1, the A/D conversion of the internal temperature
sensor is completed.
布局考虑
对于任何RF/微波电路，合理设计PCB都至关重要。对高频、
高阻抗输入和输出，采用最小宽度并尽可能短的走线，将
杂散电容降至最小。使用短的走线还有助于降低寄生电感。
一般来说，1in的PCB走线大约增加20nH的寄生电感。寄
生电感对无源器件的等效电感影响非常大。例如，连接至
100nH电感的0.5in走线会增加额外10nH的电感，或者说
10%。
为了降低寄生电感，在信号走线下方采用稳固的接地区域。
匹配元件和旁路元件应通过尽可能地的寄生电感连接到接
地区域，旁路电容尽量靠近电源引脚。所有匹配元件和旁
路元件应通过独立过孔连接至接地区域，以减小不希望的
阻抗耦合。
�� Maxim Integrated Products 49
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
定购信息
PART
MAX7049ATI+
TEMP RANGE
PIN-PACKAGE
-40NC to +125NC
28 TQFN-EP*
+表示无铅(Pb)/符合RoHS标准的封装。
*EP = 裸焊盘。
芯片信息
PROCESS: BiCMOS
封装信息
如需最近的封装外形信息和焊盘布局(占位面积)，请查询china.
maxim-ic.com/packages。请注意，封装编码中的“+”、“#”
或“-”仅表示RoHS状态。封装图中可能包含不同的尾缀字符，
但封装图只与封装有关，与RoHS状态无关。
封装类型
封装编码
外形编号
焊盘布局编号
28 TQFN-EP
T2855+3
21-0140
90-0023
�� Maxim Integrated Products 50
MAX7049
高性能、288MHz至945MHz ASK/FSK ISM发送器
修订历史
修订号
修订日期
0
6/11
说明
修改页
—
最初版本。
Maxim北京办事处
北京8328信箱邮政编码100083
免费电话：800 810 0310
电话：010-6211 5199
传真：010-6211 5299
Maxim不对Maxim产品以外的任何电路使用负责，也不提供其专利许可。Maxim保留在任何时间、没有任何通报的前提下修改产品资料和规格的权利。电
气特性表中列出的参数值(最小值和最大值)均经过设计验证，数据资料其它章节引用的参数值供设计人员参考。
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products 51
Maxim是Maxim Integrated Products，Inc.的注册商标。
19-5867; Rev 0; 6/11
EVALUATION KIT AVAILABLE
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
General Description
The MAX7049 high-performance, single-chip, ultralow-power ASK /FSK UHF transmitter operates in the
industrial, scientific, medical (ISM) band at 288MHz to
945MHz carrier frequencies. The IC also includes a low
phase noise fractional-N synthesizer for precise tuning,
fast frequency agility, and low out-of-band power. To
support narrow-band applications, the IC has both
amplitude-shaping and frequency-shaping functions that
enable the user to optimize spectral efficiency. The IC
offers Tx power up to +15dBm. These features make the
transmitter ideally suited for long-range applications.
Additional system-level features of the IC include a digital
temperature sensor and a number of flexible GPOs for
monitoring radio status and for the control of external
functions. A complete transmitter system can be built
using a low-end microprocessor control unit (MCU), the
IC, a crystal, and a small number of passive components.
The IC is available in a small, 5mm x 5mm, 28-pin TQFN
package with an exposed pad. It is specified to operate
in the -40°C to +125°C automotive temperature range.
Applications
Automatic Meter Reading (AMR)
RF Modules
Benefits and Features
STransmitter (Tx)
Provides Long Transmit Range Up to +15dBm

21mA Tx Current for +10dBm Tx Power*

41mA Tx Current for +15dBm Tx Power*

Modulation Shaping, ASK, FSK
SGeneral
Delivers Long Battery Life
< 50nA Shutdown Current
< 350nA Sleep Current

Minimizes the Number of I/Os Required
Between the IC and the MCU Serial Peripheral
Interface (SPI™)
Regulatory Compliant
FCC Part 15 Frequency Hopping
ETSI EN300-220 Compatible
On-Chip Temperature Sensor
Fast Fractional-N Synthesizer with a
User-Defined External Loop Filter
*VDD = 3.0V. Includes losses for the matching network and
regulatory-compliant harmonic filter.
Ordering Information appears at end of data sheet.
Long-Range, One-Way Remote Keyless Entry (RKE)
Wireless Sensor Networks
TPMS
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX7049.related.
Home Security
Home Automation
RFID
Remote Controls
SPI is a trademark of Motorola, Inc.
�� Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Architectural Overview and Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Digital Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Temperature Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Tx Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Frequency-Hopping Spread-Spectrum (FHSS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Fractional-N Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Tx ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Tx FSK Mode Using Frequency Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Tx Pulse FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Tx ASK Mode Using Amplitude Waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Tx FSK Mode Amplitude Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Register Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
�� Maxim Integrated Products 2
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
LIST OF FIGURES
Figure 1. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Digital Output Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. SPI Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. SPI Write Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. SPI Read Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. SPI Read-All Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. SPI Reset Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Tx Warmup Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Frequency-Hopping Spread-Spectrum (FHSS) Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Recommended Crystal Connection to the IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Fractional-N Synthesizer Configuration Tx ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Tx FSK Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Tx FSK Frequency Waveshaping Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Synthesizer Loop Filter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Lock Detector Delay Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. Power Amplifier Topology and Optimum Signal Swings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Tx ASK Mode Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. ASK Waveshaping Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 23. Tx FSK Amplitude Ramp Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. Tx FSK Amplitude Ramp Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LIST OF TABLES
Table 1. Optional Digital Input Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2. Mode Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3. Mode Option Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Sleep Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Temperature Sensor Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6. Crystal Divider Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. LO Frequency-Divider Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Tx FSK Pulse Mode Frequency Multiplier Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. PA Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
�� Maxim Integrated Products 3
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
LIST OF TABLES (continued)
Table 10. Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Group 0: Identification Register (Ident) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Ident Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. Group 1: General Configuration Registers (Conf0, Conf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. Conf0 Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. Conf1 Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Group 2: GPO, Data Output, and Clock Output Registers (IOConf0, IOConf1, IOConf2) . . . . . . . . . . . . . . 38
Table 17. IOConf0 Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Register IOConf1 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Register IOConf2 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. Group 3: Synthesizer Frequency Settings (FBase0, FBase1, FBase2, FLoad) . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Synthesizer Divider Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Synthesizer Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 24. FBase0 Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25. FBase1 Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. FBase2 Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 27. FLoad (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 28. Group 4: Transmiter Amplitude and Timing Parameters (TxConf0, TxConf1, TxTstep) . . . . . . . . . . . . . . . . . 43
Table 29. TxConf0 Register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. TxConf1 Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 31. TxTstep Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 32. Group 5: Transmitter Shaping Registers (Shape00–Shape18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 33. Shape00 Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 34. Shape01–Shape18 Registers (0x10–0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 35. Group 6: Control Registers (TestMux, Datain, EnableReg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 36. TestMux Register (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 37. Datain Register (0x3D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 38. EnableReg Register (0x3E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 39. Group 7: Read-Only Status Registers (TestBus0, TestBus1, Status0, Status1) . . . . . . . . . . . . . . . . . . . . . . . 46
Table 40. TestBus0 Register (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 41. Test Bus Signals (tbus[15:8]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 42. TestBus1 Register (0x41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 43. Test Bus Signals (tbus[7:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 44. Status0 Register (0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 45. Status1 Register (0x43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
�� Maxim Integrated Products 4
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
ABSOLUTE MAXIMUM RATINGS
PAVDD, LOVDD, VCOVDD, CPVDD, PLLVDD,
XOVDD, DVDD, and AVDD to EP.....................-0.3V to +3.6V
ENABLE, DATAIN, SDI, SDO, CS, SCLK,
GPO1, GPO2, HOP, and SHDN to EP.. -0.3V to (VDD + 0.3V)
All Other Pins to EP................................... -0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70NC)
TQFN (single-layer board)
(derate 21.3mW/NC above +70NC)..........................1702.1mW
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
Supply Voltage
SYMBOL
VDD
CONDITIONS
PAVDD, LOVDD, VCOVDD, CPVDD,
PLLVDD, XOVDD, DVDD, and AVDD
connected to power supply
PA off
Operating Current
IDD
Shutdown Current
Input Low Voltage
VIL
Input High Voltage
VIH
PA off,
PA predriver at
high current
setting
MIN
TYP
MAX
UNITS
2.1
3.0
3.6
V
fRF = 315MHz
11.2
fRF = 434MHz
10.4
fRF = 863MHz to 945MHz
10.2
fRF = 315MHz
13.2
fRF = 434MHz
12.4
fRF = 863MHz to 945MHz
12.2
868MHz +15dBm
POUT = +15dBm matching network with
harmonic filter
41
868MHz +10dBm
POUT = +10dBm matching network with
harmonic filter
21
TA = +25NC, Sleep mode
350
TA = +85NC, Sleep mode
600
TA = +125NC, Sleep mode
1700
TA = +25NC, Shutdown mode (registers reset)
50
TA = +85NC, Shutdown mode (registers reset)
200
TA = +125NC, Shutdown mode
(registers reset)
1300
mA
4000
nA
3500
0.2 x VDD
0.8 x VDD
V
�� Maxim Integrated Products 5
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
DC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Pulldown Sink Current
12.5
Pullup Source Current
12.5
Output Low Voltage
Output High Voltage
VOL
In buffer mode, GPO1 250FA sink current,
SDO 1mA sink current, and GPO2 4mA
sink current
VOH
In buffer mode, GPO1 250FA source current,
SDO 1mA source current, and GPO2 4mA
source current
MAX
UNITS
FA
0.225
V
VDD - 0.225
AC ELECTRICAL CHARACTERISTICS
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Divide-by-1 LO divider setting
863
945
Divide-by-2 LO divider setting
431.5
472.5
Divide-by-3 LO divider setting
287.7
315
UNITS
GENERAL CHARACTERISTICS
Operating Frequency
Maximum Data Rate
Maximum Frequency Deviation
Frequency Settling Time
Manchester encoded
100
NRZ encoded
200
100kHz synthesizer loop bandwidth
tON
From Enable low-to-high transition to LO
within 5kHz of final value, 100kHz synthesizer
loop bandwidth
Q150
MHz
kbps
kHz
330
Fs
From Enable low-to-high transition to LO
within 1kHz of final value, 100kHz synthesizer
loop bandwidth
400
Match to 50I, including harmonic filter
+15
dBm
Programmable PA Bias Current
Step
With Q1% 56.2kI external PA reference
current setting resistor
0.5
mA
Programmable PA Power
Dynamic Range
Power range from decimal 1 to decimal 63
on digital PA bias current
36
dB
Modulation Depth
With respect to +10dBm output power
57
dB
Maximum Carrier Harmonics
With output matching network
-50
dBc
POWER AMPLIFIER
Maximum Output Power
PMAX
�� Maxim Integrated Products 6
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FRACTIONAL-N SYNTHESIZER
VCO Gain
KVCO
Referenced to 863MHz to 945MHz LO
108
MHz/V
Close-In Phase Noise
10kHz offset, 100kHz loop BW
-101
dBc/Hz
VCO Phase Noise
1MHz offset, 863MHz to 945MHz
-126
dBc/Hz
VOUT = VCPVDD/2, low setting (icont bit = 0)
204
FA
VOUT = VCPVDD/2, high setting (icont bit = 1)
407
FA
Charge-Pump Current
ICP
1
LO Divider Settings
2
3
Minimum Synthesizer Frequency
Step
Referenced to 863MHz to 945MHz LO or
carrier frequency band
fXTAL/216
Hz
-71
dBc
48
Fs
1
VP-P
7
Bits
7.25
mV
16 to 22.4
MHz
Frequency Pulling by VDD
0.5
ppm/V
Recommended Crystal Load
Capacitance
10
Maximum Crystal Load
Capacitance
20
Reference Spur
26MHz frequency step, 902MHz to 928MHz
band, 100kHz synthesizer loop bandwidth
Frequency Switching Time
Reference Frequency Input
Level
ADC
Resolution
LSB Bit Width
CRYSTAL OSCILLATOR
Crystal Frequency
fXTAL
pF
TEMPERATURE SENSOR
Range
Digital Code Slope
-40 to +125
NC
2
NC/LSB
SPI TIMING CHARACTERISTICS (Figure 1)
Minimum SCLK Low to Falling
Edge of CS Setup Time
tSC
20
ns
Minimum CS Low to Rising Edge
of SCLK Setup Time
tCSS
30
ns
�� Maxim Integrated Products 7
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
AC ELECTRICAL CHARACTERISTICS (continued)
(Figure 2, 50I system impedance, VDD = +2.1V to +3.6V, fRF = 868MHz, TA = -40°C to +125°C, unless otherwise noted. Typical
values are at VDD = +3.0V, TA = +25°C, unless otherwise noted. All min and max values are 100% tested at TA = +125°C and are
guaranteed by design and characterization over temperature, unless otherwise noted.)
PARAMETER
SYMBOL
Minimum SCLK Low to Rising
Edge of CS Setup Time
CONDITIONS
MIN
TYP
MAX
UNITS
tHCS
30
ns
Minimum SCLK Low after Rising
Edge of CS Hold Time
tHS
20
ns
Minimum Data Valid to SCLK
Rising-Edge Setup Time
tDS
15
ns
Minimum Data Valid to SCLK
Rising-Edge Hold Time
tDH
10
ns
Minimum SCLK High Pulse
Width
tCH
30
ns
Minimum SCLK Low Pulse Width
tCL
30
ns
Minimum CS High Pulse Width
tCSH
30
ns
Maximum Transition Time from
Falling Edge of CS to Valid SDO
tCSG
CL = 10pF load capacitance from
SDO to GND
20
ns
Maximum Transition Time from
Falling Edge of SCLK to
Valid SDO
tCG
CL = 10pF load capacitance from
SDO to GND
20
ns
CS
tCSH
tCSS
tHCS
tSC
tCH
SCLK
tCL
tDH
tHS
tDS
SDI
tCSG
tCG
SDO
Figure 1. SPI Timing Diagram
�� Maxim Integrated Products 8
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Typical Operating Characteristics
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
1.0
VDD = 3.6V
0.8
VDD = 3.0V
0.6
VDD = 2.7V
0.4
VDD = 2.1V
0.2
0
-50
-25
0
25
50
75
100
125
VDD = 3.6V
1.6
1.4
1.2
1.0
0.8
VDD = 3.0V
VDD = 2.7V
VDD = 2.1V
0.6
0.4
0.2
0
-25
940
0
25
50
75
100
MAX7049 toc03
-50
-25
0
TA = +85˚C
25
50
75
100
125
CHARGE-PUMP CURRENT
vs. CONTROL VOLTAGE
(LOW CURRENT SETTING, 2.1V SUPPLY)
FREQUENCY SETTLING
AFTER POWER-UP
MAX7049 toc05
868.62MHz
868.60MHz
880
860
20
TEMPERATURE (°C)
920
900
40
125
TA = +25˚C
TA = +125˚C
840
250
-40˚C
200
+25˚C
+85˚C
150
100
-40˚C
+125˚C
DOWN
UP
50
820
868.58MHz
800
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
TRANSMIT FREQUENCY (MHz)
960
MAX7049 toc04
TA = -40˚C
60
TEMPERATURE (°C)
VCO TUNING CHARACTERISTIC
(IN 900MHz BAND) vs. CONTROL VOLTAGE
980
80
0
-50
TEMPERATURE (°C)
1000
100
MAX7049 toc06
1.2
1.8
120
TEMPERATURE SENSOR CODE (DECIMAL)
1.4
2.2
2.0
CHARGE-PUMP CURRENT (µA)
1.6
MAX7049 toc02
SHUTDOWN MODE CURRENT (µA)
1.8
2.4
SLEEP MODE CURRENT (µA)
MAX7049 toc01
2.0
TEMPERATURE SENSOR CODE
vs. TEMPERATURE
SLEEP MODE CURRENT
vs. TEMPERATURE
SHUTDOWN MODE CURRENT
vs. TEMPERATURE
CONTROL VOLTAGE WITH RESPECT TO SUPPLY (V)
0.00s
500.0µs
100.0µs/div
1.000ms
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CONTROL VOLTAGE WITH RESPECT TO GROUND (V)
�� Maxim Integrated Products 9
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
927MHz, ibsel = 1
-130
-140
10
100
1000
10,000
OFFSET FREQUENCY (kHz)
-30
-40
-50
-80
-80
-90
-90
868.590 868.594 868.598 868.602 868.606 868.610
926.990 926.994 926.998 927.002 927.006 927.010
868.592 868.596 868.600 868.604 868.608
FREQUENCY (MHz)
926.992 926.996 927.000 927.004 927.008
FREQUENCY (MHz)
0
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+10dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
0
-20
-10
-20
-50
-40
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
926.990 926.994 926.998 927.002 927.006 927.010
926.992 926.996 927.000 927.004 927.008
FREQUENCY (MHz)
POWER (dBc)
-40
-50
-70
-30
-30
-40
-60
-10
POWER (dBc)
POWER (dBc)
-20
-30
-70
UNMODULATED SPECTRUM
(palopwr = 0, 100% DUTY CYCLE,
+10dBm, 868MHz,
WITH +10dBm AT 3V MATCH)
MAX7049 toc10
-10
-20
-60
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
16MHz CRYSTAL, ibsel = 0, icont = 0)
0
-10
MAX7049 toc12
-110
MAX7049 toc08
-20
POWER (dBc)
927MHz, ibsel = 0
-120
-10
POWER (dBc)
868MHz, ibsel = 0
-100
0
MAX7049 toc11
-80
PHASE NOISE (dBc/Hz)
0
MAX7049 toc07
-70
-90
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
UNMODULATED CLOSE-IN SPECTRUM
(100Hz RBW, 100 SAMPLE AVERAGE,
22.4MHz CRYSTAL, ibsel = 0, icont = 0)
MAX7049 toc09
PHASE NOISE (VCO DOMINATED)
vs. OFFSET FREQUENCY
(CL = 0.1µF, CS = 0.01µF,
R = 200I, RP = CP = 0)
UNSHAPED
-30
-40
-50
-60
GAUSSIAN
-70
848 853 858 863 868 873 878 883 888
FREQUENCY (MHz)
-80
867.75
867.85
867.80
867.95
868.05
868.15
867.90 868.00 868.10
FREQUENCY (MHz)
868.25
868.20
�� Maxim Integrated Products 10
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
-10
-40
-50
-60
-70
GAUSSIAN
-80
867.85
867.80
867.95
-20
-20
-30
-30
-40
-50
868.15
867.90 868.00 868.10
FREQUENCY (MHz)
868.25
-70
-70
867.95
868.20
867.97
867.96
867.99
868.01
868.03
867.98 868.00 868.02
FREQUENCY (MHz)
-10
GAUSSIAN
-20
-40
-50
-10
868.05
UNSHAPED
-50
-80
-80
FREQUENCY (MHz)
868.03
-40
-70
868.6
868.01
-30
-60
868.2 868.4
867.99
FREQUENCY (MHz)
-20
-70
867.8 868.0
867.97
0
-60
-90
867.4 867.6
-80
867.95
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
POWER (dBc)
-30
868.05
868.04
FSK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
Q100kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
0
-50
-60
-80
868.05
UNSHAPED
-40
-60
MAX7049 toc16
867.75
-10
MAX7049 toc17
-30
POWER (dBc)
UNSHAPED
POWER (dBc)
POWER (dBc)
-20
GAUSSIAN
POWER (dBc)
-10
0
MAX7049 toc14
0
MAX7049 toc13
0
FSK MODULATION SPECTRUM
(1kHz RBW, 4kHz SQUARE-WAVEMODULATION,
±4kHz DEVIATION, +10dBm OUTPUT POWER,
WITH +10dBm AT 3V MATCH)
FSK MODULATION SPECTRUM (1kHz RBW,
4kHz SQUARE-WAVE MODULATION,
±4kHz DEVIATION, +10dBm OUTPUT
POWER, WITH +10dBm AT 3V MATCH)
MAX7049 toc15
ASK MODULATION SPECTRUM
(3kHz RBW, 4kHz SQUARE-WAVE MODULATION,
+9dBm OUTPUT POWER, WITH
+10dBm AT 3V MATCH)
-90
867.4 867.6
867.8 868.0
868.2 868.4
868.6
FREQUENCY (MHz)
�� Maxim Integrated Products 11
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Typical Operating Characteristics (continued)
(Figure 2, 50Ω system impedance, VDD = +2.1V to +3.6V, fRF = 288MHz to 945MHz, TA = -40°C to +125°C, unless otherwise noted.
Typical values are at VDD = +3.0V, TA = +25°C, unless otherwise noted.)
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 915MHz,
WITH +15dBm AT 3V MATCH)
15
VDD = 3.0V
10
POUT (dBm)
VDD = 3.6V
3.6V
10.30
10.20
10.10
VDD = 2.1V
10
3.0V
2.1V
5
3.6V
15
POUT (dBm)
10.40
20
MAX7049 toc19
10.50
9.90
0
-5
-5
0
25
50
75
100
-10
125
0
TEMPERATURE (°C)
8
16
24
32
40
48
56
64
0
10
12
POUT (dBm)
0
40
48
56
64
PA CODE 39
8
6
4
PA CODE 19
2
-5
32
14
10
2.4V 2.7V 3.0V 3.3V 3.6V
24
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc21
15
2.1V
16
PA CODE (DECIMAL)
PA POWER vs. PA CODE
(palopwr = 1, 100% DUTY CYCLE, 868MHz,
WITH +10dBm AT 3V MATCH)
5
8
PA CODE (DECIMAL)
MAX7049 toc22
-25
5
0
-10
-50
3.0V
2.1V
VDD = 2.7V
10.00
POUT (dBm)
Tx CURRENT (mA)
20
MAX7049 toc18
10.60
PA POWER vs. PA CODE
(palopwr = 0, 100% DUTY CYCLE, 868MHz,
WITH +15dBm AT 3V MATCH)
MAX7049 toc20
Tx CURRENT vs. TEMPERATURE
(PA OFF, 900MHz BAND, palopwr = 1)
PA CODE 10
0
-2
-10
0
8
16
24
32
40
PA CODE (DECIMAL)
48
56
64
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
125
�� Maxim Integrated Products 12
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
CS
SDI
SCLK
ENABLE
DATAIN
SDO
TOP VIEW
GPO2
Pin Configuration
21
20
19
18
17
16
15
DVDD 22
14
N.C.
HOP 23
13
XTALB
GPO1 24
12
XTALC
SHDN 25
11
XOVDD
10
N.C.
9
PLLVDD
8
CPOUT
MAX7049
AVDD 26
PA+ 27
EP
4
5
6
7
CTRL
CPVDD
PAVDD
REXTPA
3
VCOVDD
2
N.C.
1
LOVDD
+
PA- 28
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
1
PAVDD
Power Amplifier Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.
FUNCTION
2
REXTPA
External PA Bias Current Setting Resistor Connection. Couple to ground through a Q1% tolerance lowtemperature coefficient resistor. A resistor of 56.2kI is recommended for a 0.5mA nominal PA bias
current DAC LSB value.
3, 10,
14
N.C.
4
LOVDD
5
VCOVDD
6
CTRL
No Connection. Leave unconnected.
Local Oscillator (LO) Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible
to the pin.
Voltage-Controlled Oscillator (VCO) Supply Voltage. Bypass to ground with 1FF capacitor as close as
possible to the pin.
Control (Tuning) Voltage for VCO Input. Referenced to VCOVDD pin. Connect through passive loop filter to
CPOUT.
7
CPVDD
Charge-Pump Supply Voltage Input. Bypass to ground with 0.01FF capacitor as close as possible to the pin.
8
CPOUT
Charge-Pump Output. Connect through passive loop filter to CTRL.
9
PLLVDD
Synthesizer Supply Voltage Input. Bypass to ground with 33pF capacitor as close as possible to the pin.
11
XOVDD
Crystal Oscillator Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to
the pin.
�� Maxim Integrated Products 13
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Pin Description (continued)
PIN
NAME
FUNCTION
12
XTALC
Collector Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Can be driven by an AC-coupled external reference with a signal swing of
0.8VP-P to 1.2VP-P.
13
XTALB
Base Crystal Input. Connect to crystal either directly or through an AC-coupling capacitor. A shunt
capacitance to ground might be needed depending on the specified load capacitance of the crystal and
PCB stray capacitances. Must be DC shorted to ground if XTALC is driven by external reference.
15
SDO
16
DATAIN
Transmitter Data Input. The Datain function can also be controlled by SPI. Internally pulled to ground.
17
ENABLE
Enable. Drive high for active operation. Drive low or leave unconnected to put the device into Sleep mode.
The enable function can also be controlled by SPI. Internally pulled to ground.
18
SCLK
19
SDI
20
SPI Active-Low Chip Select. Internally pulled to supply.
21
CS
GPO2
22
DVDD
Digital Supply Voltage Input. Bypass to ground with 0.1FF capacitor as close as possible to the pin.
23
HOP
24
GPO1
General-Purpose Output 1. Low drive strength digital general-purpose output.
25
SHDN
Shutdown Digital Input. Turns off internal power-on-reset (POR) circuit when driven high. Register contents
are set to the initial state when driven high. Must be driven low for normal operation. Not internally pulled to
supply or ground.
26
AVDD
Analog Supply Voltage Input. Bypass to ground with a 1FF capacitor as close as possible to the pin.
27
PA+
Power Amplifier (PA) Positive Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network.
28
PA-
Power Amplifier (PA) Negative Output. Requires DC current path to supply voltage through an inductive path.
The DC current path can be part of the output impedance matching and harmonic filter network.
—
EP
Exposed Pad. This is the only ground connection. Solder evenly to the PCB ground plane for proper
operation. Multiple vias from the solder pad to the PCB ground plane are recommended.
Serial Peripheral Interface (SPI) Data Output. It can also be configured as a general-purpose digital output.
SPI Clock. Internally pulled to ground.
SPI Data Input. Internally pulled to ground.
General-Purpose Output 2. High drive strength digital general-purpose output.
Frequency Hop Pin. Transfers the base[20:0] bits to the fractional-N divider. See the Fractional-N Synthesizer
section. The hop function can also be controlled by SPI. Internally pulled to ground.
�� Maxim Integrated Products 14
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Functional Diagram
27
28
PA+ PASHDN* 25
MAX7049
2 REXTPA
6
PA
GPO1* 24
ADC
7
HOP* 23
TEMPERATURE
SENSOR
GPO2* 21
/1, /2, OR /3
8 CPOUT
CS 20
DIGITAL
CONTROL
AND MCU
INTERFACE
CHARGE
PUMP
SDI 19
SCLK 18
6 CTRL
FRACTIONAL-N
DIVIDER
PFD
ENABLE* 17
VCO
21
GROUNDED
PAD (EP)
DATAIN* 16
SDO* 15
XTAL OSCILLATOR
XTALC
XTALB
12
13
Detailed Description
Architectural Overview and
Applications Circuit
The MAX7049 includes a single precision local oscillator
fractional-N synthesizer with an integrated VCO, fractional-N divider, phase/frequency detector, charge pump,
LO divider, and lock detector. The loop filter is located
off-chip to allow the user to optimize the synthesizer noise
and transient characteristics for a particular application.
In FSK transmit mode, the synthesizer transitions between
the mark and the space frequency based on the state
of the DATAIN pin or datain bit (Datain register, 0x3D,
bit 6). A user-programmable frequency-shaping function
enables the user to precisely define the transition from the
mark frequency to the space frequency and vice versa to
minimize spectral width of the modulated Tx waveform.
* OPTIONAL I/Os FROM/TO MCU.
The bias current of the output stage is set with a combination of an external resistor and an internal amplitudeshaping function. The programmable shaping function enables the user to precisely define the transition
between carrier on and carrier off and vice versa based
on the state of the DATAIN pin or datain bit so as to
minimize the spectral width of the modulated Tx signal.
Linear amplitude ramping is used in FSK mode as the PA
is enabled at the beginning of a data burst and disabled
at the end of a data burst for spectral control.
A complete transmitter system can be built using a
low-end MCU, the IC, a crystal, and a small number of
passive components for power-supply bypassing and for
RF matching, as illustrated in Figure 2.
Communication between the MCU and the IC is accomplished through a 4-pin SPI bus and a number of optional
digital inputs and outputs.
The IC utilizes a differential emitter-coupled, dual-opencollector power amplifier for the transmitter output.
�� Maxim Integrated Products 15
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
C13
L1
DASHED LINES DENOTE OPTIONAL CONNECTIONS
C20
J1
C14
L3
L4
C12
L2
C11
50I
+
VDD
PAVDD
28
27
26
25
24
23
DVDD
HOP
GPO1
SHDN
AVDD
PA-
C15
PA+
C16
C17
22
1
21
2
20
3
19
4
18
C1
REXTPA
R1
N.C.
LOVDD
C2
C3
VCOVDD
CTRL
CPVDD
R2
MAX7049
5
17
GROUNDED
PAD (EP)
6
16
7
15
GPO2
CS
SDI
µP
SCLK
ENABLE
DATAIN
SDO
C4
C7
C8
14
N.C.
13
XTALB
12
11
XTALC
10
XOVDD
9
N.C.
8
PLLVDD
C5
CPOUT
C6
Y1
C9
C10
Figure 2. Typical Operating Circuit
�� Maxim Integrated Products 16
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Digital Inputs and Outputs
Digital Inputs
The IC’s SPI inputs are the CS, SCLK, and SDI pins. The
CS pin is active low, so this pin has an internal pullup.
The SCLK and SDI pins have internal pulldowns. In addition to the SPI inputs, there are also a number of optional
digital inputs to the IC. These inputs are DATAIN,
ENABLE, and HOP. These optional inputs, which have
internal pulldowns, give the user the option to control an
internal signal by either driving the pin to the appropriate
logic level or by setting a control bit to the appropriate
state. This is illustrated in Figure 3.
Digital Outputs
The IC has two dedicated general-purpose outputs
(GPO1 and GPO2), one SPI output (SDO) that can also
serve as a general-purpose output when CS is high. The
GPO1, GPO2, and SDO pins can be configured to output
various internal status signals and clocks, as illustrated
in Figure 4.
The outputs (GPO1 and GPO2) offer a feature where the
pin can operate either as a digital buffer or as a currentlimited source/sink output, as illustrated in Figure 5.
SPI control minimizes the number of I/Os required
between the IC and the MCU, whereas the pin control
eliminates the configuration overhead associated with
SPI communication.
22 DVDD
22 DVDD
22 DVDD
INTERNAL
CSB
SIGNAL
20 CS
INTERNAL
INPUT
SIGNAL
INPUT
‘OR’
INPUT
INPUT
GROUNDED
PAD (EP)
GROUNDED
PAD (EP)
INTERNAL
INPUT
SIGNAL
PROGRAMMABLE
CONTROL BIT
GROUNDED
PAD (EP)
INPUT = SCLK AND SDI
INPUT = DATAIN, ENABLE, AND HOP
SPI INPUTS
Figure 3. Digital Inputs
Table 1. Optional Digital Input Controls
PIN
BIT NAME
REGISTER
NAME
REGISTER
ADDRESS (hex)
BIT LOCATION (7:0)
FUNCTION
DATAIN
datain
Datain
0x3D
6
Data input to transmitter.
ENABLE
enable
EnableReg
0x3E
0
Enable input for transmitter.
HOP
hop
FLoad
0x0B
0
Initiates the transition to the next
frequency as defined by base[20:0].
�� Maxim Integrated Products 17
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
sdos[3:0]
SPI READ-ONLY REGISTERS
TestBus0 AND TestBus1 (0x40 AND 0x41)
tmux[3:0]
INTERNAL SIGNALS
MUX
SDO 15
MUX
gp1s[3:0]
tbus[15:0]
gp1md[1:0]
GPO1 24
MUX
gp2s[3:0]
gp1isht
[15:4]
MAX7049
plllock
xtal
/16
ckdiv[1:0]
/1, /2,
/4, OR /8
gp2md[2:0]
GPO2 21
MUX
/1, /2,
/4, OR /8
gp2isht
/5, /6, mclk /1, /2,
/7, OR /8
/4, OR /8
clksht
XTALC
12
XTALB
xtal[1:0]
13
Figure 4. Digital Outputs
BUFFER MODE
CURRENT MODE
DVDD 22
DVDD 22
ISOURCE
INTERNAL
SIGNAL
OUTPUT
GROUNDED
PAD (EP)
OUTPUT
INTERNAL
SIGNAL
ISINK
GROUNDED
PAD (EP)
Figure 5. Digital Output Options
�� Maxim Integrated Products 18
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
The current mode of operation can reduce digital noise
associated with large supply current spikes. The GPO1
pin has a relatively small current drive capability (80µA
or 160µA). The IOConf2 register (0x05) (gp1md[1:0] bits)
control the current settings:
and xtal is the crystal frequency, and mclk is the master
digital clock. The master digital clock is the divided crystal
frequency given by the xtal[1:0] bits (Conf0 register, 0x01),
according to:
xtal[1:0]
Divide by
gp1md[1:0]
Mode
00
5
0x
Buffer mode
01
6
10
80µA sink/source capability
10
7
11
160µA sink/source capability
11
8
GPO2 has a much larger current drive capability (up to
4mA), as this GPO can be the source of output clock
signals. The IOConf2 register (0x05) (gp2md[2:0] bits)
control the current settings:
If a clock output on GPO2 is required even when the IC
is in Sleep mode (ENABLE pin and enable bit reset to 0),
the SHDN pin is reset to 0, and the clksht bit (IOConf2
register, 0x05, bit 3) must be set to 1.
gp2md[2:0] Mode
0xx
Buffer mode
100
1.0mA sink/source capability
101 2.0mA sink/source capability
A very useful function of the GPOs is to output status
signals that reflect the state of the transmitter at any
particular instance in time. See the Register Details
section for an in-depth description of the status signals
available for the TestBus0 and TestBus1 registers.
110 3.0mA sink/source capability
111 4.0mA sink/source capability
Two other bits also control the operation of GPO1 and
GPO2. The IOConf0 register (0x03) (gp1isht and gp2isht
bits) allows the current mode operation to continue even
if the IC is disabled (Sleep mode).
The GPO2 pin is designated as the primary output for
driving a clock, as it has the strongest buffer and highest
current output capabilities.
Serial Peripheral Interface (SPI)
The IC utilizes a 4-wire SPI protocol for programming its
registers, configuring and controlling the operation of the
whole transmitter.
The following digital pins control the operation of the SPI:
CS:
Active-low SPI chip select
SDI:
SPI data input
SCLK: SPI serial clock
The GPO2 clock signal can be selected by the gp2s[3:0]
and ckdiv[1:0] bits (IOConf0 register, 0x03).
SDO:
SPI data output
gp2s[3:0]
GPO2 Output
0000
plllock
0001
mclk /(ckdiv divider)
0010
xtal/(ckdiv divider)
Any number of 8-bit data bursts (Data 1, Data 2, … Data
N) can be sent within one low cycle of CS, to allow for
burst-write or burst-read operations. The SDO pin acts
as another general-purpose output (GPO) when the CS
pin is high.
0011
xtal/16/(ckdiv divider)
The SPI operates on a byte format, as shown in Figure 6.
where the ckdiv divider is given by:
ckdiv[1:0]
Divide by
00
1
01
2
10
4
11
8
�� Maxim Integrated Products 19
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
CS
SCLK
SDI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SDO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DATA 1
DATA N
Figure 6. SPI Format
SPI Commands
The following commands are implemented in the IC:
Write: Within the same CS cycle, a write command is implemented as follows:
SDI:
<0x01> <Initial Address> <Data 1> <Data 2> … <Data N>
With this command, Data 1 is written to the address given by <Initial Address>, Data 2 is written to <Initial Address +
1>, and so on.
Read: Within the same CS cycle, a read command is implemented as follows:
SDI:
<0x02> <Address 1> <Address 2> <Address 3> … <Address N>
SDO:
<0xXX>
<0xXX>
<Data 1>
<Data 2>
<0x00>
… <Data N - 1> <Data N>
With this command, all the registers can be read within the same cycle of CS. The addresses can be given in any order.
Read All: With two CS cycles, the Read All command is implemented as follows:
SDI:
CS Cycle 1
<0x03> <Address N>
CS Cycle 2
SDO:
<0x00>
<0x00>
<0x00>
…
<0x00>
<Data N> <Data N + 1> <Data N + 2> … <Data N + n>
Reset: A SPI reset command is implemented as follows:
SDI:
<0x04>
An internal active-low master resetb signal is generated, from the falling edge of the last SCLK signal to the falling edge
of the following CS signal (tHCS + tCSH).
CS
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE COMMAND (0x01)
INITIAL ADDRESS (A[7:0])
DATA 1
D7
D0
DATA N
Figure 7. SPI Write Command Format
�� Maxim Integrated Products 20
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
CS
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7
READ COMMAND (0x02)
ADDRESS 1
ADDRESS 2
SDO
A0
ADDRESS N
D7 D6 D5 D4 D3 D2 D1 D0 D7
DATA 1
0x00
D0 D7
DATA 2
D0
DATA N
Figure 8. SPI Read Command Format
CS
SCLK
A7 A6 A5 A4 A3 A2 A1 A0
SDI
READ-ALL COMMAND (0x03)
ADDRESS N
SDO
D7 D6 D5 D4 D3 D2 D1 D0 D7
DATA N
D0 D7
D0
DATA N + 1 DATA N + n
Figure 9. SPI Read-All Command Format
INITIAL
CS
SHUTDOWN
SCLK
SLEEP
SLEEP
XTAL ON
SDI
SPI
CONFIGURATION
TEMPERATURE
SENSOR
RESET COMMAND (0x04)
resetb
Tx
FSK
ASK
Figure 10. SPI Reset Command Format
Figure 11. Operating Modes
Operating Mode Overview
The IC offers several modes of operation that allow the
user to optimize the transmitter’s power consumption for
a particular application. The primary operating modes
are Initial, Sleep, Temperature Sensor, and Tx, as illustrated in Figure 11.
When the SHDN pin is high, the IC is in Shutdown mode.
In Shutdown mode, the POR circuit internal to the IC is
disabled and draws virtually no current. In Shutdown
mode, all internal data registers are reset to the initial
states and must be rewritten for desired transmitter
operation after the SHDN pin is driven low.
�� Maxim Integrated Products 21
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
When the SHDN pin is low, the POR circuit is active and
holds the internal data registers in the initial state until the
power supply is above 2.1V and the IC enters the Initial
mode. From the Initial mode, the IC can be configured
for operation in Sleep mode, Temperature Sensor mode,
or Tx mode. In Sleep mode, there are two options available: Sleep and XTAL ON. In Sleep mode, the current
drain is typically 350nA. All register states are retained in
Sleep mode. In XTAL ON mode, controlled by the clksht
bit (IOConf2 register, 0x05, bit 3), the crystal oscillator is
enabled and the divided output of the crystal oscillator
(/1, /2, /4, /8, as set by the ckdiv[1:0] bits (IOConf0 register, 0x03, bits [5:4]) can be directed to GPO2. The XTAL
ON mode is designed so an accurate high-speed clock
is always available to the MCU.
In Temperature Sensor mode, the internal temperature
sensor function can be executed.
In Tx mode, the transmitter can be configured to transmit
ASK data or FSK data.
Table 2. Mode Control Logic
The Tx mode is determined by the logic states of the
SHDN pin, ENABLE pin, and the enable bit (EnableReg
register, 0x3E, bit 0). The transmitter is enabled if the
SHDN pin is driven low and the ENABLE pin is driven
high, or the enable bit is set. This logic is summarized
in Table 2.
The mode options are selected by the mode SPI bit
(Conf0 register, 0x01, bit 4) and these options are
summarized in Table 3.
Sleep Mode
From the Initial mode, the transmitter directly enters
Sleep mode. In XTAL ON mode, the crystal oscillator is
enabled and the divided output of the crystal oscillator
can be directed to GPO2. This mode is enabled when
the RF functions are disabled and the clksht bit is set.
The current drain in this mode is highly dependent on the
frequency of the output signal and the load capacitance
on the GPO2 pin. The current drain is typically 750µA
when the output signal is 3.2MHz and the load capacitance is 10pF. See the Digital Outputs section for more
details. Table 4 summarizes the Sleep mode functions.
Table 4. Sleep Mode Summary
SHDN PIN
ENABLE PIN
enable BIT
TRANSMITTER
MODE
0
0
0
Sleep
0
0
1
Tx
0
1
0
Tx
0
1
1
Tx
1
0
0
Shutdown
1
0
1
Shutdown
1
1
0
Shutdown
1
1
1
Shutdown
SLEEP
MODE
SETTINGS
TYPICAL
CURRENT
DRAIN
Sleep
Enable = 0
350nA
All register contents
are retained.
XTAL
ON
clksht = 1
750FA*
Divided XTAL
oscillator signal can
be directed to GPO2.
COMMENTS
*Dependent on GPO2 load capacitance and output clock
frequency.
Table 3. Mode Option Logic
mode BIT
MODE OPTION
0
ASK
1
FSK
�� Maxim Integrated Products 22
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Temperature Sensor Mode
The user must initiate the temperature sensor from Sleep
mode, and the transmitter automatically returns to sleep
when the measurement sequence is completed.
The on-chip temperature sensor is enabled when the
tsensor bit (EnableReg register, 0x3E, bit 3) is set. Once
the internal analog temperature sensor circuit has settled,
an A/D conversion is performed and the resultant ADC
value is stored in the tsadc[6:0] bits that are accessed
through the TestBus1 register (0x41, bits 6:0) when the
digital test mux bits tmux[3:0] (TestMux register, 0x3C,
bits 3:0) are set to 0. The tsensor bit is a self-reset bit,
so it returns to a zero state once the temperature sensor
measurement is completed. The tsdone status bit (Status1
register, 0x43, bit 4) is also set when the measurement
is completed. The current drain in Temperature Sensor
mode is less than 1mA and the sensor settling time plus
the ADC conversion time is less than 2ms. The pertinent
features of the Temperature Sensor mode are summarized in Table 5.
Tx Mode
There are two subsets of the Tx mode. These subsets
include FSK and ASK.
The transmitter output signal is generated by the fractional-N
synthesizer, then buffered, and amplified by the power
amplifier (PA) to the programmed output power level. There
is a finite warmup time for the transmitter. Upon entering Tx
mode from Sleep mode, the following sequence occurs:
1) The crystal oscillator is enabled and settles to a steady
state. The rising edge of the internal ckalive status signal indicates that the crystal oscillator has settled and
an accurate time base is available. All other Tx modules
are enabled except the PA. The synthesizer settles to
the desired LO frequency at the same time the other
Table 5. Temperature Sensor Mode
Summary
BIT
tsensor
EXECUTION
TIME (ms)
<2
TYPICAL
CURRENT
DRAIN (mA)
COMMENTS
<1
The tsdone status
bit is set when the
measurement is
completed. The
results are stored in
tsadc[6:0].
modules settle to their desired operating points.
A rising edge of the lockdet status signal indicates
that the synthesizer has locked. In some narrowband applications, the lockdet signal can effectively
be delayed with the plldl[2:0] bits (Conf1 register,
0x02, bits 5:3) to ensure that the synthesizer has
settled to within the desired accuracy. This delayed
signal is called plllock. The rising edge of the txready
status signal is coincident with the rising edge of the
plllock signal.
2) In ASK mode, the power amplifier ramp-up sequence
begins on the rising edge of either the DATAIN pin
or the datain bit after the internal txready signal
transitions high. In FSK mode, the power amplifier
linear ramp-up sequence begins on the rising edge
of the txready signal.
Figure 12 illustrates this warmup sequence.
In an ASK application, the output of the synthesizer
is fixed at the carrier frequency. The output power is
alternated between fully off when both the DATAIN
pin is logic 0 and the datain bit is cleared, and the
programmed output power level when either the DATAIN
enable
‘OR’
ENABLE
ckalive
105µs
(typ)
95µs
(typ)
lockdet
plldel
INTERVAL
plllock
txready
datain
‘OR’
DATAIN
PAQ*
USER-DEFINED PA RAMP
(*PA RAMP BEGINS ON THE RISING EDGE OF DATAIN IN ASK MODE
AND ON THE RISING EDGE OF txready IN FSK MODE.)
Figure 12. Tx Warmup Timing Diagram
�� Maxim Integrated Products 23
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
pin is logic 1 or the datain bit is set. The output signal
can be waveshaped in amplitude to reduce the spectral
width of the transmission. See the Power Amplifier section
for more information regarding amplitude waveshaping.
The PA power is determined by the 6-bit amplitude word
that linearly controls the PA output bias current. The LSB
current amplitude is set by an off-chip resistor placed
between the REXTPA pin and ground. The LSB current is
nominally 0.5mA for a 56.2kI resistor and allows for very
tight transmitter power control with a low-temperature
coefficient ±1% tolerance resistor.
In an FSK application, the output of the synthesizer
alternates between the space frequency when both the
DATAIN pin is logic 0 and the datain bit is cleared, and
the mark frequency when either the DATAIN pin is logic 1
or the datain bit is set. The output signal can be waveshaped in frequency to reduce the spectral width of the
transmission. See the Fractional-N Synthesizer section
for more information regarding frequency waveshaping.
The PA power is determined by the 6-bit amplitude word.
The PA output power linearly ramps between fully off and
the programmed power when the transmitter is enabled
or disabled. The ramp slope is also programmable. To
transmit the entire message at the desired power level,
the user should wait until the PA ramp is completed
before initiating the data sequence.
INITIAL STATE
ENABLE
Figure 13 shows the recommended sequence during
FHSS operation.
Use of the hop bit is preferred during initial configuration.
Use of the HOP pin is preferred over the hop bit during
active transmitter operation. This eliminates the possibility
of SPI activity during active transmitter operation and
allows for exact control of transmitter timing.
SET fska
TO ZERO
HOP
LOAD FIRST
CHANNEL
(FBase)
**CAN BE COMPLETED IN A SINGLE SPI BURST**
NO
The typical current drain in Tx mode is 10.2mA (low-power buffer mode) or 12.2mA (high-power buffer mode) plus
the programmable PA output current. The buffer power
mode is controlled by the palopwr bit (TxConf0 register,
0x0C, bit 7) and is in low-power mode when the bit is set.
Frequency-Hopping SpreadSpectrum (FHSS) Operation
The IC is fully capable of FHSS operation. The fastsettling fractional-N synthesizer and amplitude-shaping
PA work in concert to allow clean, time efficient, and
easy-to-implement frequency hopping under the control
of a low-end MCU.
CONFIGURE
LOAD SECOND
CHANNEL
(FBase)
SET fska TO
DESIRED VALUE
IF FSK MODE
DISABLE
SLEEP STATE
ENABLE
HOP
TRANSMITTER
ACTIVITY
WARMUP
SYNTHESIZER
FORCED OUT
OF LOCK
FSK MODE
ckalive
TRANSITIONS
HIGH
YES
YES
PA
RAMPED
DOWN
NO
YES
END
TRANSMITTER
ACTIVITY
SYNTHESIZER
FREQUENCY
CHANGED
LOAD NEXT
CHANNEL
(FBase)
NO
YES
SYNTHESIZER
ACQUIRES LOCK
HOP PIN
HELD
LOGIC 1
NO
FSK
TRANSMITTER
MODE
YES
PA RAMPED
UP
NO
Figure 13. Frequency-Hopping Spread-Spectrum (FHSS)
Flowchart
�� Maxim Integrated Products 24
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Functional Descriptions
Crystal Oscillator
The IC’s crystal oscillator circuitry is designed to operate
in conjunction with a parallel resonant crystal to generate
the fractional-N synthesizer reference frequency and the
clock signal for the digital control block. Only the crystal,
attached between pins XTALB and XTALC, and two
optional loading capacitors are typically required.
The oscillator typically presents a load capacitance of
approximately 8pF between the pins of the crystal when
PCB stray capacitance is considered. Capacitance
must be added equally from pin XTALC to ground
and pin XTALB to ground to operate the crystal at the
specified crystal load capacitance. If the crystal is
operated at a load capacitance different from the
specified load capacitance, the oscillation frequency
is pulled away from the specified operating frequency,
introducing an error in the fractional-N synthesizer reference frequency. Crystals specified to operate with higher
load capacitance than the applied load capacitance
oscillate at a higher than specified frequency.
XTALC
XTALB
12
13
CBLOCK
CBLOCK
CLOAD
CLOAD
fP =
CM 
1

2  C CASE + C LOAD
−

1
6
 × 10
C CASE + C SPEC 
where:
fP is the amount the crystal frequency is pulled in
ppm.
CM is the motional capacitance of the crystal.
CCASE is the case capacitance (includes package
capacitance and crystal blank capacitance).
CSPEC is the specified load capacitance.
CLOAD is the applied load capacitance.
When the crystal is loaded as specified (i.e., CLOAD =
CSPEC), the frequency pulling equals zero.
The oscillator circuitry is designed to operate with crystal
load capacitances between 8pF and 20pF. Operation at
an applied load capacitance of 10pF is recommended for
optimal startup times. Operation with applied load capacitances greater than 20pF can prevent oscillator startup.
The operating range of the crystal oscillator is 16.0MHz
to 22.4MHz. To maintain an internal 3.2MHz time base
mclk, the xtal[1:0] (Conf0 register, 0x01, bits 1:0), must
be programmed as shown in Table 6. The 3.2MHz
internal time base is recommended for all data rates
below 80kbps (Manchester coded) or 160kbps (NRZ
coded). For higher data rates (up to 100kbps (Manchester
coded) or 200kbps (NRZ coded)), a 4MHz internal time
base is needed, as shown in Table 6.
MAX7049
OPTIONAL
BLOCKING
CAPACITORS
SHORT IF NOT
REQUIRED
Frequency pulling from the specified operating frequency
can be calculated if the electrical parameters of the crystal
are known. The frequency pulling is given by:
LOADING CAPACITORS
(USED ALONG WITH THE IC INTERNAL CAPACITANCE AND PCB STRAY
CAPACITANCE TO APPLY SPECIFIED LOAD CAPACITANCE TO THE CRYSTAL.)
Figure 14. Recommended Crystal Connection to the IC
The crystal initial tolerance, temperature coefficient,
and aging must be specified so that the cumulative
error between the transmitter and companion receiver
frequencies allows proper operation. The transmitted
signal must be downconverted by the companion receiver
so that all necessary modulation sidebands are within the
Table 6. Crystal Divider Programming
CRYSTAL FREQUENCY
(MHz)
CRYSTAL DIVIDER RATIO
xtal[1:0] Conf0 REGISTER,
ADDRESS 0x01, BITS 1:0
mclk (MHz)
16.0
5
00
3.2
19.2
6
01
3.2
22.4
7
10
3.2
20.0
5
00
4.0
Note: The combinations of crystal frequency and divide ratio in this table are recommended, but not all inclusive.
�� Maxim Integrated Products 25
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
passband of the predemodulation filter to operate properly.
For channelized operation, the transmitted signal, including modulation sidebands, must be contained within a
given frequency range, placing limits on the crystal initial
tolerance, temperature coefficient, and aging.
The VCO operates over the entire specified frequency
range with no calibration required. The typical VCO gain
is 108MHz/V and the typical phase noise is -126dBc/
Hz at 1MHz offset. The phase noise improves by
20 x log10(2) for divide-by-2 LO frequency-divider
operation, and improves by 20 x log10(3) for divideby-3 LO frequency divider operation. The VCO control
voltage is applied at the CTRL pin and is referenced
to the VCOVDD pin. The ibsel bit (Conf1 register, 0x02,
bit 6) sets the VCO bias current. The VCO current
increases by 1mA with the ibsel bit set. The VCO phase
noise improves to -128dBc/Hz at 1MHz offset with the
additional current drain.
The IC provides a temperature sensor and a fine-step
fractional-N synthesizer to ease crystal frequency stability requirements. This sensor can be used by the system
MCU along with the crystal temperature coefficient to
calculate the necessary frequency correction and adjust
the fractional-N synthesizer in fXTAL/216Hz steps.
The IC allows for an external reference signal to be
applied in place of a crystal. The external reference
signal should be applied to pin XTALC through an
AC-coupling capacitor at an amplitude between 0.8VP-P
and 1.2VP-P with pin XTALB DC grounded.
The charge pump operates within a typical compliance
range of 0.4V to 0.4V below the supply voltage. The
typical charge-pump current is 204FA with the icont bit
(Conf1 register, 0x02, bit 7) reset. It nearly doubles to 407FA
with icont set. The CPOUT pin is the charge-pump output.
Fractional-N Synthesizer
The IC contains a fully integrated fractional-N synthesizer with the exception of a passive off-chip loop filter
for generating the transmitted signal frequency. This
includes an on-chip voltage-controlled oscillator
(VCO), charge pump, phase-frequency detector (PFD),
fractional-N frequency divider, LO frequency divider,
and all necessary support circuitry. The on-chip
crystal oscillator generates the reference frequency for
the fractional-N synthesizer.
Tx ASK Mode
The fractional-N frequency divider is programmed with
a 21-bit divider word. The divider word consists of a
5-bit integer portion and a 16-bit fractional portion as
illustrated in Figure 15.
The parameter D is the fractional-N divider ratio, where:
D = 32 + base[20:0]/216
and therefore, the synthesizer output frequency is given by:
The operating range of the fractional-N synthesizer is
863MHz to 945MHz. The LO frequency divider has
three modes: divide by 1, divide by 2, and divide by 3.
This allows for operation at frequencies of 863MHz
to 945MHz, 431.5MHz to 472.5MHz, and 287.7MHz
to 315MHz, respectively. The frequency resolution is
fXTAL/216 in the 863MHz to 945MHz range, and is
smaller at the LO frequency-divider output by the LO
division ratio. The division ratio of the LO frequency
divider is set by the fsel[1:0] bits (Conf0 register, 0x01,
bits 3:2). These division ratios are shown in Table 7.
fSYNTH = D x fXTAL
where fXTAL is the reference frequency generated by the
crystal oscillator.
The 21-bit divider word as defined by the contents of the
FBase0, FBase1, and FBase2 registers is latched into the
fractional-N divider on the rising edge of the Hop signal,
which is the logical OR of the HOP input pin and the hop
bit (FLoad register, 0x0B, bit 0), when the IC is enabled.
Table 7. LO Frequency-Divider Modes
fsel[1:0] Conf0 REGISTER, ADDRESS
0x01, BITS 3:2
LO DIVISION RATIO
TRANSMITTER OPERATING
FREQUENCIES (MHz)
00
3
287.7 to 315
01
2
431.5 to 472.5
10
Not used
N/A
11
1
863 to 945
�� Maxim Integrated Products 26
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Figure 15 illustrates the synthesizer operation in Tx ASK
mode, where the Tx carrier frequency is static. For Tx
FSK applications, where the frequency of the carrier
alternates between the space frequency and the mark
frequency based on the Datain input, the IC includes a
frequency waveshaping function that allows the user to
control the spectral width of the transmit signal.
Tx FSK Mode Using Frequency Waveshaping
The inputs to the waveshaping function are illustrated in Figure 16. In this mode, the wsoff bit
(TxConf0 register, 0x0C, bit 6) is cleared and the
wsmlt[1:0] bits (TxConf1 register, 0x0D, bits 7:6) are
cleared. The base[20:0] bits set the divider ratio for
the lowest (space) frequency and base1[20:0] corresponds to the divider ratio for the highest (mark)
frequency. On the rising edge of the Datain signal, the
input to the fractional-N divider transitions between
base[20:0] and base1[20:0] in 20 discrete steps, as
defined by the tstep[7:0] bits (TxTstep register, 0x0E,
bits 7:0) and the shpnn[7:0] bits (Shape00–Shape18
registers, 0x0F–0x21, bits 7:0, where nn = 00 to 18), as
shown in Figure 17.
icont = 0 → CP CURRENT = 204µA
icont = 1 → CP CURRENT = 407µA
MAX7049
fTX
icont
REGISTER
Conf1,
ADDRESS
0x02, BIT 7
fsel[1:0]
REGISTER
Conf0,
ADDRESS
0x01,
BITS 3:2
/1, /2, OR /3
fsel[1:0] = 00 → /3
fsel[1:0] = 01 → /2
fsel[1:0] = 11 → /1
fSYNTH
8 CPOUT
PROGRAMMABLE
CONTROL BITS
CHARGE
PUMP
hop
REGISTER
FLoad,
ADDRESS
0x0B,
BIT 0
FRACTIONAL-N DIVIDER D
/(32 + base[20:0]/216)
PFD
VCO
108MHz/V
6 CTRL
Hop
21-BIT LATCH
ibsel
REGISTER
Conf1,
ADDRESS
0x02,
BIT 6
base[20:16]
REGISTER
FBase0,
ADDRESS
0x08,
BITS 4:0
base[15:8]
REGISTER
FBase1,
ADDRESS
0x09,
BITS 7:0
HOP 23
base[7:0]
REGISTER
FBase2,
ADDRESS
0x0A,
BITS 7:0
XTAL OSCILLATOR
fXTAL
XTALC
12
XTALB
13
Figure 15. Fractional-N Synthesizer Configuration Tx ASK Mode
�� Maxim Integrated Products 27
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
PROGRAMMABLE
CONTROL BITS
FROM VCO
TO PFD
21
datain
16 DATAIN
FRACTIONAL-N
DIVIDER D
MAX7049
Datain
FREQUENCY
WAVESHAPING
FUNCTION
wsoff
shpnn[7:0] : nn = 00:18
wsmlt[1:0]
tstep[7:0]
base[20:0] → SPACE FREQUENCY
base1[20:0] → MARK FREQUENCY
base[20:0]
Figure 16. Tx FSK Mode Programming
Datain
base1[20:0]
base[20:0]
shp05[7:0]
shp04[7:0]
tSTEP
tSTEP
Figure 17. Tx FSK Frequency Waveshaping Timing Diagram
�� Maxim Integrated Products 28
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
The 21-bit divider word is updated at a rate defined by
the tstep[7:0] bits, and this update time step is given by:
tSTEP = tstep[7:0]/mclk
In terms of the shpnn[7:0] bits, the value of base1[20:0]
is therefore:
base1[20:0] = base[20:0] +
nn = 18
∑
shpnn[7:0]
nn = 00
As Figure 17 illustrates, the frequency ramp-down shape
is the inverse, not the mirror image, of the frequency
ramp-up shape. The frequency deviation, which is the
difference between the mark frequency and the space
frequency, can also be expressed in terms of the
shpnn[7:0] bits:
frequency deviation = fXTAL /2 16 ×
nn = 18
∑
shpnn[7:0]
nn = 00
The waveshaping function allows for the approximation of
any monotonic-shape characteristic. An example of the
waveshaping function is the approximation of a 2kbps
NRZ with linear ramp shaping of duration at a 1/2 bit
interval and deviation of 50kHz. The length of the ramp
time is 250Fs. With a 3.2MHz mclk, a decimal value of
40 (0x28) is required for the tstep[7:0] SPI bits because
each of the time steps would need to be 12.5Fs, and 40
x 0.3125Fs yields 12.5Fs. This requires a decimal value
of 11 (0xB) for the shpnn[7:0] bits if used with a 16MHz
crystal. In this case the deviation is 19 (# of frequency
steps) x 11 (frequency change per step) x 16,000,000/216
or 51.03kHz. To attain a value closer to 50kHz at the
expense of linearity, four of the Shape00–Shape18
register values could have been set to decimal 10 (0xA).
This results in a deviation of 205 x 16,000,000/216 or
50.05kHz. The maximum programmable deviation (not
typically used with companion receivers due to bandwidth limitations) in this mode with a 16.0MHz crystal is
19 x 255 x 16,000,000/216 or 1.18MHz.
Tx Pulse FSK Mode
In this mode, the wsoff bit (TxConf0 register, 0x0C, bit 6)
is set and the wsmlt[1:0] bits (TxConf1 register, 0x0D,
bits 7:6) are used to transition directly from the space
frequency to the mark frequency without the use of
shaping. The value of base1[20:0] is expressed as:
base1[20:0] = base[20:0] + wsm × shp00[7:0]
where wsm is a multiplier whose value is given in Table 8.
This mode of pulsed FSK might offer slightly better range
when compared to shaped FSK at the expense of a higher
occupied bandwidth. A waveshaping function is also
available in Tx ASK mode. This feature is documented in
the Power Amplifier section.
Loop Bandwidth
The required loop bandwidth of the fractional-N synthesizer is dependent on the required phase noise characteristics of the transmitted carrier signals, the required
frequency settling times, the FSK modulation rates, and
the current consumption.
Three components dominate the phase noise of the
fractional-N synthesizer output: close-in phase noise, VCO
phase noise, and fractional quantization phase noise.
The loop bandwidth and filter order can be set to meet
the requirements for a wide range of applications due to
the low close-in phase noise (for excellent performance
at wide-loop bandwidths) and low VCO phase noise
(for excellent performance at narrow-loop bandwidths).
The loop filter order can be increased to lessen the
effect of fractional quantization phase noise for wide-loop
bandwidths if necessary.
Table 8. Tx FSK Pulse Mode Frequency Multiplier Values
wsmlt[1:0] TxConf1 REGISTER, ADDRESS 0x0D, BITS 7:6
wsm
00
1
01
2
10
4
11
8
�� Maxim Integrated Products 29
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Generally, a 100kHz loop bandwidth works for most
applications. This choice allows for fast settling times,
within typically 48Fs for less than 5kHz offset during a
26MHz step in the 902MHz to 928MHz ISM band. This
loop bandwidth is near the optimum for minimizing the
contributions of both close-in phase noise and VCO
phase noise. In addition, this choice allows for FSK
modulation rates up to 160kbps NRZ and 80kbps
Manchester for most applications. If the phase noise at
higher offset frequencies needs to be reduced, the loop
bandwidth can be lowered to allow for the VCO noise to
dominate the phase-noise profile completely.
The loop filter components can be calculated as follows:
R = (2 x G x D x BW)/(ICP x KVCO)I
where:
R is the loop filter resistor in I.
D is the frequency division ratio of the feedback
divider of the fractional-N synthesizer.
BW is the desired fractional-N synthesizer loop bandwidth in Hz.
ICP is the charge-pump current in A.
KVCO is the VCO gain at the synthesizer output
frequency (863MHz to 945MHz) in Hz/V.
CL = (√10)/(2 x G x R x BW) in F
where:
CL is the large-loop filter capacitor in series with R.
The value of 10 is approximate.
CS = 1/(2 x G x R x BW x (√10) ) in F
where:
CS is the small-loop filter capacitor in parallel with the
series combination of R and CL.
R is the loop filter resistor in I.
BW is the desired fractional-N synthesizer loop bandwidth in Hz.
The value of 10 is approximate.
An additional RC pole can be added to the loop filter
to remove more fractional quantization phase noise at
wide-loop bandwidths. This pole is added between the
CPOUT pin and the CTRL pin. The resistance of the RC
pole should be 1.5x the value of the loop filter resistor to
limit loading while minimizing thermal noise as a phasenoise contributor. The pole frequency should be greater
than ten times the loop bandwidth. The loop filter configuration is shown in Figure 18.
Lock Detector
The primary support circuit for the fractional-N synthesizer is the lock detector. The internal lock-detect
signal is a gate for transmitter operation as illustrated in
the Operating Mode Overview section. The lock-detect
signal itself is adequate for most operating conditions,
but additional delay can be added if this signal is asserted too quickly, such that it does not allow the synthesizer
to settle to within the desired frequency accuracy as
illustrated in Figure 19.
R is the loop filter resistor in I.
BW is the desired fractional-N synthesizer loop bandwidth in Hz.
VDD
5
CP
6
CL
RP
R
CTRL
MAX7049
lockdet
VDD
7
CS
VCOVDD
CPVDD
plldel INTERVAL
CPOUT
8
plllock
SHORT RP AND CP IF EXTRA POLE IS NOT USED.
BYPASS VCOVDD AND CPVDD TO GROUND.
Figure 18. Synthesizer Loop Filter Topology
Figure 19. Lock Detector Delay Function
�� Maxim Integrated Products 30
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
The additional delay interval is set by the plldl[2:0] bits
(Conf1 register, 0x02, bits 5:3), and this delay is given by:
possible to the IC to minimize the capacitance on this node.
A temperature-stable, high-tolerance ±1% resistor is
recommended to minimize variations in output power. An
on-chip current multiplier of 25 x IR determines the LSB
of the PA bias DAC. For example, a 56.2kI resistor sets
the LSB to 0.5mA. The palopwr bit (TxConf0 register,
0x0C, bit 7) controls the bias current in the PA buffer
amplifier. When this bit is set, it lowers the buffer bias
current by 2mA for low-power applications. The buffer
amplifier sets the pedestal voltage (VP), which is required
for sufficient PA bias DAC headroom.
plldel interval = plldl[2:0] x (64/mclk)s
where plldl[2:0] is the decimal equivalent of the bits, yielding a norminal (3.2MHz mclk) plldel interval from 0 to 140Fs.
Both the lockdet and plllock status signals are available
on SDO, GPO1, and GPO2, as described in the Register
Details section for the TestBus0 and TestBus1 registers.
Power Amplifier
The IC contains a programmable current-drain, highefficiency power amplifier (PA). The PA is a differential
output stage capable of delivering more than +15dBm to
a 50I load including the losses of the matching network
and harmonic filter. The bias current for the PA (IPA) is
configurable in 64 linear steps, as illustrated in Figure 20.
The function of the matching network is to transform the
load resistance (RL) to the differential optimal PA load
resistance (ROPT). The value of ROPT is determined by
the desired output power (PD), the loss of the matching
network (Lm), the supply voltage (VDD), and the pedestal voltage (VP). Table 9 illustrates a design example for
determining ROPT and IPA_peak, where IPA_peak is the
peak value of the DC current.
An external resistor (REXT) is placed between the REXTPA
pin and ground. This resistor, along with an on-chip
reference voltage of 1.13V, sets the reference
current (IR). This resistor should be placed as close as
VDD
L
J
INSERTION LOSS
= Lm
SIGNAL SWINGS FOR
OPTIMAL LOAD
IMPEDANCE
MATCHING
NETWORK
FROM FREQUENCY
SYNTHESIZER
vi
BUFFER
AMP
RL
27
28
PA-
1.13V
REXT
2 REXTPA
IR
25x
I_lsb = 25 x IR
0
PA+
ROPT
MAX7049
PA+
VDD
VP
VP
palopwr
CURRENT MIRROR
vi
PA-
VP
PA BIAS DAC
IPA = (0:63) DIGITAL
CONTROL
x I_lsb
6
VDD
2 x (VDD - VP)
(PA+) - (PA-)
0
Figure 20. Power Amplifier Topology and Optimum Signal Swings
�� Maxim Integrated Products 31
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
The maximum efficiency of an ideal differential output
stage is 2/G and this must also be adjusted by the factor
(VDD - VP)/VDD to account for the headroom required
for the PA bias DAC current source. Note that an unbalanced differential impedance, as seen by the PA output
pins, causes different clipping levels for the PA+ pin
vs. the PA- pin. This degrades efficiency. In addition, if
the matching network does not transform the load resis-
tance to a differential impedance whose value is exactly
ROPT + j0, then this mismatch loss further degrades the
efficiency. In this PA design example, if the PA bias current
switched from zero to IPA_peak with the data input in ASK
mode, the occupied bandwidth of the modulated signal
would be significant. The IC includes an amplitude waveshaping function to reduce the occupied bandwidth of ASK
modulation.
Table 9. PA Design Example
PARAMETER
SYMBOL AND/OR EQUATION
EXAMPLE VALUE
VDD
3V
VP
0.5V
Supply Voltage
Pedestal Voltage
External PA Bias Resistance
REXT
56.2kI
I_lsb = 25 x 1.13/REXT
0.5mA
Desired Peak RF Output Power
PD
14dBm
Harmonic Filter and Composite
Matching/Combiner Network Loss
Lm
2dB
Actual PA RF Output Power
PPA = PL + Lm
16dBm
Actual PA RF Output Power
PPA_mW = 10(PPA/10)
40mW
Required PA DC Power
PDC = PPA_mW x G/2 x VDD/(VDD -VP)
75mW
Maximum PA Efficiency
Maximum efficiency = 100 x 2/G x (VDD - VP)/VDD
53%
Efficiency = 100 x 10(PD/10)/PDC
33%
Required Peak DC Current
IPA_peak = PDC/VDD
25mA
PA Code for Desired Power
idac_peak[5:0]
50 decimal (0x32)
PA Bias DAC LSB
Composite PA Efficiency (includes
Matching Network Loss)
FROM FREQUENCY
SYNTHESIZER
28
27
PA-
PA+
BUFFER
AMP
vi
idac[5:0]
datain
16 DATAIN
MAX7049
Datain
PROGRAMMABLE
CONTROL BITS
IPA = idac[5:0] x I_lsb
6
wsoff
AMPLITUDE
WAVESHAPING
FUNCTION
shpnn[7:0] : nn = 00:18
wsmlt[1:0]
tstep[7:0]
Figure 21. Tx ASK Mode Programming
�� Maxim Integrated Products 32
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Tx ASK Mode Using Amplitude Waveshaping
The ASK waveshaping function is illustrated in Figure 21.
In this mode, the wsoff bit (TxConf0 register, 0x0C, bit 6)
is cleared and the wsmlt[1:0] bits (TxConf1 register,
0x0D, bits 7:6) are cleared. After txready is high, the PA
transitions from zero bias current to IPA_peak, on the
rising edge of the Datain signal. This transition occurs
in 20 discrete steps, determined by the tstep[7:0] bits
(TxTstep register, 0x0E, bits 7:0) and the shpnn[7:0] bits
(Shape00–Shape18 registers, 0x0F–0x21, bits 7:0, where
nn = 00 to 18), as shown in Figure 22.
The PA DAC word is updated at a rate defined by the
tstep[7:0] bits, and this update time step is given by:
tSTEP = tstep[7:0]/mclk
In terms of the shpnn[7:0] bits, the value of idac_peak[5:0]
is therefore:
.
idac_peak[5:0] =
nn = 18
∑
shpnn[7:0]
nn = 00
The two most-significant bits of shpnn[7:0] should always
be zero in ASK mode. As Figure 22 illustrates, the rampdown shape is the inverse of the ramp-up shape. The
waveshaping function allows for the approximation of
any monotonic shape characteristic. Since the shpnn
registers are 8 bits wide, the PA can be pulsed from zero
current to the maximum bias current in one time step if
desired.
An example is the approximation of a 4kbps NRZ with
linear ramp shaping of 1/2 bit interval duration and
peak PA bias current of 10mA using REXT = 56.2kI.
The length of the ramp time is 125Fs. With a 3.2MHz
mclk, this requires a decimal value of 20 (0x14) for the
tstep[7:0] because each of the 20 time steps would need
to be 6.25Fs, and 20 x 0.3125Fs yields 6.25Fs. This
requires a decimal value of 1 (0x1) for each Shape00–
Shape18 register. In this case, the peak PA bias current
is 19 x 25 x 1.13/56,200, or 9.55mA. To attain a value
closer to 10mA at the expense of linearity, one of the
Shape00–Shape18 register values could have been set
to decimal 2 (0x2). This results in a peak PA bias current
of 20 x 25 x 1.13/56,200, or 10.05mA.
Datain
idac_peak[5:0]
0
shp05[7:0]
shp04[7:0]
tSTEP
tSTEP
Figure 22. ASK Waveshaping Timing Diagram
�� Maxim Integrated Products 33
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Tx FSK Mode Amplitude Ramp
In Tx FSK mode, the carrier is modulated by the
frequency-shaping function, as defined in the Fractional-N
Synthesizer section. This frequency waveshaping is
designed to minimize the occupied bandwidth of the
transmit signal in Tx FSK mode. However, the occupied
bandwidth might degrade if the PA turns on and off
abruptly at the beginning and end of a burst. A PA amplitude ramp feature is available in Tx FSK mode to prevent
the degradation of the occupied bandwidth. This feature
is illustrated in Figure 23.
After the IC is enabled and the txready signal transitions high, the PA bias current ramps up linearly to the
value fska[5:0] (TxConf0 register, 0x0C, bits 5:0) x I_lsb
in increments of fskas[5:0] (TxConf1 register, 0x0D, bits
5:0) x I_lsb, as illustrated in Figure 24.
Similarly, the PA bias current ramps down linearly on
the falling edge of the enable signal. Note that this PA
ramp feature is also automatically invoked when hopping
from one channel to another channel, as defined in the
Fractional-N Synthesizer section.
The PA DAC word is updated at a rate defined by the
tstep[7:0] bits, and this update time step is given by:
tSTEP = tstep[7:0]/mclk
To transmit the entire message at the desired power
level, the user should wait until the PA ramp is completed
before initiating the data sequence.
FROM FREQUENCY
SYNTHESIZER
28
27
PA-
PA+
BUFFER
AMP
vi
idac[5:0]
enable
17 ENABLE
MAX7049
Enable
PROGRAMMABLE
CONTROL BITS
IPA = idac[5:0] x I_lsb
6
fska[5:0]
AMPLITUDE
RAMP
FUNCTION
fskas[5:0]
tstep[7:0]
Figure 23. Tx FSK Amplitude Ramp Feature
�� Maxim Integrated Products 34
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
enable AND
txready
fska[5:0]
0
fskas[5:0]
fskas[5:0]
tSTEP
tSTEP
Figure 24. Tx FSK Amplitude Ramp Timing Diagram
Register Details
Table 10. Configuration Register Map
GROUP/FUNCTION
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
Ident
0x00
1
0
1
0
0
1
1
1
Conf0
0x01
—
—
—
mode
fsel_1
fsel_0
xtal_1
xtal_0
Conf1
0x02
icont
ibsel
plldl_2
plldl_1
plldl_0
—
—
—
IOConf0
0x03
gp1isht
gp2isht
ckdiv_1
ckdiv_0
gp2s_3
gp2s_2
gp2s_1
gp2s_0
IOConf1
0x04
sdos_3
sdos_2
sdos_1
sdos_0
gp1s_3
gp1s_2
gp1s_1
gp1s_0
IOConf2
0x05
—
—
gp1md_1
gp1md_0
clksht
gp2md_2
gp2md_1
gp2md_0
FBase0
0x08
—
—
—
base_20
base_19
base_18
base_17
base_16
FBase1
0x09
base_15
base_14
base_13
base_12
base_11
base_10
base_9
base_8
FBase2
0x0A
base_7
base_6
base_5
base_4
base_3
base_2
base_1
base_0
FLoad
0x0B
—
—
—
—
—
—
—
hop
TxConf0
0x0C
palopwr
wsoff
fska_5
fska_4
fska_3
fska_2
fska_1
fska_0
TxConf1
0x0D
wsmlt_1
wsmlt_0
fskas_5
fskas_4
fskas_3
fskas_2
fskas_1
fskas_0
TxTstep
0x0E
tstep_7
tstep_6
tstep_5
tstep_4
tstep_3
tstep_2
tstep_1
tstep_0
1
2
3
4
�� Maxim Integrated Products 35
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 10. Configuration Register Map (continued)
GROUP/FUNCTION
5
6
7
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Shape00
0x0F
shp00_7
shp00_6
shp00_5
shp00_4
shp00_3
shp00_2
shp00_1
shp00_0
Shape01
0x10
shp01_7
shp01_6
shp01_5
shp01_4
shp01_3
shp01_2
shp01_1
shp01_0
Shape02
0x11
shp02_7
shp02_6
shp02_5
shp02_4
shp02_3
shp02_2
shp02_1
shp02_0
Shape03
0x12
shp03_7
shp03_6
shp03_5
shp03_4
shp03_3
shp03_2
shp03_1
shp03_0
Shape04
0x13
shp04_7
shp04_6
shp04_5
shp04_4
shp04_3
shp04_2
shp04_1
shp04_0
Shape05
0x14
shp05_7
shp05_6
shp05_5
shp05_4
shp05_3
shp05_2
shp05_1
shp05_0
Shape06
0x15
shp06_7
shp06_6
shp06_5
shp06_4
shp06_3
shp06_2
shp06_1
shp06_0
Shape07
0x16
shp07_7
shp07_6
shp07_5
shp07_4
shp07_3
shp07_2
shp07_1
shp07_0
Shape08
0x17
shp08_7
shp08_6
shp08_5
shp08_4
shp08_3
shp08_2
shp08_1
shp08_0
Shape09
0x18
shp09_7
shp09_6
shp09_5
shp09_4
shp09_3
shp09_2
shp09_1
shp09_0
Shape10
0x19
shp10_7
shp10_6
shp10_5
shp10_4
shp10_3
shp10_2
shp10_1
shp10_0
Shape11
0x1A
shp11_7
shp11_6
shp11_5
shp11_4
shp11_3
shp11_2
shp11_1
shp11_0
Shape12
0x1B
shp12_7
shp12_6
shp12_5
shp12_4
shp12_3
shp12_2
shp12_1
shp12_0
Shape13
0x1C
shp13_7
shp13_6
shp13_5
shp13_4
shp13_3
shp13_2
shp13_1
shp13_0
Shape14
0x1D
shp14_7
shp14_6
shp14_5
shp14_4
shp14_3
shp14_2
shp14_1
shp14_0
Shape15
0x1E
shp15_7
shp15_6
shp15_5
shp15_4
shp15_3
shp15_2
shp15_1
shp15_0
Shape16
0x1F
shp16_7
shp16_6
shp16_5
shp16_4
shp16_3
shp16_2
shp16_1
shp16_0
Shape17
0x20
shp17_7
shp17_6
shp17_5
shp17_4
shp17_3
shp17_2
shp17_1
shp17_0
Shape18
0x21
shp18_7
shp18_6
shp18_5
shp18_4
shp18_3
shp18_2
shp18_1
shp18_0
TestMux
0x3C
—
—
—
—
tmux_3
tmux_2
tmux_1
tmux_0
Datain
0x3D
—
datain
—
—
—
—
—
—
EnableReg
0x3E
—
—
—
—
tsensor
—
—
enable
TestBus0
0x40
tbus_15
tbus_14
tbus_13
tbus_12
tbus_11
tbus_10
tbus_9
tbus_8
TestBus1
0x41
tbus_7
tbus_6
tbus_5
tbus_4
tbus_3
tbus_2
tbus_1
tbus_0
Status0
0x42
txready
—
adcrdy
—
gpo1out
plllock
lockdet
ckalive
Status1
0x43
—
—
—
tsdone
—
—
—
—
“—” Denotes a reserved bit. If a register contains reserved bits, write 0 to the reserved bit content.
Register 0x00 contents are always 0xA7, and can be used to identify the IC on the SPI bus.
Registers 0x40 through 0x43 are read-only registers, containing various states and status that can be read through the SPI.
�� Maxim Integrated Products 36
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Detailed Register Descriptions
Table 11. Group 0: Identification Register (Ident)
GROUP/FUNCTION
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0x00
1
0
1
0
0
1
1
1
Ident
Table 12. Ident Register (0x00)
BIT
NAME
7:0
ident[7:0]
FUNCTION
Read-only register used for identification purposes. The content of this register is always 0xA7.
Table 13. Group 1: General Configuration Registers (Conf0, Conf1)
GROUP/FUNCTION
1
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Conf0
0x01
—
—
—
mode
fsel_1
fsel_0
xtal_1
xtal_0
Conf1
0x02
icont
ibsel
plldl_2
plldl_1
plldl_0
—
—
—
Table 14. Conf0 Register (0x01)
BIT
NAME
4
mode
FUNCTION
1-bit configuration for transmit mode:
0 = ASK
1 = FSK
2-bit configuration for LO division ratio:
3:2
fsel[1:0]
00
01
10
11
3
2
Not used
1
2-bit crystal divider configuration. Based on a typical crystal selection of 16.0MHz, 19.2MHz, or
22.4MHz, these bits are usually configured to yield a constant 3.2MHz mclk frequency for timing
control and driving characteristics of the digital section of the IC. For data rates up to 200kbps,
an mclk frequency of up to 4.0MHz is needed. The typical settings are:
1:0
xtal[1:0]
Crystal 16.0MHz
19.2MHz
22.4MHz
20.0MHz
xtal[1:0]
00 01 10 00 11 Divide
Divide
Divide
Divide
Divide
by
by
by
by
by
5
6
7
5
8
(16.0/5
(19.2/6
(22.4/7
(20.0/5
=
=
=
=
3.2MHz)
3.2MHz)
3.2MHz)
4.0MHz)
�� Maxim Integrated Products 37
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 15. Conf1 Register (0x02)
BIT
NAME
FUNCTION
7
icont
Selects between low current (0 = 204FA) and high current (1 = 407FA) modes for the synthesizer
charge pump, allowing for lower noise operation with the expense of extra current.
6
ibsel
Selects between low VCO core current and high VCO core current (1 = additional 1mA) in the
synthesizer.
3-bit configuration for extra delay after lock-detect flag (lockdet) from the synthesizer is asserted
(assuming mclk = 3.2MHz):
5-3
plldl[2:0]
plldl[2:0] delay(Fs)
000 0
001 20
010 40
011 60
100 80
101 100
110 120
111 140
After this delay, an internal signal called plllock is asserted high to determine the digital lock flag
for the synthesizer.
Table 16. Group 2: GPO, Data Output, and Clock Output Registers
(IOConf0, IOConf1, IOConf2)
GROUP/FUNCTION
2
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IOConf0
0x03
gp1isht
gp2isht
ckdiv_1
ckdiv_0
gp2s_3
gp2s_2
gps2_1
gps2_0
IOConf1
0x04
sdos_3
sdos_2
sdos_1
sdos_0
gp1s_3
gp1s_2
gp1s_1
gp1s_0
IOConf2
0x05
—
—
gp1md_1
gp1md_0
clksht
gp2md_2
gp2md_1
gp2md_0
�� Maxim Integrated Products 38
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 17. IOConf0 Register (0x03)
BIT
NAME
FUNCTION
7
gp1isht
GPO1 current mode during sleep. If the IC GPO1 is configured to current drive mode (IOConf2
register, 0x05), writing 1 to this bit allows for the current mode operation even if the IC is in Sleep
mode or disabled. If this bit is 0, current mode operation is only active when the IC is enabled.
6
gp2isht
GPO2 current mode during sleep. If the IC GPO2 is configured to current drive mode (IOConf2
register, 0x05), writing 1 to this bit allows for the current mode operation even if the IC is in Sleep
mode or disabled. If this bit is 0, current mode operation is only active when the IC is enabled.
2-bit configuration for clock output divider setting. A clock source selected by gp2s[3:0] is divided by
the settings in these bits, according to the following:
5:4
ckdiv[1:0]
ckdiv[1:0] 00 01 10 11 Divide by
1
2
4
8
4-bit configuration for GPO2 signal selection:
3:0
gp2s[3:0]
gp2s[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1011 1100 1101 1110 1111 Output
plllock
mclk/(ckdiv divider)
xtal/(ckdiv divider)
xtal/16/(ckdiv divider)
tbus[4]
tbus[5]
tbus[6]
tbus[7]
tbus[8]
tbus[9]
tbus[10]
tbus[11]
tbus[12]
tbus[14]
tbus[15]
where:
mclk is the master digital clock generated from the crystal divider block (xtal[1:0]);
xtal is the crystal oscillator output clock;
xtal/16 is a divided-by-16 version of the crystal oscillator frequency;
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 39
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 18. Register IOConf1 (0x04)
BIT
NAME
FUNCTION
4-bit SPI data output GPO mode selection. When CS is low, the SDO pin outputs the SPI data output,
as described in the Serial Peripheral Interface (SPI) section. When CS is high, the SDO acts as a third
GPO, according to:
7:4
sdos[3:0]
CS sdos[3] sdos[2] sdos[1]
0
x
x
x
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
sdos[0] output
x
SPI_Dout
0
tbus[ 0]
1
tbus[ 1]
0
tbus[ 2]
1
tbus[ 3]
0
tbus[ 4]
1
tbus[ 5]
0
tbus[ 6]
1
tbus[ 7]
0
tbus[ 8]
1
tbus[ 9]
0
tbus[10]
1
tbus[11]
0
tbus[12]
1
tbus[13]
0
tbus[14]
1
tbus[15]
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
4-bit configuration for GPO1 signal selection:
3:0
gp1s[3:0]
gp1s[3] 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
gp1s[2] 0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
gp1s[1] 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
gp1s[0] 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
output
tbus[ 0]
tbus[ 1]
tbus[ 2]
tbus[ 3]
tbus[ 4]
tbus[ 5]
tbus[ 6]
tbus[ 7]
tbus[ 8]
tbus[ 9]
tbus[10]
tbus[11]
tbus[12]
tbus[13]
tbus[14]
tbus[15]
tbus[15:0] is the 16-bit bus selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 40
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 19. Register IOConf2 (0x05)
BIT
NAME
FUNCTION
2-bit
5:4
gp1md[1:0]
3
clksht
0x
10
11
GPO1 mode selection:
buffer mode
80FA current mode
160FA current mode
Enable (1) or disable (0) clock output on GPO2 during sleep.
3-bit GPO2 mode selection. The GPO2 can provide a high-frequency clock output, and therefore its
current capability is higher.
2:0
gp2md[2:0]
0xx
100
101 110
111
buffer mode
1.0mA
2.0mA
3.0mA
4.0mA
Table 20. Group 3: Synthesizer Frequency Settings (FBase0, FBase1, FBase2, FLoad)
GROUP/FUNCTION
3
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FBase0
0x08
—
—
—
base_20
base_19
base_18
base_17
base_16
FBase1
0x09
base_15
base_14
base_13
base_12
base_11
base_10
base_9
base_8
FBase2
0x0A
base_7
base_6
base_5
base_4
base_3
base_2
base_1
base_0
FLoad
0x0B
—
—
—
—
—
—
—
hop
Registers 0x08, 0x09, and 0x0A set the 21-bit base value for the control of the synthesizer frequency. Bits 20:16 form
the 5-bit integer part (base[20:16]), and bits 15:0 form the 16-bit fractional part (base[15:0]).
The synthesizer frequency is then given by:
fSYNTH = fXTAL x (32 + base[20:0]/65,536)
where fXTAL is the crystal frequency in MHz. The synthesizer frequency is then divided according to the fsel[1:0]
settings (Conf0 register, 0x01, bits 3:2) to generate the LO frequency:
Table 21. Synthesizer Divider Settings
fsel[1:0]
LO DIVIDER
00
3
01
2
11
1
�� Maxim Integrated Products 41
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
The synthesizer frequency range is from 863MHz to 945MHz, which translates to the base[20:0] values shown in Table 22.
Table 22. Synthesizer Programming Values
CRYSTAL (MHz)
16.0
19.2
22.4
20
SYNTHF (MHz)
MULTIPLIER FACTOR (dec)
base[20:0]
863
21.9375
0x15F000
945
27.0625
0x1B1000
863
12.9479
0x0CF2AB
945
17.2188
0x113800
863
6.5268
0x0686DB
945
10.1875
0x0A3000
863
11.1500
0x0B2666
945
15.2500
0x0F4000
The minimum and maximum frequency for each band is shown in Table 23.
Table 23. Frequency Ranges
SYNTHF (MHz)
300MHz (fsel = 00)
450MHz (fsel = 01)
900MHz (fsel = 11)
863
287.70
431.50
863.00
945
315.00
472.50
945.00
The hop bit allows for a parallel load of the three FBase registers. This is a self-reset bit that reverts to 0 when the operation is completed. This function can also be accomplished by use of the external HOP pin. A detailed description of the
hop operation can be found in the appropriate sections of the transmitter detailed operations descriptions.
Table 24. FBase0 Register (0x08)
BIT
NAME
4:0
base[20:16]
FUNCTION
5-bit integer value for synthesizer.
Table 25. FBase1 Register (0x09)
BIT
NAME
7:0
base[15:8]
FUNCTION
8 MSBs of fractional value for synthesizer.
Table 26. FBase2 Register (0x0A)
BIT
NAME
7:0
base[7:0]
FUNCTION
8 LSBs of fractional value for synthesizer.
Table 27. FLoad (0x0B)
BIT
NAME
0
hop
FUNCTION
Hop bit. Loads the synthesizer fractional-N divider base value to base[20:0] written in registers
8 through 10. This is a self-reset bit, and is reset to zero after the operation is completed.
�� Maxim Integrated Products 42
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 28. Group 4: Transmiter Amplitude and Timing Parameters
(TxConf0, TxConf1, TxTstep)
GROUP/FUNCTION
4
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxConf0
0x0C
palopwr
wsoff
fska_5
fska_4
fska_3
fska_2
fska_1
fska_0
TxConf1
0x0D
wsmlt_1
wsmlt_0
fskas_5
fskas_4
fskas_3
fskas_2
fskas_1
fskas_0
TxTstep
0x0E
tstep_7
tstep_6
tstep_5
tstep_4
tstep_3
tstep_2
tstep_1
tstep_0
These registers set general FSK/ASK parameters for PA amplitude and rate control (FSK), shaping control, and the step
control used for amplitude or frequency shaping.
Table 29. TxConf0 Register (0x0C)
BIT
NAME
7
palopwr
6
wsoff
5:0
fska[5:0]
FUNCTION
Reduces the PA input buffer current by 2mA when set to 1. Useful at low output power levels.
Disables (1) or enables (0) waveshaping. If waveshaping is disabled, only shp00[7:0] (Shape00
register, 0x0F) and wsmlt[1:0] (TxConf1 register, 0x0D) are used to set the amplitude (ASK) or
frequency (FSK) deviation.
6-bit final value for FSK PA amplitude (bias current) control.
Table 30. TxConf1 Register (0x0D)
BIT
NAME
FUNCTION
2-bit scaler for shp00[7:0] (Shape00 register, 0x0F), effectively multiplying the value of Shape00 by:
7:6
wsmlt[1:0]
5:0
fskas[5:0]
wsmlt[1:0] multiplier
00
1
01
2
10
4
11
8
6-bit FSK amplitude (bias current) step for ramp-up and ramp-down operations. The PA amplitude
increases/decreases by this amount for every 1/20th of the data rate time elapsed (TxTstep register,
0x0E), until it reaches the final fska[5:0] value when ramping up, or reaches 0 when ramping down.
Table 31. TxTstep Register (0x0E)
BIT
NAME
FUNCTION
8-bit update value for waveshaping. This setting corresponds to 1/20th of the data rate, given in
periods of the master digital clock (312.5ns for 3.2 MHz).
tstep[7:0] = INT (mclk/(20 x DataRate))
7:0
tstep[7:0]
For 80kbps < DataRate P 160kbps, tstep[7:0] = 1, mclk = 3.2MHz
For 40kbps < DataRate P 80kbps, tstep[7:0] = 2, mclk = 3.2MHz
For 160kbps < DataRate P 200kbps, tstep[7:0] = 1, mclk = 4.0MHz
For 4kbps, tstep = INT (3.2 x106/(20 x 4000)) = 40 (0x28), mclk = 3.2MHz
The maximum value for tstep[7:0] is 255, which allows for a minimum shaped data rate of 627bps.
These values assume shaping during the entire bit interval. The tstep value can be set lower if
possible for shaping during a portion of the bit interval.
This setting allows for the 20 sequential steps in either the amplitude (ASK) or frequency (FSK) waveshaping process,
for each symbol of the transmitted data.
�� Maxim Integrated Products 43
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 32. Group 5: Transmitter Shaping Registers (Shape00–Shape18)
GROUP/FUNCTION
5
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Shape00
0x0F
shp00_7
shp00_6
shp00_5
shp00_4
shp00_3
shp00_2
shp00_1
shp00_0
Shape01
0x10
shp01_7
shp01_6
shp01_5
shp01_4
shp01_3
shp01_2
shp01_1
shp01_0
Shape02
0x11
shp02_7
shp02_6
shp02_5
shp02_4
shp02_3
shp02_2
shp02_1
shp02_0
Shape03
0x12
shp03_7
shp03_6
shp03_5
shp03_4
shp03_3
shp03_2
shp03_1
shp03_0
Shape04
0x13
shp04_7
shp04_6
shp04_5
shp04_4
shp04_3
shp04_2
shp04_1
shp04_0
Shape05
0x14
shp05_7
shp05_6
shp05_5
shp05_4
shp05_3
shp05_2
shp05_1
shp05_0
Shape06
0x15
shp06_7
shp06_6
shp06_5
shp06_4
shp06_3
shp06_2
shp06_1
shp06_0
Shape07
0x16
shp07_7
shp07_6
shp07_5
shp07_4
shp07_3
shp07_2
shp07_1
shp07_0
Shape08
0x17
shp08_7
shp08_6
shp08_5
shp08_4
shp08_3
shp08_2
shp08_1
shp08_0
Shape09
0x18
shp09_7
shp09_6
shp09_5
shp09_4
shp09_3
shp09_2
shp09_1
shp09_0
Shape10
0x19
shp10_7
shp10_6
shp10_5
shp10_4
shp10_3
shp10_2
shp10_1
shp10_0
Shape11
0x1A
shp11_7
shp11_6
shp11_5
shp11_4
shp11_3
shp11_2
shp11_1
shp11_0
Shape12
0x1B
shp12_7
shp12_6
shp12_5
shp12_4
shp12_3
shp12_2
shp12_1
shp12_0
Shape13
0x1C
shp13_7
shp13_6
shp13_5
shp13_4
shp13_3
shp13_2
shp13_1
shp13_0
Shape14
0x1D
shp14_7
shp14_6
shp14_5
shp14_4
shp14_3
shp14_2
shp14_1
shp14_0
Shape15
0x1E
shp15_7
shp15_6
shp15_5
shp15_4
shp15_3
shp15_2
shp15_1
shp15_0
Shape16
0x1F
shp16_7
shp16_6
shp16_5
shp16_4
shp16_3
shp16_2
shp16_1
shp16_0
Shape17
0x20
shp17_7
shp17_6
shp17_5
shp17_4
shp17_3
shp17_2
shp17_1
shp17_0
Shape18
0x21
shp18_7
shp18_6
shp18_5
shp18_4
shp18_3
shp18_2
shp18_1
shp18_0
These registers set the amplitude (ASK) or frequency deviation (FSK) modulated by the incoming transmitted data.
For every 1/20th of the bit rate defined by tstep[7:0], the following shape value is added to the previous accumulated
result. All the shape values are deltas, and the final ASK amplitude or FSK deviation is given by the cumulative sum of
all the shape registers.
In ASK, the initial value is 0. For FSK, the initial value is given by base[20:0]. There are 20 intervals (hence 19 shape
registers) that are added on the 0-1 transition of the transmitted data or subtracted from on the 1-0 transition.
Table 33. Shape00 Register (0x0F)
BIT
7:0
NAME
shp00[7:0]
FUNCTION
First 8-bit value for waveshaping. This value is effectively multiplied by the wsmlt[1:0] setting
(TxConf1 register, 0x0D). If the wsoff bit is high, this is the only value that is added or subtracted to
perform either amplitude (ASK) or frequency (FSK) modulation.
�� Maxim Integrated Products 44
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 34. Shape01–Shape18 Registers (0x10–0x21)
BIT
NAME
7:0
shp01[7:0]
shp02[7:0]
shp03[7:0]
shp04[7:0]
shp05[7:0]
shp06[7:0]
shp07[7:0]
shp08[7:0]
shp09[7:0]
shp10[7:0]
shp11[7:0]
shp12[7:0]
shp13[7:0]
shp14[7:0]
shp15[7:0]
shp16[7:0]
shp17[7:0]
shp18[7:0]
FUNCTION
18 8-bit values for waveshaping. These values, along with shp00[7:0], yield the 19 different values
(20 intervals) used for waveshaping, one for each of the 20 updates occurring during each 0-1 or
1-0 transmitted data transition.
Table 35. Group 6: Control Registers (TestMux, Datain, EnableReg)
GROUP/FUNCTION
6
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TestMux
0x3C
—
—
—
—
tmux_3
tmux_2
tmux_1
tmux_0
Datain
0x3D
—
datain
—
—
—
—
—
—
EnableReg
0x3E
—
—
—
—
tsensor
—
—
enable
This register group combines status bus control (tbus[15:0]), GPO controls, temperature sensor control, register control
of pin function (txdata), and enable controls.
Table 36. TestMux Register (0x3C)
BIT
NAME
3:0
tmux[3:0]
FUNCTION
4-bit selection of tbus[15:0] (TestBus0 and TestBus1 registers, 0x40 and 0x41) contents. See the
TestBus0 and TestBus1 register descriptions for a complete description of what can be observed
through this 16-bit bus.
�� Maxim Integrated Products 45
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 37. Datain Register (0x3D)
BIT
6
NAME
FUNCTION
datain
Transmit datain bit. This is a register equivalent of the DATAIN pin. When either the DATAIN pin or datain bit is 1,
the transmit data is 1. Only when both are 0 the transmit data is 0 (logical OR function). Keep 0 if only the external DATAIN pin is used, and keep DATAIN pin 0 if the internal datain bit is used.
Table 38. EnableReg Register (0x3E)
BIT
3
0
NAME
FUNCTION
tsensor
Writing a 1 to this bit starts the temperature sensor A/D conversion. This is a self-reset bit, where the
bit is automatically reset when the conversion is finished. The result can then be read through the
TestBus1 register (0x41). This function is available only in Sleep mode.
enable
Enables (1) or disables (0) the IC’s transmitter operations. To enable the IC, SHDN must be driven low. This is a
register equivalent of the ENABLE pin. When either the ENABLE pin or enable bit is 1, the IC transmit operation
is enabled. Only when both are 0 the transmitter is disabled (logical-OR function). Keep 0 if only the external
ENABLE pin is used, and keep ENABLE pin 0 if the internal enable is used.
Table 39. Group 7: Read-Only Status Registers (TestBus0, TestBus1, Status0, Status1)
GROUP/FUNCTION
7
HEX
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TestBus0
0x40
tbus_15
tbus_14
tbus_13
tbus_12
tbus_11
tbus_10
tbus_9
tbus_8
TestBus1
0x41
tbus_7
tbus_6
tbus_5
tbus_4
tbus_3
tbus_2
tbus_1
tbus_0
Status0
0x42
txready
—
adcrdy
—
gpo1out
plllock
lockdet
ckalive
Status1
0x43
—
—
—
tsdone
—
—
—
—
Registers 0x3F–0x43 are read-only registers used for A/D results, status, and test.
Table 40. TestBus0 Register (0x40)
BIT
NAME
FUNCTION
7:0
tbus[15:8]
8 MSBs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (TextMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 46
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 41. Test Bus Signals (tbus[15:8])
tmux[3:0]
tbus[15]
tbus[14]
tbus[13]
tbus[12]
tbus[11]
tbus[10]
tbus[9]
tbus[8]
0x0
—
—
—
—
—
—
—
—
0x1
—
—
—
—
—
—
—
—
0x2
—
—
—
—
—
—
—
—
0x3
—
—
—
—
—
—
—
—
0x4
—
—
—
—
—
—
—
—
0x5
—
—
pabia[5]
pabia[4]
pabia[3]
pabia[2]
pabia[1]
pabia[0]
0x6
frac[15]
frac[14]
frac[13]
frac[12]
frac[11]
frac[10]
frac[9]
frac[8]
0x7
—
—
—
—
—
—
—
—
0x8
—
—
—
—
—
—
—
—
0x9
—
—
—
—
—
—
—
—
0xA
—
—
—
—
—
—
—
—
0xB
—
—
—
—
—
—
—
mclk
0xC
—
—
—
—
—
—
—
plllock
0xD
—
—
—
—
—
—
—
—
0xE
—
—
—
—
—
—
—
—
0xF
—
—
—
—
—
—
—
—
where:
tmux[3:0]
Signal
Description
0x0–0x4
—
Reserved signals for test purposes
0x5
pabia[5:0]
PA amplitude control bus
0x6
frac[15:8]
MSBs of fractional value sent to frequency synthesizer
0x7–0xA
—
Reserved signals for test purposes
0xB
mclk
Master digital clock
0xC
plllock
Synthesizer lock signal
0xD–0xF
—
Reserved signals for test purposes
Table 42. TestBus1 Register (0x41)
BIT
NAME
FUNCTION
7:0
tbus[7:0]
8 LSBs of the internal 16-bit bus tbus[15:0], selected by tmux[3:0] (TestMux register, 0x3C, bits 3:0).
�� Maxim Integrated Products 47
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 43. Test Bus Signals (tbus[7:0])
tmux[3:0]
tbus[7]
tbus[6]
tbus[5]
tbus[4]
tbus[3]
tbus[2]
tbus[1]
tbus[0]
0x0
tsdonef
tsadc[6]
tsadc[5]
tsadc[4]
tsadc[3]
tsadc[2]
tsadc[1]
tsadc[0]
0x1
—
—
—
—
—
—
—
—
0x2
—
—
—
—
—
—
—
—
0x3
—
—
—
—
—
—
—
—
0x4
—
—
—
—
—
—
—
—
0x5
palopwr
—
—
integ[4]
integ[3]
integ[2]
integ[1]
integ[0]
0x6
frac[7]
frac[6]
frac[5]
frac[4]
frac[3]
frac[2]
frac[1]
frac[0]
—
0x7
—
—
—
—
—
—
—
0x8
—
—
—
—
—
—
—
—
0x9
—
—
—
ents
—
—
—
tsdonef
0xA
—
—
—
—
—
—
—
—
0xB
—
—
—
—
—
—
—
—
0xC
—
lockdet
ckalive
—
—
—
txready
—
0xD
—
—
—
—
—
—
—
—
0xE
—
—
—
—
—
—
—
—
0xF
—
—
—
—
mclk
—
—
—
where:
tmux[3:0]
Signal
Description
0x0
tsdonef
Temperature sensor conversion done flag
tsadc[6:0]
Temperature sensor A/D result
0x1–0x4
—
Reserved signals for test purposes
0x5
palopwr
PA low-power mode flag
integ[4:0]
Integer value sent to frequency synthesizer
0x6
frac[7:0]
LSBs of fractional value sent to frequency synthesizer
0x7, 0x8
—
Reserved signals for test purposes
0x9
ents
Enable temperature sensor conversion signal
tsdonef
Temperature sensor done flag
0xA, 0xB
—
Reserved signals for test purposes
0xC
lockdet
Synthesizer lock-detect signal
ckalive
Crystal oscillator clock alive flag
txready
Tx ready flag
0xD, 0xE
—
Reserved signals for test purposes
0xF
mclk
Master digital clock
Note that each of the signals available on the digital test bus can be observed on GPO1, GPO2, or SDO, as discussed
in the Digital Outputs section.
�� Maxim Integrated Products 48
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Table 44. Status0 Register (0x42)
BIT
NAME
FUNCTION
7
txready
Transmit ready flag. After this bit goes to 1, the IC is ready to accept transitions on the DATAIN pin
or on the datain bit inputs. Both these bits should be 0 before the txready flag is 1.
5
adcrdy
Internal test flag that signals the end of the A/D warmup time.
3
gpo1out
Register copy of the GPO1 pin logical state.
2
plllock
Synthesizer lock flag, after programmable plldl[2:0] expires.
1
lockdet
Synthesizer lock detect flag.
0
ckalive
Crystal oscillator clock alive flag, indicating clock activity from the crystal oscillator.
Table 45. Status1 Register (0x43)
BIT
4
NAME
tsdone
FUNCTION
Temperature sensor conversion done flag. When 1, the A/D conversion of the internal temperature
sensor is completed.
Layout Considerations
A properly designed PCB is an essential part of any RF/
microwave circuit. On high-frequency, high-impedance
inputs and outputs, use minimum width lines and keep
them as short as possible to minimize stray capacitance.
Keeping the traces short also reduces parasitic inductance. Generally, 1in of PCB trace adds approximately
20nH of parasitic inductance. The parasitic inductance
can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5in trace
connecting to a 100nH inductor adds an extra 10nH of
inductance, or 10%.
To reduce parasitic inductance, use a solid ground
plane below the signal traces. Also, use low-inductance
connections to the ground plane for shunt matching and
bypassing components, and place bypassing capacitors
as close as possible to all power-supply pins. Use separate vias to the ground plane for all shunt matching and
bypassing components to reduce unwanted common
impedance coupling.
�� Maxim Integrated Products 49
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Ordering Information
PART
MAX7049ATI+
TEMP RANGE
PIN-PACKAGE
-40NC to +125NC
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855+3
21-0140
90-0023
�� Maxim Integrated Products 50
MAX7049
High-Performance, 288MHz to 945MHz
ASK /FSK ISM Transmitter
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011
Maxim Integrated Products 51
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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