-27一
功率因数控制器 ML4812
●新 特 器 件 应 用
功率 d毅 控制 器 ML4812
爿
’
叶朝斌
赵虎
摘要 :ML481z主 要用于功率因数校 正 系统,本 文介 绍其基本 工作原理 ,并 重点讨论 由
ML481z组 成的功率 因数校 正 电路的参数设计和元件选择。
PFC 增 益调制器
关键 词 ∶
占空 因数
●精确的 5V参 考电压
●增益调制器可减少外部元件并提高抗干
;
1.概 述 及特 点
电流控制 型升压 PFC(功 率 因数校 正 )系
统申采有的 ML4812,由 于采用了专利技术 ,增
加 了系统的抗干扰性。滞 后电压为 6V的 欠压
锁定电路 可以简化启动。采 用外部电阻调整斜
波补偿 ,可 使 占空因数超过 sO%,并 使器件稳
定工作。ML鲳 1z内 部电路包括 :基 准电压、增
益 调制、误差放大器、过压保护、斜坡补偿及大
电流输 出级等。其内部框 图如图 1所 示。
主要特点如下
扰能力 ;
^
●可调整的斜坡补偿 电路
● 1A峰 流推拉输出驱动 ; 。
●过压比较器可防止输出电压失控
●振荡器高振幅可提高抗干扰能力。
;
;
2,管 脚功能
:
:
h0ˇP
k
管脚排列如图 2所 示 ,各 脚功 熊如下
脚 1(蚰N乩 ):从 电流检测 互感 器到 PWM
比较器 (十 )的 输人。
脚 z【 GM OUT):增 益调
制器输出,此 脚到地 之间接一
~ :
欠1E锁 存输出
押≡
嘈益啁制槲
‘
r
图
1 ML+s1z内 部框图
只 电阻 ,可 把 电流转 换 为 电
压。该脚电压箝位到 SV,并 接
至 PWM比 较器的(-)端 。
、 脚 ×EA OUD:误 差放大
器输出。
脚 4(EAˉ ):误 差放大器的
反相输人。
脚 s【 oVP):过 压 比较器
的输人。
脚 α飞INE):电 流增益调制
器输人。
脚 T【 RAMP COMP):振
荡器斜坡的缓冲输 出,电 阻接
LA乘 积 中
地可设定从
・
提取的电流。`NE与
-28-
|9叨 年第 11期
1998年 11月
脚 8(RT):振 荡器定时 电阻 脚。5V电 源可
设定 给 CT充 电的 电流 。
Isε
・
脚 吖CLOCK):数 字时钟输出♂
彳舻
脚 1O(sHDN):该 脚 的 TTL兼 容低 电平
断开输 出。
′
脚 11(PWR GND)∶ 大电流推拉输出的返
回端。
脚 ⒓(OuT):大 电流推拉输出。
脚 13(Vcc):IC的 正 电源输人。
Ⅱ
脚 ⒕(VREF):5V基 准电压 的缓冲输出。
∶脚 15(oND):模 拟信号地。
脚 “(cT):振 荡器的定时电容端。
2
' E^0UT
3
4
E^-
:可
3。
极 限值
oˇP
s
lsBN:
6
mPcOMP
15
、
14
13
12
11
7
10
B,
RT
9
CNo
VRIF
ˇcc
0V丁
P、
″R
CND
s"DN
C10C“
T0Pˇ |曰 ″
图2
ML481z管 脚排列
IsEt
←
∴
电源电流 砬 :即 mA;
输出电流 :1.oA;
输 出能量 :0.51tJ;
增益调制器输人
。
⒛谀
`INE△
误差放大器灌 电流 :1OmA;
TDˉ ●
刂△
叫卜
RAMP PEAκ
;
图 3 振荡器框图和振荡波形图
模 拟输
阻 把整 流 线输人 的正 弦波 电压 转换 为 电流 ,此
^:to.3~5.5V;
4.功 能说明
时 ,微弱 的接地 噪声对 增 益 调制 器 影 响不 大 ,增
4.1振 荡器
ML碉 ⒓ 振荡 器外 部 电容 的充 电电流为
5/RT,电 容电压 达 nlJ最 高阈值 时 ,比 较器反
转 玎 电容通过 Q1放 电至 最 低 阈值 ,电 容器
放 电时 ,Qz输 出脉 冲,振 荡周期 由下 式卉
・
∴
算:
∷
To∞ =TRAMP十
TDvfE=cT×
TDEADTME
V斜 坡谷 到详 /8・ 4mA-rsε
4.2误 差放大器 和输 出驱动器
T
误荐放大器是 高开环增益的宽带放大器。
输 出驱动器 峰值输 出电流可达 1A,可 快速驱动
容性负载。 ∵
∷
4.3增 益调制器
可
溢
丫
大
功
骥雯
霎
遛
雾
罩
晏
:
~
RAMP V^11:V -
振荡器充 电电流 :zmA;
‰
CI
Ns【
CM oVT
uT与 凡砥 x1EA成 比例 ,其 中
凡N是 流 过 降压 电阻 的电 流 , 凡A与 误 差 放大 器
益 调制器 的电流
1。
输出电压成比列。 当误差放大器为高 电平时
增益调制器输出约等于 凡N输 入 电流。用一 电
阻把增益调制器输出电流转换为 pwM比 较器
的基准电压,当 输出电压箝位在 5v时 ,可 完成
限流,通 过 CT驱 动的缓冲器∴
晶体管可完成斜
坡补偿。
4.4欠 压锁定
ML481z具 有欠压锁定功能,⒕c为 16V
时,IC工 作,‰ 低于 1oV.时 ,欠 压锁定电路工
作,此 时,5V的 ‰EF脚 为 “
OFF” ,并 把它作为
启动 PWM变 换器的信号。
:
5.元 件参数选择
5.1输 入 电 感 L1
功率因数控制器 ML4812
输 人 升 压 电感 器 是 升 压 变 换 器 的 核 心 元
件 ,其 值 计算 如下
(1)最 小 工 作 电流
-29—
SCPwM=RT×
cTX页
:
侧 扩
Ⅱ
hm洲
Rsc的 值 可 由下 式计算
式 中 ∴Asc为 斜 坡 补偿 量 。
“
0V,‰
(狃
∷接在脚 2的 RM值 可 由脚 6的 RP值 算
出: !
h)=sOw,
IN(m犰 )卿 尼=0.272A
刀阝么
(⑷ 选择电感电流终止时的最小电流,本 例
选 (1)步 中峰值电流的 40%,即 廴DRY=1O0mA
(3)代 入数据计算电感值
‰ DRY=[1=D犰 (?n¨ )Jx%Lr
式中,铷 =f TON/(‰ 十T。 FF)J(通 常取
E掭 (狃 )为 0.95)
:
d∝
=
卜
20V× 0.95
1H
100mA× 10G引 Hz =2″
振荡器频率 由下式确定
4・
亠AK≡
^那
⊥芏兰Ⅹ旦珥廴 1.⒋ 4× ⒛ 0≡ 3.1轵
么 ,Rs=」 匕
筲 〓 严 ,屐
Rs为
定
Nc・
0。
%,T。 F|=
R∞ =
L「
/邓
2.5× RM
柢 ×S~x
ˉ
巳卫
=1000pF
扌:圣 卩fΣ
为 sO匝 时
$跏 和 R⒏
1O0Ω ,可 计算
=0・
,
定时龟阻为
^
Ⅰ
Ⅱ±
艹
甥品卩L× 焉
呈
早 2犭
=黄母
汝
cT=-彐
9×
电感 器 的峰值 电流为 :
峰 流为 轵 ,由
:
频率 为 100kHz,占 空 因 数 为
500ns时
兰
丝
RP=l智
=75(kΩ
∴
争
羔
岁
磊
另
瑟=2%?瑟犭
旦
R耘 =Ι生
丁 75(kΩ ~2:。 &Ω
肖
号
肾
卓
∶
六
'I∴
5.2振 荡器元件
ro∞
:
Rsc=Asc× S蚰 M
舡=
VDl(犰 α臼)亍
若
芟
0.7×
fO。
RTx CT
2.5× 28。 &Ω
225× 1σ )× 1Z饨 Ω×1mF
=33尼 Ω
=13。 ⒍ Ω
skΩ
∶计 算 中需 用 到 下 列 数 值 ‰ =⒛ 。
Asc=0.7,RT=1绌 Ω,G='1nF,在 计算中,应
当电感电流连续 且 占空 因数超过 sO%时
才需要斜坡补偿 ,因 此,反 映 PWM输 人的斜坡
为
考虑到元件的误差,实 际应用时,为 避免意外的
限流动作,箝 位电压 ⒕LAMP通 常为4.9V。
5.4电 压调节元件
电压调节电阻 ,最 好用两个 (1丨啪 )电 阻串
联 ,功 率为 0.4W,输 出为 ssOV时
R1=・ (380V)2/0.4W=360尼 Ω
:
,
RT=r。
1.36
sx cT二 1O∝ HzX1OOOpF
选 RT=14kΩ
5.3电 流检测与斜坡补偿 元 件
,
:
SPwM=%田
^vFNDRY x器
可选两个 1SOkΩ 电阻串联
(№ 是 电流 互 感 器 T1的 匝 比 ),平 均 电流 为
7SmA的 电 流 互 感 器输 出端 的整 流 二 极 管 可 选
1N4148。
∷
PWM比
为
:
较 器 反 相 端 的斜 坡 补偿 值
,
sCmM
Rh=
=
;
丬 ⒄
实际取 4。 %kΩ 。
在电压调节环路 中,误 差放大器的反馈电容
G可 以抑制输 出电压中的 120Hz纹 波,G计
・
算公式如下 :
-30-
《国外电子元器件》1998年 第 11期 1g9s年 11月
爿 扩
’
Ι
:ˉ
’
Ⅱ
・
,ˉ
Ⅱ
图 42tXJW功 率 因数校正 电路
|辶
ENHANcIHENt C旧 Cu了 “ 1△
卩
丁丽蹋“
季
"{跻
1~ˉ ˉ
ˉˉˉˉˉˉˉˉˉˉˉˉˉ≡
LFr2~ˉ
ˉ
〓
~。
犯Φ
丨
V= I
sV
I
:。
ˉ
1kW输 人功率,功 率因数校正电路
5.5过 压保护元件
RIx BW・
确定过压保护元件 -可 使系统安全运行 ,过
1
3.1‘ ⒓ ×36o尼
=0。 狃 FtF
F柳
3.△ 42×
μ
ˉ
〓
〓
卿
卿
↑
珈
⑾
〓
Q
CF
啷
・""
〓“"
擗
〓
≡
i
图5
Ω ×剑Hz
压保护电路高压 端 电阻 选择方 法与上面相 同
R4等 于 360kΩ ,那 么 : ∷
,
‘
'
Common ControI Methods fora Boost PFC
(Discont∶ nous and Peak CiL:rrent ControI)ˉ
囵
咖
・ ・
・
Commlon ContrOI Ⅲethods
.囤
砧
B00st PFC (current Loop)
for
匡
|
April 1998
ML4812
Power Factor Controller
GENERAL DESCRIPTION
FEATURES
The ML4812 is designed to optimally facilitate a peak
current control boost type power factor correction system.
Special care has been taken in the design of the ML4812
to increase system noise immunity. The circuit includes a
precision reference, gain modulator, error amplifier, overvoltage protection, ramp compensation, as well as a high
current output. In addition, start-up is simplified by an
under-voltage lockout circuit with 6V hysteresis.
■
Precision buffered 5V reference (±0.5%)
■
Current-input gain modulator reduces external
components and improves noise immunity
■
Programmable ramp compensation circuit
■
1A peak current totem-pole output drive
In a typical application, the ML4812 functions as a
current mode regulator. The current which is necessary to
terminate the cycle is a product of the sinusoidal line
voltage times the output of the error amplifier which is
regulating the output DC voltage. Ramp compensation is
programmable with an external resistor, to provide stable
operation when the duty cycle exceeds 50%.
■
Overvoltage comparator helps prevent output
voltage “runaway”
■
Wide common mode range in current sense
comparators for better noise immunity
■
Large oscillator amplitude for better noise immunity
BLOCK DIAGRAM
(Pin Configuration Shown is for DIP Version)
OVP
–
5V
1
ISENSE
+
–
–
5V
2
3
4
SHDN
+
5
S
Q
R
Q
10
VCC
OUT
12
PWR GND
GM OUT
11
EA OUT
EA–
+
5V
UNDER
VOLTAGE
LOCKOUT
ERROR
AMP
ISINE
VCC
–
IEA
6
VREF
14
13
32V
GAIN MODULATOR
GND
15
7
16
5V
RAMP COMP
CT
CLOCK
9
8
RT
OSC
1kΩ
REV. 1.0 10/10/2000
ML4812
PIN CONFIGURATION
EA OUT
3
14
VREF
EA–
4
13
VCC
OVP
5
12
OUT
ISINE
6
11
PWR GND
RAMP COMP
7
10
SHDN
RT
8
9
CLOCK
3
2
GND
GND
CT
15
1 20 19
EA OUT
4
18
EA–
5
17
VREF
VCC
NC
6
16
NC
OVP
7
15
OUT
ISINE
8
14
PWR GND
9 10 11 12 13
TOP VIEW
SHDN
2
CLOCK
GM OUT
ISENSE
NC
CT
NC
16
RT
1
RAMP COMP
ISENSE
GM OUT
ML4812
20-Pin PLCC (Q20)
ML4812
16-Pin PDIP (P16)
TOP VIEW
PIN DESCRIPTION
PIN
1
2
NAME
ISENSE
GM OUT
FUNCTION
Input from the current sense
transformer to the non-inverting input
of the PWM comparator.
Output of gain modulator.
A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.
PIN
NAME
FUNCTION
8
RT
Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
CT.
9
CLOCK
Digital clock output.
10
SHDN
A TTL compatible low level on this pin
turns off the output.
11
PWR GND Return for the high current totem pole
output.
3
EA OUT
Output of error amplifier.
4
EA–
Inverting input to error amplifier.
12
OUT
High current totem pole output.
5
OVP
Input to over voltage comparator.
13
VCC
Positive Supply for the IC.
6
ISINE
Current gain modulator input.
14
VREF
Buffered output for the 5V voltage
reference.
7
RAMP
COMP
Buffered output from the oscillator
ramp (CT). A resistor to ground sets the
current which is internally subtracted
from the product of ISINE and IEA in
the gain modulator.
15
GND
Analog signal ground.
16
CT
Timing capacitor for the oscillator.
2
REV. 1.0 10/10/2000
ML4812
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Supply Current (ICC) ............................................... 30mA
Output Current Source or Sink (OUT) DC ................ 1.0A
Output Energy (capacitive load per cycle) .................. 5µJ
Gain Modulator ISINE Input (ISINE) ......................... 1.2mA
Error Amp Sink Current (EA OUT) .......................... 10mA
Oscillator Charge Current ........................................ 2mA
Analog Inputs (ISENSE, EA–, OVP) ............... –0.3V to 5.5V
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (soldering 10 sec.) ..................... 260°C
Thermal Resistance (θJA)
20-Pin PLCC .................................................... 60°C/W
16-Pin PDIP .................................................... 65°C/W
OPERATING CONDITIONS
Temperature Range
ML4812CX ................................................ 0°C to 70°C
ML4812IX ............................................. –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V , RT = 14kΩ, CT = 1000pF, TA = Operating Temperature Range (Notes 1, 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
91
98
105
kHz
OSCILLATOR
Initial Accuracy
TJ = 25°C
Voltage Stability
12V < VCC < 18V
0.3
Temperature Stability
Total Variation
2
Line, temperature
90
Ramp Valley to Peak
%
108
3.3
RT Voltage
Discharge Current (RT open)
%
kHz
V
4.8
5.0
5.2
V
TJ = 25°C, VCT= 2V
7.8
8.4
9.0
mA
VCT = 2V
7.3
8.4
9.3
mA
0.2
0.5
V
Clock Out Voltage Low
RL = 16kΩ
Clock Out Voltage High
RL = 16kΩ
3.0
3.5
Output Voltage
TJ = 25°C, IO = 1mA
4.95
5.00
5.05
V
Line Regulation
12V < VCC < 25V
2
20
mV
Load Regulation
1mA < IO < 20mA
2
20
mV
V
REFERENCE
Temperature Stability
Total Variation
0.4
Line, load, temp.
4.9
%
5.1
V
µV
Output Noise Voltage
10Hz to 10kHz
50
Long Term Stability
TJ = 125°C, 1000 hours
5
25
mV
Short Circuit Current
VREF = 0V
–85
–180
mA
±15
mV
–1.0
µA
–30
ERROR AMPLIFIER
Input Offset Voltage
Input Bias Current
–0.1
Open Loop Gain
1 < VEA OUT < 5V
60
75
dB
PSRR
12V < VCC < 25V
60
75
dB
Output Sink Current
VEA OUT = 1.1V, VEA– = 6.2V
2
12
mA
Output Source Current
VEA OUT = 5.0V, VEA– = 4.8V
–0.5
–1.0
mA
Output High Voltage
IEA OUT = –0.5mA, VEA– = 4.8V
5.3
5.5
V
Output Low Voltage
IEA OUT = 1mA, VEA– = 6.2V
Unity Gain Bandwidth
REV. 1.0 10/10/2000
0.5
1.0
1.0
V
MHz
3
ML4812
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GAIN MODULATOR
ISINE Input Voltage
ISINE = 500µA
0.4
0.7
0.9
V
Output Current (GM OUT)
ISINE = 500µA, EA– = VREF –20mV
430
470
510
µA
3
10
µA
860
940
1020
µA
ISINE = 500µA, EA– = VREF + 20mV
ISINE = 1mA, EA– = VREF – 20mV
ISINE = 500µA, EA– = VREF – 20mV,
IRAMP COMP = 50µA
Bandwidth
PSRR
12V < VCC < 25V
455
µA
200
kHz
70
dB
OVP COMPARATOR
Input Offset Voltage
Output Off
–25
Hysteresis
Output On
95
+5
mV
105
115
mV
Input Bias Current
–0.3
–3
µA
Propagation Delay
150
ns
PWM COMPARATOR: ISENSE
Input Offset Voltage
±15
mV
Input Offset Current
±1
µA
5.5
V
–10
µA
Input Common Mode Range
–0.2
Input Bias Current
–2
Propagation Delay
150
ILIMIT Trip Point
VGM OUT = 5.5V
4.8
ns
5
5.2
V
IOUT = –20mA
0.1
0.4
V
IOUT = –200mA
1.6
2.2
V
OUTPUT
Output Voltage Low
Output Voltage High
IOUT = 20mA
13
13.5
V
IOUT = 200mA
12
13.4
V
Output Voltage Low in UVLO
IOUT = –5mA, VCC = 8V
0.1
Output Rise/Fall Time
CL = 1000pF
50
Shutdown
VIH
0.8
V
ns
2.0
V
VIL
0.8
V
IIL, VSHDN = 0V
–1.5
mA
IIH, VSHDN = 5V
10
µA
V
UNDER-VOLTAGE LOCKOUT
Startup Threshold
Shutdown Threshold
9
15
16
17
10
11
V
VREF Good Threshold
4.4
V
SUPPLY
Supply Current
Internal Shunt Zener Voltage
Start-Up, VCC = 14V, TJ = 25°C
0.8
1.2
mA
Operating, TJ = 25°C
20
25
mA
30
34
V
ICC = 30mA
25
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: VCC is raised above the Startup Threshold first to activate the IC, then returned to 15V.
4
REV. 1.0 10/10/2000
ML4812
FUNCTIONAL DESCRIPTION
TOSC = TRAMP + TDEADTIME
OSCILLATOR
The ML4812 oscillator charges the external capacitor (CT)
with a current (ISET) equal to 5/RSET. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.
The Oscillator period can be described by the following
relationship:
where:
VOUT =
VIN
1 - D ON
and:
TDEADTIM E =
C T ´ VRAM P VALLEY TO PEAK
8.4mA - I SET
90%
10
5nF
2nF
8
85%
1nF
EXTERNAL
CLOCK
5
CSYNC
RT (kΩ)
80%
SYNC
10
Q2
3
70%
ISET
RSYNC
20nF
RT
2
9
MAXIMUM DUTY CYCLE (%)
10nF
RT
16
CT
ISET
CT
1
10
+
8.4mA
5.6V
100
-
Q1
1000
OSCILLATOR FREQUENCY (kHz)
Figure 2. Oscillator Timing Resistance vs. Frequency
15
VCC = 15V
80µs PULSED LOAD
120Hz RATE
tD
RAMP PEAK
V(CT)
RAMP VALLEY
Figure 1. Oscillator Block Diagram
OUTPUT SATURATION VOLTAGE (V)
VCC
CLOCK
14
13
SOURCE SATURATION
LOAD TO GROUND
SINK SATURATION
LOAD TO VCC
3
2
1
GND
0
0
200
400
600
800
OUTPUT CURRENT (mA)
Figure 3. Output Saturation Voltage vs. Output Current
REV. 1.0 10/10/2000
5
ML4812
FUNCTIONAL DESCRIPTION (Continued)
OUTPUT DRIVER STAGE
The ML4812 output driver is a 1A peak output high speed
totem pole circuit designed to quickly drive capacitive
loads, such as power MOSFET gates. (Figure 3)
ERROR AMPLIFIER
the output of the error amplifier. When the error amplifier
is saturated high, the output of the gain modulator is
approximately equal to the ISINE input current. The gain
modulator output current is converted into the reference
voltage for the PWM comparator through a resistor to
ground on the gain modulator output. The gain modulator
output is clamped to 5V to provide current limiting.
Ramp compensation is accomplished by subtracting 1/2
of the current flowing out of RAMP COMP through a
buffer transistor driven by CT which is set by an external
resistor.
The ML4812 error amplifier is a high open loop gain,
wide bandwidth, amplifier.(Figures 4-5)
GAIN MODULATOR
The ML4812 gain modulator is of the current-input type
to provide high immunity to the disturbances caused by
high power switching. The rectified line input sine wave is
converted to a current via a dropping resistor. In this way,
small amounts of ground noise produce an insignificant
effect on the reference to the PWM comparator. The
output of the gain modulator is a current of the form: IOUT
is proportional to ISINE ↔ IEA, where ISINE is the current in
the dropping resistor, and IEA is a current proportional to
UNDER VOLTAGE LOCKOUT
On power-up the ML4812 remains in the UVLO
condition; output low and quiescent current low. The IC
becomes operational when VCC reaches 16V. When VCC
drops below 10V, the UVLO condition is imposed.
During the UVLO condition, the 5V VREF pin is “off”,
making it usable as a “flag” for starting up a downstream
PWM converter.
ERROR CURRENT
5V
8V
6
ISINE
9V
ISINE × ERROR CURRENT
0.5mA
+
– IRAMP COMP/2
EA–
–
4
5V
GM OUT
2
RAMP COMP
EA OUT
7
3
16
100
500
60
PHASE
-60
40
-90
20
-120
GAIN
0
-150
-20
-180
10M
MULTIPLE OUTPUT CURRENT (µA)
-30
EXCESS PHASE (degrees)
AVOL, OPEN LOOP GAIN (dB)
Figure 6. Gain Modulator Block Diagram
0
80
CT
4.5
400
4.0
3.5
300
3.0
200
2.5
100
2.0
ERROR AMP OUTPUT VOLTAGE (V)
Figure 4. Error Amplifier Configuration
IRAMP COMP
1.5
6
10
100
1k
10k
100k
1M
0
0
100
200
300
400
500
FREQUENCY (Hz)
SINE INPUT CURRENT (µA)
Figure 5. Error Amplifier Open-Loop Gain and
Phase vs Frequency
Figure 7. Gain Modulator Linearity
REV. 1.0 10/10/2000
ML4812
TYPICAL APPLICATIONS
25
INPUT INDUCTOR (L1) SELECTION
One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.
20
ICC (mA)
The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns
will be high. So a balance must be reached between
distortion and core size.
15
10
5
0
10
0
20
30
40
VCC (V)
Figure 9a. Total Supply Current vs. Supply Voltage
25
For the boost converter at steady state:
VIN
1- D ON
20
(1)
cycle [T
[TON
/(TON
+ TOFF)]. The
Where DON is the duty cycle
ON/(T
ON +
input boost inductor will dry out when the following
condition is satisfied:
VIN(t ) < VOUT ´ (1- D ON )
(2)
SUPPLY CURRENT (mA)
VOUT =
OPERATING CURRENT
15
10
5
or
STARTUP
VIND RY = [1 - D ON (max)] ´ VOUT
(3)
VINDRY: voltage where the inductor dries out.
VOUT: output DC voltage.
0
–60 –40 –20
0
20
40
60
80 100 120 140
TEMPERATURE (degrees)
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver
during the OFF time. The net result is that the inductor
dries out.
Figure 9b. Supply Current (ICC) vs. Temperature
0
-4
∆VREF (mV)
-8
ENABLE
VREF
-16
VREF
GEN.
5V VREF
-20
9V
–
INTERNAL
BIAS
VCC
+
Figure 8. Under-Voltage Lockout Block Diagram
REV. 1.0 10/10/2000
-12
-24
0
20
40
60
80
100
120
IREF (mA)
Figure 10. Reference Load Regulation
7
ML4812
TYPICAL APPLICATIONS (Continued)
The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors. For example, if: VOUT =
380V and DON (max) = 0.95, then substituting in (3)
yields VINDRY = 20V. The effect of drying out is an
increase in distortion at low voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform, i.e. as the input voltage sweeps from zero volts
to a maximum value equal to its peak so does the current.
The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.
By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:
Step 1:
Find minimum operating current.
IIN(min)PEAK =
1414
´ PIN(min)
.
VIN(max)
(4)
PIN(min) = 50W
Gapped Ferrites, Molypermalloy, and Powdered Iron
cores are typical choices for core material. The core
material selected should have a high saturation point and
acceptable losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4119PL00-3C8 made by Philips Components
(Ferroxcube). This ungapped core will require a total gap
of 0.180" for this application.
OSCILLATOR COMPONENT SELECTION
fOSC =
then:
IIN(min)PEAK = 0.272A
136
.
RT ´ CT
(6)
For example:
Step 2: Choose a minimum current at which point the
inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.
then:
ILDRY = 100mA
Step 3: The value of the inductance can now be found
using previously calculated data.
L1 =
8
Step 4: The presence of the ramp compensation will
change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the above value of L1 can be optimized after a
few iterations.
The oscillator timing components can be calculated by
using the following expression:
VIN(max) = 260V
VIND RY ´ D ON (max)
ILD RY ´ fOSC
20 V ´ 0.95
=
= 2mH
100mA ´ 100KHz
The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.
Step 1: At 100kHz with 95% duty cycle TOFF = 500ns
calculate CT using the following formula:
CT =
TOFF ´ IDIS
= 1000pF
VOSC
(7)
Step 2: Calculate the required value of the timing
resistor.
RT =
136
.
136
.
=
fOSC ´ C T 100KHz ´ 1000pF
= 136
. kW choose R T = 14kW
(8)
(5)
REV. 1.0 10/10/2000
ML4812
TYPICAL APPLICATIONS (Continued)
CURRENT SENSE AND SLOPE (RAMP) COMPENSATION
COMPONENT SELECTION
Slope compensation in the ML4812 is provided internally.
Rather than adding slope to the noninverting input of the
PWM comparator, it is actually subtracted from the
voltage present at the inverting input of the PWM
comparator. The amount of slope compensation should be
at least 50% of the downslope of the inductor current
during the off time, as reflected to the inverting input of
the PWM comparator. Note that slope compensation is
required only when the inductor current is continuous
and the duty cycle is more than 50%. The downslope of
the inductor current at the verge of discontinuity can be
found using the expression given below:
diL VOUT - VIN DRY 380 V - 20V
=
=
= 0.18 A / ms (9)
2mH
dt
L
The downslope as reflected to the input of the PWM
comparator is given by:
S PWM =
S PWM =
VOUT - VIN DRY
L
´
RS
NC
(10)
380 V - 20 100
´
= 0.225V / ms
2mH
80
Where RS is the current sense resistor and NC is the turns
ratio of the current transformer (T1) used. In general,
current transformers simplify the sensing of switch
currents (especially at high power levels where the use of
sense resistors is complicated by the amount of power
they have to dissipate). Normally the primary side of the
transformer consists of a single turn and the secondary
consists of several turns of either enameled magnet wire
or insulated wire. The diameter of the ferrite core used in
this example is 0.5" (SPANG/Magnetics F41206-TC). The
rectifying diode at the output of the current transformer
can be a 1N4148 for secondary currents up to 75mA
average.
Sense FETs or resistive sensing can also be used to sense
the switch current. The sensed signal has to be amplified
to the proper level before it is applied to the ML4812.
The value of the ramp compensation (SCPWM) as seen at
the inverting terminal of the PWM comparator is:
SC PWM =
25
. ´RM
R T ´ C T ´ R SC
(11)
The required value for RSC can therefore be found by
equating: SCPWM = ASC × SPWM, where ASC is the amount
of slope compensation and solving for RSC. The value of
GM OUT depends on the selection of RAMP COMP.
RP =
VIN (max) PEAK 260 ´ 1414
.
=
= 750kΩ
0.5mA
I SINE (PEAK)
REV. 1.0 10/10/2000
(12)
RM =
VCLAMP ´ R P 49
. ´ 750kΩ
=
= 288
. kΩ
90 ´ 1414
.
VIN (PEAK)
(13)
The peak of the inductor current can be found
approximately by:
ILPEAK =
´ POUT 1414
1414
.
´ 200
.
=
= 314
. A
90
VIN (RM S )
(14)
Selection of NC which depends on the maximum switch
current, assume 4A for this example is 80 turns.
RS =
VCLAM P ´ NC 4.9 ´ 80
=
= 100W
4
ILPEAK
(15)
Where RS is the sense resistor, and VCLAMP is the current
clamp at the inverting input of the PWM comparator. This
clamp is internally set to 5V. In actual application it is a
good idea to assume a value less than 5V to avoid
unwanted current limiting action due to component
tolerances. In this application, VCLAMP was chosen as
4.9V.
Having calculated RS, the value SPWM and of RSC can
now be calculated:
25
. ´ RM
R SC =
A SC ´ S PWM ´ R T ´ C T
(16)
25
. ´ 28.8kΩ
= 33kΩ
R SC =
6
0.7 ´ (0.225 ´ 10 ) ´ 14K ´ 1nF
The following values were used in the calculation:
RM = 28.8kΩ
RT = 14kΩ
ASC = 0.7
CT = 1nF
VOLTAGE REGULATION COMPONENTS
The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note
that voltage safety regulations require the use of sense
resistors that have adequate voltage rating. As a rule of
thumb if 1/4W resistors are chosen, two of them should
be used in series. The input bias current of the error
amplifier is approximately 0.5µA, therefore the current
available from the voltage sense resistors should be
significantly higher than this value. Since two 1/4W
resistors have to be used the total power rating is 1/2W.
The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:
R 1 = ( 380V) 2 / 0.4W = 360kΩ
(17)
Choose two 178kΩ, 1% connected in series. Then R2 can
be calculated using the formula below:
VREF ´ R 1
5V ´ 356kΩ
=
= 4747
. kΩ
R2 =
(18)
380V - 5V
VOUT - VREF
9
ML4812
TYPICAL APPLICATIONS (Continued)
Choose 4.75kΩ, 1%. One more critical component in the
voltage regulation loop is the feedback capacitor for the
error amplifier. The voltage loop bandwidth should be set
such that it rejects the 120Hz ripple which is present at
the output. If this ripple is not adequately attenuated it
will cause distortion on the input current waveform.
Typical bandwidths range anywhere from a few Hertz to
15Hz. The main compromise is between transient
response and distortion. The feedback capacitor can be
calculated using the following formula:
1
´ R 1 ´ BW
3142
.
1
= 0.44mF
CF =
´ 356kΩ ´ 2Hz
3142
.
CF =
(19)
OVERVOLTAGE PROTECTION (OVP) COMPONENTS
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above VOUT is generally a good
setpoint. This sets the maximum transient output voltage
to about 395V. By choosing the high voltage side resistor
of the OVP circuit the same way as above i.e. R4 = 356K
then R5 can be calculated as:
R5 =
VREF ´ R 4
5V ´ 356kΩ
= 4564
=
. kΩ
395V - 5V
VOVP - VREF
(20)
Choose 4.53kΩ, 1%. Note that R1, R2, R4 and R5 should
be tight tolerance resistors such as 1% or better.
CONTROLLER SHUTDOWN
The ML4812 provides a shutdown pin which could be
used to shutdown the IC. Care should be taken when this
pin is used because power supply sequencing problems
could arise if another regulator with its own bootstrapping
follows the ML4812. In such a case a special circuit
should be used to allow for orderly start up. One way to
accomplish this is by using the reference voltage of the
ML4812 to inhibit the other controller IC or to shut down
its bias supply current.
OFF-LINE START-UP AND BIAS SUPPLY GENERATION
The ML4812 can be started using a “bleed resistor” from
the high voltage bus. After the voltage on VCC exceeds
16V, the IC starts up. The energy stored on the 330µF,
C15, capacitor supplies the IC with running power until
the supplemental winding on L1 can provide the power to
sustain operation.
10
The values of the start-up resistor R10 and capacitor C15
may need to be optimized depending on the application.
The charging waveform for the secondary winding of L1 is
an inverted chopped sinusoid which reaches its peak
when the line voltage is at its minimum. In this example,
C9 = 0.1µF, C15 = 330µF, D8 = 1N4148, R10 = 39kΩ,
2W.
ENHANCEMENT CIRCUIT
The power factor enhancement circuit shown in Figure 12
is described in detail in Application Note 11. It improves
the power factor and lowers the input current harmonics.
Note that the circuit meets IEC 1000-3-2 specifications
(with the enhancement) on the harmonics by a large
margin while correcting the input power factor to better
than 0.99 under most steady state operating conditions.
CONSTRUCTION AND LAYOUT TIPS
High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly
recommended. All critical switching leads (power FET,
output diode, IC output and ground leads, bypass
capacitors) should be kept as small as possible. This is to
minimize both the transmission and pick-up of switching
noise.
There are two kinds of noise coupling; inductive and
capacitive. As the name implies inductive coupling is due
to fast changing (high di/dt) circulating switching currents.
The main source is the loop formed by Q1, D5, and
C3–C4. Therefore this loop should be as small as possible,
and the above capacitors should be good high frequency
types.
The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the
FET with a high frequency capacitor (CH in Figure 12).
The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with
a very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops
should be avoided. Star grounding or ground plane
techniques are preferred.
REV. 1.0 10/10/2000
ML4812
TYPICAL APPLICATIONS (Continued)
MATERIAL
MANUFACTURER
PART #
TURNS (#24AWG)
Powdered Iron
Powdered Iron
Molypermalloy
Micrometals
Micrometals
SPANG (Mag. Inc.)
T225-8/90
T184-40
58076-A2 (high flux)
200
120
180
Table 1. Toroidal Cores (L1)
MAGNETICS TIPS
T1 — Sense Transformer
L1 — Main Inductor
In addition to the core type mentioned in the parts list, the
following Siemens cores should be suitable for
substitution and may be more readily available in Europe.
As shown in Table 1, one of several toroidal cores can be
used for L1. The T184-40 core above is the most
economical, but has lower inductance at high current.
This would yield higher ripple current and require more
line EMI filtering. The value for RSC (slope compensation
resistor on RAMP COMP) was calculated for the T225-8/
90 and should be recalculated for other inductor
characteristics. The various core manufacturers have a
range of applications literature available. A gapped ferrite
core can also be used in place of the powdered iron core.
One such core is a Philips Components (Ferroxcube) core
#4229PL00-3C8. This is an ungapped core. Using 145
turns of #24 AWG wire, a total air gap of 0.180" is
required to give a total inductance of about 2mH. Since
1/2 of the gap will be on the outside of the core and 1/2
the gap on the inside, putting a 0.09" spacer in the center
will yield a 0.180" total gap. To prevent leakage fields
from generating RFI, a shorted turn of copper tape should
be wrapped around the gap as shown in Figure 11. For
production, a gapped center leg can be ordered from most
core vendors, eliminating the need for the external
shorted copper turn when using a potentiometer core.
MATERIAL
SIZE CODE
PART #
N27
N30
R16/6.3
R16/6.3
B64290-K45-X27
B64290-K45-X830
The N27 material is for high frequency and will work
better above 100KHz but both are adequate. In addition,
Philips Components (Ferroxcube) core 768T188-3C8 can
be used. Please also refer to the list of core vendors below
SPANG/Magnetics Inc.
Micrometals
Philips Components
COPPER FOIL
SHORTED TURN
1 (800) 245-3984, or
(412) 282-8282
1 (800) 356-5977
(914) 247-2064
0.09" GAP
Figure 11. Copper Foil Shorted Turn
REV. 1.0 10/10/2000
11
12
90 TO
260 VAC
N
AC IN
L
P1
C1
1µF
630V
D4
1N5406
D3
1N5406
D2
1N5406
R13
22kΩ
22kΩ
C17
RGMOUT
27kΩ
+
R12
1K Q3
R3
D11
D12
D13
C19
R2B
3.9kΩ
R2A
10kΩ
CF
R1B
180kΩ
R1A
180kΩ
R5B
3.9kΩ
R5A
10kΩ
R4B
180kΩ
R4A
180kΩ
NP
RSC
33kΩ
RPB
150kΩ
RPA
360kΩ
1
NS
Q3 = 2N2222 OR EQUIVALENT.
1
2
3
4
5
6
7
8
IC1
16
15
14
13
12
11
10
9
ML4812
RT
7.5kΩ
2
L1
7812
Q2
** SEE NOTES BELOW
R10
39kΩ
2W
C16 +
100µF
25V
D9
NOTES:
1. ALL UNSPECIFIED DIODES ARE 1N4148.
2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.
3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.
4. ADJUST R2A AND R5A WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.
FUSE F1
5A 250V
D1
1N5406
OPTIONAL
ENHANCEMENT
CKT.
1N5406
D10
CT 2nF
D8
P3*
C6
680µF
200V
C5
680µF
200V
C4
1µF
630V
FOR HIGHER POWER USE MORE VCC DECOUPLING.
2µF OR MORE BE REQUIRED AT 1KW LEVELS.
CH
6.8nF
HEATSINK
R7
150kΩ
1W
R6
150kΩ
1W
C3
6.8nF
1kV
***
IRF840
Q1
T1
D5 MUR850
FIXED RESISTORS CAN BE USED FOR THE SENSING
COMPONENTS. BELOW ARE 1% STANDARD
RESISTORS THAT WILL FORCE THE CORRECT
OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178kΩ 1%,
R2B = 4.75 1%, R5B = 4.53kΩ 1%.
USE JUMPERS INSTEAD OF R2A AND R5A (POTS).
RG
10
B
A
–
+
**
RS
100
D6
VCC
P3 IS USED AT INITAL TURN-ON TO
CHECK THE IC FOR PROPER OPERATION.
APPLY ≈ 16VDC.
C8
0.1µF
C11
1nF
1µF
C10
*
C9
0.1µF
***
R11
33kΩ
330µF
25V
C15
C18
+
OFF-LINE START-UP
AND BIAS SUPPLY
–
+
VOUT
P2
380 VDC
ML4812
Figure 12. Typical Application, 200W Power Factor Correction Circuit
REV. 1.0 10/10/2000
ML4812
REFERENCE
DESCRIPTION
REFERENCE
DESCRIPTION
C1, C4
C3, CH
C5, C6
C8, C9
C10, C19
C11
C15
C16
C17
CF
CT
D1, D2, D3, D4, D10
D5
D6, D8, D9
D11, D12, D13
F1
IC1
L1
Q1
Q2
Q3
1µF, 630V Film (250VAC)
6.8nF, 1KV Ceramic disk
680µF, 200V Electrolytic
0.1µF, 50V Ceramic
1µF, 50V Ceramic
0.001µF, 50V Ceramic
330µF, 25V Electrolytic
100µF, 25V Electrolytic
10µF, 25V Electrolytic
0.47µF, 50V Ceramic
0.002µF, 50V Ceramic
1N5406 (Motorola)
MUR850 (Motorola)
1N4148
R1A, R1B, R4A, R4B
R2A, R5A
180kΩ
10kΩ TRIMPOT BOURNS
3299 or equivalent
3.9kΩ
22kΩ
150kΩ
39kΩ, 2W
33kΩ
1kΩ
10Ω
27kΩ
360kΩ
100kΩ
33kΩ
7.5kΩ
SPANG F41206-TC
NS = 80, NP = 1 (see note)
5A, 250V 3AG with clips
ML4812CP (Micro Linear)
2mH, 4A IPEAK (see note)
IRF840 or MTPN8N50
LM7815CT
2N2222 or equivalent
R2B, R5B
R3, R13
R6, R7, RPB
R10
R11
R12
RG
RM
RPA, R15
RS
RSC
RT
T1
Notes:
All resistors 1/4W unless otherwise specified. Some reference designators
are skipped (e.g. C2, C12, etc.) and do not appear on the schematic.
These designators were used in previous revisions of the board and are
not used on this revision. Additional information on key components is
included in the attached appendix.
Table 2. Component Values/Bill of Materials for Figure 12
REV. 1.0 10/10/2000
13
14
C3
C2
C1
1µF 1µF
1µF
500V 500V 500V
BRIDGE
RECTIFIER
RM
27K
1N5406
R2B
3K
R2A
5K
R5B
3K
R5A
5K
R4B
180K
R1B
180K
CF
R4A
360K
R1A
180K
**
22K
RPB
150K
1
2
3
4
5
6
7
8
Q3 = 2N2222 OR EQUIVALENT.
16
15
14
13
12
11
10
9
IC1
22K
VCC
ML4812
RT
6.2K
GND
RSC
51K
L1
566µH
RPA
360K
R6
C13
10µF
NOTES:
1. ALL UNSPECIFIED DIODES ARE 1N4148.
2. ALL UNSPECIFIED RESISTORS ARE 1/4 WATT.
3. ALL UNSPECIFIED CAPACITOR VOLTAGE RATINGS ARE 50V.
4. ADJUST R2A AND R5A WITH CAUTION TO AVOID OVER VOLTAGE CONDITIONS.
N
15A 250V
FUSE F1
330K
+
ENHANCEMENT CIRCUIT SEE TEXT
R2
CT 2.2nF
R7
R3
33K
D2
VZ
3.5V
Q3
2N2222
C6
1µF
GND
1T
C8
15µF
630V
R4
150K
1W
C9
15µF
630V
FIXED RESISTORS CAN BE USED FOR THE SENSING
COMPONENTS. BELOW ARE 1% STANDARD
RESISTORS THAT WILL FORCE THE CORRECT
OUTPUT VOLTAGES R1A, R1B, R4A, R4B = 178kΩ 1%,
R2B = 4.75Ω 1%, R5B = 4.53kΩ 1%.
USE JUMPERS INSTEAD OF R2A AND R5A (POTS).
FOR HIGHER POWER USE MORE VCC DECOUPLING.
**
***
–
VOUT
C11
680µF
250V
C10
680µF
250V
C12
1µF
630V
GND
AT INITIAL TURN-ON TO CHECK
THE IC FOR PROPER OPERATION,
APPLY ≈ 16VDC.
C7
0.1µF
RG2
3
RG1
3
T1
R5
150K
Q1
Q2
1W
APT5025 APT5025
C14
1µF
***
RS
22Ω 80T
D5 MUR3050
*
C4
0.1µF
VCC
C5
1nF
D4
+
IN
AC
L
D1
R1
ML4812
Figure 13. 1kW Input Power, Power Factor Correction Circuit
REV. 1.0 10/10/2000
ML4812
PHYSICAL DIMENSIONS inches (millimeters)
Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
16
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.02 MIN
(0.50 MIN)
(4 PLACES)
0.055 - 0.065
(1.40 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.016 - 0.022
(0.40 - 0.56)
0.125 MIN
(3.18 MIN)
0.008 - 0.012
(0.20 - 0.31)
0º - 15º
Package: Q20
20-Pin PLCC
0.385 - 0.395
(8.89 - 10.03)
0.042 - 0.056
(1.07 - 1.42)
0.350 - 0.356
(8.89 - 9.04)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
1
0.042 - 0.048
(1.07 - 1.22)
6
PIN 1 ID
16
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(8.89 - 10.03)
0.200 BSC
(5.08 BSC)
0.290 - 0.330
(7.36 - 8.38)
11
0.009 - 0.011
(0.23 - 0.28)
0.050 BSC
(1.27 BSC)
0.026 - 0.032
(0.66 - 0.81)
0.165 - 0.180
(4.19 - 4.57)
0.146 - 0.156
(3.71 - 3.96)
0.100 - 0.110
(2.54 - 2.79)
0.013 - 0.021
(0.33 - 0.53)
SEATING PLANE
REV. 1.0 10/10/2000
15
ML4812
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4812CP
ML4812CQ
0°C to 70°C
0°C to 70°C
Molded PDIP (P16)
Molded PLCC (Q20)
ML4812IP
ML4812IQ
–40°C to 85°C
–40°C to 85°C
Molded PDIP (P16)
Molded PLCC (Q20)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
16
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2000 Fairchild Semiconductor Corporation
REV. 1.0 10/10/2000