Power Driver Integrated Full Digital Audio Amplifier NTP-8230 NTP-8230 High Performance, High Fidelity Power Driver Integrated Full Digital Audio Amplifier Datasheet Revision 0.1 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 1 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier General Description NTP-8230 Features The NTP-8230 is a single chip full digital audio amplifier including power stage for stereo amplifier system. NTP-8230 is integrated with versatile digital audio signal processing functions, highperformance, high-fidelity fully digital PWM modulator, a stereo headphone amplifier and two high-power full-bridge MOSFET power stages. The NTP-8230 receives digital serial audio data with sampling frequency from 8kHz through 192kHz. It delivers 2 x 30 watts in stereo mode without heat sink. The NTP-8230 has a mixer and Bi-Quad filters which can be used to implement the essential audio signal processing functions like loudness control, compensation of a loud speaker response and parametric equalization. All the functions of the NTP-8230 can be controlled by internal register values via I2C host interface bus. 2 CH Stereo (30W x 2 @28V,8Ω) 2.1 channel (10W x 2 + 25W @24V,8Ω) Wide Operating Supply Voltage Range (7V to 28V) Floating Point Operation 25 Programmable Bi-Quad Filters Speaker Compensation LPF, HPF Parametric Equalizer Loudness Control 100dB Dynamic Range 2 Band Dynamic Range Control 5 Band Graphic Equalizer 3D Surround Protection Circuit OCP(Over Current Protection) OTP(Over Temperature Protection) UVP(Under Voltage Protection) High Efficiency DC cut filter 48 47 46 45 44 43 42 41 40 39 38 PVDD1 PVDD1 PVDD1 OUT1A OUT1A PGND1A BST1A /RESET AD CLK_I CLK_OUT VDD_IO Package 37 AVDD_PLL 1 36 OUT1B DVDD_PLL 2 35 OUT1B LF 3 34 PGND1B GND 4 33 BST1B SDATA 5 32 VDR1 WCK 6 31 VCC5 BCK 7 30 AGND SDA 8 29 VDR2 NTP-8230 SCL 9 28 BST2A DVDD 10 27 PGND2A /FAULT 11 26 OUT2A PWM_MASK_2 12 25 OUT2A 24 PVDD2 23 PVDD2 22 PVDD2 21 OUT2B 20 OUT2B 19 PGND2B 18 BST2B 17 HP_MUTE 16 HP_R 15 HP_L 14 MONITOR_1 MONITOR_0 13 Applications PDP TV or LCD TV Docking Station Mini-Component Audio Solution Ordering Information Product ID Package Type Pin Size NTP-8230 MLF 48 7 x 7mm ( 48 pin MLF 7mm x 7mm Package ) NeoFidelity, Inc. #1901, Ace High-End Tower 2, 222-14, Guro-dong, Guro-gu, Seoul 152-848 Korea, Phone +82-2-6340-1000, Fax +82-2-6675-1109, Email [email protected], Web www.neofidelity.com Disclaimer NeoFidelity, Inc. reserves the right to make changes without notice in the product described in this datasheet including circuits, software and ICs, described herein for the purpose of improvement of design and performance. NeoFidelity, Inc. assumes no responsibilities and liabilities for the use of the product, conveys no license under any patent or copyright, and makes no warranties that the product is free from patent or copyright infringement, unless otherwise specified. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 2 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Table of Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. BLOCK DIAGRAM .......................................................................................................................................4 PIN ASSIGNMENTS .....................................................................................................................................4 PIN DESCRIPTIONS ....................................................................................................................................5 CHARACTERISTICS AND SPECIFICATIONS ............................................................................................7 4.1. Absolute Maximum Ratings ....................................................................................................................7 4.2. Recommended Operating Conditions ....................................................................................................7 4.3. DC Electrical Characteristics ..................................................................................................................7 4.4. Performance Specification ......................................................................................................................8 4.5. Switching Characteristics – I2C Control .................................................................................................9 4.6. Switching Characteristics – Audio Interface ...........................................................................................9 I2C BUS OF NTP-8230 ............................................................................................................................. 10 5.1. General Description of I2C Bus ........................................................................................................... 10 5.1.1. Writing Operation............................................................................................................................... 11 5.1.2. Reading Operation ........................................................................................................................... 12 5.1.3. I2C Glitch Filter ................................................................................................................................. 13 CLOCK, RESET & CONTROL .................................................................................................................. 14 6.1. System Clock....................................................................................................................................... 14 6.2. Reset Timing........................................................................................................................................ 14 AUDIO INPUT ............................................................................................................................................ 15 7.1. I2S and Serial Audio Interface ............................................................................................................. 15 MIXER ........................................................................................................................................................ 17 PRE-PROCESSING .................................................................................................................................. 18 9.1. Pre Bi-Quad Filter Chain ..................................................................................................................... 18 9.2. 3D Surround ........................................................................................................................................ 18 9.3. Configurable Graphic Equalizer .......................................................................................................... 19 9.4. Post Bi-Quad Filter Chain .................................................................................................................... 19 9.5. Loudness Control ................................................................................................................................ 20 VOLUME & DYNAMIC RANGE CONTROL ............................................................................................. 21 10.1. Master Volume Control ...................................................................................................................... 21 10.2. Channel Volume Control ................................................................................................................... 21 10.3. Master Volume Fine Control .............................................................................................................. 21 10.4. Mute and Soft Volume Change ......................................................................................................... 21 10.5. Auto Mute .......................................................................................................................................... 21 10.6. Dynamic Range Control .................................................................................................................... 22 OUTPUT INTERFACE ............................................................................................................................... 23 11.1. Output Configuration.......................................................................................................................... 23 11.2. AM Interference Relief Mode ............................................................................................................. 23 11.3. PWM Output Mapper ......................................................................................................................... 23 11.4. Switching Output Mode ..................................................................................................................... 23 11.5. Soft start............................................................................................................................................. 24 TYPICAL APPLICATION SCHEMATICS (2CH Stereo) ........................................................................... 25 TYPICAL APPLICATION SCHEMATICS (2.1 Channel) .......................................................................... 26 APPENDIX ................................................................................................................................................. 27 A. Configuration Register Summary ....................................................................................................... 27 B. ROM address for BiQuads Coefficients and Parameters (Refer to Reg 0x7E) ................................. 43 C. Configuration Resister Value Reference ............................................................................................ 48 D. Outline and Mechanical Data ............................................................................................................. 54 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 3 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 1. BLOCK DIAGRAM SDATA WCK Serial Audio I/F AGC FBQ/PBQ 3D GEQ DRC Soft Mute VOL Mixer BCK PLL MCLK SCL CH1 FETout OUT1A OUT1B CH2 FETout OUT2A OUT2B PWM Protection Logic Regulator Control Register I2C I/F SDA /FAULT Head-Phone/ Sub-Woofer Figure 1. NTP-8230 Block Diagram 48 47 46 45 44 43 42 41 40 39 38 PVDD1 PVDD1 PVDD1 OUT1A OUT1A PGND1A BST1A /RESET AD CLK_I CLK_OUT VDD_IO 2. PIN ASSIGNMENTS 37 AVDD_PLL 1 36 OUT1B DVDD_PLL 2 35 OUT1B LF 3 34 PGND1B GND 4 33 BST1B SDATA 5 32 VDR1 WCK 6 31 VCC5 BCK 7 30 AGND SDA 8 29 VDR2 SCL 9 28 BST2A DVDD 10 27 PGND2A /FAULT 11 26 OUT2A PWM_MASK_2 12 25 OUT2A NTP-8230 24 PVDD2 23 PVDD2 22 PVDD2 21 OUT2B 20 OUT2B 19 PGND2B 18 BST2B 17 HP_MUTE 16 HP_R 15 HP_L 14 S-WOOFER_A/ MONITOR_0 S-WOOFER_B/ MONITOR_1 13 Figure 2. NTP-8230 Pin Assignments Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 4 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 3. PIN DESCRIPTIONS PIN NAME TYPE DESCRIPTION 1 AVDD_PLL P Regulator output for PLL analog block, 1.8V 2 DVDD_PLL P Regulator output for PLL digital block, 1.8V 3 LF I/O 4 GND P This pin should be connected to Ground 5 SDATA I I2S serial data input 6 WCK I/O I2S word clock 7 BCK I/O I2S bit clock 8 SDA I/O I2C data 9 SCL I I2C clock 10 DVDD P Regulator output for Core block, 1.8V External PLL loop filter 11 /FAULT I Input from external power device 12 O External power device on/off control to protect O Monitoring signal out from processor block O Monitoring signal out from processor block 15 PWM_MASK_2 S_WOOFER_A/ MONITOR_0 S_WOOFER_B/ MONITOR_1 HP_L O Left audio channel Headphone signal 16 HP_R O Right audio channel Headphone signal 17 HP_MUTE O External Headphone mute signal 18 BST2B P Bootstrap supply, external capacitor to OUT2B is required 19 PGND2B P Ground 20 OUT2B O Power stage PWM output 2B 21 OUT2B O Power stage PWM output 2B 22 PVDD2 P Power supply for PWM Power stage 2A, 2B 23 PVDD2 P Power supply for PWM Power stage 2A, 2B 24 PVDD2 P Power supply for PWM Power stage 2A, 2B 25 OUT2A O Power stage PWM output 2A 26 OUT2A O Power stage PWM output 2A 27 PGND2A P Ground 28 BST2A P Bootstrap supply, external capacitor to OUT2A is required 29 VDR2 P Gate drive voltage regulator decoupling pin, capacitor to GND is required 30 AGND P Ground 31 VCC5 P Logic voltage decoupling pin, capacitor to GND is required 32 VDR1 P Gate drive voltage regulator decoupling pin, capacitor to GND is required 33 BST1B P Bootstrap supply, external capacitor to OUT1B is required 34 PGND1B P Ground 35 OUT1B O Power stage PWM output 1B 36 OUT1B O Power stage PWM output 1B 37 PVDD1 P 38 PVDD1 P Power supply for PWM Power stage 1A, 1B Power supply for PWM Power stage 1A, 1B 39 PVDD1 P Power supply for PWM Power stage 1A, 1B 40 OUT1A O Power stage PWM output 1A 13 14 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 5 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 PIN NAME TYPE 41 OUT1A O Power stage PWM output 1A 42 PGND1A P Ground 43 BST1A P Bootstrap supply, external capacitor to OUT1A is required 44 /RESET I Active low to reset NTP-8230, Schmitt trigger input 45 AD I I2C device address selection 46 CLK_I I System master clock input 47 CLK_OUT O System master clock output VDD_IO P Power supply for digital interface I/O, 3.3V 48 DESCRIPTION P = Power Supply or Ground, I = Input, O = Output, I/O = Input/Output Table 1. NTP-8230 Pin Description Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 6 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 4. CHARACTERISTICS AND SPECIFICATIONS 4.1. Absolute Maximum Ratings Parameter Reference Rating Unit DGND -0.3 ~ 2.5 V GND_IO -0.3 ~ 4.4 V Logic Input voltage GND -0.3 ~ 5.5 V Logic output voltage GND -0.3 ~ 4.4 V PVDDXX voltage PGNDXX 31 V OUTXX voltage PGNDXX -0.3 ~ PVDDXX V BSTXX voltage PGNDXX 37.6 V VDRX voltage PGNDXX -0.3 ~ 6.6 V VCC5 voltage GND 0.3 ~ 5.5 V Storage Temperature Tstg -55 ~ 150 C Junction Temperature Tj 150 C HBM 2000 V MM 200 V CDM - V Reference Rating Unit VDD_IO voltage GND_IO 3.0 ~ 3.6 V PVDDXX voltage PGNDXX 7 ~ 28 V VDRX voltage PGNDXX 6.1 V VCC5 voltage GND 5.3 V Ambient Operating temperature TAMB 0~85 C Thermal resistance θJa - C/W Thermal resistance θJc - C/W - W 8 Ω DVDD voltage VDD_IO voltage ESD 4.2. Recommended Operating Conditions Parameter Power dissipation Load condition Speaker 4.3. DC Electrical Characteristics Parameter Symbol Condition Min Typ Max Unit Logic Block (VDD_IO=3.3V, TA=+25C, unless otherwise specified.) Input High Voltage Vih - 2.0 Input Low Voltage Vil -0.3 Input Current Il VDD_IO=MAX, 0V ≤ Vin ≤ 5.5V 40kΩ pull down 40kΩ pull up Output Low Voltage Vol Iol=2,4,…28mA Output High Voltage Voh Ioh=-2,-4,…-28mA 2.4 V 0.8 V 10 uA 40 160 uA -160 -40 uA 0.4 V V Output Low Current Iol Vol=0.4V, 4mA 4.7 8.0 10 mA Output High Current Ioh Voh=2.4V, 4mA 5.6 11.9 19 mA Output Current Limit Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Sourcing & Sinking - A Page 7 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier Threshold point Vt NTP-8230 - 1.09 V Input leakage current ILEAK - uA Tri-state leakage current Schmitt trig. Low to High threshold point Schmitt trig. High to Low threshold point Pull up resistance ILEAKT - uA Pull down resistance Vt+ - 1.4 2.0 V Vt- - 0.8 1.2 V RPU - KΩ RPD - KΩ 120 mΩ Power Driver Block (PVDDXX=20V, TA=+25C, unless otherwise specified.) PVDDXX=10V, without FET turn on resistance Rdson bonding VDD_IO=3.3V, No Input, ICC No Load Current consumption PVDD=24V, No Input, IPVDD 8 Ω Load with 10uH LDO output voltage VLDO Peak Current Limit Thermal Shutdown Temperature Under Voltage protection Limit OCP - OTPUVP - 35 mA 100 1.8 V 5.5 A 150 C 7 V 4.4. Performance Specification Parameter Condition Min Typ Max Unit Master volume 100 dB Channel volume - dB Gain matching - % AES17, A-weighting filter 100 dB 1W, 1kHz PVDD=24V @8Ω, THD 1% (Continuous Output power, 1 min.) Peak output power, 10msec 0.01 % 15 W 30 W PVDD=24V,Output Power=1W@ 8Ω 70 dB DC offset voltage No input - mV Output noise voltage No input - uV - mSec - % 384 KHz - dB Gain SNR THD+N POUT Cross talk Start up time Efficiency PVDD=18V, POUT=1W@ 8Ω LC filter 22uH,470nF,100nF PWM frequency PSRR VRIPPLE=200mVrms,Pout= 1W Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 8 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 4.5. Switching Characteristics – I2C Control Parameter Symbol Condition Min Max Unit I2C Control Port SCL clock frequency Fscl - 400 kHz Thdsta 600 - ns Low period of the SCL clock Tlow 1300 - ns High period of the SCL clock Thigh 600 - ns Rise time of SDA and SCL signals Trise - 300 ns Fall time of SDA and SCL signals Tfall - 300 ns Tsusto 600 - ns Hold time for START condition Setup time for STOP condition Trise Tfall SDA Tlow SCL Thdsta Thigh Tsusto 2 Figure 3. I C Mode Timing 4.6. Switching Characteristics – Audio Interface Parameters Symbol min max units BCK high time tbh 20 - ns BCK low time tbl 20 - ns SDATA setup time before BCK rising edge tds 10 - ns SDATA hold time after BCK rising edge tdh 10 - ns WCK setup time before BCK rising edge tws 20 - ns BCK rising edge before WCK edge twh 20 - ns tbl tb h BCK tw h tw s WCK tds tdh S D A TA Figure 4. Audio Interface Timing Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 9 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 5. I2C BUS OF NTP-8230 The NTP-8230 uses an industry standard Inter IC Control (I2C) bus to communicate with host IC. A host IC can write or read internal registers of the NTP-8230 via the I2C bus. 5.1. General Description of I2C Bus The I2C bus uses two signal lines – a serial clock line (SCL) and a serial data line (SDA). Because the SDA line is open-drain type port, both the NTP-8230 and a host IC can only drive these pins low or leave them open. In I2C bus, a master device means the device which generates serial clock on the SCL. A slave device means the device which receives serial clock. There can be many master and slave devices on an I2C bus. But, when one master device works on the bus, the other master devices should not generate signal on the lines. These unexpected interrupts can make other slave devices to fail to communicate with the mater device. The NTP-8230 supports only slave mode of I2C bus. So, the NTP-8230 always receives serial clock from a host IC. The slave mode is enough to write/read data to/from the NTP-8230. R Slave address SDA 0 1 0 1 0 1 MSB SCL 1 Acknowledgement signal From NTP-8230 2 3 4 5 6 0 7 Sr … W LSB 8 MSB 9 1 ACK S or Sr A … 2- 8 P LSB 9 ACK Byte complete START or Repeated START condition A Sr or P STOP or Repeated START condition Figure 5. Basic signaling elements of I2C bus If there are no communication on I2C bus, lines must keep in high state. I2C bus begins communication with the start condition and ends communication with the stop condition. The start condition can be generated by changing the SDA state high to low, during the SCL state remains in high. The stop condition can be generated by changing the SDA state low to high during the SCL remains in high state. Be aware that the stop condition always reset the internal status of I2C bus control logic. Except these two conditions, the SDA may not change during the SCL in high state. Otherwise, abnormal start or stop condition will be generated. I2C bus transfers the MSB of a byte on 1st data slot and the LSB of a byte on 8th data slot. I2C bus checks success or fail of transfer on every 1 byte transfer. The device which found an expected data on SDA must generate acknowledgement (keep low on SDA) on 9th clock. If there is no acknowledgement on 9th clock, the device which generated a data on SDA may stop transfer. The NTP-8230 will generate acknowledgement for every successful data transfer of 1 byte in write mode. But, in read mode, because data is generated by the NTP-8230, the NTP-8230 will not generate an acknowledgement. In this case, on the contrary, the NTP-8230 will check SDA state on 9th clock that the master device received a read data properly. Because there can be many other slave device on the I2C bus, the master device sends a target slave address on the 1st byte. 7 bits from 1st to 7th bit of 1st byte are used for the slave address. The NTP8230 will response with slave address 0101010 or 0101011. If the AD pin was on low state in low to high transient of the RESET pin, the NTP-8230 will use 0101010 for a slave address. Else if the AD pin was on high state in low to high transient of the RESET pin, the NTP-8230 will use 0101011 for a slave address. AD 0 1 I2C Address 0x54 0x56 Table 2. I2C Address Last 8th bit of the 1st byte is used to indicate whether the master device want to write or read data. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 10 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 5.1.1. Writing Operation When last 8th bit of the 1st byte is set to low state, the writing operation of I2C bus begins. The NTP8230 supports 3 kind of writing operations which presented on Figure 6 The type presented on Figure 6-(a) is single byte write operation. “Sub address” on 2nd byte means the internal register address of the NTP-8230. The “Data” on 3rd byte will be written into the internal register address on “Sub address”. If stop condition is not generated, writing “data” on specific “sub address” can be repeated like Figure 6-(b). “Data #n” will be written on “sub address #n”. The type presented on Figure 6-(c) is burst byte write operation under address auto increment mode. The AIF is the address Auto Increment Flag which is 1st bit of 2nd byte of I2C packet. On SDA, if AIF is set to high state, the NTP-8230 starts auto incrementing the address with respect to given “sub address” and host send write data continuously over SDA. In AIF mode, access to the register addresses 0x3B~0x49, 0x4F and 0x5E are automatically skipped. (a) S Slave address W A AIF Sub Address A Data A P Slave address W A AIF Sub Address #1 A Data #1 A AIF Slave address W A AIF Sub Address #1 A Data #1 A (b) S Sub Address #2 A Data #2 A P (c) S Data #n A P Figure 6. Single Byte Write Mode Sequence Figure 7-(a), Figure 7-(b), and Figure 7-(c) represent 4 byte writing operations. Coefficient Mode Register address 0x00~0x6B are used to configure Bi-Quad filter coefficients, Low Shelf BQ filter coefficients, Loudness gains and DRC clip down gain. The data size of these coefficients and gains is 4 byte for each. The difference between 4byte writing operation and single byte writing operation is only the size of transferring data. So, after sending “Sub address”, 4 sequential bytes must be transferred from the MSB(most significant byte) to the LSB(least significant byte) sequence. The type presented on Figure 7-(c) is quad byte write operation under address auto increment mode, AIF function. Please compare the data transfer size between Figure 6 and Figure 7. (a) S Slave address W A AIF Sub Address A Data (Byte #4) A Data (Byte #3) A Data (Byte #2) A Data (Byte #1) A P Slave address W A AIF Sub Address #1 A Data (Byte #4) A Data (Byte #3) A Data (Byte #2) A Data (Byte #1) A AIF Sub Address #n A Data #n (Byte #4) A Data #n (Byte #3) A Data #n (Byte #2) A Data #n (Byte #1) A Data (Byte #4) A Data (Byte #3) A Data (Byte #2) A Data (Byte #1) A Data #n (Byte #4) Data #n (Byte #2) A Data #n (Byte #1) (b) S A P (c) S Slave address W A AIF Sub Address A Data #n-1 (Byte #1) Data #n (Byte #3) A A P Figure 7. Quad Byte Write Mode Sequences In write operation, the register 0x7E value needs to be set first for performing the configuration of the registers belong to all channels. The 0x7E register also support to configuring byte writes operation and word i.e. 4 byte writes operation. If 0x7E register is configure to 0x00, it support byte write operation and for word i.e. 4 byte write operation for each channel it needs to configure as 0x01 for channel 1, 0x02 for channel 2, 0x04 for Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 11 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 channel 3 and 0x08 for PEQ. Also to configure channel1 and channel2 with the same values, the 0x7E register needs to configure as 0x03. So the same values get sets for both the channel with only one write operation. The register addresses from 0x00 to 0x3B and from 0x41 to 0x63 are used for the Bi-Quad filter coefficients in the coefficient mode. Each Bi-Quad filter uses 5 coefficients. Any unexpected coefficient value changes on any part of 5 coefficients can generate unstable Bi-Quad filter response. For example, if only one of 5 coefficients for a Bi-quad filter is changed and downloaded, its combined 5coefficient set can have unstable operation while old and new coefficients are mixed together. Therefore to prevent this kind of problem, the NTP-8230 writes coefficients to coefficient registers only when the last 5th coefficients of each Bi-Quad filter are downloaded, which means all of 5 coefficients are fully ready. Please refer to 9.1 for more detailed operation. 5.1.2. Reading Operation Figure 8-(a) represents single byte reading operation from the NTP-8230. To read data from the NTP8230, generate start condition to start transfer. After then, send “slave address” with write mode flag and send the register address(sub address). By regenerating start condition (Sr) again and transferring “slave address” with read mode flag, reading operation begins. The NTP-8230 will generate data on SDA signal synchronizing with serial clocks on the SCL. Because the SDA signal generated from the NTP-8230, the master device must generate ACK on 9th slot to confirm that the master received read 1 byte successfully. However, if this is just one byte reading operation, NAK (not acknowledged) signal must be generated. Then stop condition must be generated to end transfer. When AIF set to high on sub address like Figure 8-(b), data will be read continuously with register addresses which are increased from initial “sub address” for every byte. In continue reading operation, the master must generate ACK signal on every 9th bit of the packet to confirm that master has received 1 byte successfully. Otherwise, reading operation will be terminated. At the end of AIF reading operation, the NAK should be generated on 9th bit of the last data read to stop the AIF continuous reading operation. Also in reading operation access to the register mention in the “Write Operation‟ are skipped. (a) S Slave address W A AIF Sub address A Sr Slave address R A Data NAK P Slave address W A AIF Sub address A Sr Slave address R A Data A (b) S Data NAK P Figure 8. Single Byte Read Mode Sequence Figure 9 represents quad byte reading operation. The difference between quad byte reading operation and single byte reading operation is only the size of receiving data. So, after sending “Sub address”, 4 sequential bytes must be received from the MSB to the LSB sequence. The type presented on Figure 9-(b) is quad byte read operation under address auto increment mode, AIF function. Please compare the data receive size between Figure 8 and Figure 9. Before reading operation, the value of register 0x7E should be set first. In case single byte reading operation, set the register 0x7E to “0000”. In case 4 byte reading operation, set the register 0x7E to “0001” for channel1, “0010” for channel2, “0100” for channel3, or “1000” for PEQ. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 12 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 (a) S Slave address W A AIF Subaddress A Sr Slave address R A Data (Byte #4) A Data (Byte #3) A Data (Byte #2) A Slave address W A AIF Subaddress A Sr Slave address R A Data #1 (Byte #4) A Data #1 (Byte #3) A Data #1 (Byte #2) A Data #n(Byte #3) A Data #n (Byte #2) Data (Byte #1) NAK P (b) S A Data #n-1 (Byte #4) A Data #n (Byte #4) A A Data #1 (Byte #1) Data #n (Byte #1) Figure 9. Quad Byte Read Mode Sequence In read operation, the register 0x7E value needs to be set first for performing the configuration of the registers belong to all channels. The 0x7E register also support to configuring byte reads operation and word i.e. 4 byte reads operation. If 0x7E register is configure to 0x00, it support byte read operation and for word i.e. 4 byte read operation for each channel it needs to configure as 0x01 for channel 1, 0x02 for channel 2, 0x04 for channel 3 and 0x08 for PEQ. Also to configure channel1 and channel2 with the same values, the 0x7E register needs to configure as 0x03. So the same values get sets for both the channel with only one read operation. 5.1.3. I2C Glitch Filter To clean out the threats of noise in today‟s high-speed-board system, the NTP-8230 has a glitch elimination filter on the I2C ports. Glitches in the transmission lines of the I2C port can be safely removed with this function. Please refer to the register 0x3A. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 13 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 6. CLOCK, RESET & CONTROL 6.1. System Clock The internal system clock of the NTP-8230 is generated from an external master clock by the on-chip PLL. The NTP-8230 supports external master clock frequency from 2.048 MHz to 24.576MHz. For proper operation, the registers for the PLL should be set correctly according to master clock frequency (Address 0x02). 6.2. Reset Timing For proper initialization of NTP-8230, the reset signal should be low more than 0.1usec when the 3.3V I/O supply is stabilized as shown in Figure 10. 3.3V I/O supply voltage (VDD_IO) 0V ~7us 3.3V RESET 0V T1 Normal Operation Initialization T1>>0.1usec Figure 10. Reset Timing While in normal operation, if /RESET pin is set to a low state, the NTP-8230 enters the reset state to bring up the actions as follows. 1) Each control register resets to the default value. 2) All the internal registers, multipliers, adders, counters, and etc. are cleared to zero. 3) All of the output pins keep low state as long as the /RESET is active. The /RESET pin should be maintained in the low state more than 0.1usec, and it takes around 7µs to initialize the NTP-8230 after the reset pin is raised to the high state as shown in Figure 10. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 14 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 7. AUDIO INPUT 7.1. I2S and Serial Audio Interface NTP-8230 receives audio data through digital audio interface. There are 2 different formats generally used in digital audio interface - the Inter-IC Sound (I2S) Interface and General Serial Audio Interface (GSA). These two interfaces have some common features. These interfaces use 2 clock lines and 1 data line to transfer audio data. One of these clock lines is the WCK. A period of the WCK is same with sampling period of audio data. This property enables the clock receiving device to synchronize data word-wise transmitting or receiving timing with clock generating device. Another functional aspect of the WCK is indication of current channel. In I2S mode, low state of the WCK indicates 1st channel or left channel, and high state of the WCK means 2nd channel or right channel. The other clock line is BCK. This clock line is used to synchronize bit-wise timing. The number of clock for one WCK period can be selected on BCKS(Bit Clock Size Select) of register address 0x01. NTP-8230 functions as a slave on the bus. In slave mode, NTP-8230 receives WCK and BCK from external source. The data transfer is done via SDATA line. The data being synchronized with the BCK must be loaded on this line. NTP-8230 reads data on the rising edge of the BCK. NTP-8230 reads data from defined bit range of WCK period. The bit range is selected by the interface type. The bit range for I2S is predefined. GSA interface can select a bit range with LRJ, MLF and BS of register address 0x01. Please refer to in Figure 11 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 15 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 1/fs WCK (I/ O) BCK (I/ O) LE F T C H A N N E L S D A TA (I) X X 0 R IG H T C H A N N E L 1 n-1 n MSB X X X 0 1 n-1 MSB LS B X X X X 0 X X 0 n X n X LS B I2 S 1/fs WCK (I/ O ) BCK (I/ O ) LE F T C H A N N E L S D A TA (I) X 0 R IG H T C H A N N E L 1 n-1 n MSB X X 0 1 n-1 n MSB LS B LS B G S A , Left Justified , M S B first 1/fs WCK (I/ O ) BCK (I/ O ) LE F T C H A N N E L S D A TA (I) X 0 R IG H T C H A N N E L 1 n-1 n LS B X X 0 1 n-1 n LS B MSB MSB G S A , Left Justified , LS B first 1/fs WCK (I/ O ) BCK (I/ O ) LE F T C H A N N E L S D A TA (I) n X X 0 1 R IG H T C H A N N E L n-1 MSB n X X 0 1 n-1 MSB LS B LS B G S A , R ight Justified , M S B first 1/fs WCK (I/ O) BCK (I/ O) LE F T C H A N N E L S D A TA (I) n X X 0 LS B 1 R IG H T C H A N N E L n-1 n X MSB X 0 1 LS B n-1 n X MSB G S A , R ight Justified , LS B first Figure 11. Serial audio interface format Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 16 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 8. MIXER Channel mixer can be used in lots of application needs like pseudo stereo and etc. User can mix input channels into each output channels with designated gains and polarity. Step size of mixer gain is variable according to the gain level as shown below. Volume Range (dB) Step (dB) +18 ~ +6 1 +5.5 ~ -5.5 0.5 -6 ~ -32 1 ≤ 32 -∞ Table 3. Variable step mixing gain In total, 6 mixing gain coefficients denoted as M[0x03], M[0x04], M[0x05], … M[0x08] are defined as shown in the equation below. Each Mxx stores volume value in dB scale, and the number values versus gain in dB are shown in the Appendix C. There are some places in the mixing matrix that are considered as trivial connections and thus predefined as -∞ dB. [Output Channels] = [Mixer Matrix] x [Input Channels] CH1 OUT CH2 OUT CH3 OUT = M[0x03] M[0x04] M[0x05] M[0x06] M[0x07] M[0x08] . CH1 IN CH2 IN Figure 12. Mixer Matrix In order to load mixer coefficients into internal memory, send the index value in the gain value table to the register address 0x03~ 0x08. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 17 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 9. PRE-PROCESSING 9.1. Pre Bi-Quad Filter Chain NTP-8230 has two kinds of Bi-Quad filter chains. One is Pre Bi-Quad filter chain and the other is Post Bi-Quad filter chain for bass management, loudness control, loud-speaker EQ, etc. The former is called pre Bi-Quad filter chain and two 2nd order floating point Bi-Quad filters are connected serially to all the three channels. The structure is shown in Figure 13. 0 CH 1 BQ1 0 BQ2 1 1 0 CH 2 BQ1 0 BQ2 1 1 0 CH 3 BQ1 1 0 BQ2 1 Figure 13. Pre Bi-Quad Filter Structure Filter coefficients are 32-bit floating point numbers and can be downloaded thru I2C interface. To download the pre Bi-Quad filter coefficients to internal memory of NTP-8230, designer should change the flags of register Address 0x7E to „enable coefficient write‟ status. When CH1(or CH2 or CH3) Flag of register Address 0x7E is set to 1, BQ ROM Address 0x00~0x04 designates coefficients of 1st pre Bi-Quad filter chain of channel 1(or channel 2 or channel 3) and indicates b0, b1, b2, a1, a2 respectively. BQ ROM Address 0x05~0x09 designates the coefficients of 2nd chain of channel 1(channel 2 or channel 3). The Bi-Quad filter structure is shown in Figure 14. b0 x Z-1 Z-1 + b1 a1 x x b2 a2 x x Z-1 Z-1 Figure 14. Bi-Quad Filter Structure 9.2. 3D Surround 3D surround expands the sound field of two channel stereo to the extent that is wider than the actual speaker spacing. Because this feature is acoustically valid for two channel signal, no other channels except channel 1/2 have this internal block. NTP-8230 realizes the 3D effect by combining delay and band-pass filter. At first, define the size of delay by using register Address 0x0D. Possible maximum delay is 40 samples delay and this is about 0.4msec based on 96kHz signal input. And then download the band-pass filter coefficients to internal memory of NTP-8230 (same with the BiQuad filter coefficient download procedure). The BPF is two 2nd order IIR filter. Each channel can have different BPF. Change the 3D flag status of register Address 0x7E to „enable coefficient write‟ status and write the actual coefficient values to ten register Addresses 0x0A~ 0x13. Also, internal 2x2 mixer helps ease of design. For using 3D mixer, download the gain values to two register Addresses 0x3C~0x3D. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 18 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 + Ch 1 + Ch 2 2x2 Mixer BQ2 BQ1 BQ2 BQ1 Delay Figure 15. 3D Surround Structure 9.3. Configurable Graphic Equalizer NTP-8230 provides 5 band graphic equalizer and PEQ to 1/2 channel. EQ on/off can be selected by EQ flag of register Address 0x0F. The gains for each band can be controlled by writing the gain values (refer Graphic equalizer band gain table in Appendix C) to register Addresses 0x10~14 respectively. In PEQ the BQ1 ~ BQ5 can be used as programmable Bi-Quad filters. 0 BQ1 BQ2 BQ3 BQ4 BQ5 BQ1 BQ2 BQ3 BQ4 BQ5 1 1 0 Figure 16. Configurable Graphic Equalizer 9.4. Post Bi-Quad Filter Chain The post Bi-Quad filter chains of NTP-8230 can be used in various purposes - bass management, loudness control, parametric EQ, loud-speaker EQ, etc. Independent filter design for 1, 2 channels are possible and five 2nd order floating point parametric filters are linked serially. Especially for loudness control, as shown in Figure 17, last 3 filters are different from first 2 filters. Filter coefficients are 32-bit floating point numbers and can be downloaded thru I2C interface. To download post Bi-Quad filter coefficients to NTP-8230, select download channel by using CH flag in register Address 0x7E first. And then write actual coefficient values to 55 BQ ROM Addresses, from 0x14 to 0x3B for Ch1&2 Control (or 40 BQ ROM Addresses, from 0x0A to 0x18 for Ch3 control). BQ ROM Address 0x14~0x18 designates 1st chain coefficients and means b0, b1, b2, a1, a2 in sequence. Address 0x19~0x1D designates 2nd chain, and so on. The enable/disable operation of these Bi-Quads can be made by using BQF flag in register Addresses 0x17~0x1B(include Ch3 control). (refer register Address table in Appendix A and refer BQ ROM Address table in Appendix B) Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 19 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Figure 17. Post Bi-Quad Filter Structure For the enhancement of 3D effect or redirection of Bass signal back into Main channel, Ch3 fire back structure is integrated like Figure 17. 9.5. Loudness Control NTP-8230 provides loudness control function using post Bi-Quad filter chains. Loudness control means the compensation of frequency characteristics in low volume level to fit the acoustic characteristics of human ears There are 3 Bi-Quad filters for loudness gain per each channel. To download a loudness gain of each Bi-Quad, the page flag register 0x7E should be set as same in the case of downloading the filter coefficients. The loudness gain values are applied for both channel 1 and 2 and when downloading the loudness gain values, a user should set the register 0x7E as 0x03. loudness gains of CH1/CH2 register Address 0x7E= 0x03 case loudness gains of CH3 register Address 0x7E= 0x04 case BQ ROM Address 0x3E 0x3F 0x40 L1 L2 L3 BQ ROM Address 0x1E 0x1F 0x20 L1 L2 L3 Table 4. Address for Loudness Gain Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 20 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 10. VOLUME & DYNAMIC RANGE CONTROL Master and channel volumes of the NTP-8230 are independently controlled and softly changed. The system register address 0x2E is the master volume control that affects 3 channels simultaneously and the address 0x2F, 0x30 and 0x31 correspond to the channel volume control register for channel 1, 2 and 3 respectively. The possible Maximum Gain is +48.375dB with using master volume fine control, master volume and channel volume because the master volume applies the gain to an input signal independent from a channel volume. However, in such a case, a clipping might occur to prevent a signal overflow error if the magnitude of the input signal is large enough to exceed 0dB under the combined volume setting. 10.1. Master Volume Control By setting volume control register (address 0x2E), master volume is controlled from negative infinity through 24dB with selectable step size as follows. For details on the master volume setting, see the register value table shown in Appendix C. Step Range 0.5 dB +24 ~ -100 dB 10 dB -100 ~ -150 dB Table 5. Level dependent master volume steps 10.2. Channel Volume Control By setting volume control registers (address 0x2F~0x31), channel volumes are independently controlled from negative infinity through +24dB with two selectable step sizes as described below, and in the Appendix C, exact values for channel volume setting are described. Step Range 0.5 dB +24 ~ -100 dB 10 dB -100 ~ -150 dB Table 6. Level dependent Channel volume steps 10.3. Master Volume Fine Control Fine control for master volume is possible (+0.0625dB step up to maximum +0.4375dB boost). Refer the system register Address 0x2D in the Appendix A. 10.4. Mute and Soft Volume Change The NTP-8230 enters mute state by setting soft mute flag of register Address 0x26. Soft mute is implemented so that the volume gradually increases or decreases when mute is turned off or on respectively. Also the soft mute speed and soft volume change speed rates are programmable. Designers can minimize the pop noise by controlling the soft mute speed and volume change intervals. Refer SMH flag of register Address 0x26 and SVI flag of register Address 0x32. 10.5. Auto Mute The NTP-8230 can mute the sound automatically when the level of input audio signal is lower than the register-controlled threshold value. The mute can be done by soft mute or PWM switching with 50 % duty ratio or PWM switching off. Auto mute is supported for internal channels 1~3 after 2x3 mixer block. Refer register Address 0x33 and 0x34. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 21 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 10.6. Dynamic Range Control Dynamic range control can be turned on or off with programmable compression threshold and attack/release rates. The threshold parameters of DRC can be controlled separately for channel 1/2 and channel 3. For detailed setting, please refer to the system register Addresses 0x1C~0x25 and refer to the BQ ROM addresses in Table 7. HPF H-DRC + LPF L-DRC Figure 18. Block diagram of dynamic range control. 2B‟ DRC BQ ROM Address 0x46 ~ 0x4A 0x4B ~ 0x4F 0x50 ~ 0x54 0x55 ~ 0x59 0x5A ~ 0x5E 0x5F ~ 0x63 Register Address 0x7E = 0x03 BQ1 BQ2 BQ3 BQ4 Attack Low Attack High 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B Release Gain Low Release Gain High THD Gain Low THD Gain High PowerMeter Gain Attack Gain Low Attack Gain High Attack Gain Post Table 7. BQ ROM address map for dynamic range control Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 22 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 11. OUTPUT INTERFACE 11.1. Output Configuration The output mode of NTP-8230 is 2.0 stereo reproduction mode and 2.1 reproduction mode. To produce proper output signal, register 0x35~0x37 should be set to appropriate values. 11.2. AM Interference Relief Mode The NTP-8230 has AM interference reduction mode. In this mode SNR performance of NTP-8230 can be degrade down to 90 dB and the PWM switching frequency is spread from 384kHz through 768kHz. 11.3. PWM Output Mapper Any internal channel that produces a PWM output can be assigned to any PWM output hardware port (or pin) by mapping output port register. This feature is very helpful for the hardware designer because it can relieve difficulties in the power stage signal routing and channel assignment if the output channel order is fixed. See the system register address 0x35~0x37 in the Appendix A. 11.4. Switching Output Mode There are two selectable switching output modes in NTP-8230. The difference between two output modes lies in the relationship of the relative signal pattern between PWM OUTxA and PWM OUTxB for a channel x. The first one is called as AD mode. This AD mode can be applied to both half bridge and full bridge output stage. Output A Output B Figure 19. PWM Output Signals in AD Mode AD asynchronous pair means the normal AD mode PWM output. In other words, A output and B output of each PWM output pair are mutually complementary. In the case of AD synchronous pair, A output and B output is perfectly identical, and its relation is not complementary. This is useful in some special case including single-ended power stage design. The other one is called as NTX (Neo Trinity Amplification), which is D-BTL mode. This mode is applied only for BTL, and its operation is dynamically-biased BTL, compared to the normal BTL. An example of output signals in D-BTL mode is shown in Figure 20 Output A Output B Figure 20. PWM Output Signals in D-BTL mode Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 23 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 For D-BTL mode, there are two additional parameters, which are MLP (Minimum Linear Pulse Length) and MPC (Maximum Pulse Length to Compensate). MLP defines the minimum pulse length that can guarantee a linear relationship between the input and output pulse length. Generally, the width of the output pulse is proportional to that of the input pulse. However, as the width of input pulse becomes narrower, such linear relation is not maintained due to the characteristic of a power device. The minimum MLP value is preferred as long as linear relationship between the input and the output pulse is satisfied. In addition, in terms of power consumption, a minimal MLP value is preferred. MPC determines the width of compensation pulse. In other words, since a short-length pulse tends to have non-linear relationship between input and output, an input pulse which has the equal or less length of MPC is counterbalanced using compensation pulse. Whereas, an input pulse which exceeds the length of MPC has no compensation. This compensation is illustrated in Figure 21, when the input data is equal or less than the MPC width. Data+MLP Output A Output B Data MLP Figure 21. Compensation by MPC and MLP 11.5. Soft start The soft_start reduces pop noise by controlling rapidly increased energy of PWM. To begin soft_start operation, PWM soft start enable register (0x52: PSE) should be set to high, and then PWM switching on/off register (0x27: POF) should be set to low. The duty ratio of PWM output increases from 127:1 (Low:High) to 50:50 (Low:High). Step repeat time register (0x52: SRT) means repeat number of PWM output. Soft_start operation with 17 repetitions is shown in the Figure 22. HIGH PSE LOW HIGH POF LOW 44.48us HIGH pwm_a LOW 384kHz (2.6μs) HIGH LOW pwm_b HIGH 180˚ LOW 17 17 1 20.3ns 127 (2.58us) 2 40.6ns 126 (2.56us) Figure 22. Soft start operation timing Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 24 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 12. TYPICAL APPLICATION SCHEMATICS (2CH Stereo) Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 25 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 13.TYPICAL APPLICATION SCHEMATICS (2.1 Channel) Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 26 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 14. APPENDIX A. Configuration Register Summary Addr 0x00: Audio Input Format Bit Name 7 X 6 X Name INS Description Input format FSM Sampling Frequency in Master mode IIS 5 X 4 FSM 3 2 1 INS Value b’00 b‟01 b‟10 b‟11 b‟000 b‟001 b‟010 b‟011 b‟100 b‟101 b‟110 b‟111 Meaning 2 I S, slave mode 2 I S, master mode General serial audio, slave mode General serial audio, master mode 48 kHz 8 kHz 16 kHz 32 kHz 12 kHz 24 kHz 96 kHz 192 kHz 0 Ref. Addr 0x01: General Serial Audio Format Bit Name 7 X 6 X Name LRJ Description Serial data justify MLF Serial bit order BS Serial bit size BCKS Bit clock size select 5 BCKS 4 3 BS Value b’0 b‟1 b’0 b‟1 b’00 b‟01 b‟10 b‟11 b’00 b‟01 b‟10 Meaning Left justify Right justify MSB first LSB first 24 bit 20 bit 18 bit 16 bit 64 BCK/WCK 48 BCK/WCK 32 BCK/WCK 2 1 MLF 0 LRJ Ref. Addr 0x02: Master Clock Frequency Control Bit Name 7 X 6 X Name MCF Description Master Clock Frequency Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 X 4 X 3 X 2 X 1 MCF 0 Value b’00 b‟01 b‟10 b‟11 Meaning 12.288 MHz 24.576 MHz 18.432 MHz User defined frequency. Required to set address 0x63 and address 0x64 first Ref. Page 27 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x03~0x08: Mixer Gain Bit Name 7 X 6 MG Name MG Description Mixer gain 5 4 3 2 Value b‟0000000 ~ b‟1111111 Meaning Mixer gain (refer to gain table) 1 0 Ref. Reserved addr 0x09~0x0B Addr 0x0C : Front Bi-quad Filter Chain (FBQ) Configurations for Ch 1&2&3 Bit Name 7 X 6 X 5 FBQ32 Name FBQ11 Description st 1 FBQ flag for CH1 FBQ12 2nd FBQ flag for CH1 FBQ21 1 FBQ flag for CH2 FBQ22 2nd FBQ flag for CH2 FBQ31 1 FBQ flag for CH3 FBQ32 2nd FBQ flag for CH3 4 FBQ31 3 FBQ22 Value b’0 b„1 b’0 b„1 b’0 b„1 b’0 b„1 b’0 b„1 b’0 b„1 st st 2 FBQ21 1 FBQ12 Meaning Bypass Enable Bypass Enable Bypass Enable Bypass Enable Bypass Enable Bypass Enable 0 FBQ11 Ref. Addr 0x0D: 3D delay amount Bit Name 7 X 6 X 5 4 3D_Delay Name Description 3D_Delay 3D_Delay Value b’000001 3 2 1 Meaning 0 ~ 40 (unsigned decimal) 0 Ref. Addr 0x0E: 3D effect control configuration Bit Name 7 X 6 X Name 3DEN Description 3D Bypass Flag 5 X 4 X 3 X Value b’0 b„1 Meaning 3D off 3D on 2 X 1 X 0 3DEN Ref. Addr 0x0F : Equalizer (EQ) Configuration Bit Name 7 X 6 X 5 X Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 4 X 3 X 2 X 1 EQ 0 Page 28 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier Name EQ Description Graphic equalizer configuration Value b’00 b„01 b„11 NTP-8230 Meaning Bypass 5-band graphic equalizer (GEQ) mode (0x10~0x14 let GEQ choose preset BQ coeffs) Programmable Graphic Equalizer (PEQ) 5 biquad chain is programmed for applicationspecific equalizer (refer to 0x7E register to program) Ref. Addr 0x10~0x14: GEQ Gain for Band 1 ~ 5 Bit Name 7 X Name BG Description Band Gain Name BG 6 X Address 0x10 0x11 0x12 0x13 0x14 Band BQ1 BQ2 BQ3 BQ4 BQ5 5 X 4 BG Value Meaning See register value table. Default b‟00000 b‟00000 b‟00000 b‟00000 b‟00000 3 2 1 0 Ref. GEQ Default Frequency 100Hz 300Hz 1kHz 3kHz 10kHz Ref. Addr 0x15: CH1&CH2 Prescaler Value Configuration Bit Name 7 PS 6 Name PS Description Prescaler 5 4 3 Value b‟0000000 ~ b‟11111111 Meaning 208 (0xD0)default 2 1 0 Ref. Addr 0x16: CH3 Prescaler Value Configuration Bit Name 7 PS 6 Name PS Description Prescaler 5 4 3 Value b‟0000000 ~ b‟11111111 Meaning 208 (0xD0)default 2 1 0 Ref. Addr 0x17~0x18: Post Biquad Filter (PBQ) Configuration0 for Ch 1 and Ch2, respectively Bit Name 7 X 6 X Name BQ1 Description On/off Bi-Quad 1 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 X 4 BQ5 3 BQ4 2 BQ3 Value b’0 Meaning Bypass Bi-Quad 1 of channel n 1 BQ2 0 BQ1 Ref. Page 29 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier BQ2 BQ3 BQ4 BQ5 of ch. n (n= 1,2) On/off Bi-Quad 2 of ch. n (n= 1,2) On/off Bi-Quad 3 of ch. n (n = 1,2) On/off Bi-Quad 4 of ch. n (n = 1,2) On/off Bi-Quad 5 of ch. n (n = 1,2) b‟1 b’0 b‟1 b’0 b‟1 b’0 b‟1 b’0 b‟1 NTP-8230 Enable Bi-Quad 1 of channel n Bypass Bi-Quad 2 of channel n Enable Bi-Quad 2 of channel n Bypass Bi-Quad 3 of channel n Enable Bi-Quad 3 of channel n Bypass Bi-Quad 4 of channel n Enable Bi-Quad 4 of channel n Bypass Bi-Quad 5 of channel n Enable Bi-Quad 5 of channel n Addr 0x19~0x1A : Post Biquad Filter (PBQ) Configuration1 for Ch 1 and Ch 2, respectively Bit Name 7 X 6 X Name BQ6 Description On/off Bi-Quad 6 of ch. n (n = 1,2) BQ7 On/off Bi-Quad 7 of ch. n (n = 1,2) BQ8 On/off Bi-Quad 8 of ch. n (n = 1,2) 5 BQ8 4 3 BQ7 2 1 BQ6 Value b’00 b‟01 b‟10 b’00 b‟01 b‟10 b’00 b‟01 b‟10 Meaning Bypass Bi-Quad 6 of channel n Enable Bi-Quad 6 of channel n Enable Bi-Quad 6 as Loudness Filter Bypass Bi-Quad 7 of channel n Enable Bi-Quad 7 of channel n Enable Bi-Quad 7 as Loudness Filter Bypass Bi-Quad 8 of channel n Enable Bi-Quad 8 of channel n Enable Bi-Quad 8 as Loudness Filter 0 Ref. Addr 0x1B : Post Biquad Filter (PBQ) Configuration for Ch 3 Bit Name 7 X 6 X Name BQ1 Description On/off Bi-Quad 1 of ch 3 BQ2 On/off Bi-Quad 2 of ch 3 BQ3 On/off Bi-Quad 3 of ch 3 5 BQ3 4 3 BQ2 2 1 BQ1 Value b’00 b‟01 b‟10 b’00 b‟01 b‟10 b’00 b‟01 b‟10 Meaning Bypass Bi-Quad 1 of channel n Enable Bi-Quad 1 of channel n Enable Bi-Quad 1 as Loudness Filter Bypass Bi-Quad 2 of channel n Enable Bi-Quad 2 of channel n Enable Bi-Quad 2 as Loudness Filter Bypass Bi-Quad 3 of channel n Enable Bi-Quad 3 of channel n Enable Bi-Quad 3 as Loudness Filter 0 Ref. Addr 0x1C: DRC Control 0 Bit Name 7 CPR_L Name CTS_L CPR_L 6 CTS_L 5 4 Description DRC threshold for low band Value b’0000000 ~ b‟1111111 DRC enable for b’0 Meaning -57 ~ 12dB unsigned 7-bit DRC threshold for 1 band mode. In 2 band mode, it will control the threshold of low band. Refer to DRC threshold value table for threshold values. Dynamic Range Compression off Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 3 2 1 0 Ref. Page 30 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier b‟1 low band NTP-8230 Dynamic Range Compression on Addr 0x1D : DRC Control 1 Bit Name 7 X 6 C1C_L Name A1C_L Description DRC attack time (low band) C1C_L DRC release time (low band) 5 4 3 X 2 A1C_L 1 0 Value Meaning b‟000 ~ Attack time control for 1 band mode. b‟111 In 2 band mode, it will control the attack time of low band. (See attack time table below.) (default = b’001) b’000 ~ Release time control for 1 band mode. b‟111 In 2 band mode, it will control the release time of low band. (See release time table below.) Ref. Attack time 6dB, fs = 96,000 011 30 msec 010 15 msec 001 8 msec 000 4 msec 111 2 msec 110 1 msec 101 0.5 msec 100 0.25 msec Table 8. DRC Attack Time Table Release time Value of Register 6dB, fs = 96,000 011 5.0 sec 010 2.0 sec 001 1.0 sec 000 0.5 sec 111 0.2 sec 110 0.1 sec 101 0.05sec 100 0.025sec Table 9. DRC Release Time Table Value of Register Addr 0x1E : DRC Control 2 Bit Name 7 CPR_H Name CTS_H CPR_H 6 CTS_H 5 4 Description DRC threshold for high band Value b’0000000 ~ b‟1111111 DRC enable for high band b’0 b‟1 Meaning -57 ~ 12dB unsigned 7-bit DRC threshold for high band. It has effect only in 2 band mode. Refer to DRC threshold value table for threshold values. Dynamic Range Compression off Dynamic Range Compression on Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 3 2 1 0 Ref. Page 31 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x1F : DRC Control3 Bit Name 7 X 6 C1C_H Name A1C_H Description DRC attack time (high band) C1C_H DRC release time (high band) 5 4 3 X 2 A1C_H 1 0 Value Meaning b‟000 ~ Attack time control for high band mode. b‟111 It has effect only in 2 band mode. (default = b’001) (See attack time table in Addr 0x1D.) b’000 ~ Release time control for high band mode. b‟111 It has effect only in 2 band mode. (See release time table in Addr 0x1D.) Ref. Addr 0x20 : DRC Control 4 Bit Name 7 CPR_SW 6 5 CTS_SW 4 3 2 1 0 Name CTS_SW Description DRC threshold Value b’0000000 ~ b‟1111111 Meaning Sub-woofer uses 1-band DRC -57 ~ 12dB unsigned 7-bit DRC threshold When ch1 and ch2 is working in 2band mode, this will be effective. CPR_SW DRC enable for high band b’0 b‟1 Dynamic Range Compression off Dynamic Range Compression on Ref. Addr 0x21: DRC Control 5 Bit Name 7 X 6 5 C1C_SW Name A1C_SW Description DRC attack time C1C_SW DRC release time 4 3 X 2 1 A1C_SW 0 Value Meaning b‟000 ~ Attack time control for sub-woofer. (default = b’001) b‟111 When ch1 and ch2 is in 2band mode, it will be effective. (See attack time table in Addr 0x1D.) b’000 ~ Release time control for sub-woofer. b‟111 When ch1 and ch2 is in 2band mode, it will be effective. (See release time table in Addr 0x1D.) Ref. Addr 0x22 : DRC Control 6 Bit Name 7 CPR_P 6 CTS_P Name CTS_P Description DRC threshold for post- band CPR_P DRC enable for post-band Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 4 3 2 1 0 Value b’0000000 ~ b‟1111111 b’0 b‟1 Meaning -57 ~ 12dB unsigned 7-bit DRC threshold Refer to DRC threshold value table. Ref. Dynamic Range Compression off Dynamic Range Compression on Page 32 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x23: DRC Control 7 Bit Name 7 X Name A1C_P Description DRC attack time (post-DRC) DRC release time (post-DRC) C1C_P 6 C1C_P 5 4 3 X 2 A1C_P 1 0 Value b‟000 ~ b‟111 b‟000 ~ b‟111 Meaning Attack time (default = b’001) 5 X 4 DLL Value b‟00000~ b’10100 Meaning Delay line length. 0~20(decimal) 5 DTS2 4 2BM Ref. b’0 b‟1 b’0 b‟1 b’0 b‟1 b’0 b‟1 Meaning Enable coupled allpass structure Disable coupled allpass structure Uses Threshold parameters in Table Uses Threshold parameters from external loading Uses Release parameters in Table Uses Release parameters from external loading Uses Attack parameters in Table Uses Attack parameters from external loading 1 band DRC 2 band DRC P-DRC new mode P-DRC old mode LH-DRC new mode LH-DRC old mode Clip on Clip off 5 X 4 X 0 SM1 Value b‟0 b’1 b’0 b‟1 Meaning increase for channel n decrease for channel n 42/46 msec(at 96/88.2kHz)) Hard change Ref. Release time (default = b’100) Addr 0x24 : DRC Control 8 Bit Name 7 X 6 X Name DLL Description Delay line length 3 2 1 0 Ref. Addr 0x25 : DRC Control 9 Bit Name 7 CCO Name CAS Description Coupled Allpass Structure enable Threshold parameter select bit Value b’0 b‟1 b’0 b‟1 RSB Release parameter select bit b’0 b‟1 ASB Attack parameter b’0 select bit b‟1 2BM 2band mode enable DTS2 P-DRC type select DTS1 LH-DRC type select CCO Clip control option TSB 6 DTS1 3 ASB 2 RSB 1 TSB 0 CAS Addr 0x26 : Soft mute Control 0 Bit Name 7 SMH 6 X Name SMn Description Softmute SMH Softmute speed Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 3 X 2 SM3 1 SM2 Ref. Page 33 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x27 : PWM Switching On/Off Control Bit Name 7 X 6 X Name POFn Description Switching output On/off control 5 X 4 X 3 X 2 POF3 Value b‟0 b’1 Meaning Channel n PWM switching on Channel n PWM switching off 1 POF2 0 POF1 Ref. Addr 0x28 : PWM_MASK Control 0 Bit Name 7 X Name PWMM Description PWM MASK register Permanent PWM_MASK Low disable flag FAULT disable FPMLD SRD 6 X 5 X 4 X 3 SRD 2 FPMLD 1 PWMM 0 Value b’10 otherwise b’0 b‟1 Ref. b’0 b‟1 Meaning PWM MASK output is low. (reset default) PWM MASK output is high. No effect Reset the auto_PWM_MASK_restore_counter to 0 FAULT is effect for PROTECT FAULT is ineffective for PROTECT 5 X 4 X 0 POF Value b’0 Meaning Even if Auto PWM_MASK condition is met, the PWM output of all channel is not affected. When Auto PWM_MASK condition is met, the PWM output of all channel goes to the defined state which is set by the PWM off state control register (Addr 0x1E). Even if Auto PWM_MASK condition is met, the PWM_MASK output of all channel is not affected. When Auto PWM_MASK condition is met, the PWM_MASK output goes to Low state. Ref. 5 VMSK1 4 VMSK0 0 PMSK0 Meaning Ref. Mask bit indicating the validity of n-th bit of Addr 0x5E system register: If the n-th bit of this register is zero, the n-th bit of Addr 0x5E system register is invalid. The n-th bit of Addr 0x5E is valid only when the n-th mask bit is one. Addr 0x29: PWM_MASK Control 1 Bit Name 7 X 6 X Name POF Description PWM off flag b‟1 APM PWM_MASK flag b’0 b‟1 3 X 2 X 1 APM Addr 0x2A : PWM_MASK Control 2 Bit Name 7 VMSK3 Name PMSK Description Masking bit of PWM off control Value b’0 Masking bit of PWM_MASK signal b’0 VMSK 6 VMSK2 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 b‟1 b‟1 3 PMSK3 2 PMSK2 1 PMSK1 Page 34 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x2B : PWM_MASK Control 3 Bit Name 7 IRC 6 Name PHT Description PWM_MASK Low Hold Time AVRCT Auto PWM_MASK Restore Counter Threshold IRC Auto PWM_MASK Restore Interval Ratio Control 5 AVRCT 4 3 2 PHT Value b‟000 b‟001 b‟010 b’011 b‟100 b‟101 b‟000 b’001 b‟010 b‟011 b‟100 b‟101 b‟110 b‟111 b’00 b‟01 Meaning 0.5 msec Hold Time 1 msec Hold Time 2 msec Hold Time 4 msec Hold Time (Default) 8 msec Hold Time 16msec Hold Time 4 10 (Default) 20 30 40 50 60 Infinity 2 (Default) 4 5 X 4 X Value b‟000 b‟001 b‟010 b’011 b‟100 b‟101 b‟110 b‟0 b’1 Meaning 100 msec Hold Time 200 msec Hold Time 400 msec Hold Time 600 msec Hold Time (Default) 800 msec Hold Time 1 sec Hold Time 2 sec Hold Time Disable Enable (Default) b’0 b‟1 Disable (Default) Enable 1 0 Ref. Addr 0x2C: PWM_MASK Control 4 Bit Name 7 SHE Name HT2 Description Hold Time 2 apply start point (restore counter) POE PWM off when Fault detected and PWM on when PWM_MASK Recover Second Hold time Enable SHE 6 POE 3 X 2 HT2 1 0 Ref. Addr 0x2D: Master Volume Fine Control Bit Name 7 X 6 X Name MVFC Description Master volume fine control Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 X 4 X 3 X 2 MVFC 1 Value b’000 ~ b‟111 Meaning 0 dB ~ 0.5 dB with 0.0625 dB step 0 Ref. Page 35 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x2E~0x31: Master Volume, and Ch1/2/3 volume, respectively Bit Name 7 VOL 6 Name VOL Description Volume control 5 4 3 2 1 0 Value b‟00000000 ~ b‟11111111 Meaning Ref. See volume control register tables. Reset default is 0 (0x00) ( = − dB)for Master and 207 (0xCF) for Channel Addr 0x32: Soft Volume Control Bit Name 7 X 6 X Name SVI Description Soft volume change 5 X 4 X 3 X 2 X Value b’00 b‟01 b‟10 b‟11 Meaning Medium speed High speed Low speed soft volume change disable 1 SVI 0 Ref. Addr 0x33: Auto-mute Control for CH1 & CH2 Bit Name 7 X Name Description Auto-mute detection threshold Auto-mute response time AT II EAMC 6 EAMC Effect of Auto-mute condition 5 II 4 Value b’0000 ~ b‟1111 b’00 b‟01 b‟10 b‟11 b’0 b‟1 Meaning 3 AT 2 1 0 Ref. Unsigned integer between 0 and 15 5 msec 50 msec 500 msec 2 sec Auto mute disable(No-Effect) Continue switching if auto-mute Addr 0x34: Auto-mute Control for CH3 Bit Name 7 X Name Description Auto-mute detection threshold Auto-mute response time AT II EAMC 6 EAMC Effect of Auto-mute condition Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 II 4 Value b’0000 ~ b‟1111 b’00 b‟01 b‟10 b‟11 b’0 b‟1 Meaning 3 AT 2 1 0 Ref. Unsigned integer between 0 and 15 5 msec 50 msec 500 msec 2 sec Auto mute disable(No-Effect) Continue switching if auto-mute Page 36 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x35 : PWM output port Control for PWM port 1A & 1B Bit Name 7 X 6 X Name OPM1A Description Select source channel for PWM output port 1A OPM1B Select source channel for PWM output port 1B 5 OPM1B 4 3 2 OPM1A 1 Value 000 001 010 011 100 101 000 001 010 011 100 101 Meaning PWM1A is connected to PWM port 1A PWM1B is connected to PWM port 1A PWM2A is connected to PWM port 1A PWM2B is connected to PWM port 1A PWM3A is connected to PWM port 1A PWM3B is connected to PWM port 1A PWM1A is connected to PWM port 1B PWM1B is connected to PWM port 1B PWM2A is connected to PWM port 1B PWM2B is connected to PWM port 1B PWM3A is connected to PWM port 1B PWM3B is connected to PWM port 1B 0 Ref. Addr 0x36 : PWM output port Control for PWM port 2A & 2B Bit Name 7 X 6 X Name OPM2A Description Select source channel for PWM output port 2A OPM2B Select source channel for PWM output port 2B 5 OPM2B 4 3 2 OPM2A 1 Value 000 001 010 011 100 101 000 001 010 011 100 101 Meaning PWM1A is connected to PWM port 2A PWM1B is connected to PWM port 2A PWM2A is connected to PWM port 2A PWM2B is connected to PWM port 2A PWM3A is connected to PWM port 2A PWM3B is connected to PWM port 2A PWM1A is connected to PWM port 2B PWM1B is connected to PWM port 2B PWM2A is connected to PWM port 2B PWM2B is connected to PWM port 2B PWM3A is connected to PWM port 2B PWM3B is connected to PWM port 2B 0 Ref. Addr 0x37 : PWM output port Control for PWM port 3A & 3B Bit Name 7 X 6 X Name OPM3A Description Select source channel for PWM output port 3A OPM3B Select source channel for PWM output port 3B Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 OPM3B 4 3 2 OPM3A 1 Value 000 001 010 011 100 101 000 001 010 011 Meaning PWM1A is connected to PWM port 3A PWM1B is connected to PWM port 3A PWM2A is connected to PWM port 3A PWM2B is connected to PWM port 3A PWM3A is connected to PWM port 3A PWM3B is connected to PWM port 3A PWM1A is connected to PWM port 3B PWM1B is connected to PWM port 3B PWM2A is connected to PWM port 3B PWM2B is connected to PWM port 3B 0 Ref. Page 37 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier 100 101 NTP-8230 PWM3A is connected to PWM port 3B PWM3B is connected to PWM port 3B Addr 0x38: Miscellaneous PWM Control Bit Name 7 X Name MD Description PWM output mode AHL A-out state When switching off B-out state when switching off Ch3 polarity Control BHL POL 6 X 5 X 4 POL 3 BHL 2 AHL 1 MD Value b’00 b‟01 b‟10 b‟11 b’0 b‟1 b’0 b‟1 b’0 b‟1 Meaning AD mode with asynchronous signal pair AD mode with synchronous signal pair PWM D-BTL MODE (see 0x4E) AM Interference mode Low High Low High Normal Inverse 0 Ref. Addr 0x39: I2C Glitch filter Bit Name 7 GFO 6 DUR Name DUR Description glitch width GFO Glitch filter enable/disable 5 4 3 2 1 0 Value b‟0000000 ~ b‟1111111 b’0 b‟1 Meaning minimum pulse width = DUR + 20 ns reset default = 15 * 10 ns (DUR default = b’0001111) Glitch filter on Bypass Ref. Addr 0x3A : Headphone Mute Control Bit Name 7 X 6 X Name Description HP_MUTE Use this register to mute external headphone 5 X 4 X Value b’0 Meaning Default. External headphone is muted by active low signal External headphone is muted by active high signal. b‟1 3 X 2 X 1 X 0 HP_MUTE Ref. Reserved addr 0x3B~0x49 Addr 0x4A : SE Soft Start Control 0 Bit Name 7 X 6 X Name SSE Description SE_STE Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 X 4 X 3 X 2 X 1 X Value b’0 b‟1 Meaning SE Soft Start Disable (SE Normal Start) SE Soft Start Enable 0 SSE Ref. Page 38 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x4B : SE Soft Start Control 1 Bit Name 7 X 6 SSC Name SSC Description SE_CHARGE_TIME 5 4 3 2 1 0 Value 0x00~ 0x7F Meaning PWM output delay time from point of PWM STBY signal to high. The unit of 1bit is 10ns. (default : 0x22) Ref. 5 4 0 Value 0x01 ~ 0xFF Meaning The repeat time of se soft start (default: 1 – means repeat 1 times) Addr 0x4C : SE Soft Start Control 2 Bit Name 7 SSR 6 Name SSR Description SE_ REAPEAT 3 2 1 Ref. Addr 0x4D : SE Soft Start Control 3 Bit Name 7 Name SPD 6 5 Description SE_PERIOD 4 SPD Value 0x01 ~ 0x7E 3 2 1 0 Meaning Half period of PWM output start point. The unit of 1bit is 10ns. (default : 0x01 – means half period 20ns) Ref. Addr 0x4E : PWM D-BTL MODE Control 0 Bit Name 7 X 6 MLP Name MLP Description Minimum Linear pulse length 5 4 3 2 Value b’0001000 Meaning Unsigned 0~127 1 0 Ref. Reserved addr 0x4F Addr 0x50 : PWM D-BTL Mode Control 1 Bit Name Name NSS 7 6 5 4 3 2 X Description NS Select Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 1 0 NSS Value b’00 b‟01 b‟10 b„11 Meaning 7bits NS (AD mode) Reserved 8bits NS New 8bits NS (D-BTL mode) Ref. Page 39 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Addr 0x51 : PWM Phase Control Bit Name 7 PPC Name PFC Description PWM phase Fine Control PWM Phase Control PPC 6 5 4 3 PFC Value b’0000 ~ b‟1001 b‟0000 ~ b‟1100 Meaning PPC level 1.66° step 5 4 2 1 0 Ref. In Single ended mode, fixed as PFC = b‟0000, and PPC = b‟ 0110 (90°) b‟0000 (0°) ~ b‟1100(180°), width:15° default : b’0110 Addr 0x52 : PWM Soft start Bit Name 7 PSE Name SRT Description Step Repeat Time PSE 6 SRT Value b‟000000 ~ b‟111111 BTL PWM soft start b‟0 Enable b’1 3 2 1 Meaning The repeat time of each step (default : b’0010000 – means repeat 17 times) Disable Enable (Default) 0 Ref. In Single Ended Mode, should be disabled Addr 0x53: Power Meter Control Bit Name 7 X 6 X Name PDCH Description Power meter Detect Channel PDPOS Power meter Detect Position 5 X Value 00 01 10 11 0 1 4 PDPOS 3 X 2 X 1 0 PDCH Meaning L+R (default) L channel R channel reserved After volume (default) Before volume Ref. Addr 0x54: Power Meter (read-only) Bit Name 7 0 6 0 5 0 4 0 3 0 2 0 1 0 3 MD3 2 1 MD12 0 0 Addr 0x55: Modulation Index & NS-Type Control Bit Name 7 X 6 M0 Name MD12 Description Modulation index Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 4 NT Value b’11 Meaning Minimum pulse width = 2 0 Ref. Page 40 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier MD3 NT M0 control by Minimum pulse width for Ch 1&2 Modulation index control by Minimum pulse width for Ch 3 Noise shaping Type for Ch 1&2 Dither Position Selector b‟10 b‟01 b‟00 b’11 b‟10 b‟01 b‟00 b’0 b‟1 b’00 b‟01 b‟10 b‟11 NTP-8230 Minimum pulse width = 4 Minimum pulse width = 6 Minimum pulse width = 8 Minimum pulse width = 2 Minimum pulse width = 4 Minimum pulse width = 6 Minimum pulse width = 8 Type 1 (fourth order) Type 2 (fifth order) No left shift on dither value = Dither off 1bit left shift on dither value 2bit left shift on dither value 3bit left shift on dither value Reserved addr 0x56~0x5D Addr 0x5E: System Error Status (Read-only) Bit Name 7 FSI Name PPM Description Permanent PWM_MASK Indication flag Sampled PLL Unlock error SRC lock status ULCK LSRC MPW FSI 6 MCK/WCK Ratio error Sampling Frequency Information 5 4 Value b‟0 b‟1 Meaning b‟0 b‟1 b‟0 b‟1 b‟0 b‟1 b‟0000 b‟0001 b‟0010 b‟0011 b‟0100 b‟0101 b‟0110 b‟0111 b‟1000 b‟1001 b‟1010 b‟1011 3 MPW 2 LSRC 1 ULCK 0 PPM Ref. Indicated that PWM_MASK is in Permanent LOW state PLL is locked state. PLL is unlocked state. SRC is unlocked state. SRC is locked state Ratio is incorrect. Ratio is correct. 8 kHz 11.025 KHz 12 kHz 16 kHz 22.025kHz 24 kHz 32 kHz 44.1 kHz 48 kHz 88.2 kHz 96 kHz 192 kHz Reserved addr 0x5F~0x60 Addr 0x61: I2S Glitch filter Bit Name 7 GFE 6 WTH Name Description Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 5 4 Value Meaning 3 2 1 0 Ref. Page 41 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier WTH glitch width GFE Glitch filter enable/disable b‟0000000 ~ b‟1111111 b‟0 b’1 NTP-8230 minimum pulse width = WTH + 20 ns reset default = 1 * 10 ns (WTH default = b’0000001) Glitch filter on Bypass Addr 0x62: Driver Control Bit Name 7 X Name KMS Description Fault glitch elimination PWM Mode PM 6 X 5 X 4 SB Value b’0 b‟1 00 01 Meaning fault glitch elimination filter off fault glitch elimination filter on Normal Operation 1 chip 2.1 channel mode (Single Ended Mode) cf) Should be disable 0x52 PSE 1 chip 2.0 channel mode or 2.1 channel with external power stage (BTL Mode) cf) Should be disable 0x4A SSE Stand-by No stand-by 10 SB Stand-by in 2 channel mode 0 1 3 PM 2 1 KMS 0 X Ref. Reserved addr 0x63~0x7D Addr 0x7E: Bi-Quad Filter Coefficient Page Bit Name 7 X Name CH1 Description Coefficient write enable Coefficient write enable Coefficient write enable Coefficient write enable CH2 CH3 PEQ 6 X 5 X 4 X 3 PEQ 2 CH3 Value b’0 b‟1 b’0 b‟1 b’0 b‟1 b’0 b‟1 Meaning Disable coefficient write for ch1 Enable coefficient write for ch1 Disable coefficient write for ch2 Enable coefficient write for ch2 Disable coefficient write for ch3 Enable coefficient write for ch3 Disable coefficient write for PEQ Enable coefficient write for PEQ 1 CH2 0 CH1 Ref. Ref) In convenience, a device programmer can write same biquad filter coefficients for CH1 and CH2 at a single time by setting Reg 0x7E as “x03”. See the next pages to know register map and biquad filter. Addr 0x7F: Chip ID 0x99 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 42 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 B. ROM address for BiQuads Coefficients and Parameters (Refer to Reg 0x7E) CH1&CH2 BiQuad Coefficients & Parameters The value of Reg 0x7E should be 0x01, 0x02 to program BiQuad coefficients and parameters only for channel 1 and channel 2, respectively. In case of Reg 0x7E = “0x03”, same values will be applied to channel 1 and 2. Caution! To program one BiQuad filter, five coefficients (b0,b1,b2,a1,a2) should be written consecutively in incremental address. Otherwise, the chip may be in malfunction mode. Same rule will be applied for channel 3 and Tone Control programming. Address (decimal) Address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 CH1 only 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 REG 0x7E CH2 only 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 Both x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 description default in hex FBQ1 b0 FBQ1 b1 FBQ1 b2 FBQ1 a1 FBQ1 a2 FBQ2 b0 FBQ2 b1 FBQ2 b2 FBQ2 a1 FBQ2 a2 3D BQ1 b0 3D BQ1 b1 3D BQ1 b2 3D BQ1 a1 3D BQ1 a2 3D BQ2 b0 3D BQ2 b1 3D BQ2 b2 3D BQ2 a1 3D BQ2 a2 PBQ1 b0 PBQ1 b1 PBQ1 b2 PBQ1 a1 PBQ1 a2 PBQ2 b0 PBQ2 b1 PBQ2 b2 PBQ2 a1 PBQ2 a2 PBQ3 b0 PBQ3 b1 PBQ3 b2 PBQ3 a1 PBQ3 a2 PBQ4 b0 PBQ4 b1 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 Page 43 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier Address (decimal) Address (hexadecimal) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 CH1 only 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 REG 0x7E CH2 only 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 NTP-8230 Both x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 description default in hex PBQ4 b2 PBQ4 a1 PBQ4 a2 PBQ5 b0 PBQ5 b1 PBQ5 b2 PBQ5 a1 PBQ5 a2 PBQ6 b0 PBQ6 b1 PBQ6 b2 PBQ6 a1 PBQ6 a2 PBQ7 b0 PBQ7 b1 PBQ7 b2 PBQ7 a1 PBQ7 a2 PBQ8 b0 PBQ8 b1 PBQ8 b2 PBQ8 a1 PBQ8 a2 3D Mixer M1 3D Mixer M2 Loudness gain 1 Loudness gain 2 Loudness gain 3 AGC BQ b0 AGC BQ b1 AGC BQ b2 AGC BQ a1 AGC BQ a2 QMF_BQ1 b0 QMF_BQ1 b1 QMF_BQ1 b2 QMF_BQ1 a1 QMF_BQ1 a2 QMF_BQ2 b0 QMF_BQ2 b1 QMF_BQ2 b2 QMF_BQ2 a1 QMF_BQ2 a2 QMF_BQ3 b0 QMF_BQ3 b1 QMF_BQ3 b2 QMF_BQ3 a1 QMF_BQ3 a2 QMF_BQ4 b0 QMF_BQ4 b1 QMF_BQ4 b2 QMF_BQ4 a1 QMF_BQ4 a2 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x20000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x0D31EAD7 0x0B1404D4 0x0A140503 0x1164C41A 0x10D27EE0 0x0D31EAD7 0x0D31EA65 0x20000000 0x10521801 0x20000000 0x10680650 0x11E8069C 0x106806E8 0x1164C41A 0x10D27EE0 0x10680650 0x10E805B8 0x20000000 0x10521801 0x20000000 Page 44 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier Address (decimal) Address (hexadecimal) 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B CH1 only REG 0x7E CH2 only NTP-8230 Both x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 x03 description default in hex Attack_low BQ b0 Attack_low BQ b1 Attack_low BQ b2 Attack_low BQ a1 Attack_low BQ a2 Attack_high BQ b0 Attack_high BQ b1 Attack_high BQ b2 Attack_high BQ a1 Attack_high BQ a2 Release Gain L Release Gain H THD Gain L THD Gain H PowerMeter_Gain Attack Gain Low Attack Gain High Attack Gain Post 0x0318B4A4 0x0418B4A4 0x0318B4A4 0x117BA189 0x10F75628 0x0318B4A4 0x0418B4A4 0x0318B4A4 0x117BA189 0x10F75628 0x107FFF0F 0x107FFF0F 0x11000000 0x11000000 0x107FFB49 0x11000000 0x11000000 0x11000000 CH3 BiQuad Coefficients & Parameters To program BiQuad filter coefficients and parameters for channel 3, the value of Reg 0x7E should be “0x04”. Also, five coefficients should be consecutively in incremental address form to program one BiQuad filter. Address (decimal) Address (hexadecimal) REG 0x7E description default in hex 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 FBQ1 b0 FBQ1 b1 FBQ1 b2 FBQ1 a1 FBQ1 a2 FBQ2 b0 FBQ2 b1 FBQ2 b2 FBQ2 a1 FBQ2 a2 PBQ1 b0 PBQ1 b1 PBQ1 b2 PBQ1 a1 PBQ1 a2 PBQ2 b0 PBQ2 b1 PBQ2 b2 PBQ2 a1 PBQ2 a2 PBQ3 b0 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 45 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Address (decimal) Address (hexadecimal) REG 0x7E description default in hex 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 PBQ3 b1 PBQ3 b2 PBQ3 a1 PBQ3 a2 Attack SW BQ b0 Attack SW BQ b1 Attack SW BQ b2 Attack SW BQ a1 Attack SW BQ a2 Loudness gain 1 Loudness gain 2 Loudness gain 3 Release Gain SW THD Gain SW Attack Gain SW 0x20000000 0x20000000 0x20000000 0x20000000 0x0318B4A4 0x0418B4A4 0x0318B4A4 0x117BA189 0x10F75628 0x20000000 0x20000000 0x20000000 0x107FFE1D 0x11000000 0x11000000 BiQuad Coefficients for Programmable Equalizer (PEQ) PEQ BiQuad filters are programmed after setting Reg 0x7E as “0x08”. Also, five coefficients should be consecutively in incremental address form to program one BiQuad filter. address (decimal) address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 REG 0x7E PEQ Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 description default in hex PEQ CH1 BQ1 b0 PEQ CH1 BQ1 b1 PEQ CH1 BQ1 b2 PEQ CH1 BQ1 a1 PEQ CH1 BQ1 a2 PEQ CH1 BQ2 b0 PEQ CH1 BQ2 b1 PEQ CH1 BQ2 b2 PEQ CH1 BQ2 a1 PEQ CH1 BQ2 a2 PEQ CH1 BQ3 b0 PEQ CH1 BQ3 b1 PEQ CH1 BQ3 b2 PEQ CH1 BQ3 a1 PEQ CH1 BQ3 a2 PEQ CH1 BQ4 b0 PEQ CH1 BQ4 b1 PEQ CH1 BQ4 b2 PEQ CH1 BQ4 a1 PEQ CH1 BQ4 a2 PEQ CH1 BQ5 b0 PEQ CH1 BQ5 b1 PEQ CH1 BQ5 b2 PEQ CH1 BQ5 a1 PEQ CH1 BQ5 a2 PEQ CH2 BQ1 b0 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 Page 46 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier address (decimal) address (hexadecimal) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 REG 0x7E PEQ Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 NTP-8230 description default in hex PEQ CH2 BQ1 b1 PEQ CH2 BQ1 b2 PEQ CH2 BQ1 a1 PEQ CH2 BQ1 a2 PEQ CH2 BQ2 b0 PEQ CH2 BQ2 b1 PEQ CH2 BQ2 b2 PEQ CH2 BQ2 a1 PEQ CH2 BQ2 a2 PEQ CH2 BQ3 b0 PEQ CH2 BQ3 b1 PEQ CH2 BQ3 b2 PEQ CH2 BQ3 a1 PEQ CH2 BQ3 a2 PEQ CH2 BQ4 b0 PEQ CH2 BQ4 b1 PEQ CH2 BQ4 b2 PEQ CH2 BQ4 a1 PEQ CH2 BQ4 a2 PEQ CH2 BQ5 b0 PEQ CH2 BQ5 b1 PEQ CH2 BQ5 b2 PEQ CH2 BQ5 a1 PEQ CH2 BQ5 a2 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 0x11000000 0x20000000 0x20000000 0x20000000 0x20000000 Page 47 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 C. Configuration Resister Value Reference Master & Channel Volume Index FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB DA D9 D8 D7 D6 D5 dB 24 23.5 23 22.5 22 21.5 21 20.5 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 3.5 3 Index D4 D3 D2 D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 BF BE BD BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AF AE AD AC AB AA dB 2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 -10 -10.5 -11 -11.5 -12 -12.5 -13 -13.5 -14 -14.5 -15 -15.5 -16 -16.5 -17 -17.5 -18 -18.5 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Index A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80 7F dB -19 -19.5 -20 -20.5 -21 -21.5 -22 -22.5 -23 -23.5 -24 -24.5 -25 -25.5 -26 -26.5 -27 -27.5 -28 -28.5 -29 -29.5 -30 -30.5 -31 -31.5 -32 -32.5 -33 -33.5 -34 -34.5 -35 -35.5 -36 -36.5 -37 -37.5 -38 -38.5 -39 -39.5 -40 Index 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 dB -40.5 -41 -41.5 -42 -42.5 -43 -43.5 -44 -44.5 -45 -45.5 -46 -46.5 -47 -47.5 -48 -48.5 -49 -49.5 -50 -50.5 -51 -51.5 -52 -52.5 -53 -53.5 -54 -54.5 -55 -55.5 -56 -56.5 -57 -57.5 -58 -58.5 -59 -59.5 -60 -60.5 -61 -61.5 Index 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 dB -62 -62.5 -63 -63.5 -64 -64.5 -65 -65.5 -66 -66.5 -67 -67.5 -68 -68.5 -69 -69.5 -70 -70.5 -71 -71.5 -72 -72.5 -73 -73.5 -74 -74.5 -75 -75.5 -76 -76.5 -77 -77.5 -78 -78.5 -79 -79.5 -80 -80.5 -81 -81.5 -82 -82.5 -83 Index 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 9 8 7 6 5 4 3 2 1 0 dB -83.5 -84 -84.5 -85 -85.5 -86 -86.5 -87 -87.5 -88 -88.5 -89 -89.5 -90 -90.5 -91 -91.5 -92 -92.5 -93 -93.5 -94 -94.5 -95 -95.5 -96 -96.5 -97 -97.5 -98 -98.5 -99 -99.5 -100 -110 -120 -130 -140 -150 -150 -150 Page 48 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Mixer Gain & Polarity Index Polarity dB Index Polarity dB Index Polarity dB Index Polarity dB 7E + 18 7D - 18 3E + -4 3D - -4 7C + 17 7B - 17 3C + -4.5 3B - -4.5 7A + 16 79 - 16 3A + -5 39 - -5 78 + 15 77 - 15 38 + -5.5 37 - -5.5 76 + 14 75 - 14 36 + -6 35 - -6 74 + 13 73 - 13 34 + -7 33 - -7 72 + 12 71 - 12 32 + -8 31 - -8 70 + 11 6F - 11 30 + -9 2F - -9 6E + 10 6D - 10 2E + -10 2D - -10 6C + 9 6B - 9 2C + -11 2B - -11 6A + 8 69 - 8 2A + -12 29 - -12 68 + 7 67 - 7 28 + -13 27 - -13 66 + 6 65 - 6 26 + -14 25 - -14 64 + 5.5 63 - 5.5 24 + -15 23 - -15 62 + 5 61 - 5 22 + -16 21 - -16 60 + 4.5 5F - 4.5 20 + -17 1F - -17 5E + 4 5D - 4 1E + -18 1D - -18 5C + 3.5 5B - 3.5 1C + -19 1B - -19 5A + 3 59 - 3 1A + -20 19 - -20 58 + 2.5 57 - 2.5 18 + -21 17 - -21 56 + 2 55 - 2 16 + -22 15 - -22 54 + 1.5 53 - 1.5 14 + -23 13 - -23 52 + 1 51 - 1 12 + -24 11 - -24 50 + 0.5 4F - 0.5 10 + -25 0F - -25 4E + 0 4D - 0 0E + -26 0D - -26 4C + -0.5 4B - -0.5 0C + -27 0B - -27 4A + -1 49 - -1 0A + -28 09 - -28 48 + -1.5 47 - -1.5 08 + -29 07 - -29 46 + -2 45 - -2 06 + -30 05 - -30 44 + -2.5 43 - -2.5 04 + -31 03 - -31 42 + -3 41 - -3 02 + -32 01 - -32 40 + -3.5 3F - -3.5 00 + -150 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 49 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Dynamic Range Control Threshold dB Value dB Value dB Value dB Value -57 FF -5.5 BF -2.3 7F 0.9 3F -54 FD -5.4 BD -2.2 7D 1 3D -51 FB -5.3 BB -2.1 7B 1.25 3B -48 F9 -5.2 B9 -2 79 1.5 39 -45 F7 -5.1 B7 -1.9 77 1.75 37 -42 F5 -5 B5 -1.8 75 2 35 -39 F3 -4.9 B3 -1.7 73 2.25 33 -36 F1 -4.8 B1 -1.6 71 2.5 31 -33 EF -4.7 AF -1.5 6F 2.75 2F -30 ED -4.6 AD -1.4 6D 3 2D -27 EB -4.5 AB -1.3 6B 3.25 2B -24 E9 -4.4 A9 -1.2 69 3.5 29 -21 E7 -4.3 A7 -1.1 67 3.75 27 -18 E5 -4.2 A5 -1 65 4 25 -15 E3 -4.1 A3 -0.9 63 4.25 23 -12 E1 -4 A1 -0.8 61 4.5 21 -11.5 DF -3.9 9F -0.7 5F 4.75 1F -11 DD -3.8 9D -0.6 5D 5 1D -10.5 DB -3.7 9B -0.5 5B 5.5 1B -10 D9 -3.6 99 -0.4 59 6 19 -9.5 D7 -3.5 97 -0.3 57 6.5 17 -9 D5 -3.4 95 -0.2 55 7 15 -8.5 D3 -3.3 93 -0.1 53 7.5 13 -8 D1 -3.2 91 0 51 8 11 -7.5 CF -3.1 8F 0.1 4F 8.5 0F -7 CD -3 8D 0.2 4D 9 0D -6.5 CB -2.9 8B 0.3 4B 9.5 0B -6 C9 -2.8 89 0.4 49 10 09 -5.9 C7 -2.7 87 0.5 47 10.5 07 -5.8 C5 -2.6 85 0.6 45 11 05 -5.7 C3 -2.5 83 0.7 43 11.5 03 -5.6 C1 -2.4 81 0.8 41 12 01 ※ CPR bit = 1 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 50 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 ※ Auto Mute Detection Threshold Table Name AT Description Auto-mute Detection threshold Value dB 0000 -126 0001 -120 0010 -114 0011 -108 0100 -102 0101 -96 0110 -90 0111 -84 1000 -78 1001 -72 1010 -66 1011 -60 1100 -54 1101 -48 1110 -42 1111 Auto-mute ※ Do not use value 1111. Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 51 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 Power Meter Reading Table addr 0x54 addr 0x54 (Decimal) (Hex) dB addr 0x54 addr 0x54 (Decimal) (Hex) dB addr 0x54 addr 0x54 (Decimal) (Hex) dB addr 0x54 addr 0x54 (Decimal) (Hex) dB 0 0x00 -0.0 64 0x40 -32.0 128 0x80 -64.0 192 0xC0 -96.0 1 0x01 -0.5 65 0x41 -32.5 129 0x81 -64.5 193 0xC1 -96.5 2 0x02 -1.0 66 0x42 -33.0 130 0x82 -65.0 194 0xC2 -97.0 3 0x03 -1.5 67 0x43 -33.5 131 0x83 -65.5 195 0xC3 -97.5 4 0x04 -2.0 68 0x44 -34.0 132 0x84 -66.0 196 0xC4 -98.0 5 0x05 -2.5 69 0x45 -34.5 133 0x85 -66.5 197 0xC5 -98.5 6 0x06 -3.0 70 0x46 -35.0 134 0x86 -67.0 198 0xC6 -99.0 7 0x07 -3.5 71 0x47 -35.5 135 0x87 -67.5 199 0xC7 -99.5 8 0x08 -4.0 72 0x48 -36.0 136 0x88 -68.0 200 0xC8 -100.0 9 0x09 -4.5 73 0x49 -36.5 137 0x89 -68.5 201 0xC9 -100.5 10 0x0A -5.0 74 0x4A -37.0 138 0x8A -69.0 202 0xCA -101.0 11 0x0B -5.5 75 0x4B -37.5 139 0x8B -69.5 203 0xCB -101.5 12 0x0C -6.0 76 0x4C -38.0 140 0x8C -70.0 204 0xCC -102.0 13 0x0D -6.5 77 0x4D -38.5 141 0x8D -70.5 205 0xCD -102.5 14 0x0E -7.0 78 0x4E -39.0 142 0x8E -71.0 206 0xCE -103.0 15 0x0F -7.5 79 0x4F -39.5 143 0x8F -71.5 207 0xCF -103.5 16 0x10 -8.0 80 0x50 -40.0 144 0x90 -72.0 208 0xD0 -104.0 17 0x11 -8.5 81 0x51 -40.5 145 0x91 -72.5 209 0xD1 -104.5 18 0x12 -9.0 82 0x52 -41.0 146 0x92 -73.0 210 0xD2 -105.0 19 0x13 -9.5 83 0x53 -41.5 147 0x93 -73.5 211 0xD3 -105.5 20 0x14 -10.0 84 0x54 -42.0 148 0x94 -74.0 212 0xD4 -106.0 21 0x15 -10.5 85 0x55 -42.5 149 0x95 -74.5 213 0xD5 -106.5 22 0x16 -11.0 86 0x56 -43.0 150 0x96 -75.0 214 0xD6 -107.0 23 0x17 -11.5 87 0x57 -43.5 151 0x97 -75.5 215 0xD7 -107.5 24 0x18 -12.0 88 0x58 -44.0 152 0x98 -76.0 216 0xD8 -108.0 25 0x19 -12.5 89 0x59 -44.5 153 0x99 -76.5 217 0xD9 -108.5 26 0x1A -13.0 90 0x5A -45.0 154 0x9A -77.0 218 0xDA -109.0 27 0x1B -13.5 91 0x5B -45.5 155 0x9B -77.5 219 0xDB -109.5 28 0x1C -14.0 92 0x5C -46.0 156 0x9C -78.0 220 0xDC -110.0 29 0x1D -14.5 93 0x5D -46.5 157 0x9D -78.5 221 0xDD -110.5 30 0x1E -15.0 94 0x5E -47.0 158 0x9E -79.0 222 0xDE -111.0 31 0x1F -15.5 95 0x5F -47.5 159 0x9F -79.5 223 0xDF -111.5 32 0x20 -16.0 96 0x60 -48.0 160 0xA0 -80.0 224 0xE0 -112.0 33 0x21 -16.5 97 0x61 -48.5 161 0xA1 -80.5 225 0xE1 -112.5 34 0x22 -17.0 98 0x62 -49.0 162 0xA2 -81.0 226 0xE2 -113.0 35 0x23 -17.5 99 0x63 -49.5 163 0xA3 -81.5 227 0xE3 -113.5 36 0x24 -18.0 100 0x64 -50.0 164 0xA4 -82.0 228 0xE4 -114.0 37 0x25 -18.5 101 0x65 -50.5 165 0xA5 -82.5 229 0xE5 -114.5 38 0x26 -19.0 102 0x66 -51.0 166 0xA6 -83.0 230 0xE6 -115.0 39 0x27 -19.5 103 0x67 -51.5 167 0xA7 -83.5 231 0xE7 -115.5 40 0x28 -20.0 104 0x68 -52.0 168 0xA8 -84.0 232 0xE8 -116.0 41 0x29 -20.5 105 0x69 -52.5 169 0xA9 -84.5 233 0xE9 -116.5 42 0x2A -21.0 106 0x6A -53.0 170 0xAA -85.0 234 0xEA -117.0 43 0x2B -21.5 107 0x6B -53.5 171 0xAB -85.5 235 0xEB -117.5 44 0x2C -22.0 108 0x6C -54.0 172 0xAC -86.0 236 0xEC -118.0 45 0x2D -22.5 109 0x6D -54.5 173 0xAD -86.5 237 0xED -118.5 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 52 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier addr 0x54 addr 0x54 (Decimal) (Hex) dB addr 0x54 addr 0x54 (Decimal) (Hex) dB NTP-8230 addr 0x54 addr 0x54 (Decimal) (Hex) dB addr 0x54 addr 0x54 (Decimal) (Hex) dB 46 0x2E -23.0 110 0x6E -55.0 174 0xAE -87.0 238 0xEE 47 0x2F -23.5 111 0x6F -55.5 175 0xAF -87.5 239 0xEF -119.0 -119.5 48 0x30 -24.0 112 0x70 -56.0 176 0xB0 -88.0 240 0xF0 -120.0 49 0x31 -24.5 113 0x71 -56.5 177 0xB1 -88.5 241 0xF1 -120.5 50 0x32 -25.0 114 0x72 -57.0 178 0xB2 -89.0 242 0xF2 -121.0 51 0x33 -25.5 115 0x73 -57.5 179 0xB3 -89.5 243 0xF3 -121.5 52 0x34 -26.0 116 0x74 -58.0 180 0xB4 -90.0 244 0xF4 -122.0 53 0x35 -26.5 117 0x75 -58.5 181 0xB5 -90.5 245 0xF5 -122.5 54 0x36 -27.0 118 0x76 -59.0 182 0xB6 -91.0 246 0xF6 -123.0 55 0x37 -27.5 119 0x77 -59.5 183 0xB7 -91.5 247 0xF7 -123.5 56 0x38 -28.0 120 0x78 -60.0 184 0xB8 -92.0 248 0xF8 -124.0 57 0x39 -28.5 121 0x79 -60.5 185 0xB9 -92.5 249 0xF9 -124.5 58 0x3A -29.0 122 0x7A -61.0 186 0xBA -93.0 250 0xFA -125.0 59 0x3B -29.5 123 0x7B -61.5 187 0xBB -93.5 251 0xFB -125.5 60 0x3C -30.0 124 0x7C -62.0 188 0xBC -94.0 252 0xFC -126.0 61 0x3D -30.5 125 0x7D -62.5 189 0xBD -94.5 253 0xFD -126.5 62 0x3E -31.0 126 0x7E -63.0 190 0xBE -95.0 254 0xFE 63 0x3F -31.5 127 0x7F -63.5 191 0xBF -95.5 255 0xFF -127.0 -127.5 under ※ Output 8bit value : (-dB * 2) n dB = output 8bit *0.5 Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 53 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier NTP-8230 D. Outline and Mechanical Data C.1 48-pin MLF Package Dimension Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 Page 54 2011-01-11 Power Driver Integrated Full Digital Audio Amplifier Copyright ⓒ NeoFidelity, Inc. Document Number: DS8230 draft ver. 0.1 NTP-8230 Page 55 2011-01-11