RKP9000
Integrated Stereo Audio CODEC and Power Management IC
General Description
The RKP9000 is an integrated stereo I2S audio CODEC and power management IC, which includes an integrated linear charger
for a single-cell Lithium Ion battery, six linear regulators, two high efficiency buck converters, one class D audio amplifier and
one I2S audio CODEC. Besides that, there is also one comparator, one reset, and I2C serial interface to program CODEC, buck,
and regulator output voltages as well as power-on timing controls for complete flexibility.
The linear charger charges the battery in three modes: pre-charge, constant current and constant voltage, and the thermalregulation circuit limits the chip temperature during the fast charging or when the circuits are exposed to high ambient
temperatures to allow maximum charging current without damaging the IC.
The two buck converters are high efficiency PWM DC-DC converters, and they are optimized for small size inductor and high
efficiency applications. The bucks integrate soft start, reference voltage, temperature protection and over current protection.
The LDOs are low noise and low dropout, which provide 60dB of power supply rejection at 1kHz and have only 100uVrms of
output noise for the 100Hz to 100kHz frequency range to power noise sensitive RF sections. Besides that, the LDOs integrate
reference voltage, temperature protection, current limitation and short protection.
The I2S audio CODEC is a highly integrated, low power high quality stereo CODEC. The block includes mono audio ADC, stereo
audio DACs, stereo headphone drivers and mono Class D speaker driver. Besides that, it provides digital interface, analog line and
MIC input. The digital interface supports I2S or PCM interface timing, and audio input has one mono differential microphone
input or two single-end MIC input with microphone bias and amplifier, and left/right LINE inputs.
The I2C interface is provided for system to read/wire registers in I2S Audio CODEC and power management IC.
RKP9000 is a 8 mm *8 mm, 56pin QFN package.
Features
Charger
-AC_IN & USB_IN & battery three input with Auto Power Dynamic Path (APDP).
-Switch well for charger power
-Set charge current by ISET Pin
-Auto stop charge timer
-Charge status indicator
-Interrupt for AC adaptor or USB plug in/out
-Battery temperature monitoring/protection
-Power on/off control
Buck
-Buck1 for DDR memory adjustable 2.6V/2.5V/1.8V, 800mA output current
-Buck2 for CORE PDN 1.2V(from 1.0 to 1.4v) with 25mV/step I2C adjustable, 800mA output current
-Max. Efficiency over 90%
LDO
-Auto-Discharge at shutdown
-LDO1 – 3.3V/300mA
-LDO2 – 1.2V/50mA for PLL
-LDO3 – 1.2V/50mA, Pre-Core with 25mV/step I2C adjustable
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-1July. 2009, Version 1.4
-LDO4 – 1.8V/2.5V/2.85V/3.3V/100mA for ADC, TSC, and USB PHY, (PSRR 60dB)
-LDO5 – 3.3V/300mA for AUDIO CODEC, USB PHY (PSRR 60dB)
-LDO6 – 3.3V/50mA for RTC
I2S AUDIO CODEC
-DAC SNR 90dB, ADC 86dB ('A' weighted) at 48kHz, 3.3V
-On-chip headphone Driver
- Single-ended or BTL (differential) driver
- >40mW output power on 16Ω/3.3V
- DAC to 32Ω BTL headphone: SNR 84dB, THD-65dB
-Class D mono speaker amplifier
- High Mono output power 1.5W at 10% THD+N with 8ohms Speaker, 3W at 4ohms Speaker
- Direct battery power operation
-Mono differential or single-ended microphone input
-24-bit Digital signal processing（DSP）engine
- Bass and Treble Tone Control
- Soft-Ramp & Zero-Cross Transitions
-High performance 24-bit converters
- Multi-bit Delta Sigma Architecture
- Very low 64Fs Power Down Management
-Analog & Digital Routing/Mixers
-Flexible Clocking Options
Other
-System Reset
-Low Battery Voltage Detector
-I²C compatible Interface
-Power-on Timing Control
Applications
GPS
Hand-held devices
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-2July. 2009, Version 1.4
PRELIMIARY DATASHEET
Rock Semiconductor Ltd.,.
RKP9000
GND1
OUT5
AINAIN+
IN2
OUT4
MIC+
PWR_IN
OUT6
Bypass
MIC-
MICBIAS
LBI
PBSTAS
HP/LINE_OUTA
REF
RESET
INT
PWR_EN
FB2
LX2
PGND2
HP/LINE_OUTB
VHP
VA
SDOUT
SDIN
SPK_GND
PIN CONFIGURATIONS
Figure 1：Pin Configuration
-3July. 2009, Version 1.4
OUT3
OUT2
LDO5
LDO4
LDO3
LDO2
IN2
OUT4
LDO6
OUT1
OUT5
BUCK1
OUT6
LX1
IN1
FB1
FUNCTION BLOCK
LDO1
RESET
RESET
BATT
TS
Li-lon Linear
Charger
Control
UVLO
FB2
BUCK2
LX2
THERAML
SHUTDOWN
VSYS
PWR_EN
PWR_IN
PBSTAS
ON/OFF
CONTROL&
I2C INTERFACE
DS_READY
Bit
320ms
Debounce
PWR_ON
EXT_ON
BUCK1
OK
CHG_S
ISETA
320ms
Debounce
LBO
PWR_HOLD
1.2V +
INT
SCL
LBI
SDA
VP
LRCR
SPKR_OUT+
MCLK
SPKR_OUT-
AUDIO CODEC
SCLK
HP/LINE _OUTB
GND
VHP
AGND
VA
REF
MICBIAS
MIC-
MIC+
AIN-
AIN+
SDOUT
SDIN
VB
HP/LINE _OUTA
Figure 2：Function Diagram
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-4July. 2009, Version 1.4
I2S AUDIO CODEC BLOCK
Figure 3：I2S AUDIO CODEC BLOCK
PIN DESCRIPTION
PIN NO.
NAME
1
2
3
4
5
6
IN1
LX1
PGND1
FB1
PWR_HOLD
PWR_ON
7
LRCR
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
EXT_ON
MCLK
SDA
SCL
VP_VSYS
SPKR_OUT+
SPKR_OUTSPK_GND
SDIN
SDOUT
VA
VHP
HP/LINE_OUTB
HP/LINE_OUTA
REF
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
DESCRIPTION
BUCK’s input power supply (Must be shorted to VSYS IN2,VP_VSYS)
Inductor connection to the drains of the internal N-Channel and P-Channel MOSFETs
Buck1’s power ground
Voltage feedback1— FB1 regulates to 0.6V nominal
Logic low from application processor turns off the PMU
Active high power on/off key input. This pin has an internal 2uA Pull-Down current to GND. When the Push Button
is closed, It is shorted to battery, not ground. This input is de-bounced with 320ms(typ)
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio
data line
Active high power on/off key input. This input is de-bounced with 320ms(typ)
Master Clock - Clock source for the delta-sigma modulators
Serial Control Data(I/O) – SDA is a data I/O in I2C
Serial Control Port Clock – serial clock for the serial control port
Power supply for PWM output stages
Full-bridge PWM output
Full-bridge PWM output
Power ground for PWM output stages
Serial Audio Data Input - Input for two’s complement serial audio data
Serial Audio Data Output - Output for two’s complement serial audio data
Analog Power - Positive power for the internal analog section
Analog Power for Headphone
Headphone/Line Audio Output – Stereo headphone or line level analog output
Headphone/Line Audio Output – Stereo headphone or line level analog output
Reference Bypass with 4.7uF
RKP9000
-5July. 2009, Version 1.4
23
MICBIAS
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
MICMIC+
AINAIN+
PWR_IN
VSYS
BATT
BATT
PWR_ID
GND4
CHG_S
ISETA
TS
GND2
SCLK
VB
OUT3
OUT2
OUT1
IN2
OUT5
GND1
OUT4
OUT6
Bypass
LBI
PBSTAS
RESET
INT
PWR_EN
FB2
PGND2
LX2
Exposed Pad
Microphone Bias - Low noise bias supply for an external microphone. Electrical characteristics are specified in the
DC Electrical Characteristics table
Differential Microphone Inputs - Differential stereo microphone inputs
Differential Microphone Inputs – Differential stereo microphone inputs
Line-Level Analog Inputs
Line-Level Analog Inputs
Power source input
Connect to system
Main battery supply input terminal
Main battery supply input terminal
Logic low for USB power source input; logic high for AC_IN power source input
GND
Charge status indicator
AC_IN charge current setting pin
Temperature sense PIN
GND
Serial Clock - Serial clock for the serial audio interface
Power supply for digital core and digital I/O
Pre-core with 25mV/step I2C adjustable. Default 1.3V
1.2V/200mA LDO. Hi-Z in off condition
3.3V 500mA LDO. Hi-Z in off condition
Must be shorted to VSYS, IN1 and VP_VSYS
LDO5 output. Hi-Z in off condition. Default 3.3V, OFF
GND
LDO4 output. Hi-Z in off condition. Default 2.5V, ON
LDO6 output
Reference Bypass
Connect to battery. Feedback voltage 1.2V
Power on/off signal to inform application processor, active low, open drain output
Open drain reset output, active low. RESET is low in shutdown
Open drain, active Low. Interrupt signal output
Buck2 & LDO2&LDO4&LDO5 enable pin from CPU
Voltage feedback2. FB2 regulates to 0.6V nominal
Buck2’s power ground
Inductor connection to the drains of the internal N-Channel and P-Channel MOSFETs
Ground
Table 1：Pin Description
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-6July. 2009, Version 1.4
Operating Conditions
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Power Supply Input
Charger Supply Input
IO Input
Maximum power dissipation
Package thermal resistance
Symbol &Conditions
TSTOR
TAMB
VBAT
VCHG
All I/O, unless otherwise stated
At maximum ambient operating temperature
QFN 8mm*8mm 56 PIN package
Min
-40
-30
-0.3
-0.3
-0.3
Max
+95
+85
+5.5
+5.5
VBAT + 0.3
3.5
21
Unit
°C
°C
V
V
V
W
°C/W
Min
-20
2.8
4.6
Max
+85
4.8
5.5
Unit
°C
V
V
Table 2: Absolute Maximum Ratings
Recommended Operating Condition
Parameter
Operating temperature
Power Supply Input
Charger Supply Input
Symbol & Conditions
TAMB
VBAT
VCHG
Table 3: Recommended Operating Condition
ELECTRICAL CHARACTERISTICS
General Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Quiescent Current
Input supply voltage
Shutdown battery supply current 1
Sleep mode supply current 2
Battery Voltage Lockout
Under voltage lockout
Under voltage lockout
Thermal Shutdown
Threshold
Hystersis
Condition
Min
Typ.
Max
Unit
VBATT = 4.2V, OUT1~6, LX1, LX2 to ground
VBATT =3.7V, PWR_EN=L
2.7
-
-
5.5
250
TBD
V
μA
μA
VBATT rising
VBATT falling, refer LDO1 and BUCK1 VOUT
-
3.2
-
90
V
%
-
150
20
-
℃
℃
Table4: General Electrical Characteristics
Buck Converter 1 Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C .
Parameter
Output adjustable range
Input supply voltage
FB1 threshold voltage
FB1 threshold line regulation
FB threshold voltage accuracy (falling)
(%of VFB1)
FB BIAS current
Current limit
On-resistance
Rectifier off current threshold
Minimum on times
Soft start time
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
Condition
VFB1 falling
VIN=2.7V to 5.5V
ILOAD = 0
Shutdown
VFB = 0.5V
PFET switch
NFET switch
PFET switch, ILX=-40mA
NFET SWITCH, ILX=40mA
Ton
-
RKP9000
Min
Typ.
Max
VREF
2.7
-
0.6
0.3
VIN
5.5
-
Unit
V
V
V
%/V
-0.3
-
0.3
%
1000
600
-
0.1
0.1
1500
1000
0.35
0.3
50
107
160
2000
1500
-
μA
μA
mA
mA
Ohm
Ohm
mA
ns
us
-7July. 2009, Version 1.4
Table 5: Buck Converter 1 Electrical Characteristics
Buck Converter 2 Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output adjustable range
Input supply voltage
FB1 threshold voltage
FB1 threshold line regulation
FB threshold voltage accuracy (falling)
(%of VFB1)
FB BIAS current
Current limit
On-resistance
Rectifier off current threshold
Minimum on times
Programmable FB voltage
Each programmable FB voltage step
FB voltage accuracy
Soft start time
Condition
VFB1 falling
VIN=2.7V to 5.5V
ILOAD = 0
Shutdown
VFB = 0.5V
PFET switch
NFET switch
PFET switch, ILX=-40mA
NFET switch, ILX=40mA
Ton
VFB1 falling
Min
Typ.
Max
Unit
VREF
2.7
-
0.6
0.3
VIN
5.5
-
V
V
V
%
-0.3
-
0.3
%
1000
600
0.5
-1
-
0.1
0.1
1500
1000
0.6
0.3
50
107
12.5
2000
1500
0.7
1
-
μA
μA
mA
mA
Ohms
Ohms
mA
nsec
V
mV
%
us
Unit
160
Table 6: Buck Converter 2 Electrical Characteristics
OUT1 (LDO1) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Condition
Output voltage OUT1
Iload=300mA & Vin=3.7 V
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection.△Vout/△Vin
Ground current t
VOUT1 =0V
Iload=300mA
OUT1+0.5V ≦VBATT=VIN1≦5.5V,Iload=300mA
VIN1=3.7V, 50μA < Iload < 300mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V, Iload=30mA
Min
Typ.
Max
3.201
2.716
500
-
3.3
2.8
300
25
60
21
3.399
2.884
850
150
6
-
mA
mA
mV
mV
mV
dB
μA
V
Table7: OUT1 (LDO1) Electrical Characteristics
OUT2 (LDO2) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output voltage OUT2
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection. △Vout/△Vin
Ground current t
Condition
Iload=200mA & Vin=3.7 V
VOUT2 =0V
Iload=50mA
OUT2+0.5V ≦VBATT=VIN1≦5.5V,Iload=50mA
VIN1=3.7V, 50μA < Iload <50mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V,Iload=30mA
-
Min
Typ.
Max
Unit
1.164
-
1.2
100
300
25
60
21
1.236
50
4.6
-
V
mA
mA
mV
mV
mV
dB
μA
Table 8: OUT2 (LDO2) Electrical Characteristics
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-8July. 2009, Version 1.4
OUT3 (LDO3) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output voltage OUT3
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection. △Vout/△Vin
Ground current t(Design Guide)
Condition
Iload=200mA & Vin=3.7 V
VOUT3 =0V
Iload=50mA
OUT3+0.4V ≦VBATT=VIN1≦5.5V,Iload=50mA
50μA < Iload <50mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V,Iload=30mA
-
Min
Typ.
Max
Unit
1.164
-
1.2
100
300
25
60
21
1.236
50
4.6
-
V
mA
mA
mV
mV
mV
dB
μA
Table 9: OUT3 (LDO3) Electrical Characteristics
OUT4 (LDO4) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output voltage OUT4
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection. △Vout/△Vin
Ground current t(Design Guide)
Output ripple
Condition
Iload=200mA & Vin=3.7 V
VOUT4 =0V
Iload=100mA
OUT4+0.5V ≦VBATT=VIN1≦5.5V,
Iload=100mA
50μA < Iload <100mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V,Iload=30mA
Iout=50mA
Min
Typ.
Max
Unit
2.425
-
2.5
300
300
2.575
100
-
V
mA
mA
mV
-
-
6.5
mV
-10
25
60
21
-
+10
mV
dB
μA
mV
Table10: OUT4 (LDO4) Electrical Characteristics
OUT5 (LDO5) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output voltage OUT5
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection △Vout/△Vin
Ground current
Condition
Iload=200mA & Vin=3.7 V
VOUT5 =0V
Iload=300mA
OUT5+0.4V ≦VBATT=VIN1≦5.5V,Iload=300mA
50μA < Iload <300mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V,Iload=30mA
-
Min
Typ.
Max
Unit
3.201
-
3.3
200
400
300
25
60
21
3.399
6
-
V
mA
mA
mV
mV
mV
dB
μA
Table 11: OUT5 (LDO5) Electrical Characteristics
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
-9July. 2009, Version 1.4
OUT6 (LDO6) Electrical Characteristics
Operating conditions (unless otherwise specified):
VBATT=IN1=IN2=VP_VSYS =+3.7V, CBATT+ΣCIN1,2=50μF, CREFBYPASS=4.7uF, TA =-40°C to +85°C
Parameter
Output voltage OUT5
Output current
Current limit
Drop-out voltage
Line regulation
Load regulation
Power supply rejection △Vout/△Vin
Ground current
Condition
Iload=200mA & Vin=3.7 V
VOUT5 =0V
Iload=200mA
OUT5+0.4V ≦VBATT=VIN1≦5.5V,Iload=200mA
50μA < Iload <200mA
F=10Hz-10kHz (Cout=1μF),Vout>2.5V,Iload=30mA
-
Min
Typ.
Max
Unit
3.201
-
3.3
50
100
300
25
60
21
3.399
6
-
V
mA
mA
mV
mV
mV
dB
μA
Min
Typ.
Max
Unit
4.5
4.5
-
300
5.5
5.5
500
V
V
uA
4.158
4.2
-
4.2
4.4
400
1.2
-
4.242
4.6
-
200
V
V
mΩ
mΩ
mΩ
100
-
1200
mA
2.7
2.8
20
2.9
8
10
12
V
mV
%
-
300
-
mV
-
65
-
mV
-
500
-
mA
94
0.485
-
100
0.5
-
106
0.515
500
2500
uA
V
mA
mA
Min
Typ.
Max
Unit
-
3.3
VBATT
3.3
3.3
-
V
V
V
V
Table 12: OUT6 (LDO6) Electrical Characteristics
Li-Ion Charger Electrical Characteristics
Operating conditions (unless otherwise specified):AC_IN = 5V, VBATT = 4V, TA =-40°C to +85°C
Parameter
Condition
Input Voltage Range and Input Current
ACIN input operation voltage range
USB input voltage range
ACIN/USB standby current
VBATT=4.5V, VACIN=4.4V,USB=4.4V
Voltage Regulation
BATT regulation voltage
IBATT= 60mA
System regulation voltage
VACIN=5V, IACIN=100mA
ACIN power FET RDSON
VACIN=5V, IAC = 1A
USB power FET RDSON
VUSB=5V, IUSB=100mA,ISETU = High
System to battery RDSON
VBATT=5V, ISYS=1A
Current Regulation
Full charge setting range
Pre-charge
BATT pre-charge threshold
BATT pre-charge threshold hysteresis
Pre-charge current
VBATT=2V
Recharge Threshold
BATT re-charge falling threshold VREG –VBATT
hysteresis
Logic Input/Output
CHG_S pull down voltage
I/CHG_S=5mA
USB Charge Current
USB port input current limit
Protection
TS pin source current
VTS=1.5V
TS pin threshold voltage
AC_IN current limit
PWR_ID=H
PWR_ID=L
Table 13: Li-Ion Charger Electrical Characteristics
I2S Audio CODEC Electrical Characteristics
Parameter
DC Power Supply
Condition
Analog/HP Amplifier
Speaker OUT
Digital
Serial/Control Port Interface
Table 14：Audio CODEC Electrical Characteristics
Rock Semiconductor Ltd.,.
PRELIMIARY DATASHEET
RKP9000
- 10 July. 2009, Version 1.4
Reset and Low Battery Electrical Characteristics
Operating conditions (unless otherwise specified):AC_IN = 5V, VBATT = 4V, TA =-40°C to +85°C
Parameter
Output low voltage
RESET threshold
RESET active Time-out period
LBI feedback voltage (falling)
LBI hysteresis
Condition
Internal logic supply, Isink = 500μA
With respect to BUCK2
From Buck2 ≥87% until RESET =HIGH
-
Min
Typ.
Max
Unit
84
1.21
40
87
200
1.25
50
0.3
90
1.28
60
V
%
ms
V
mV
Typ.
Max
Unit
Table 15: Reset and Low Battery Electrical Characteristics
Audio Input Electrical Characteristics
VB = 3.3V, VA = 3.3V, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
Parameter
SYMBOL
LINEL/R, MIC1/2A/2B and MONOIN pins
Full Scale Input Signal Level (0dBFS)
VINFS
Input Resistance
RIN
Input Capacitance
Line input to ADC (LINEL, LINER, MONOIN)
Signal to Noise Ratio (A-weighted)
SNR
Total Harmonic Distortion
THD
Power Supply Rejection
PSRR
Microphone input to ADC (MIC1/2A/2B pins)
Signal to Noise Ratio (A-weighted)
SNR
Total Harmonic Distortion
THD
TEST CONDITIONS
VA = 3.3V
VA = 2.7V
differential input mode (MS = 01) VA = 3.3V
differential input mode (MS = 01) VA = 2.7V
0dB PGA gain
12dB PGA gain
Min
25.6
10.4
80
1.0
0.8
0.5
0.4
32
13
5
-3dBFS input
20Hz to 20kHz
87
-86
50
20dB boost enabled
20dB boost enabled
80
-80
V rms
38.4
15.6
kΩ
pF
dB
dB
dB
-80
dB
dB
Table 16: Audio Input Electrical Characteristics
Audio Output Electrical Characteristics
VB=3.3V, AC_IN = 5V, VA=VHP =3.3V, TA = +25°C, 1kHz signal, fs = 48kHz, 24- bit audio data unless otherwise stated.
Parameter
SYMBOL
TEST CONDITIONS
DAC to Line-Out (HPL/R, SPKL/R or MONO with 10kΩ/ 50pF load)
Full-scale output (0dBFS)
VA = 3.3V, PGA gains set to 0dB
Signal to Noise Ratio (A-weighted)
SNR
Total Harmonic Distortion
THD
-3dB output
Power Supply Rejection
PSRR
100mV, 20Hz to 20kHz signal on AVDD
Headphone Output (HPL/R, OUT3/4 or SPKL/SPKR with 16Ω or 32Ω load)
Output Power per channel
PO
Output power is very closely correlated with
THD; see below.
Total Harmonic Distortion
THD
PO=10mW, RL=16Ω
PO=10mW, RL=32Ω
PO=20mW, RL=16Ω
PO=20mW, RL=32Ω
Signal to Noise Ratio (A-weighted)
SNR
Mono Class D Speaker Output (SPKout with 8Ω.bridge tied load,)
Output Power at 1% THD
PO
THD = 1%
Abs. max output power
POmax
THD=10%
Total Harmonic Distortion
THD
PO = 250mW
Oscillator frequency
Pch MOS on resistance
Nch MOS on resistance
Efficiency
Signal to Noise Ratio (A-weighted)
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Fosc
PO = 1W with BTL 8ohms Load, SPKVDD=5V
RKP9000
Min
Typ.
Max
Unit
1
85
-80
50
V rms
dB
dB
dB
-80
-80
-78
-79
85
dB
dB
1000
1300
60
0.1%
250
450
400
85
80
mW(ms)
mW(ms)
dB
%
kHz
mohms
mohms
%
dB
- 11 July. 2009, Version 1.4
Notes:
1. Filterless application has been tested with speaker directly connected with speaker amp.
2. POPless features has been extensively tested and has acceptable performance
Table 17: Audio Output Electrical Characteristics
Reference Voltages Electrical Characteristics
VB=3.3V, AC_IN = 5V, VA = 3.3V, TA = +25°C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
Parameter
Audio ADCs, DACs, Mixers
Reference Input/Output
Buffered Reference Output
Microphone Bias
Bias Voltage
Bias Current Source
Output Noise Voltage
SYMBOL
TEST CONDITIONS
Min
Typ.
Max
Unit
BYPASS in
VREF pin
1.21
1.61
1.25
1.65
1.28
1.67
V
V
VMICBIAS
IMICBIAS
Vn
2.92
2.97
3.00
3
1KHz to 20kHz
15
V
mA
nV/√Hz
Table 18: Reference Voltages Electrical Characteristics
POWER CONSUMPTION
The power consumption of the RKP9000 depends on the following factors:
Supply voltages: Reducing the supply voltages also reduces digital supply currents, end therefore results in significant power
savings especially in the digital sections of the RKP9000.
Operating mode: Significant power savings can be achieved by always disabling parts of the RKP9000 that are not used (e.g.
audio ADC, DAC,HP, Speaker Amp).
Sample rates: Running at lower sample rates will reduce power consumption significantly. The figures below are for 48kHz
(unless otherwise specified), but in many scenarios it is not necessary to run at this frequency.
MODE DESCRIPTION
Off (lowest possible power)
Clocks stopped. This is the default configuration after
power-up.
LPS (Low Power Standby)
VREF maintained using 1Mohm string
Record from mono microphone
Stereo DAC Playback (PCM to headphone)
Stereo DAC Playback (PCM to classD, with PLL )
Stereo DAC Playback (PCM to headphone)PLL
running with 13MHz input to MCLKB
Maximum Power - everything on
VA Analog
Supply
Current V / mA
VB Logic
Supply
Current V / mA
VHP headphone
Supply
Current V / mA
3.3
0.01
3.3
0
3.3
0.005
0.05
3.3
0.014
3.3
0
3.3
0.005
0.06
3.3
3.3
3.3
2.63
2.63
4.01
3.3
3.3
3.3
44.3
10.2
44.3
3.3
3.3
3.3
0
1.2
0
46.93
14.03
48.31
3.3
3.33
3.3
44.3
3.3
1.2
48.83
3.3
7.22
3.3
44.5
3.3
1.2
52.95
Total Power (mW)
Notes:
1. Unless otherwise specified, all figures are at TA = +25℃, audio sample rate fs = 48kHz, with zero signal (quiescent), and
voltage references settled.
Table 19: Power Consumption
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RKP9000
- 12 July. 2009, Version 1.4
TIMING SEQUENCE
First Power-On Sequence
PW R_ON
320ms
LDO6
LDO3
700us
BUCK2
LDO1
BUCK1
100us
100us
PWR_EN
LDO2
LDO4
100us
LDO5
1ms
PWR_HOLD
RESET
200ms
Figure 4：First Power-On Sequence
Need add power hold control information(if power off or power hold)
Power-On Sequence（Normal to Sleep to Normal）
Figure 5：Power-On Sequence（Normal to Sleep to Normal）
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- 13 July. 2009, Version 1.4
Power-On Sequence（Normal to Deep Sleep to Normal）
Figure 6：Power-On Sequence（Normal to Deep Sleep to Normal）need add register information
PMU Behavior Description
PMU On/Off behavior. PWR_ON, EXT_ON and PWR_HOLD are inputs for PMU’s on/off control.
PWR_ON connect with on/off button, when 1st time main battery plug-in, if the PWR_ON is “LOW” for “320ms” and no valid
LBO signal, then PMU provides power to system according to power on sequence. When PMU is in normal and sleep mode, LBO
can not affect PMU’s mode change.
PWR_HOLD is used for system to turn-off PMU, after PMU provide power to system, System will feedback PWR_HOLD
with ”high” level to PMU to make PMU keep providing power to system before PWR_ON key is released. Whenever system pull
PWR_HOLD to “Low”, then PMU will be powered down and stop providing power to system except LDO6.
EXT_ON is other source to make PMU power on, if PMU is in power down mode or deep sleep mode, whenever EXT_ON is
“high” (EXT_ON have 320ms level debounce timer), PMU will provide power to system on sequence.
Work Mode change. There are three signals for PMU’s mode change, which are PWR_EN, PWR_DS and DS_RDY.
When PWR_ON is pulled down, PMU send an application to system for mode change by PBSTAS. Then PMU enter sleep mode
from normal mode when PWR_EN is “low” level (PWR_DS is “low” level”), and return to normal mode when PWR_EN is
“high” level.
If system wants to enter deep sleep, system can change DS_RDY from “low” level to “high” level that means system is OK and
PMU can enter deep sleep mode. Then PMU enter deep sleep mode by setting PWR_DS equal to “1” by system.
When PMU wants to return to normal mode, press PWR_ON, then PMU provide power to system according to power on
sequence by setting PWR_DS equal to “0” if there is no “low battery” issue.
In idle mode and deep sleep, PWR_EN can not control BUCK2, and it is shielded by X_PWR_EN bit. When PMU is normal and
sleep mode, X_PWR_EN is set “1” and PWR_EN control BUCK2 on/off.
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RKP9000
- 14 July. 2009, Version 1.4
FSM flow
Figure 7：FSM flow
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RKP9000
- 15 July. 2009, Version 1.4
PACKAGE DESCRIPTION
8.000±0.050
6.200±0.050
Exp.DAP
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RKP9000
- 39 July. 2009, Version 1.4
© 2009 by Rock Semiconductor
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Reproduction or duplication by any means of any portion of this document without the prior written consent of Rock Semiconductor is expressly
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The information provided herein is preliminary, and may change with product qualification. Rock Semiconductor assumes no responsibility for
inaccuracies, errors, or omissions. Rock Semiconductor assumes no responsibility for the use of this information, and all use of such information shall
be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
www.rockic.com
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- 40 July. 2009, Version 1.4