TSP840M / TSF840M
500V N-Channel MOSFET
General Description
Features
This Pow er MOSFET is produced using Tr uesemi‘s
advanced planar stripe DMOS technology.
This advanced technology has been espe cially tailored to
minimize o n-state r esistance, pr ovide superior switching
performance, and withstand high ener gy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency sw itched mode power supp lies,
active power factor corr ection based on half br idge
topology.
•
•
•
•
•
9.0A, 500V, RDS(on) = 0.80Ω @VGS = 10 V
Low gate charge ( typical 30nC)
Fast witching
s
100% avalanche tested
Improved dv/dt capability
{
D
●
◀
▲
{G
G DS
TO-220
●
●
TO-220F
GD S
{S
Absolute Maximum Ratings
Symbol
VDSS
ID
TC = 25°Cunless otherwise noted
Parameter
Drain-Source Voltage
- Continuous (TC = 25°C)
Drain Current
TSP840M
- Continuous (TC = 100°C)
IDM
Drain Current
VGSS
Gate-Source Voltage
EAS
Single Pulsed Avalanche Energy
EAR
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (TC = 25°C)
dv/dt
PD
TJ, TSTG
TL
- Pulsed
TSF840M
500
(Note 1)
Units
V
9.0
9.0*
A
5.4
5.4 *
A
36 *
A
36
± 30
V
(Note 2)
360
mJ
(Note 1)
13.9
4.5
-55 to +150
mJ
V/ns
W
W/°C
°C
300
°C
(Note 3)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
139
1.11
45.5
0.36
* Drain current limited by maximum junction temperature.
Thermal Characteristics
Symbol
RθJC
Parameter
Thermal Resistance, Junction-to-Case
TSP840M
0.90
TSF840M
2.75
Units
°C/W
RθCS
Thermal Resistance, Case-to-Sink Typ.
0.5
--
°C/W
RθJA
Thermal Resistance, Junction-to-Ambient
62.5
62.5
°C/W
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TSP840M / TSF840M
Electrical Characteristics
Symbol
TC = 25°C unless otherwise noted
Parameter
Test Conditions
Min
Typ
Max
Units
500
--
--
V
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS
/
∆TJ
Breakdown Voltage Temperature
Coefficient
ID = 250 µA, Referenced to 25°C
--
0.6
--
V/°C
VDS = 500 V, VGS = 0 V
1
µA
IDSS
Zero Gate Voltage Drain Current
--
--
VDS = 400 V, TC = 125°C
--
--
10
µA
IGSSF
Gate-Body Leakage Current, Forward
VGS = 30 V, VDS = 0 V
--
--
100
nA
IGSSR
Gate-Body Leakage Current, Reverse
VGS = -30 V, VDS = 0 V
--
--
-100
nA
2.0
--
4.5
V
--
0.65
0.80
Ω
On Characteristics
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID =
4.5 A
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
--
870
--
pF
--
130
--
pF
--
25
--
pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 250 V, ID = 9.0A,
RG = 25 Ω
(Note 4, 5)
VDS = 400 V, ID = 9.0 A,
VGS = 10 V
(Note 4, 5)
--
20
--
ns
--
70
--
ns
--
90
--
ns
--
60
--
ns
--
30
-
nC
--
4.0
--
nC
--
15
--
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
--
--
9.0
A
ISM
--
--
36.0
A
VSD
Maximum Pulsed Drain-Source Diode Forward Current
VGS = 0 V, IS = 9.0 A
Drain-Source Diode Forward Voltage
--
--
1.4
V
trr
Reverse Recovery Time
--
340
--
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 9.0 A,
dIF / dt = 100 A/µs
--
3.0
--
µC
(Note 4)
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 8 mH, IAS = 9.0 A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 9.0 A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
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Typical Characteristics
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
Figure 3. On-Resistance Variation vs
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation with Source Current
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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Typical Characteristics
(Continued)
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 9-1. Maximum Safe Operating Area
for TSP840M
Figure 8. On-Resistance Variation
vs Temperature
Figure 9-2. Maximum Safe Operating Area
for TSF840M
Figure 10. Maximum Drain Current
vs Case Temperature
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Typical Characteristics
(Continued)
Figure 11-1. Transient Thermal Response Curve
for TSP840M
Figure 11-2. Transient Thermal Response Curve
for TSF840M
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Gate Charge Test Circuit & Waveform
50KΩ
200nF
12V
VGS
SameType
asDUT
Qg
10V
300nF
VDS
VGS
Qgs
Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
V
D
S
R
G
R
L
V
D
S
9
0
%
V
D
D
V
G
S
1
0
%
V
G
S
D
U
T
1
0
V
td
(o
n
)
tr
td
(o
ff)
to
n
to
ff
tf
Unclamped Inductive Switching Test Circuit & Waveforms
V
D
S
B
V
D
S
S
1
IAS2 -------------------E
A
S=---- L
2
V
B
D
S
S-V
D
D
L
B
V
D
S
S
IAS
ID
R
G
V
D
D
D
U
T
1
0
V
tp
ID(t)
V
D
S(t)
V
D
D
tp
T
im
e
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Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
D U T
V
D S
_
I
S D
L
D r iv e r
R
V
V GS
( D r iv e r )
G
S a m e Ty p e
as DU T
G S
V
D D
• d v / d t c o n t r o l l e d b y RG
• I S D c o n t r o lle d b y p u ls e p e r io d
D
G a te P u ls e W id th
=-------------------------G a t e P uls e P er io d
10V
IF M , B o d y D io d e F o r w a r d C u r r e n t
I
S D
d i/d t
( D U T )
IR
M
B o d y D io d e R e v e r s e C u r r e n t
V DS
( D U T )
B o d y D io d e R e c o v e r y d v / d t
V
S D
V
D D
B o d y D io d e
F o r w a r d V o lt a g e D r o p
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