ETC UC3724

AM丁
3
呵
〈国外电子元器件} 1997 年第 7 期
1997 年 7 月
@新特器件应用
MOSFET
陷落.3ã 勃器 UC3724/UC3725
航天工业总公司 771 研究所
摘要:
林建伟
UC3724/ UC3725 是 UNITRODE 公司推出的一组 .MOSFET 隔离驱动芯片，
它们利用变压器进行隔离，能同时传递驱动逻辑信号与驱动功率，内部包含欠压、过
流保护电路。它们配合使用，具有电路简单、隔离度高、供电方便的特点。本文介绍了
它们的特点、工作原理，并给出了典型应用电路。
关键词: MOSFET
隔离驱动
占空比调制
欠压保护
过流保护
·欠压保护;
1 、功能介绍
@可通过变压器传递直流信号;
UC3:724 与 UC3725 配合使用，提供了
一套独特的功率 MOSFET 驱动方案，它们
特别适用于驱动高压 H 桥中的高边 MOS­
• 600kHz 的工作频率。
2.2 功能描述
UC3724 的内部组成见图 1 ，主要包含
欠压锁定电路、控制逻辑与单稳触发器、输
FET。
UC3724 为一隔离驱动传送器，它采用
低成本的脉冲变压器传递驱动逻辑信号与功
入比较器、两个带有零电流比较器的三电
平输出级。
率到隔离驱动电路 UC3725 ，而 UC3725 接
欠压保护电路门限电压为 7. 75V ，有一
收 UC3724 传递的信号，完成信号解调、
1V 滞环。欠压时该电路将关断输出，一旦供
MOSFET 的驱动与保护。由于采用了独特
电电压足够高时内部偏置电路产生适当的电
的占空比词制技术，保证了。 ~100% 占空比
压、电流使输出使能，从而保证在上电时或低
的驱动信号均能被可靠的传输。高达 600kHz
压时能正常操作。
的调制频率大大降低了隔离变压器的成本与
体积。
单稳态触发器用来产生占空比调制所用
的载波，载波周期为单稳态触发器输出脉宽
本文将详细介绍 UC3724/ UC3725 的
时间与磁芯复位时间之和，单稳态触发器输
电路组成、占空比调制/解调原理与使用设.
出脉宽时间为载波周期的三分之一。脉冲宽
计方法。，
度可由下式表示，
‘
Tpw
= O. 51 XRt X Ct+ .l 50ns(s)
。
UC3724 为一隔离驱动传送器，主要特
点如下:
脚 6、脚 4 为两路输出，接脉冲变压器初
级，连续输入/输出电流达 O.3A，最大脉冲电
.500mA的吸人/源出电流;
流为 1A，输出被调制的 PHI 控制信号。
.8~35V 的工作电压;
,
2.3 占空比调制原理
输
@迅速传递逻辑信号;
·工作频率可编程;
v
UC3724 驱动芯片采用了独特的占空比
调制技术，可以由一个脉冲变压器同时传递
壁〕手持、恨，雀益M
慧E
，a毒最惊密"哈争汇区弘&e抱
p碴
h
TTL 电平兼容，该拚入信号将被载波调制。
2.1 特点
缸，，‘ES
脚 7(PH I)为控制输入端。输入电平与
lg&ts$'
2、 UC3724 的功能描述
户、
J
司、时
MOSFET 隔离驱动器 UC3724/UC3725
, ~. ~
vcc
|锢，产生与欠压锁←耐的R阳
OUTPUTA
RT
噜、斗'吨
,
-a
凰
。UT问灯8
'
i 叫一一份
GND
PWR GND
图 1 UC3724 方框图
置于零。这样变压器初级绕组中励磁电流均
匀上升。单稳复位后 ;A 输出置l/2Vcc ; 初级
输入'5VJd~
逼迫
绕组两端电压倒向，、电流下降。;电流下降斜
1回翩翩W
遮遮2
率为上升斜率的一半。在绕组两端所加电压
.01
为 Vα 时，驱动功率被传输到变压器次级，此
V田lC. A-8 2rNIdPi
通越3
时初级中流动电流为励磁电流与等效负载电
输出 2rNldW (N
通il4
流之和，而在绕组两端所加电压为 11
'北lIizontal
50μSIDJY
2Vcc
时，初级绕组 9=t流动电流仅有磁芯复位电
~.
流。内部的零电流检验电路保证仅在初级励
图 2 占空比调制波形
磁电流为零时，才再次触发单稳态触发器，开
驱动逻辑信号与驱动功率到 UC3725 ，无论
始下一周期，从而保证变压器可以可靠的复
传递交流信号或直流信号都不必担心变压器
位，而不会发生磁饱和。
饱和，占空比调制波形如图 2 所示。 F
当控制信号 PHI 输入为低时，单稳触发
器输出为高电平期间 A 输出 V(、C ，而 B 输出
当 PHI 输入为高时 .A 、 B 输出刚好与上
述相反，不再赘述。
PHI 状态发生改变时振荡周期立即被
43f0
〈国外电子元器件)1997 年第 7 期
1997 年 7 月
终止，重新开始一个新的振荡周期。由于零
Vc汇部分整形，从而获得驱动控制信号。为防
电流检测器的作用，使得初级电流首先达到
止次级振铃引起滞回比较器误触发，可在变
零，这样就保证了 PHI 信号占空比 0-100%
压器次级并一阻尼电阻，参见图 4。
变化时，均可以可靠的传输，变压器不会饱
限流比较器的门限电压为 0.5V，当 4 脚
和。载波周期为三倍单稳态输出脉宽，最高
SENSE 端子电压大于 0.5V 时，限流比较器
载频 600kHz，大大减小了脉冲变压器的成本
触发单稳态触发器，从而将输出关闭。为防
及体积。
止因分布电容充电引起的电流前沿尖峰误触
发，可在 4 脚外串一简单的 RC 滤波器。该滤
3 、 UC3725 的功能描述
波器电容应十分靠近 GND 端子，以防因地
环流误触发。过流时，触发的单稳态输出脉
3.1 特点
UC3725 为隔离高边 MOSFET 驱动器，
宽为:
Toff= 1. 28 XRoff X Coff
主要特点如下:
Roff、 Coff 分别为并接在 5 脚与地之间
·驱动电压为 9-15V;
·具有欠压保护;
的定进电阻、电容。 Toff 时间后触发器复位，
·可编程过流关断，可再启动;
输出使能。选择 Roff、 Coff 时应保证连续过
·连续驱动电流为 0.5A，脉冲驱动电流
流时 MOSFET 结温在安全范围内，若不使用
限流功能时，可将 4 脚接地， 5 脚开路。
最大为2A。
输出级可以提供连续 0.5A 或峰值2A
3.2 功能描述
UC3725 的基本组成如图 3 所示，主要包
的电流，欠压锁定电路保证输出电平不低于
含输入/输出级、电流限制/定时电路、欠压保
9V ，最高钳位到 15V。由于采用了推挽输出
护与使能电路。
结构，可以不使用门极并联电阻。实际应用
UC3725 的 A、 B 输人端(脚 7、脚 8) 分别
接脉冲变压器次级，该脉冲变压器初级连接
UC3724 的输出。输入端包含有一肖特基全
波整流桥，它将 UC3724 传递过来的调制波
整流，把能量储存在 3 脚 (Vcc ) 、 1 脚 (GND)
时应在门极串一小阻值电阻，以防振荡。
使能端 6 脚提供了一数字关断接口，可
根据情况使用。 J
4 、典型应用电路设计举例
之间的外接电容上而获得供电电压 Vα 。该
UC37241 UC3725 典型应用电路见图
电源电压比输认信号峰值电压低。接于 7 脚、
50 该电路中高边 MOSFET 用 UÇ~7241
8 脚之间的椭圆比舷幡将调制墟中幅值摇过
V自
·λ
UC372S 隔离驱动，低边 MOSFET 用
UC3725 直接驱动。该电路驱动参数如下:
.200mW. 平均门极驱动功率;
• 100kHz 的开关频率;
.也
αJTPUT
+vCJ:;
-
w
GRα，由
TIMIIING
图 3. UC3725 方框图
。UTPUT 一一「
卢
困 4 输入波形
2 在扎德pvegptz
们
SENSE
『-
43
MOSFET 隔离驱动器 UC3724/UC3725
/ ,-
U臼725
.飞
、
υC3724
。UTA
voc
OUTa
SGNO
问 NO
RT
CT
PHI
GND
1RF1 40
Q2
RS2
图 6 半桥应用电路
感系数为 2000mH/1000T:
Ni = 241 X 1(]I 1 2000
NT = llT
'取:6. B = O. 05T ，估算磁芯截
面积:
Ac = (1 3V X 556ns X 10000)1
(11 X O. 05) = O. 131cm2
RT
由此可选用相应磁芯，但必须
,
进行二次核算。此驱动电路在高边
·图 5 UC3724/UC3725 典型应用
e15V 供电;
供电电压达 300V 的应用中，当电
压变化率达 25kVIμs 时，来引起误导遇。
elkV 的隔离电压。
半桥应用电路见图 6，参数设计同上。
在此电路中选择 600证恒的载波频率
必须注意的是为避免 Q1 ， Q2 直通，半
单稳脉宽 T阿=
11 (3 X 600kHz)
=
556ns
电阻不同，以实现快关/缓开，该技术也可用
选定时电阻 Rt=2kn ， 则 Ct= 衍56-
150)ns/(0. 51 X 2k) = 398pF( 用 390pF)
取峰值磁化电流 30时，则励吆电感:
Lpγi
桥应用中电路关断时门极电阻与开通时门极
= (1 5 - 2) X 556nsl
3臼丑A=
241μH ， l 5V为供电电压， 2V 为管压降，取电
于减少 MOSFET 管体寄生二极管的反向恢
复电流。
咨询编号 :970709
..
UC1724
UC2724
UC3724
Isolated Drive Transmitter
FEATURES
DESCRIPTION
• 500mA Output Drive, Source or Sink
The UC1724 family of Isolated Drive Transmitters, along with the UC1725
Isolated Drivers, provide a unique solution to driving isolated power
MOSFET gates. They are particularly suited to drive the high-side devices
on a high-voltage H-bridge. The UC1724 devices transmit drive logic, and
drive power, to the isolated gate circuit using a low cost pulse transformer.
• 8 to 35V Operation
• Transmits Logic Signal Instantly
• Programmable Operating Frequency
• Under-Voltage Lockout
• Able To Pass DC Information Across
Transformer
• Up To 600kHz Operation
This drive system utilizes a duty-cycle modulation technique that gives instantaneous response to the drive control transistions, and reliably passes
steady-state, or DC, conditions. High frequency operation, up to 600kHz,
allows the cost and size of the coupling transformer to be minimized.
These devices will operate over an 8 to 35 Volt supply range. The dual high
current totem pole outputs are disabled by an uder-voltage lockout circuit to
prevent spurious responses during startup or low voltage conditions.
These devices are available in 8 pin plastic or ceramic dual-inline packages, as well as 16 pin SOIC package.
BLOCK DIAGRAM
Note: Pin numbers refer to DIL-8 packages.
04/99
UDG-92037
UC1724
UC2724
UC3724
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Source/Sink Current (Pulsed) . . . . . . . . . . . . . . . . . . . . . . . . 1A
Source/Sink Current (Continuous) . . . . . . . . . . . . . . . . . . . 0.5A
Ouput Voltage (Pins 4, 6). . . . . . . . . . . . . . . –0.3 to (VIN +0.3)V
PHI, RT, and CT inputs (Pins 1, 7, and 8) . . . . . . . . . –0.3 to 6V
Operating Junction Temperature (Note 2) . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
Note 1: All voltages are with respect to GND (Pin 2); all currents are positive into, negative out of part.
Note 2: Consult Unitrode Integrated Circuit Databook for thermal limitations and considerations of package.
Note 3: Pin numbers refer to DIL-8 packages.
DIL-8 (Top View)
J Or N Package
SOIC-16 (Top View)
DW Package
RECOMMENDED OPERATION CONDITIONS
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9V to +35V
Sink/Source Load Current (each output) . . . . . . . . . 0 to 500mA
Timing Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . 2kW to 10kW
Timing Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . 300pF to 3nF
Operating Temperature Range (UC1724) . . . –55°C<TA<125°C
Operating Temperature Range (UC3724) . . . . . . 0°C<TA<70°C
Note 4: Range over which the device is functional and
parameter limits are guaranteed.
ORDERING INFORMATION
TEMPERATURE RANGE
–55°C to +125°C
–25°C to +85°C
UC1724J
UC2724DW
UC2724N
UC3724DW
UC3724N
0°C to +70°C
PACKAGE
CDIP
SOIC-Wide
PDIP
SOIC-Wide
PDIP
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 20V, RT = 4.3kΩ, CT = 1000pF, no load on any
output and these specifications apply for: –55oC < TA < 125oC for the UC1724, –25oC < TA < 85oC for the UC2724, and
0oC < TA < 70oC for the UC3724. TA=TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Under-Voltage Lockout
Start-Up Threshold
VIN Rising
Threshold Hysteresis
7.75
9.5
V
0.4
1.0
1.5
V
1.9
2.25
µs
Retriggerable One-Shot
Initial Accuracy
TJ = 25°C
1.54
Temperature Stability
Over Operating TJ
1.0
Voltage Stability
VIN = 10 to 35V
0.2
2.9
µs
0.5
%/V
Operating Frequency
LLOAD = 1.4mH
100
150
200
kHz
Minimum Pulse Width
RT = 2k CT = 300pF
100
500
1200
ns
Operating Frequency
RT = 2k CT = 300pF LLOAD = 1.4mH
500
750
1100
kHz
2
UC1724
UC2724
UC3724
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 20V, RT = 4.3kΩ, CT = 1000pF, no load on any
output and these specifications apply for: –55oC < TA < 125oC for the UC1724, –25oC < TA < 85oC for the UC2724, and
0oC < TA < 70oC for the UC3724. TA=TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Phi Input (Control Input)
HIGH Input Voltage
2.0
V
LOW Input Voltage
HIGH Input Current
LOW Input Current
0.8
VIH = +2.4V
VIL = +0.4V
V
–220
–130
µA
–600
–300
µA
Delay to One-Shot
350
ns
Delay to Output
250
ns
0.4
V
Output Drivers
Output Low Level
Output High Level (Volts Below VCC)
Rise/Fall Time
ISINK = 50mA
0.3
ISINK = 250mA
0.5
2.1
V
ISOURCE = 50 mA
1.5
2.1
V
ISOURCE = 250 mA
1.7
2.5
V
No load
30
90
ns
CT = 1.4V
15
30
mA
Total Supply Current
Supply Current
Additional Information
Please refer to the following Unitrode application topics.
[1] Application Note U-127, Unique Chip Pair Simplified
Isolated High-Side Switch Drive by John A. O’Connor.
[2] Design Note DN-35, IGBT Drive Using MOSFET Gate
Drivers by John A. O’Conner.
UDG-92038
Figure 1. Typical application
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC1724J
OBSOLETE
CDIP
J
8
TBD
Call TI
Call TI
UC2724J
OBSOLETE
CDIP
J
8
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
UC2724N
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
UC3724DW
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC3724DWTR
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC3724J
OBSOLETE
CDIP
J
8
TBD
Call TI
Call TI
UC3724N
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
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U-130
APPLlCATlON NOTE
DEDICATED ICs SIMPLIFY BRUSHLESS DC SERVO AMPLIFIER DESIGN
John A. O’Connor
INTRODUCTION
Brushless DC motors have gained considerable commercial success in high end four quadrant servo systems, as
well as in less demanding, one and two quadrant requirements. Cost sensitive four quadrant applications thus far
have not fared as well. Designs which meet cost goals often suffer from poor linearity, and cumbersome protection
circuits to assure reliable operation in all four quadrants. Better performance en tails more complex circuitry and the
resulting additional components quickly increase size and cost. Part of the design challenge results from the lack of
control ICs tailored to four quadrant applications. The other major obstacle has been implementing a reliable and cost
effective high-side switch drive. With recently introduced integrated circuits in both areas, it is now possible to design
a rugged, low cost, four quadrant brushless DC servo amplifier with relatively low component count and cost.
related to accuracy, bandwidth, and quadrant transition
linearity.
SERVO AMPLIFIER REQUIREMENTS
First, let’s quickly review general servo amplifier requirements. Figure 1 displays motor speed versus torque,
depicting four possible modes of operation. While a
system may be considered four quadrant by simply
having the ability to operate reliably in all four modes, a
servo system generally requires controlled operation in
Most simple brushless DC amplifiers provide two quadrant control, since even the simplest output stages
(typically 3 phase bridge) allow rotation reversal. Note
that this is operation in quadrants one and three where
torque and rotation are in the same direction. This differs
from brush motor terminology where two quadrant control normally implies unidirectional rotation with torque
control in either direction. Although limited to a single
rotation direction, bidirectional torque allows servo velocity control, with rapid, controlled acceleration and
deceleration. These characteristics are well suited to
numerous applications such as spindle and conveyer
drives. With the two quadrant brushless DC amplifier,
there are no provisions other than friction to decelerate
the load, limiting the system to less demanding applications. Attempting to operate in quadrants two and four will
result in extremely nonlinear behavior, and under many
circumstances, severe damage to the output stage will
follow. This occurs because the two quadrant brushless
DC amplifier is unable to completely control current
during torque reversal.
TWO QUADRANT VERSUS FOUR QUADRANT
CONTROL
Figure 1 - Four Quadrants of Operation
all four modes. In addition, a smooth, linear transition
between quadrants is essential for high accuracy position and velocity control. The major performance differences between brushless DC servo amplifiers are
Figure 2 shows a three phase bridge output stage for
driving a brushless DC motor. Current flow is shown for
two quadrant control when operation is in quadrants one
or three. The switches commutate based on the motor’s
3-213
APPLICATION
U-130
NOTE
rotor position, typically using Hall effect sensors for
position feedback. Current is controlled by pulse width
modulating (PWM) the lower switches. Figure 3 shows
current flow if the direction of torque were reversed. The
upper switch essentially shorts the motor’s back EMF
(BEMF), causing current to quickly decay and reverse
direction. The current then rises to a value limited only by
the motor and drive impedance, yet is undetected by
supply or ground sense resistors. As the motor speed
rises, its BEMF proportionally increases, quickly escalating the potential circulating current. Even if the output
stage is built rugged enough to withstand this abuse, the
high uncontrolled current causes high uncontrolled torque,
making this technique unsuitable for most servo control
applications.
Figure 2 - Two Quadrant Chopping
By pulse width modulating the upper switches along with
the lower switches, uncontrolled circulating currents are
avoided. With both upper and lower switches off during
during the PWM off time, motor current will always decay
as shown in figure 4. Additionally, motor current always
flows through the ground sense resistor, allowing easy
detection for feedback. The remainder of this article will
feature this mode of control, as it is well suited for a
variety of demanding requirements. It should be noted
however, that a penalty in the form of reduced efficiency
must be paid for the improvement in control characteristics. With two switches operating at the PWM frequency,
as opposed to one with two quadrant control, switching
losses are nearly doubled. Ripple current is also increased which results in greater motor core loss. Although this is a small price to pay under most circumstances, extremely demanding applications may require
switching between two and four quadrant operation for
optimum efficiency and control.
Figure 3 - Two Quadrant Reversal
FOUR QUADRANT CONTROLLER
REQUIREMENTS
In addition to switching both upper and lower transistors,
a few supplementary functions are required from the
control circuit for reliable four quadrant operation. With
two quadrant switching, there is inherent dead time
between conduction of opposing upper and lower
switches, making cross conduction virtually impossible.
Four quadrant control immediately reverses the state of
opposing switches at torque reversal, thus requiring a
delay between turning the conducting device off and the
opposing device on to avoid simultaneous conduction
and possible output stage damage.
Figure 4 - Four Quadrant Reversal
When torque is reversed, energy stored in the rotating
load is transferred back to the power supply, quickly
charging the bus storage capacitor. A clamp circuit is
3-214
APPLICATION
NOTE
U-130
typically used to dissipate the energy and limit the
maximum bus voltage. As a second line of defense, an
over-voltage comparator is often employed to disable
the output if the bus voltage exceeds the clamp voltage
by more than a few volts.
CURRENT LOOP CONTROL TECHNIQUE
A transconductance amplifier is normally used for
brushless DC servo applications, providing direct control
of motor torque. Average current feedback is usually
employed rather than the more familiar peak current
UC3625
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3-215
U-130
APPLICATION NOTE
control for several reasons. Peak current control is
subject to subharmonic oscillation at the switching frequency for duty cycles above 50%. This condition is
easily circumvented in power supply applications by
summing an appropriately scaled ramp signal derived
from the PWM oscillator with the current sense signal.
This technique is commonly refered to as slope compensation. It can also be shown [3] that for a given inductor
current decay rate, which is essentially fixed in a power
supply application, there is an optimal compensation
level which will produce an output current independent of
duty cycle. Unfortunately, the inductor current decay rate
in a four quadrant motor control system varies with both
speed and supply voltage, making an optimal slope
compensation circuit fairly complex. Simpler circuits
which provide overcompensation assure stability but will
degrade accuracy. Furthermore, severe gain degradation occurs when inductor current becomes discontinuous regardless of slope compensation, causing large
nonlinearity at light load. This effect can be particularly
troublesome for a position control servo. Average current feedback avoids these problems, and is therefore
the preferred current control technique for servo
applications.
UC3625 BRUSHLESS DC CONTROLLER
Figure 5 shows the UC3625 block diagram. Designed
specifically for four quadrant operation, it minimizes the
external circuitry required to implement a brushless DC
servo amplifier. Flexible architecture and supplementary
features make the UC3625 well suited to less demanding applications as well. The UC3625 is described in
detail in references [4] and [7], however a few features
critical for reliable four quadrant operation should be
noted.
Cross conduction protection latches eliminate the possibility of simultaneous conduction of upper and lower
switches due to driver and switch turn-off delays. Additional analog delay circuits normally associated with this
function are eliminated allowing direct switch interface
and reduced component count. An absolute value buffer
following the current sense amplifier provides an average winding current signal suitable for feedback as well
as protection. An over-voltage comparator disables the
outputs if the bus voltage becomes excessive.
Although not absolutely necessary for four quadrant
systems, a few additional features enhance two quadrant operation and simplify implementation of switched
two / four quadrant control for optimized systems. A
direction latch with analog speed input prevents reversal
until an acceptably low speed is reached, preventing
output stage damage. Two or four quadrant switching
can be selected during operation with the Quad Select
input. A brake input provides current limited dynamic
braking, suitable for applications which require rapid
deceleration, but do not need tight servo control.
A SIMPLE BRUSHLESS DC SERVO AMPLIFIER
To demonstrate the relative simplicity with which a
brushless DC servo amplifier can be implemented, a 6
amp, off-line 115 VAC amplifier was designed and
constructed. Note that current and voltage rather than
horsepower are specified. Although theoretically capable of in excess of one horsepower, simultaneous high
speed and torque are typically not required in servo
applications, reducing the actual output power, and the
corresponding power supply requirement. Average current feedback is employed, providing good bandwidth
and power supply rejection, thus making the amplifier
suitable for many demanding requirements. A complete
amplifier schematic is shown in figure 6.
A high performance brushless servo motor from MFM
Technology, Inc. was used to evaluate the amplifier.
While most of the design is independent of motor parameters, several functions should be optimized for a particular motor and operating conditions. The motor used
has the following electrical specifications:
Model M - 178
Kr
RM
LM
Poles
79 oz.in./Amp
1.3 ohms
5.5 mH
18
OUTPUT STAGE DESIGN
Having selected a four quadrant control strategy, we
proceed to the output stage design, and work back to the
controller. High voltage MOSFETs are well suited to this
power level, however IGBTs may also be incorporated.
MOSFETs were selected to minimize size and complexity, since the body diodes can be used for the flyback
rectifiers. Unfortunately, this places greater demands on
the MOSFET, and increases the device dissipation. The
MOSFETs body diode is typically slower and stores
more charge than a discrete high speed rectifier, which
necessitates a slower turn-on and a corresponding increase in switching losses. These losses are partially
offset by choosing a MOSFET with sufficiently low conduction losses which offers the secondary benefits of
greater peak current capability and reduced thermal
3-216
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U-130
APPLICATION
U-130
NOTE
Figure 7 - UC3724/UC3725 Isolated MOSFET Driver
resistance. APT4030BN MOSFETs were selected for
the output stage to handle the 6 amp load currents while
providing good supply voltage transient immunity. Rated
at 400 volts and 0.30 ohms, they allow high efficiency
operation and have sufficient breakdown voltage for
reliable off-line operation.
While the lower three FETs require simple ground referenced drive, and are easily driven directly from the
UC3625 the design of the drive circuit for the upper three
FETs has traditionally been challenging. Discrete implementation of the required power supply and signal transmission is often bulky and expensive. In an effort to
reduce size and cost, critical functions are often omitted,
opening the door to potential reliability problems. Specifically designed for high-side MOSFET drive in motor
control systems, the UC3724 / UC3725 IC pair shown in
figure 7, offers a compact, low cost solution. A high
frequency carrier transmits both power and signal across
a single pulse transformer, eliminating separate DC/DC
converters, charge pump circuits, and opto-couplers.
Signal and power transmission function down to DC,
imposing no duty cycle or on-time limitations typical of
commonly used charge pump techniques. Under-voltage lockout, gate voltage clamp, and over current protection assure reliable operation.
Design of the upper driver is a straight forward procedure, and is described in detail in reference [5].
For this application, the driver is designed with the
following specifications:
500 V minimum isolation
300 kHz carrier frequency
10 Amp over-current fault
10 ms over-current off time
The pulse transformer uses a 1/2 inch O.D. toroid core
(Philips 204T250-3E2A) with a 15 turn primary and 17
turn secondary. For high voltage isolation, Teflon insulated wire is used for both primary and secondary.
To provide rapid turn-off for minimal switching losses,
with slower turn-on for di/dt control, a resistor/resistordiode network is used in place of a single gate resistor.
Although present generation MOSFETs can reliably
commutate current from an opposing FETs body diode
at high di/dt, the resulting high peak current and diode
snap limit practical circuits to a more moderate rate. This
increases dissipation, but significantly eases RFI filtering
and shielding, as well as relaxing layout constraints.
Additionally, a low impedance is maintained in the off
state while turn-on dv/dt is decreased, dramatically reducing the tendency for dv/dt induced turn on. The same
gate network is used for both upper and lower MOSFETs.
A sense resistor in series with the bridge ground return
provides a current signal for both feedback and current
limiting. This resistor, as well as the upper driver current
sense resistors should be non-inductive to minimize
ringing from high di/dt. Any inductance in the power
circuit represents potential problems in the form of additional voltage stress and ringing, as well as increasing
switching times. While impossible to eliminate, careful
3-218
U-130
APPLICATION NOTE
layout and bypassing will minimize these effects. The
output stage should be as compact as heat sinking will
allow, with wide, short traces carrying all pulsed currents.
Each half-bridge should be separately bypassed with a
low ESR/ESL capacitor, decoupling it from the rest of the
circuit. Some layouts will allow the input filter capacitor to
be split into three smaller values, and serve double duty
as the half-bridge bypass capacitors.
CONTROLLER SETUP
The UC3625 switching frequency is programmed with a
timing resistor and capacitor. Unless the motor’s inductance is particularly low, 20 kHz will provide acceptable
ripple current and switching losses while minimizing
audible noise.
(1)
F = 2 / R,,C,,
The relatively small oscillator signal amplitude requires
careful timing capacitor interconnect for maximum frequency stability. Circuit board traces should to be as
short as possible, directly connecting the capacitor between pins 25 and 15, with no other circuits sharing the
board trace to pin 15 (ground).
When tight oscillator stability is required, or multiple
systems must be synchronized to a master clock, the
circuit shown in figure 8 can be used. As shown, the
circuit buffers, and then differentiates the falling edge of
the master oscillator. The last stage provides the necessary current gain to drive the 47 ohm resistor in series
with the timing capacitor. If the master clock is from a
digital source, the first two stages are omitted, and the
clock signal is interfaced directly to the final stage through
a restive divider as shown. The slaves are programmed
to oscillate at a lower frequency than the master. The
pulse injected across the 47 ohm resistor causes the
oscillator to terminate its cycle prematurely, and thus
synchronize to the master clock.
LOW VALUE DIVIDER
Figure 9 - Balance Impedance Current Sense Input Circuits
The RC-Brake pin serves two functions: Brake command input (not used in this design), and tachometer /
digital commutation filter one-shot programming. Whenever the commutation state changes, the one-shot is
triggered, outputting a tach pulse and inhibiting another
commutation state change until the one-shot terminates.
The one-shot pulse width is programmed for approximately 1/2 the shortest commutation period.
(2)
where the shortest commutation
period = 20 / (RPM,,N,,,,,)
CURRENT SENSING AND FEEDBACK
For optimum current sense amplifier performance, the
input impedance must be balanced. Low value resistors
(100 to 500 ohm) are used to minimize bias current errors
and noise sensitivity. Additionally, if the sense voltage
must be trimmed, a low value input divider or a differential
divider should be used to maintain impedance matching,
as shown in figure 9.
Figure 8 - External Synchronization Circuit
An average current feedback loop is implemented by the
circuit shown in figure 10. With four quadrant chopping,
motor current always flows through the sense resistor.
When PWM is off however, the flyback diodes conduct,
3-219
APPLICATION NOTES
U-130
is suppressed using a NTC thermistor, while a bridge
rectifier and capacitive filter complete the high voltage
supply. A small 60 Hz. transformer supplies 15 Volts
through a three pin regulator to power the control and
drive circuits.
A bus clamp is easily designed around a UC3725
MOSFET driver, as shown in figure 11. As in the highside switch drive, the UC3725 assures reliable operation, particularly during power-up and power-down. The
divider current is set to 1 mA at the threshold, which is
a reasonable compromise between input bias current
error and dissipation. An additional tap programs the
over-voltage coast a few volts above the bus clamp,
saving a resistor and some dissipation while reducing
the tolerance between the bus clamp and the overvoltage coast. Setting the bus clamp discharge current
equivalent to the maximum motor current will assure
effective clamping under all conditions. The load resistor
value is therefore:
Figure 10 - Average Current Feedback Circuit Configuration
causing the current to reverse polarity through the sense
resistor. The absolute value amplifier cancels the current
polarity reversal by inverting the negative current sense
signal during the flyback period. The output of the
absolute value amplifier therefore is a reconstructed
analog of the motor current, suitable for protection as well
as feedback loop closure.
When the current sense output is used to drive a summing resistor as in this application example, the current
sense output impedance adds to the summing resistor
value. The internal output resistor and the amplifier
output impedance can both significantly effect current
sense accuracy if the external resistance is too low.
Although not specified, the total output impedance is
typically 430 ohms at 25 degrees C. Over the military
temperature range of -55 to +125 degrees C, the impedance ranges from approximately 350 to 600 ohms. An
external 2 k resistor will result in an actual 2.43 k summing resistance with reasonable tolerance. A higher
value external resistor and trim pot will be required if high
closed current loop accuracy is required.
The current sense output offset voltage is derived from
the +5 V reference voltage. By developing the command
offset from the +5 V reference, current sense drift over
temperature is minimized. The offset divider must be
trimmed initially to accommodate the current sense
amplifier offset tolerance.
POWER SUPPLY AND BUS CLAMP
Input power is filtered to reduce conducted EMI, and
transient protected using MOVs. Power-up current surge
where
J = inertia in Nm sec2
Wl = initial velocity in rad/sec
42 = final velocity in rad/sec
Note that if the deceleration time approaches the load
resistor’s thermal time constant, a higher power resistor
will be required to maintain reliability.
CURRENT LOOP OPTIMIZATION
The block diagram of the current control loop is shown
in figure 12. The current sense input filter has minimal
affect on the loop and can be ignored, since the filter pole
must be much higher than the system bandwidth to
maintain waveform integrity for over-current protection.
The current sense resistor R,, is chosen to establish the
peak current limit threshold, which is typically set 20%
higher than the maximum current command level to
provide over-current protection during abnormal conditions. Under normal circumstances with a properly
compensated current loop, peak current limit will not be
exercised. The input divider network provides both
offset adjustment and attenuation, with R,, selected to
accomodate the current command signal range.
3-220
U-130
APPLICATION NOTE
Figure 11 - Power Supply and Bus Clamp
All PWM circuits are prone to subharmonic oscillation if
the modulation comparator’s two input waveform slopes
are inappropriately related. This behavior is most common in peak current feedback schemes, where slope
compensation is typically required to achieve stability.
Average current feedback systems will exhibit similar
behavior if the current amplifier gain is excessively high
at the switching frequency. As described by Dixon [2] to
avoid subharmonic oscillation for a single pole system:
The amplified inductor current downslope at one input of
the PWM comparator must not exceed the oscillator
ramp slope at the other comparator input. This criterion
sets the maximum current amplifier gain at the switching
frequency, and indirectly establishes the maximum current loop gain crossover frequency.
A voltage proportional to motor current, which is the
inductor current, is generated by the current sense
resistor and the current sense amplifier circuitry internal
to the UC3625 This waveform is amplified and inverted
by the current amplifier and applied to the PWM comparator input. Due to the signal inversion, the motor
3-221
Figure 12 - Current Loop Block Diagram
U-130
APPLICATION NOTE
Where: V, is the oscillator ramp peak to peak voltage
(1.2 V for the UC3625)
T, is the switching period
1, is the switching frequency
The maximum current amplifier gain at the switching
frequency is determined by setting the amplified inductor
current downslope equal to the oscillator ramp slope.
GAIN
(dB)
(5)
PHASE
(deg)
Figure 13 - Open Loop Gain and Phase Versus Frequency
current downslope appears as an upslope as shown in
figure 12. To avoid subharmonic oscillation, the current
amplifier output slope must not exceed the oscillator
ramp slope. A motor control system typically operates
over a wide range of output voltages, and is usually
powered from an unregulated supply. The operating
conditions which cause the greatest motor current
downslope must be determined in order to determine the
maximum current amplifier gain which will maintain
stability. When four quadrant chopping is used, the
inductor discharge rate is described by:
Motor Current Downslope =
The greatest discharge slope therefore occurs when the
supply and BEMF voltages are maximum.
The maximum BEMF and supply voltage for the design
example are 87 and 175 Volts respectively, which translates to a motor speed of 1500 RPM, and a high-line
supply voltage of 125 Volts AC. Using equation (5) with
an oscillator voltage of 1.2 volts peak to peak at a
frequency of 20 kHz, the maximum value for G,, is 20.2,
or 26 dB. The current sense amplifier’s gain of two is also
part of G,,. With R, equal to 2.43 k, 20 k is selected for R,
to allow for tolerances, resulting in an actual G,, of 16.5,
or 24 dB.
The small-signal control to output gain of the current loop
power section is described by:
Note that the factor of two in the numerator is a result of
four quadrant chopping which only utilizes one-half of
the modulator’s input range for a given quadrant of
operation.
The overall open loop gain of the current loop is the
product of the actual current amplifier gain and the
control to output gain of the power circuit. The result is set
equal to one to solve for the loop gain crossover
frequency, f,:
The oscillator ramp slope is simply:
Oscillator Ramp Slope =
3-222
U-130
APPLICATION NOTE
At high line, where the supply is 175 Volts DC, f, is 3.5
kHz. The crossover frequency drops to 2.8 kHz at low
line, where the supply is approximately 140 Volts DC. If
greater bandwidth is required, the current amplifier gain
must be increased, requiring a corresponding increase
in switching frequency to satisfy equation (5).
Up to this point the motor’s resistance (R,) has been
ignored. This is valid since L predominates at the
switching frequency. The motor’s electrical time constant L,JRhn, creates a pole, which is compensated for by
placing zero R,C, at the same frequency. Additionally,
pole R&CR /(C,,+C,J is placed at fs to reduce sensitivity to noise spikes generated during switching transitions. The filter pole at fs also reduces the amplitude and
slope of the amplified inductor current waveform, possibly suggesting that the current amplifier gain could be
increased beyond the maximum value from equation (5).
Experimentally increasing G,, may incur subharmonic
oscillation however, since equation (5) is only valid for a
system with a single pole response at f,. For the design
example, standard values are chosen for C,, and C,, of
0.22 PF and 390 pF respectively, placing the zero at 36
Hz, and the pole at 20 kHz. Figure 13 shows open loop
gain and phase verses frequency.
At very light loads, the motor current will become discontinuous - motor current reaches zero before the switching
period ends. At this mode boundary, the power stage
gain suddenly decreases, and the single pole characteristic of continuous mode operation with its 90 degree
phase lag disappears. The current loop becomes more
stable, but much less responsive. Fortunately, the high
gain of current amplifier is sufficient to maintain acceptable closed current loop gain and phase characteristics
at typical outer velocity and/or position loop crossover
frequencies.
R, /(R,,+R,,). For the design example, the overall
amplifier transconductance is 1.25 amps/volt, allowing
full scale current (6 amps) with a 5 volt input command.
BIPOLAR TO SIGN/MAGNITUDE CONVERSION
The servo amplifier as shown in figure 6 requires a
separate sign and magnitude input command. This is
convenient for many microcontroller based systems
which solely utilize digital signal processing for servo
loop compensation. Analog compensation circuits however, usually output a bipolar signal and require conversion to sign/magnitude format to work with this amplifier.
The circuit shown in figure 14 employs a differential
amplifier for level shifting and ground noise rejection, and
an absolute value circuit with polarity detection for conversion to sign/magnitude format. The current command
signal is slightly attenuated and level shifted up 5 volts to
allow single supply operation. The input divider circuit
has been slightly modified from figure 9 to restore gain
and provide a suitable offset adjustment range. Precision resistors (1%) should be used for both the differential amplifier and the absolute value circuit to minimize
DC offset errors. Figure 15 shows approximately 2 Amp
peak motor current with a 500 Hz sinwave command.
Motor current follows the input command with minimal
phase lag, however some crossover distortion is present.
This is not crossover distortion in the traditional sense,
rather it is simply a fixed off-time caused by the cross
conduction protection circuitry. Since this distortion is
current amplitude independent, and decreases with frequency, its effect on overall servo loop performance is
minimal.
When the current loop is closed, the output voltage of the
current sense amplifier (2V,,) is equal to the current
programming voltage (V,,) at frequencies below the
crossover frequency. The closed current loop
transconductance is simply:
At the open loop crossover frequency, the
transconductance rolls off and assumes a single pole
characteristic. The input divider network attenuates the
current command signal to provide compatibility with
typical servo controller output voltages, and decreases
the closed loop transconductance by the ratio of
Figure 14 - Bipolar to Sign/Magnitude
3-223
U-130
APPLICATION NOTE
When the direction command is reversed while the motor
is rotating, operation switches to quadrant two or four,
shifting the modulator’s maximum output voltage point
from full duty cycle to zero duty cycle.
Figure 15 - 5OOHz Sine Wave Command and Output Currents
DIRECT DUTY CYCLE CONTROL
There are many less demanding brushless DC servo
applications which do not need a transconductance
amplifier function yet require controlled operation in all
four quadrants. For these systems, direct duty cycle
control, also known as voltage mode control is often
employed. Note that this is not voltage feedback, which
requires additional demodulation circuitry to develop a
feedback signal. With direct duty cycle control the amplifier simply provides open loop voltage gain. This technique is particularly advantageous when a microcontroller
is used for servo loop compensation. By outputting a
PWM signal directly, a digital to analog conversion is
eliminated along with the analog pulse width modulator.
While the simplicity of this technique is appealing, there
are two major problems which must be addressed. The
first and less severe problem is the complete lack of
power supply rejection. Good supply filtering will often
reduce transients to acceptable levels, while the servo
loop compensates for slow disturbances. The second
and more troublesome predicament is the output
nonlinearity which occurs when transitioning between
quadrants. This is best illustrated by examining the DC
equations for the two possible cases.
Note that the gain does not change, only the reference
point has shifted. This occurs because the modulator
only has a single quadrant control range -four quadrant
operation results from the output control logic which is
after the modulator. With the transconductance amplifier
previously described, the error amplifier quickly slews
during quadrant transitions, providing four quadrant control with minimal disturbance. When direct duty cycle
control is used however, the servo loop filter must slew
to maintain control. Unfortunately, this causes an immediate loop disturbance, with the greatest severity at the
duty cycle extremes. This behavior can greatly effect the
performance of an analog compensated servo, and
therefore limits such systems to lower performance
requirements.
With a microcontroller providing the servo loop compensation, nonlinear duty cycle changes can be accommodated, restoring linearity when transitioning between
quadrants. Although nonlinear behavior still occurs when
motor current becomes discontinuous, the effect on
overall system performance is usually minimal. By correcting for quadrant transition nonlinearities, the advantages of an all digital interface can be exploited without
severely degrading system performance. The control
system is fully digital right up to the output stage, where
the motor’s inductance finally makes the conversion to
analog by integrating the output switching waveform.
The circuit shown in figure 16 uses a PWM input from a
microcontroller to set the output duty cycle and synchronize the oscillator, while another input controls direction.
When operating in either quadrant one or three, rotation
and torque are in the same direction. Assuming operation is above the continuous/discontinuous current mode
boundary, the output voltage is described by:
where
D = PWM duty cycle
Figure 16 - Digital PWM Interface
3-224
APPLICATION NOTE
U-130
Complete line isolation can easily be achieved by using
opto-couplers. Although the performance of this technique falls short of the transconductance amplifier, the
circuitry’s simplicity while maintaining all of the protection
features of the UC3625 make it well suited to many cost
sensitive applications.
UNITRODE DATA SHEETS
7.
UC3625
8.
UC3724
9.
UC3725
SUMMARY
ADDITIONAL REFERENCES:
The application example demonstrates the relative simplicity in implementing a brushless DC transconductance
servo amplifier using the latest generation controller and
driver ICs. For less demanding applications, direct duty
cycle control using a dedicated controller provides size
and cost reduction, without sacrificing protection features. While more and more control functions are implemented in microcontrollers today, the task of interfacing
to output devices, and providing reliable protection under
all conditions will remain a hardware function. Dedicated
integrated circuits offer considerable improvement over
the discrete solutions used in the past, reducing both size
and cost, while enhancing reliability.
10. APT4030BN Data Sheet, Advanced Power Technology, Bend OR
11. M-178 Brushless Motor DataSheet, MFM Technology, Inc., Ronkonkoma NY
12. “DC Motors - Speed Controls - Servo Systems”,
Electro-craft Corporation, Hopkins MN
REFERENCES
Unitrode Publications:
1.
W. Andreycak, “A New Generation of High Performance MOSFET Drivers Features High Current,
High Speed Outputs”, Application Note # U-126
2.
L. Dixon, “Average Current Mode Control of Switching Power Supplies”, Unitrode Power Supply Design Seminar SEM700, topic 5
3.
B. Holland, “Modelling, Analysis and Compensation of the Current-Mode Converter”, Application
Note # U-97
4.
B. Neidorff, “New Integrated Circuit Produces Robust, Noise Immune System For Brushless DC
Motors”, Application Note # U-115
5.
J. O’Connor, “Unique Chip Pair Simplifies Isolated
High Side Switch Drive”, Application Note # U-127
6.
C. de Sa e Silva, “A Simplified Approach to DC
Motor Modeling For Dynamic Stability Analysis”,
Application Note # U-120
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3-225
IMPORTANT NOTICE
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to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated
DN-35
Design Notes
IGBT DRIVE USING MOSFET GATE DRIVERS
John A. O’Connor
IGBT Drive Requirements
opposing devices can occur in such circuits, often
with catastrophic results if proper gate drive and
layout precautions are not followed. This behavior is
caused by parasitic collector to gate (miller)
capacitance, effectively forming a capacitive divider
with the gate to emitter capacitance and thus
inducing a gate to emitter voltage as illustrated in
figure 1.
Insulated gate bipolar transistors (IGBTs) are
gaining considerable use in circuits requiring high
voltage and current at moderate switching
frequencies. Typically these circuits are in motor
control, uninterruptible power supply and other
similar inverter applications. Much of the IGBTs
popularity stems from its simple MOSFET-like gate
drive requirement. In comparison to bipolar
transistors which were formally used in such
designs, the IGBT offers a considerable reduction in
both size and complexity of the drive circuitry.
Recent improvements in IGBT switching speed has
yielded devices suitable for power supply
applications, thus IGBTs will compete with
MOSFETs for certain high voltage applications as
well. Many designers have therefore turned to
MOSFET drivers for their IGBT drive requirements.
When high off-state dv/dt is not present, the IGBT
can be driven like a MOSFET using any of the gate
drive circuits in the UC37XX family as well as from
the drivers internal to many switching power supply
controllers. Normally 15 volts is applied gate to
emitter during the on-state to minimize saturation
voltage. The gate resistor or gate drive current
directly controls IGBT turn-on, however turn-off is
partially governed by minority carrier behavior and
is less effected by gate drive.
There are several techniques which can be
employed to eliminate simultaneous conduction
when high off-state dv/dt is present. The most
important technique, which should always be
employed, is a Kelvin connection between the IGBT
emitter and the driver’s ground. High di/dt present in
the emitter circuit can cause substantial transient
voltages to develop in the gate drive circuit if it is not
properly referenced. The Kelvin drive connection
also minimizes the effective driver impedance for
maximum attenuation of the dv/dt induced gate
voltage. This requirement adds complication to
driving multiple ground referenced IGBTs due to
finite ground circuit impedance. Substantial voltages
may develop across the ground impedance during
switching, requiring level shift or isolation circuitry at
the command signal to allow Kelvin drive circuit
connections.
Figure 1. High dv/dt at the collector couples to the gate
through parasitic capacitance.
IGBT drive requirements can be divided into two
basic application categories: Those that do not apply
high dv/dt to the collector/emitter of the IGBT when
it is off, and those that do. Examples of the former
are buck regulators and forward converters, where
only one switch is employed or multiple switches are
activated synchronously. High dv/dt is applied
during the off-state in most bridge circuits such as
inverters and motor controllers, when opposing
devices are turned on. Simultaneous conduction of
Bipolar Gate Driver
A Kelvin connected unipolar driver may often be
adequate at lower switching speeds, however
negative gate bias must be applied during the
off-state to utilize the IGBT at higher rates. This
becomes apparent when one considers that the gate
to emitter threshold voltage drops to approximately
1.4 volts at high temperature. With high dv/dt at the
collector, a very low and impractical drive
4-11
Design Notes
insufficient supply voltage is present. The positive
supply,+Vcc, is normally 15 to 16 volts and the
negative supply, -VEE, typically ranges between -5
and -15 volts depending on circuit conditions. A PNP
level shift circuit references the drive signal to
ground. Opto-couplers are also commonly
employed, and may be interfaced directly to the gate
driver by referencing the signal to the negative
supply. Note that this is a very demanding
application for optocouplers, and only devices rated
for high CMRR should be used.
impedance is required to assure that the device
remains off. By utilizing a negative turn-off bias, an
adequate voltage margin is easily achieved,
allowing the use of a more practical gate drive
impedance. Fortunately most gate drivers have
sufficient voltage capability to be used with bipolar
Isolated Gate Driver
A bipolar IGBT gate driver with over-current
protection can be implemented using the
UC3724/UC3725 isolated gate driver pair as shown
in figure 3. The UC3724/UC3725 transmits both
power and signal across a small pulse transformer,
thereby achieving low cost, high voltage isolation.
An additional transformer winding develops a
negative voltage, providing a bipolar supply for the
UC3708. The UC3724/UC3725 can also be used for
circuits which do not require negative turn-off bias
by simply eliminating the negative supply and
external driver, and using the UC3725 to drive the
IGBT gate directly. Application note U-127 covers
the UC3724/UC3725 in depth.
Figure 2. Bipolar IGBT gate drive using the U3708
power supplies. The UC3708 shown in figure 2 can
deliver up to 6 amps peak with both output’s
paralleled, and is particularly suited to driving IGBTs.
For added reliability during power sequencing, its
output’s “self bias”, actively sinking current when
Figure 3. Power and signal are coupled to the UC3708 through the UC3724 / UC3725 Isolated Gate Driver Pair.
UNITRODE CORPORATION
7 CONTINENTAL BLVD.. MERRIMACK. NH 03054
TEL (603) 424-2410 l FAX (603) 424-3460
4-12
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated
UC1725
UC2725
UC3725
Isolated High Side FET Driver
FEATURES
DESCRIPTION
•
Receives Both Power and Signal Across
the Isolation Boundary
•
9 to 15 Volt High Level Gate Drive
•
Under-voltage Lockout
The UC1725 and its companion chip, the UC1724, provide all the necessary features to drive an isolated MOSFET transistor from a TTL input signal. A unique modulation scheme is used to transmit both power
and signals across an isolation boundary with a minimum of external
components.
•
Programmable Over-current Shutdown
and Restart
•
Output Enable Function
Protection circuitry, including under-voltage lockout, over-current shutdown, and gate voltage clamping provide fault protection for the MOSFET. High level gate drive is guaranteed to be greater than 9 volts and
less than 15 volts under all conditions.
Uses include isolated off-line full bridge and half bridge drives for driving motors, switches, and any other load requiring full electrical isolation.
The UC1725 is characterized for operation over the full military temperature range of -55°C to +125°C while the UC2725 and UC3725 are
characterized for -25°C to +85°C and 0°C to +70°C respectively.
BLOCK DIAGRAM
UDG-92051-1
1/94
UC1725
UC2725
UC3725
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (pin 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Power inputs (pins 7 & 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output current, source or sink (pin 2)
DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5 us) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Enable and Current limit inputs (pins 4 & 6). . . . . . . . -0.3 to 6V
Power Dissipation at TA ≤ 25°C (DIL-8) . . . . . . . . . . . . . . . . 1W
Power Dissipation at TA ≤ 25°C (SO-14) . . . . . . . . . . . . 725mW
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . 300°C
PLCC-20 (Top View)
Q Package
Note 1: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the specified terminals (pin numbers refer to DIL-8 package).
Note 2: See Unitrode Integrated Circuits databook for
information regarding thermal specifications and limitations of
packages.
DIL-8 (Top View)
J Or N Package
SOIC-16 (Top View)
DW Package
PACKAGE PIN FUNCTION
FUNCTION
PIN
N/C
ISENSE
N/C
Timing
Enable
N/C
Input A
N/C
Input B
Gnd
VCC
N/C
Output
1
2
3-5
6
7
8-9
11
12-14
15
16
17
18-19
20
DIL-16 (Top View)
JE Or NE Package
ELECTRICAL CHARACTERISTICS: (Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for
UC1725; -25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) =
0 to 15V, RT=10k, CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER INPUT SECTION (PINS 7 & 8)
Forward Diode Drop, Schottky Rectifier
IF = 50ma
.55
.7
V
IF = 500ma
1.1
1.5
V
Input bias current
VPIN4 = OV
-1
-10
µA
Threshold voltage
Delay to outputs
VPIN4 = 0 to 1V
CURRENT LIMIT SECTION (PIN 4)
0.4
0.5
0.6
V
100
250
ns
TIMING SECTION (PIN 5)
Output Off Time
27
30
33
µs
Upper Mono Threshold
6.3
7.0
7.7
V
Lower Mono Threshold
1.9
2.0
2.3
V
7.0
Vcc/2
8.0
V
HYSTERESIS AMPLIFIER (PINS 7 & 8)
Input Open Circuit Voltage
Inputs (pins 7 & 8), Open Circuited, TA= 25°C
Input Impedance
TA = 25°C
Hysteresis
Delay to Outputs
VPIN7 - VPIN8 = VCC + 1V
2
23
28
33
kΩ
26.5
2*Vcc
100
30.5
V
300
ns
UC1725
UC2725
UC3725
ELECTRICAL
CHARACTERISTICS (cont.)
(Unless otherwise stated, these specifications apply for -55°C≤TA≤+125°C for UC1725;
-25°C≤TA≤+85°C for UC2725; 0°C≤TA≤+70°C for UC3725; VCC (pin 3) = 0 to 15V, Rt=10k,
CT=2.2nf, TA =TJ, pin numbers refer to DIL-8 package.)
PARAMETER
ENABLE SECTION (PIN 6)
TEST CONDITIONS
High Level Input Voltage
MIN
2.1
TYP
MAX
UNITS
1.4
V
Low Level Input Voltage
1.4
.8
V
Input Bias Current
-250
-500
µA
OUTPUT SECTION
Output Low Level
Output High Level
Rise/Fall Time
IOUT = 20mA
0.35
0.5
V
IOUT = 200mA
0.6
2.5
V
IOUT = -20mA
IOUT = -200mA
13
12
13.5
13.4
V
V
VCC = 30V, Iout = -20mA
14
15
V
CT = 1nf
30
60
ns
20mA, VCC = 8V
0.8
1.5
V
UNDER VOLTAGE LOCKOUT
UVLO Low Saturation
Start-up Threshold
11.2
12
12.6
V
Threshold Hysteresis
.75
1.0
1.12
V
12
16
ma
TOTAL STANDBY CURRENT
Supply Current
APPLICATION AND OPERATION INFORMATION
add a damping resistor across the transformer secondary
to minimize ringing and eliminate false triggering of the
hysteresis amplifier as shown in Figure 3.
INPUTS: Figure 1 shows the rectification and detection
scheme used in the UC1725 to derive both power and
signal information from the input waveform. Vcc is generated by peak detecting the input signal via the internal
bridge rectifier and storing on a small external capacitor,
C1. Note that this capacitor is also used to bypass high
pulse currents in the output stage, and therefore should
be placed direclty between pins 1 and 3 using minimal
lead lengths.
UDG-92048
FIGURE 2 - Input Waveform (DIL-8 Pin 7 - Pin 8)
UDG-92047
FIGURE 1 - Input Stage
Signal detection is performed by the internal hysteresis
comparator which senses the polarity of the input signal
as shown in Figure 2. This is accomplished by setting
(resetting) the comparator only if the input signal exceeds Vcc (-Vcc). In some cases it may be necessary to
UDG-92049
FIGURE 3 - Signal Detection
3
UC1725
UC2725
UC3725
capacitor and resistor as shown in Figure 4. This, in turn,
controls the output off time according to the formula:
TOFF= 1.28 • RC.
If current limit feature is not required, simply ground pin 4
and leave pin 5 open.
OUTPUT: Gate drive to the power FET is provided by a
totem pole output stage capable of sourcing and sinking
currents in excess of 1 amp. The undervoltage lockout
circuit guarantees that the high level output will never be
less than 9 volts. In addition, during undervoltage lockout, the output stage will actively sink current to eliminate
the need for an external gate to source resistor. High
level output is also clamped to 15 volts. Under high capacitive loading however, the output may overshoot 2 to
3 volts, due to the drivers’ inabitlity to switch from full to
zero output current instantaneously. In a practical circuit
this is not normally a concern. A few ohms of series gate
resistance is normally required to prevent parasitic oscillations, and will also eliminate overshoot at the gate.
UDG-92050
FIGURE 4 - Current Limit
CURRENT LIMIT AND TIMING: Current sensing and
shutdown can be implemented directly at the output using the scheme shown in Figure 4. Alternatively, a current
transformer can be used in place of RSENSE. A small RC
filter in series with the input (pin 4) is generally needed to
eliminate the leading edge current spike caused by
parasitic circuit capacitances being charged during turn
on. Due to the speed of the current sense circuit, it is
very important to ground CF directly to Gnd as shown to
eliminate false triggering of the one shot caused by
ground drops.
ENABLE: An enable pin is provided as a fast, digital input that can be used in a number of applications to directly switch the output. Figure 6 shows a simple means
of providing a fast, high voltage translation by using a
small signal, high voltage transistor in a cascode configuration. Note that the UC1725 is still used to provide
power, drive and protection circuitry for the power FET.
One shot timing is easily programmed using an external
UDG-92052
UDG-92053
FIGURE 6 - Using Enable Pin as a High Speed Input
Path
FIGURE 5 - Output Circuit
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4
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
UC2725J
OBSOLETE
CDIP
J
8
TBD
Call TI
Call TI
UC3725DW
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC3725DWTR
OBSOLETE
SOIC
DW
16
TBD
Call TI
Call TI
UC3725N
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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