9 81 51 44 71 85 ， QQ ： IT6601 43 41 5 HEAC Transmitter and Receiver with CEC Controller ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 Preliminary Datasheet www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 General Description The IT6601 is an HEAC transmitter and receiver with CEC function, fully compliant with HDMI1.4. The IT6601 supports 100Base-TX IEEE802.3 Ethernet standard, IEC60958-1 audio standard and HDMI1.4 CEC feature. QQ ： 71 44 51 81 9 HDMI Ethernet and Audio Return Channel (HEAC) use signal pair composed of the HEAC- and HEAC+ lines or use only the HEAC+ line for ARC function. The HEAC transmitter is composed HEC transmitter and ARC transmitter. HEC transmitter employs MLT-3 signaling in differential mode. ARC transmitter employs a single SPDIF signal in common mode or signal mode. All combinations of HEC and ARC are allowed. 18 66 43 41 5 85 ， The IT6601 integrates a fully-compliant CEC PHY, which when operating with an external MCU provides full CEC supports. CEC controller handles arbitration, flow control, frame re-transmission, frame validation error detection and error handling. Features 合 讯 科 技 有 限 公 司 ， Support HEC transmitter and receiver in differential mode. Support ARC transmitter and receiver in common mode. Support ARC transmitter and receiver in signal mode. Support HEAC (HEC and ARC) transmitter and receiver. Support HEAC (HEC and ARC) PHY enabled by hardware trap mode. Support HEAC (HEC and ARC) PHY enabled by software control mode. Support CEC PHY controller Support four serial programming device addresses. 28-pin SSOP package 深 圳 市 金 www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 26 25 24 23 22 21 20 19 18 17 16 15 51 27 43 41 5 85 ， QQ ： 71 44 28 81 9 Pin Diagram 3 4 5 6 7 ， 2 8 9 10 11 12 13 14 Figure 1. IT6601 pin diagram 深 圳 市 金 合 讯 科 技 有 限 公 司 1 18 66 SSOP-28 Top View www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 Pin Description HEAC Analog Front-End Interface Pins Analog HEAC positive I/O HEAC 3 HEACN Analog HEAC negative I/O HEAC 2 ETH_INP Analog Ethernet positive input MLT-3 27 ETH_INN Analog Ethernet negative input MLT-3 26 ETH_OUTP Analog Ethernet positive output MLT-3 24 ETH_OUTN Analog Ethernet negative output MLT-3 23 Pin Name Direction Description CEC I/O CEC PHY I/O pin(5v-tolerant) Schmitt 5 SPDIFI Input S/PDIF audio input LVTTL 21 SPDIFO Output S/PDIF audio output LVTTL 18 SCAN_CLK Input Scan test clock LVTTL 6 81 HEACP 9 Pin No. 51 Type 44 Description 71 Direction Digital Pins Pin No. 18 66 43 41 5 85 ， Type QQ ： Pin Name ， Programming Pins Direction Description SYSRSTN Input Hardware reset pin. Active LOW(5v-tolerant) PCSCL Input Serial programming clock for chip 司 Pin Name Type Pin No. 14 LVTTL 15 LVTTL 17 LVTTL 10, 16 HEC enable. Active HIGH LVTTL 7 ARC_TX_EN Input ARC_TX enable. Active HIGH LVTTL 8 ARC_RX_EN Input ARC_RX enable. Active HIGH LVTTL 9 ENTEST Must be tied low via a resistor LVTTL 13 技 有 限 公 Schmitt programming (5V-tolerant) I/O Serial programming data for chip 讯 科 PCSDA programming (5V-tolerant) 市 金 合 Input 圳 PCADR1 PCADR0 Control of serial programming device address: "00": 0x9C "01": 0x9E 深 "10": 0xAC “11”: 0xAE HEC_EN www.ite.com.tw Input Input Aug-2010 Rev:0.2 7/30 IT6601 Power/Ground Pins Description Type Pin No. IVDD Digital logic power(1.8V) Power 11, 20 IVSS Digital logic ground Ground 12, 19 OVDD I/O pin power Power 1, 22, 28 OVSS I/O pin ground Ground 4, 25 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Pin Name www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 Block Diagram The IT6601 provides complete solutions for HDMI1.4 system, supporting HEAC transmitter and Figure 2. Functional block diagram of IT6601 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 receiver. The functional block diagram of the IT6601 is shown in Figure 2, which describes clearly the data flow. www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 CEC Processing Flow 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 The IT6601 integrates a fully-compliant CEC PHY, which when operating with an external MCU provides full CEC supports. Refer to Figure 3. In the case of receiving commands, the incoming CEC Signals are decode and the results are stored in CEC buffer, which includes a header block, an opcode block and operand block. The external MCU could then read the CEC commands to determine how the IT6601 should respond. 深 圳 市 金 合 讯 科 Figure 3. CEC block diagram of IT6601 In the case of issuing a command, the external MCU first writes proper header, opcode and operands into the CEC buffer. The CEC I/O translates data packet into CEC-compliant signals and drives them onto the CEC bus. www.ite.com.tw Aug-2010 Rev:0.2 7/30 IT6601 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Package Dimensions www.ite.com.tw Aug-2010 Rev:0.2 7/30