9 81 51 44 71 85 ， QQ ： IT6613 ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 HDMI 1.4 Transmitter with 3D Support www.ite.com.tw Oct-2010 Rev:0.9 1/36 IT6613 General Description 71 44 51 81 9 The IT6613 is a high-performance HDMI transmitter, fully compatible with HDMI 1.3, compatible with HDMI 1.4a 3D and HDCP 1.4 compliance and also backward compatible to DVI 1.0 specifications. The IT6613 supports color depth of up to 36 bits (12 bits/color) and ensures robust transmission of high-quality uncompressed video content, along with state-of-the-art uncompressed and compressed digital audio content such as DTS-HD and Dolby TrueHD in DVD/HD-DVD/Bluray players and settop boxes. The IT6613 also supports all the primary 3D formats which are compliant with HDMI1.4a 3D Specification 43 41 5 85 ， QQ ： Aside from the various video output formats supported, the IT6613 also encodes and transmits up to 8 channels of I2S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. In addition, an S/PDIF input port takes in compressed audio of up to 192kHz frame rate, while Super Audio Compact Disc (SACD) is supported through dedicated DSD ports (Direct Stream Digital ports) at up to 88.2kHz one-bit audio. The High-Bit Rate (HBR) audio is also provided by the IT6613 in two interfaces: with the four I2S input ， 18 66 ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported at up to 768kHz. 技 有 限 公 司 Each IT6613 chip comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.4 standard so as to provide secure transmission of high-definition content. Users of the IT6613 need not purchase any HDCP keys or ROMs. 合 市 金 Features 讯 科 The IT6613 is pin compatible with the CAT6613, the previous generation HDMI 1.3 transmitter. 深 圳 HDMI 1.4 transmitter Pin compatible with CAT6613 Compliant with HDMI 1.3, HDMI 1.4a 3D, HDCP 1.4 and DVI 1.0 specifications Supporting link speeds of up to 2.25Gbps (link clock rate of 225MHz). Supporting all the primay 3D formats which are compliant with HDMI1.4a 3D Specification Supporting 3D video up to1080P@50/59.95/60Hz, [email protected]/24/29.97/30Hz, 1080i@50/59.94/60/Hz, [email protected]/24/29.97/30Hz, 720P@50/59.94/60Hz Supporting formats: Framing Packing, Side-by-Side ( half ), Top-and-Bottom. Various video input interface supporting digital video standards such as: 24/30/36-bit RGB/YCbCr 4:4:4 www.ite.com.tw Oct-2010 Rev:0.9 2/36 IT6613 9 81 51 85 ， QQ ： 71 44 16/20/24-bit YCbCr 4:2:2 8/10/12-bit YCbCr 4:2:2 (CCIR-656) 12/15/18-bit double data rate interface (data bus width halved, clocked with both rising and falling edges) for RGB/YCbCr 4:4:4 Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit/10-bit component to 8-bit Support Gammat Metadata packet Digital audio input interface supporting up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and smaple sizes of 16~24 bits S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S ， 司 公 限 技 有 讯 科 深 圳 合 市 金 18 66 43 41 5 interface or the S/PDIF interface, with frame rates as high as 768kHz Support for 8-channel DSD audio through dedicated inputs Compatible with IEC 60958 and IEC 61937 Audio down-sampling of 2X and 4X Software programmable, auto-calibrated TMDS source terminations provide for optimal source signal quality Software programmable HDMI output current level MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK. Integrated pre-programmed HDCP keys Purely hardware HDCP engine increasing the robustness and security of HDCP operation Monitor detection through Hot Plug Detection and Receiver Termination Detection Embedded full-function pattern generator Intelligent, programmable power management 100-pin LQFP package Ordering Information Model Temperature Range Package Type Green/Pb free Option IT6613E 0~70 100-pin LQFP Green www.ite.com.tw Oct-2010 Rev:0.9 3/36 IT6613 D30 61 D29 62 D28 63 IVDD 64 IOVSS 65 OVDD 66 D27 67 D26 68 D25 69 D24 70 D23 71 D22 72 D21 73 D20 74 D19 75 PCSDA PCSCL DDCSDA DDCSCL NC AVCC33 PGND2 PVCC2 AGND TX2P TX2M AVCC18 TX1P TX1M AGND TX0P TX0M AVCC18 TXCP TXCM AGND PVCC1 REXT PGND1 34 33 32 31 30 29 28 27 26 25 9 60 35 SYSRSTN 81 D31 36 24 51 D32 59 37 44 58 38 71 D33 39 ： 57 40 QQ D34 41 85 ， 56 42 IT6613E 43 41 5 55 D35 43 LQFP-100 Top View 18 66 IVDD 44 ， 54 45 司 IOVSS 46 公 53 47 限 OVDD 48 技 有 ENTEST 52 49 讯 科 51 50 91 92 93 94 95 96 97 98 99 100 D2 D1 D0 IVDD IOVSS 市 金 90 INT 23 DSD3L 22 DSD3R 21 DSD2L 20 DSD2R 19 DSD1L 18 DSD1R 17 DSD0L 16 DSD0R 15 DCLK 14 OVDD 13 IOVSS 12 IVDD 11 SCK 10 WS 9 I2S0 8 I2S1 7 I2S2 6 I2S3 5 MCLK 4 SPDIF 3 VSYNC 2 HSYNC 1 DE 深 圳 89 D3 D13 88 D4 D14 87 D5 D15 86 D6 D16 85 D7 D17 84 D8 D18 83 OVDD 82 PCLK 81 IOVSS 80 D9 79 D10 78 D11 77 D12 76 IVDD 合 HPD PCADR Pin Diagram www.ite.com.tw Figure 1. IT6613 pin diagram Oct-2010 Rev:0.9 4/36 IT6613 Pin Description Digital Video Input Pins Pin Name Direction Description D[35:0] Input Digital video input pins. Type Pin No. LVTTL 56-63, 67-75, 77-86, 90-98 HSYNC Input Horizontal sync. signal LVTTL VSYNC Input Vertical sync. signal LVTTL PCLK Input Input data clock LVTTL 1 9 LVTTL 81 Data enable 51 Input 2 3 88 ： 71 44 DE QQ Digital Audio Input Pins Direction Description Type Pin No. MCLK Input Audio master clock input LVTTL 5 SCK Input I2S serial clock input LVTTL 11 WS Input I2S word select input LVTTL 10 I2S0 Input I2S serial data input LVTTL 9 I2S1 Input I2S serial data input LVTTL 8 I2S2 Input I2S serial data input LVTTL 7 I2S3 Input I2S serial data input LVTTL 6 SPDIF Input S/PDIF audio input LVTTL 4 DCLK Input DSD Serial audio clock input LVTTL 15 DSD0R Input DSD Serial Right CH0 data input LVTTL 16 DSD0L Input DSD Serial Left CH0 data input LVTTL 17 DSD1R Input DSD Serial Right CH1 data input LVTTL 18 DSD1L Input DSD Serial Left CH1 data input LVTTL 19 DSD2R Input DSD Serial Right CH2 data input LVTTL 20 DSD2L Input DSD Serial Left CH2 data input LVTTL 21 Input DSD Serial Right CH3 data input LVTTL 22 Input DSD Serial Left CH3 data input LVTTL 23 Type Pin No. 43 41 5 18 66 ， 司 公 限 技 有 讯 科 合 市 金 深 DSD3L 圳 DSD3R 85 ， Pin Name Programming Pins Pin Name Direction Description INT# Output Interrupt output. Default active-low (5V-tolerant) LVTTL 24 SYSRSTN Input Hardware reset pin. Active LOW (5V-tolerant) Schmitt 25 DDCSCL I/O I2C Clock for DDC (5V-tolerant) Schmitt 46 Schmitt 47 DDCSDA www.ite.com.tw I/O 2 I C Data for DDC (5V-tolerant) Oct-2010 Rev:0.9 5/36 IT6613 PCSCL Input Serial Programming Clock for chip programming (5V-tolerant) Schmitt 48 PCSDA I/O Serial Programming Data for chip programming (5V-tolerant) Schmitt 49 PCADR Input Serial programming device address select LVTTL 50 HPD Input Hot Plug Detection (5V-tolerant) LVTTL 51 ENTEST Input Must be tied low via a resistor. LVTTL 52 Could be left unconnected 45 81 9 NC Pin Name Direction Description Pin No. TX2P Analog HDMI Channel 2 positive output TMDS 40 TX2M Analog HDMI Channel 2 negative output TMDS 39 TX1P Analog HDMI Channel 1 positive output TMDS 37 TX1M Analog HDMI Channel 1 negative output TMDS 36 TX0P Analog HDMI Channel 0 positive output TMDS 34 TX0M Analog HDMI Channel 0 negative output TMDS 33 TXCP Analog HDMI Clock Channel positive output TMDS 31 TXCM Analog HDMI Clock Channel negative output TMDS 30 REXT Analog External resistor for setting TMDS output level. Default tied to Analog 27 43 41 5 85 ， QQ ： 71 44 Type 18 66 51 HDMI front-end interface pins 司 ， AVCC18 via a 698-Ohm SMD resistor. 公 Power/Ground Pins Description IVDD Digital logic power (1.8V) Power 12, 55, 64, 76, 99 OVDD I/O Pin power (3.3V) Power 14, 53, 66, 89 IOVSS Digital logic and I/O pin common ground Ground 13, 54, 65, 87, 100 AVCC18 HDMI analog frontend power (1.8V) Power 32, 38 AVCC33 HDMI analog frontend power (3.3V) Power 44 AGND HDMI analog frontend ground Ground 29, 35, 41 HDMI core PLL power (1.8V) Power 28 HDMI core PLL ground Ground 26 PVCC2 Filter PLL power (1.8V) Power 42 PGND2 Filter PLL ground Ground 43 合 市 金 深 圳 PVCC1 PGND1 讯 科 技 有 限 Pin Name www.ite.com.tw Type Pin No. Oct-2010 Rev:0.9 6/36 IT6613 Functional Description 44 51 81 9 The IT6613 is the 3nd generation HDMI transmitter and provides complete solutions for HDMI v1.4 Source systems, supporting processing and transmission of Deep Color video and state-of-the-art digital audio such as DTS-HD and Dolby TrueHD. The IT6613 supports color depths of 10 bits and 12 bits up to 1080p. Advanced processing algorithms are employed to optimize the performance of video processing such as color space conversion and up/down sampling. The functional block digram of the IT6613 is shown in Figure 1, which describes clearly the data flow. SYSRSTN Configuration Register Blocks 85 ， 43 41 5 DDCSDA HDCP Cipher & Encryption Enginer TX2P/M TMDS TX (DVI/ HDMI) TX1P/M TX0P/M TXCP/M 限 公 司 ， Color Space Conversion 4:2:2 4:4:4 Pixel Repeat 技 有 Audio Data Capture Interrupt Controller HPD Figure 2. Functional block diagram of IT6613 市 金 合 MCLK SCK WS I2S[3:0] SPDIF DCLK DSD[3:0]R DSD[3:0]L INT Video Data Capture & DE Generator DDCSCL 讯 科 PCLK VSYNC HSYNC DE D[35:0] I2C Master (HDCP Controller) 18 66 PCADR HDCP Key QQ ： 71 PCSCL PCSDA 圳 Video Data Processing Flow 深 Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most of the block enablings and path bypassings are controlled through register programming. Please refer to IT6613 Programming Guide for detailed and precise descriptions. As can be seen from Figure 3, the first step of video data processing is to prepare the video data (Data), data enable signal (DE), video clock (Clock), horizontal sync and vertical sync signals (H/VSYNC). While the video data and video clock are always readily available from input pins, the preparation of the data enable and sync signals require special extraction process (Embedded Ctrl. www.ite.com.tw Oct-2010 Rev:0.9 7/36 IT6613 Signals Extraction & DE Generator) depending on the format of input video data. 44 51 81 9 All the data then undergo a series of video processing including YCbCr up/down-sampling, color-space conversion and dithering. Depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. For the sake of flexibility, this is all done in software register programming. Therefore, extra care should be taken in keeping the selected input-output format combination and the corresponding video processing block selection. Please refer to the IT6613 Programming Guide for suggested register setting. Clock ： H/VSYNC H/VSYNC Data 43 41 5 Embedded Ctrl. Signals Extraction DE 85 ， DE Generator QQ DE H/VSYNC 71 PCLK DE YCbCr (upsampler) (CSC) ٛ Dithering 12-to-8 YCbCr444 to YCbCr422 TX2 HDCP TMDS Driver (downsampler) TX1 TX0 TXC 技 有 限 公 RGB 司 YCbCr422 to YCbCr444 ， 18 66 D[35:0] 讯 科 Figure 3. Video data processing flow of the IT6613 市 金 合 Designated as D[35:0], the input video data could take on bus width of 8 bits to 36 bits. This input interface could be configured to support various data formats as listed in Table 1. 深 圳 All the major video processings in the IT6613 are done in 14 bits per channel in order to minimize rounding errors and other computational residuals that occur during processing. General description of block functions is as follows: Extraction of embedded control signals (Embedded Ctrl. Signals Extraction) Input video formats with only embedded sync signals rely on this block to derive the proper Hsync, Vsync and DE signals. Specifically, CCIR-656 video streams includes Start of Active Video (SAV) and End of Active Video (EAV) that this block uses to extract the required control signals. Generation of data enable signal (DE Generator) DE signal defines the region of active video data. In cases where the video decoders supply no such www.ite.com.tw Oct-2010 Rev:0.9 8/36 IT6613 DE signals to the IT6613, this block is used to generate appropriate DE signal from Hsync, Vsync and Clock. Upsampling (YCbCr422 to YCbCr444) In cases where input signals are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during upsampling. 44 51 81 9 Bi-directional Color Space Conversion (YCbCr ↔ RGB) Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order to offer full compatibility between various Source and Sink combination, this block offers bi-directional QQ ： 71 RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the maxtrix coefficients of the CSC engine in the IT6613 are fully programmable. Users could elect to employ their preferred conversion formula. 43 41 5 85 ， Dithering (Dithering 12-to-8) For outputing to the 8-bits-per-channel formats, decimation from 12 bits to 8 bits is required. This block performs the necessary dithering for decimation to prevent visible artifacts from appearing. 18 66 Downsampling (YCbCr444 to YCbCr422) In cases where input signals are in YCbCr 4:4:4 format and output is selected as YCbCr 4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during downsampling. 技 有 限 公 司 ， HDCP engine (HDCP) The HDCP engine in the IT6613 handles all the processing requried by HDCP mechanism in hardware. Software intervention is not necessary except checking for revocation. Preprogrammed HDCP keys are also embedded in the IT6613. Users need not worry about the purchasing and management of the HDCP keys. 市 金 合 讯 科 TMDS driver (TMDS Driver) The final step of the data processing flow is TMDS serializer. The TMDS driver serializes the input parallel data and drive out the proper electrical signals to the HDMI cable. The output current level is controlled through connecting a precision resistor of proper value to Pin 27 (REXT). 圳 Supported Input Video Formats 深 The IT6613 supports deep-color video of 30-bit (10-bit per color) and 36-bit (12-bit per color). At the maximum resolution and bit depth, namely 36-bit/1080p, the TMDS data rate at the link is as high as 2.25Gbps. Table 1 lists the input video formats supported by the IT6613. www.ite.com.tw Oct-2010 Rev:0.9 9/36 IT6613 Input Pixel Clock Frequency (MHz) Color Video Bus Hsync/ Space Format Width Vsync 480p XGA 720p 1080i SXGA 1080p UXGA 13.5 27 65 74.25 74.25 108 148.5 162 13.5 27 65 74.25 74.25 108 148.5 13.5 27 65 74.25 74.25 13.5 27 65 74.25 74.25 108 148.5 13.5 27 65 74.25 74.25 108 Separate 13.5 27 65 74.25 74.25 Separate 13.5 27 74.25 74.25 Embedded 13.5 27 74.25 74.25 Separate 27 54 148.5 148.5 Embedded 27 54 148.5 148.5 4:4:4 Separate 30/36 12/15/18 YCbCr 16/20/24 4:2:2 8/10/12 81 24 162 148.5 51 Separate 44 12/15/18 71 30/36 ： 4:4:4 148.5 148.5 QQ RGB Separate 85 ， 24 9 480i Table 1. Input video formats supported by the IT6613 18 66 43 41 5 Notes: 1. Table cells that are left blanks are those format combinations that are not supported by the IT6613. 2. Input channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are arranged. Refer to Video Data Bus Mappings for better understanding. 3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY. ， Supported 3D Formats 圳 市 金 合 讯 科 技 有 限 公 1920x1080P@50Hz -- Top-and-Bottom [email protected]/60Hz -- Top-and-Bottom [email protected]/30Hz -- Framing Packing, Top-and-Bottom [email protected]/24Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1920x1080i@50Hz – Frame Packing, Side-by-Side ( Half ) [email protected]/60Hz – Frame Packing, Side-by-Side ( Half ) 1280x [email protected]/30Hz -- Framing Packing 1280x [email protected]/24Hz -- Framing Packing 1280x 720P@50Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 1280x [email protected]/60Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom 深 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 司 The IT6613 supports all the HDMI 1.4a 3D mandatory formats and all the primary 3D formats including Audio Data Capture and Processing The IT6613 supports all audio formats and interfaces specified by the HDMI Specification v1.3 through I2S, S/PDIF and optional one-bit audio inputs. I 2S Four I2S inputs are provided to support 8-channel uncompressed audio data at up to 192kHz sample www.ite.com.tw Oct-2010 Rev:0.9 10/36 IT6613 51 81 9 rate. If the input audio data come with a multiple (master) clock, pin 5 (MCLK) takes in the clock to faciliate audio processing. Note that this is optional. By default IT6613 generates the MCLK internally to process the audio. Neither I2S nor S/PDIF inputs requires MCLK input, coherent or not. However, if the user prefers inputing MCLK from external audio source, such configuration could be enabled through register setting. Refer to IT6613 Programming Guide for such setting. The supported multiplied factor and sample frequency as well as the resultant MCLK frequencies are summarized in Table 2. 85 ， QQ ： 71 44 S/PDIF The S/PDIF input supports 2-channel uncompressed PCM data (IEC 60958) or compressed multi-channel data (IEC 61937) at up to 192kHz. By default the clock of S/PDIF is carried within the datastream itself via coding. The IT6613 could also process the S/PDIF audio with coherent MCLK input as indicated in Table 2. Audio sample frequency Multiple of audio sample frequency 32kHz 44.1kHz 48kHz 128 4.096 5.645 6.144 256 8.192 11.290 12.288 512 16.384 22.579 1024 32.768 45.158 96kHz 176.4kHz 192kHz 11.290 12.288 22.579 24.576 22.579 24.576 45.158 49.152 24.576 45.158 49.152 90.317 98.304 49.152 90.316 98.304 (180.634) (196.608) ， 18 66 43 41 5 88.2kHz 司 Table 2. Output MCLK frequencies (MHz) supported by the IT6613 讯 科 技 有 限 公 Notes: 1. The MCLK frequencies in parenthesis are MCLK frequencies over 100MHz. These frequencies are implemented in the IT6613 and could be output through register setting as well. However, the I/O circuit of the MCLK pin does not guarantee to be operating at such a high frequency under normal operation conditions. In addition, few audio frontend ICs outputs such high MCLK frequencies. Therefore, using the MCLKs in parenthesis is strongly discouraged. 深 圳 市 金 合 One-Bit Audio (DSD/SACD) Direct stream digital (DSD) audio is an one-bit audio format which is prescribed by Super Audio CD (SACD) to provide superiore audio hearing experiences. The IT6613 provides dedicated input pins for DSD audio. A total of 8 data inputs are provided for right channels and left channels. High-Bit-Rate Audio (HBR) High-Bit-Rate Audio is also new to the HDMI standard. It is called upon by high-end audio system such as DTS-HD and Dolby TrueHD. No specific interface is defined by the HBR standard. The IT6613 supports HBR audio in two ways. One is to employ the four I2S inputs simultaneously, where the original streaming DSD audio is broken into four parallel data streams before entering the IT6613. The other is to use the S/PDIF input port. Since the data rate here is as high as 98.304Mbps, a coherent MCLK is required in this application. www.ite.com.tw Oct-2010 Rev:0.9 11/36 IT6613 Audio Downsampling Audio data can be down sampled in cases where the sinks only support audio with lower sampling rates. The IT6613 offers audio down-sampling of both a factor of two and a factor of four. Refer to Table 3 for supported down-samplings. 96kHz → 48kHz 88.2kHz → 44.1kHz 192kHz → 48kHz 176.4kHz → 44.1kHz 81 9 176.4kHz → 88.2kHz 51 Down-sampling factor of 4 192kHz → 96kHz 44 Down-sampling factor of 2 QQ ： 71 Table 3. Audio down-samplings supported by the IT6613 85 ， Interrupt Generation 技 有 限 公 司 ， 18 66 43 41 5 The system micro-controller should monitor the interrupt output by the IT6613 at PIN 24 (INT). The IT6613 generates an interrupt signal with events involving the following signals or situations: 1. A status change at Pin 51 (HPD), implicating hot-plug/unplug events 2. Receiver detection circuit in the IT6613 reports the presence or absence of an active termination at the TMDS Clock Channel (Register 0Eh[5], RxSENDetect) 3. DDC bus is hanged for whatever reasons 4. Audio FIFO overflows 5. HDCP authentication fails 6. Video data is stable or not 圳 市 金 合 讯 科 In an HDMI link the transmitter is responsible for initialize the link, which should be based on interrupt signal and appropriate register probing. Recommended flow is detailed in IT6613 Programming Guide. Simply put, the microcontroller should monitor the HPD status first. Upon valid HPD event, move on to check RxSENDetect register to see if the receiver chip is ready for further handshaking. When RxSENDetect is asserted, start reading EDID data through DDC channels and carry on the rest of the handshaking subsequently. 深 If the micro-controller makes no use of the interrupt signal as well as the above-mentioned status registers, the link establishment might fail. Please do follow the suggested initialization flow recommended in IT6613 Programming Guide. www.ite.com.tw Oct-2010 Rev:0.9 12/36 IT6613 Configuration and Function Control 81 9 The IT6613 includes two serial programming ports by default (i.e. with embedded HDCP keys): one for interfacing with micro-controller, the other for accessing the DDC channels of HDMI link. The serial programming interface for interfacing the micro-controller is a slave interface, comprising PCSCL (Pin 48) and PCSDA (Pin 49). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input logic level of 44 51 PCADR (Pin 50). If PCADR is pulled high by the user, the device address is 0x9A. If pulled low, 0x98. 85 ， QQ ： 71 The I2C interface for accessing the DDC channels of the HDMI link is a master interface, comprising DDCSCL (Pin 46) and DDCSDA (Pin 47). the IT6613 uses this interface to read the EDID data and perform HDCP authentication protocol with the sink device over the HDMI cable. 18 66 43 41 5 For temporarily storing the acquired EDID data, the IT6613 embedded a dedicated FIFO of 32 bytes. The micro-controller may command the IT6613 to acquire 32 bytes of EDID information at a time, read them back and then continue to read the next 32 bytes until all neccessary EDID informations are retrieved. Slave Addr (7) R A Read Data (8) A Read Data (8) A Read Data (8) NA P 讯 科 S 技 有 限 公 司 ， The HDCP protocol of the IT6613 is completely implemented in hardware. No software intervention is needed except for revocation list checking. Various HDCP-related statuses are stored in HDCP registers for the reference of micro-controller. Refer to IT6613 Programming Guide for detailed register descriptions. The HDCP Standard also specifies a special message read protocol other than the standard I2C protocol. See Figure 4 for checking HDCP port link integrity. Figure 4. HDCP port link integrity message read 市 金 合 S=Start; R=Read; A=Ack; NA=No Ack; P=Stop 深 圳 All serial programming interfaces conform to standard I2C transactions and operate at up to 100kHz. www.ite.com.tw Oct-2010 Rev:0.9 13/36 IT6613 Electrical Specifications Absolute Maximum Ratings Unit -0.3 2.5 V I/O pins supply voltage -0.3 4.0 V AVCC18 HDMI analog frontend supply voltage -0.3 2.5 V AVCC33 HDMI analog frontend supply voltage -0.3 PVCC1 HDMI core PLL supply voltage -0.3 PVCC2 Filter PLL supply voltage -0.3 VI Input voltage -0.3 VO Output voltage -0.3 TJ Junction Temperature TSTG Storage Temperature ESD_HB Human body mode ESD sensitivity 81 51 OVDD 4.0 V 2.5 V 2.5 V OVDD+0.3 V OVDD+0.3 V 125 °C 150 °C 44 Core logic supply voltage 9 Max 71 IVDD Typ ： Min. QQ Parameter 85 ， Symbol -65 V 43 41 5 2000 ， 18 66 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. 司 Functional Operation Conditions Min. Typ Max Unit IVDD Core logic supply voltage 1.62 1.8 1.98 V OVDD I/O pins supply voltage 2.97 3.3 3.63 V AVCC18 HDMI analog frontend supply voltage 1.71 1.8 1.89 V AVCC33 HDMI analog frontend supply voltage 2.97 3.3 3.63 V PVCC1 HDMI core PLL supply voltage 1.62 1.8 1.98 V PVCC2 Filter PLL supply voltage 1.62 1.8 1.98 V VCCNOISE Supply noise 100 mVpp 70 °C 公 Parameter 讯 科 合 市 金 TA 技 有 限 Symbol Ambient temperature 0 25 °C/W 深 圳 Junction to ambient thermal resistance Θja Notes: 1. AVCC18, AVCC33, PVCC1 and PVCC2 should be regulated. 2. See System Design Consideration for supply decoupling and regulation. www.ite.com.tw Oct-2010 Rev:0.9 14/36 IT6613 IOVDD_OP Max Unit 27MHz 29 32 mA 74.25MHz 69 76 mA 148.5MHz 113 127 mA 222.75MHz 138 154 mA 27MHz 1 1 74.25MHz 1 148.5MHz 1 OVDD current under normal operation mA 1 mA 1 1 mA 35 38 mA 74.25MHz 36 40 mA 148.5MHz 38 43 mA 222.75MHz 41 45 mA 27MHz 1 1 mA 74.25MHz 1 1 mA 148.5MHz 1 1 mA 222.75MHz 1 1 mA 27MHz 2 2 mA 74.25MHz 3 3 mA 148.5MHz 5 6 mA 222.75MHz 9 10 mA 27MHz 2 2 mA 74.25MHz 3 3 mA 148.5MHz 6 6 mA 222.75MHz 8 8 mA 27MHz 129 154 mW 74.25MHz 206 249 mW 148.5MHz 298 368 mW 222.75MHz 359 437 mW 27MHz 43 41 5 18 66 AVCC33 current under normal operation 85 ， QQ ： AVCC18 current under normal operation IAVCC33_OP PVCC1 current under normal operation 限 公 司 ， IPVCC1_OP PVCC2 current under normal operation 讯 科 技 有 IPVCC2_OP Total power consumption under normal operation3 深 圳 市 金 合 PWTOTAL_OP mA 1 222.75MHz IAVCC18_OP 9 IVDD current under normal operation Typ 81 IIVDD_OP TMDSCLK 44 Parameter 71 Symbol 51 Operation Supply Current Specification Notes: 1. Typ: OVDD=AVCC33=3.3V, IVDD=AVCC18=PVCC1=PVCC2=1.8V Max: OVDD=AVCC33=3.6V, IVDD=AVCC18=PVCC1=PVCC2=1.98V 2. TMDSCLK refer to the differential clock 3. TMDSCLK=27MHz: 480p with 48kHz/8-channel audio, TMDSCLK=74.25MHz: 1080i with 192kHz/8-channel audio, TMDSCLK=148.5MHz: 1080p with 192kHz/8-channel audio, TMDSCLK=222.75MHz: 1080p@36-bit Deep Color with 192kHz/8-channel audio 4. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. www.ite.com.tw Oct-2010 Rev:0.9 15/36 IT6613 DC Electrical Specification VIL Input low voltage1 LVTTL VT Switching threshold1 LVTTL VT- Schmitt trigger negative going threshold Schmitt Conditions Min. 2.0 Typ 0.8 V 1.6 1 IIN Input leakage current IOZ Tri-state output leakage current1 Serial programming output sink current Vswing TMDS output single-ended swing3 IOH=-2~-16mA 0.4 all VIN=5.5V or 0 ±5 μA all VIN=5.5V or 0 ±10 μA Schmitt VOUT=0.2V TMDS RLOAD=50Ω 2.4 43 41 5 IOL 2 LVTTL 71 Output high voltage V IOL=2~16mA ： VOH 2.0 LVTTL QQ 1 85 ， Output low voltage1 VOL 44 voltage V 1.1 51 Schmitt 1 0.8 V voltage Schmitt trigger positive going threshold Unit V 1.5 1 VT+ Max 9 Pin Type LVTTL 81 Under functional operation conditions Symbol Parameter VIH Input high voltage1 4 16 mA 400 600 mV 18 66 VLOAD=3.3V 3 REXT=698Ω 合 讯 科 技 有 限 公 司 ， IOFF Single-ended standby output current TMDS VOUT=0 10 μA Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of the IT6613 are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to IT6613 Programming Guide for proper register setting. 3. Internal source turned off. Limits defined by HDMI Specifications v1.3a 市 金 Audio AC Timing Specification 深 圳 Under functional operation conditions Symbol Parameter FS_I2S I2S sample rate FS_SPDIF S/PDIF sample rate www.ite.com.tw Conditions Up to 8 channels Min. 32 2 channels 32 Typ Max 192 Unit kHz 192 kHz Oct-2010 Rev:0.9 16/36 IT6613 Video AC Timing Specification Fpixel PCLK pixel clock frequency1 TCDE PCLK dual-edged clock period2 PCLK dual-edged clock frequency TPDUTY PCLK clock duty cycle TPJ PCLK worst-case jitter Video data setup time3 162 MHz 8.88 40 ns 25 82 MHz Single-edged 1.0 clocking 0.5 Dual-edged clocking 1.0 81 1.0 ns - ns - ns - ns QQ 3 60% 51 TSDE 25 44 Video data hold time Unit ns 71 TH 3 Max 40 ： Video data setup time clocking Typ 40% 3 TS Min. 6 Dual-edged clocking 2 FCDE Conditions Single-edged 9 Under functional operation conditions Symbol Parameter Tpixel PCLK pixel clock period1 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， THDE Video data hold time 0.5 ns Notes: 1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding pixel frequencies. 2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i. 3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user through register programming. www.ite.com.tw Oct-2010 Rev:0.9 17/36 IT6613 Video Data Bus Mappings The IT6613 supports various output data mappings and formats, including those with embedded control signals only. Corresponding register setting is to be taken care of for any chosen input data mappings. Refer to IT6613 Programming Guide for detailed instruction. 4:4:4 YCbCr 24/30/36 Seperate 1X 12/15/18 Seperate Dual-edged 10 24/30/36 Seperate 0.5X, Dual-edged 5 24/30/36 Seperate 1X 5 12/15/18 Seperate Dual-edged 10 24/30/36 Seperate 0.5X, Dual-edged 5 Seperate 1X 6 Embedded 1X 7 Seperate 2X 9 Embedded 2X 8 16/20/24 43 41 5 4:2:2 81 51 44 5 18 66 8/10/12 Table 9 Clocking 71 4:4:4 H/Vsync ： RGB Bus Width QQ Video Format 85 ， Color Space 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Table 4. Output video format supported by the IT6613 www.ite.com.tw Oct-2010 Rev:0.9 18/36 IT6613 RGB 4:4:4 and YCbCr 4:4:4 with Separate Syncs 讯 科 市 金 圳 深 18 66 51 81 9 24-bit grounded grounded grounded grounded Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 grounded grounded grounded grounded Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 grounded grounded grounded grounded Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 HSYNC VSYNC DE ： 71 44 YCbCr 30-bit grounded grounded Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Cb8 Cb9 grounded grounded Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 grounded grounded Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 Cr8 Cr9 HSYNC VSYNC DE QQ 85 ， 36-bit Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Cb8 Cb9 Cb10 Cb11 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 Cr8 Cr9 Cr10 Cr11 HSYNC VSYNC DE 43 41 5 24-bit grounded grounded grounded grounded B0 B1 B2 B3 B4 B5 B6 B7 grounded grounded grounded grounded G0 G1 G2 G3 G4 G5 G6 G7 grounded grounded grounded grounded R0 R1 R2 R3 R4 R5 R6 R7 HSYNC VSYNC DE ， 司 公 限 技 有 36-bit B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 HSYNC VSYNC DE 合 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE RGB 30-bit grounded grounded B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 grounded grounded G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 grounded grounded R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 HSYNC VSYNC DE Table 5. RGB & YCbCr 4:4:4 Mappings These are the simplest formats, with a complete definition of every pixel in each clock period. Figure 5 www.ite.com.tw Oct-2010 Rev:0.9 19/36 IT6613 and Figure 6 give two examples Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... blank D[35:24] val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 .... val val val D[23:12] val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 .... val val val D[11:0] val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6 .... val 81 9 blank val 51 val 71 44 PCLK ： DE 85 ， QQ H/VSYNC Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 .... val val val val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 .... val val val val Bpix0 Bpix3 Bpix4 Bpix5 Bpix6 .... val val val Bpix2 市 金 合 PCLK DE Bpix1 讯 科 D[1:0] 技 有 限 D[13:12] D[11:2] blank 公 D[23:14] 司 D[25:24] 18 66 blank ， D[35:26] 43 41 5 Figure 5. 36-bit RGB 4:4:4 Timing Diagram 深 圳 H/VSYNC www.ite.com.tw Figure 6. 30-bit RGB 4:4:4 Timing Diagram Oct-2010 Rev:0.9 20/36 IT6613 YCbCr 4:2:2 with Separate Syncs 深 圳 市 金 ： 71 44 51 81 9 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 HSYNC HSYNC VSYNC VSYNC DE DE 18 66 43 41 5 85 ， QQ 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 grounded grounded grounded grounded grounded grounded grounded grounded Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 HSYNC HSYNC VSYNC VSYNC DE DE ， 司 公 限 技 有 讯 科 合 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE 24-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 grounded grounded grounded grounded grounded grounded grounded grounded Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 HSYNC HSYNC VSYNC VSYNC DE DE Table 6. Mappings of YCbCr 4:2:2 with separate syncs YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is www.ite.com.tw Oct-2010 Rev:0.9 21/36 IT6613 given for every pixel, while the two chroma channels are given alternatively on every other clock period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each component could take on different lengths. The DE period should contain an even number of clock periods. Figure 7 and Figure 8 give two timing examples. Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... blank val Cbpix0 [11:4] Crpix0 [11:4] Cbpix2 [11:4] Crpix2 [11:4] Cbpix4 [11:4] Crpix4 [11:4] Cbpix6 [11:4] .... val Ypix0 [11:4] Ypix1 [11:4] Ypix2 [11:4] Ypix3 [11:4] Ypix4 [11:4] Ypix5 [11:4] Ypix6 [11:4] .... D[11:8] val Cbpix0 [3:0] Crpix0 [3:0] Cbpix2 [3:0] Crpix2 [3:0] Cbpix4 [3:0] Crpix4 [3:0] Cbpix6 [3:0] D[7:4] val Ypix0 [3:0] Ypix1 [3:0] Ypix2 [3:0] Ypix3 [3:0] Ypix4 [3:0] Ypix5 [3:0] Ypix6 [3:0] val val 71 44 D[27:24] val val val .... val val val .... val val val ： D[23:16] val 51 D[35:28] 81 9 blank 43 41 5 18 66 D[3:0] 85 ， QQ D[15:12] PCLK 司 ， DE 限 公 H/VSYNC 市 金 D[27:24] val 合 D[35:28] 圳 D[23:16] Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] Cbpix6 [7:0] .... val val val Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] Ypix6 [7:0] .... val val val 讯 科 blank 技 有 Figure 7. 24-bit YCbCr 4:2:2 with separate syncs val blank 深 D[15:0] PCLK DE H/VSYNC Figure 8. 16-bit YCbCr 4:2:2 with separate syncs www.ite.com.tw Oct-2010 Rev:0.9 22/36 IT6613 YCbCr 4:2:2 with Embedded Syncs 深 圳 市 金 ： 71 44 51 81 9 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 embedded embedded embedded embedded embedded embedded 18 66 43 41 5 85 ， QQ 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 grounded grounded grounded grounded grounded grounded grounded grounded Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 embedded embedded embedded embedded embedded embedded ， 司 公 限 技 有 讯 科 合 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE 24-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 grounded grounded grounded grounded grounded grounded grounded grounded Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 embedded embedded embedded embedded embedded embedded Table 7. Mappings of YCbCr 4:2:2 with embedded syncs Similar to YCbCr 4:2:2 with Separate Sync. The only difference is that the syncs are now non-explicit, www.ite.com.tw Oct-2010 Rev:0.9 23/36 IT6613 i.e. embedded. Bus width could be 16-bit, 20-bit or 24-bit. Figure 9 and Figure 10 give two timing examples SAV Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... .... val val val val Cbpix0 [11:4] Crpix0 [11:4] Cbpix2 [11:4] Crpix2 [11:4] Cbpix4 [11:4] Crpix4 [11:4] Cbpix6 [11:4] FF 00 00 XY Ypix0 [11:4] Ypix1 [11:4] Ypix2 [11:4] Ypix3 [11:4] Ypix4 [11:4] Ypix5 [11:4] Ypix6 [11:4] D[11:8] val val val val Cbpix0 [3:0] Crpix0 [3:0] Cbpix2 [3:0] Crpix2 [3:0] Cbpix4 [3:0] Crpix4 [3:0] D[7:4] val val val val Ypix0 [3:0] Ypix1 [3:0] Ypix2 [3:0] Ypix3 [3:0] val FF Cbpix6 [3:0] .... val Ypix6 [3:0] .... val 51 .... 44 D[23:16] blank 9 D[27:24] 81 D[35:28] Pixel0 QQ ： 71 D[15:12] Ypix5 [3:0] 85 ， Ypix4 [3:0] D[3:0] 43 41 5 PCLK 18 66 Figure 9. 24-bit YCbCr 4:2:2 with embedded syncs val FF 00 限 D[27:24] D[23:16] val Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] Cbpix6 [7:0] .... val Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] Ypix6 [7:0] .... FF ， val Pixel1 司 val Pixel0 blank 公 D[35:28] 技 有 SAV XY 讯 科 D[15:0] 00 Figure 10. 16-bit YCbCr 4:2:2 with embedded syncs 深 圳 市 金 合 PCLK www.ite.com.tw Oct-2010 Rev:0.9 24/36 IT6613 CCIR-656 Format 深 圳 85 ， 43 41 5 18 66 81 9 8-bit PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded ： 71 44 51 PCLK#2N grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 C1 C2 C3 C4 C5 C6 C7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded QQ 10-bit PCLK#2N PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded ， 司 公 限 技 有 讯 科 合 市 金 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE 12-bit PCLK#2N PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Table 8. Mappings of CCIR-656 The CCIR-656 format is yet another variation of the YCbCr formats. The bus width is further reduced www.ite.com.tw Oct-2010 Rev:0.9 25/36 IT6613 Pixel2 ... 51 Pixel0 ~ Pixel1 00 XY Cbpix0-1 [11:4] Ypix0 [11:4] Crpix0-1 [11:4] val val val val Cbpix0-1 [3:0] Ypix0 [3:0] Crpix0-1 [3:0] 85 ， D[15:8] Cbpix2-3 [11:4] Ypix2 [11:4] .... FF Ypix1 [3:0] Cbpix2-3 [3:0] Ypix2 [3:0] .... val 43 41 5 D[7:4] Ypix1 [11:4] ： 00 QQ FF 71 D[35:24] D[23:16] blank 44 SAV 81 9 by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To compensate for the halving of data bus, PCLK frequency is doubled. With the double-rate output clock, luminance channel (Y) and chroma channels (Cb or Cr) are alternated. Normally this mode is used only for 480i, 480p, 576i and 576p. The IT6613 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at 148.5MHz. CCIR-656 format supports embedded syncs only. Figure 11 and Figure 12 give two examples. D[3:0] 18 66 PCLK 司 ， Figure 11. 12-bit CCIR-656 限 blank 00 00 XY Cbpix0-1 [7:0] Ypix0 [7:0] Crpix0-1 [7:0] Ypix1 [7:0] Cbpix2-3 [7:0] Ypix2 [7:0] .... FF Figure 12. 8-bit CCIR-656 深 圳 市 金 合 D[15:0] PCLK Pixel2 ... 讯 科 FF 技 有 D[35:24] D[23:16] Pixel0 ~ Pixel1 公 SAV www.ite.com.tw Oct-2010 Rev:0.9 26/36 IT6613 CCIR-656 + separate syncs 深 圳 85 ， 43 41 5 18 66 81 9 8-bit PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE ： 71 44 51 PCLK#2N grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 C1 C2 C3 C4 C5 C6 C7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE QQ 10-bit PCLK#2N PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC HSYNC VSYNC VSYNC DE DE ， 司 公 限 技 有 讯 科 合 市 金 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE 12-bit PCLK#2N PCLK#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC HSYNC VSYNC VSYNC DE DE Table 9. Mappings of CCIR-656 + separate syncs This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus www.ite.com.tw Oct-2010 Rev:0.9 27/36 IT6613 separate syncs. Figure 13 and Figure 14 give two examples blank Pixel0 ~ Pixel1 Pixel2 ~ Pixel3 ... blank D[35:24] val val val Cbpix0-1 [11:4] Ypix0 [11:4] Crpix0-1 [11:4] Ypix1 [11:4] Cbpix2-3 [11:4] Ypix2 [11:4] Crpix2-3 [11:4] Ypix3 [11:4] val val val Cbpix0-1 [3:0] Ypix0 [3:0] Crpix0-1 [3:0] Ypix1 [3:0] Cbpix2-3 [3:0] Ypix2 [3:0] Crpix2-3 [3:0] Ypix3 [3:0] val 51 81 D[15:8] .... val 44 D[7:4] .... 9 D[23:16] ： 71 D[3:0] QQ PCLK 85 ， DE 43 41 5 H/VSYNC 18 66 Figure 13. 12-bit CCIR-656 + separate syncs blank Pixel0 ~ Pixel1 val Cbpix0-1 [11:4] val 司 val Ypix0 [11:4] Crpix0-1 [11:4] Ypix1 [11:4] Cbpix2-3 [11:4] Ypix2 [11:4] Crpix2-3 [11:4] Ypix3 [11:4] .... val 技 有 限 D[15:0] PCLK Figure 14. 8-bit CCIR-656 + separate syncs 深 圳 市 金 合 讯 科 DE H/VSYNC blank 公 D[23:16] ... ， D[35:24] Pixel2 ~ Pixel3 www.ite.com.tw Oct-2010 Rev:0.9 28/36 IT6613 24/15/18-bit RGB 4:4:4 and YCbCr 4:4:4 Using Dual-Edge Triggering 深 85 ， 43 41 5 18 66 ， 司 公 限 技 有 81 9 12-bit 1st 2nd edge edge gnded gnded gnded gnded gnded gnded gnded gnded Cb0 Y4 Cb1 Y5 Cb2 Y6 Cb3 Y7 Cb4 Cr0 Cb5 Cr1 Cb6 Cr2 Cb7 Cr3 gnded gnded gnded gnded gnded gnded gnded gnded Y0 Cr4 Y1 Cr5 Y2 Cr6 Y3 Cr7 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded 51 44 71 ： 18-bit 1st 2nd edge edge Cb0 Y6 Cb1 Y7 Cb2 Y8 Cb3 Y9 Cb4 Y10 Cb5 Y11 Cb6 Cr0 Cb7 Cr1 Cb8 Cr2 Cb9 Cr3 Cb10 Cr4 Cb11 Cr5 Y0 Cr6 Y1 Cr7 Y2 Cr8 Y3 Cr9 Y4 Cr10 Y5 Cr11 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded YCbCr 15-bit 1st 2nd edge edge gnded gnded gnded gnded Cb0 Y5 Cb1 Y6 Cb2 Y7 Cb3 Y8 Cb4 Y9 Cb5 Cr0 Cb6 Cr1 Cb7 Cr2 Cb8 Cr3 Cb9 Cr4 gnded gnded gnded gnded Y0 Cr5 Y1 Cr6 Y2 Cr7 Y3 Cr8 Y4 Cr9 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded QQ 12-bit 1st 2nd edge edge gnded gnded gnded gnded gnded gnded gnded gnded B0 G4 B1 G5 B2 G6 B3 G7 B4 R0 B5 R1 B6 R2 B7 R3 gnded gnded gnded gnded gnded gnded gnded gnded G0 R4 G1 R5 G2 R6 G3 R7 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded 讯 科 合 圳 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 HSYNC VSYNC DE 市 金 Pin Name 18-bit 1st 2nd edge edge B0 G6 B1 G7 B2 G8 B3 G9 B4 G10 B5 G11 B6 R0 B7 R1 B8 R2 B9 R3 B10 R4 B11 R5 G0 R6 G1 R7 G2 R8 G3 R9 G4 R10 G5 R11 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded RGB 15-bit 1st 2nd edge edge gnded gnded gnded gnded B0 G5 B1 G6 B2 G7 B3 G8 B4 G9 B5 R0 B6 R1 B7 R2 B8 R3 B9 R4 gnded gnded gnded gnded G0 R5 G1 R6 G2 R7 G3 R8 G4 R9 gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded gnded HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC DE DE DE DE DE DE DE DE DE DE DE DE Table 10. Mappings of 12/15/18-bit 4:4:4 dual-edge triggered www.ite.com.tw Oct-2010 Rev:0.9 29/36 IT6613 Pixel0 Pixel1 Pixel2 ... blank 81 blank 9 In this double-edge triggering mode, PCLK frequency remains at the nominal pixel clock rate. The halved data pins, however, run at a data rate double that of the nominal pixel clock rate. Each set of data are clocked out by the rising edge and the falling edge alternatively. Overall one complete pixel is output within one PCLK period. Figure 15 and Figure 16 give two examples. Gpix0 [5:0] Rpix0 [11:6] Gpix1 [5:0] Rpix1 [11:6] Gpix2 [5:0] Rpix2 [11:6] .... val D[11:6] val Bpix0 [11:6] Rpix0 [5:0] Bpix1 [11:6] Rpix1 [5:0] Bpix2 [11:6] Rpix2 [5:0] .... D[5:0] val Bpix0 [5:0] Gpix0 [11:6] Bpix1 [5:0] Gpix1 [11:6] Bpix2 [5:0] Gpix2 [11:6] .... val val val val val val val val val 43 41 5 PCLK 71 val 85 ， val ： val QQ D[17:12] 44 51 D[35:18] DE 18 66 H/VSYNC Pixel0 D[15:12] 合 val 市 金 D[11:8] D[7:4] 技 有 val Gpix0 [3:0] ... blank Rpix0 [7:4] Gpix1 [3:0] Rpix1 [7:4] Gpix2 [3:0] Rpix2 [7:4] .... val val val val Bpix0 [7:4] Rpix0 [3:0] Bpix1 [7:4] Rpix1 [3:0] Bpix2 [7:4] Rpix2 [3:0] .... val val val val Bpix0 [3:0] Gpix0 [7:4] Bpix1 [3:0] Gpix1 [7:4] Bpix2 [3:0] Gpix2 [7:4] .... val val val val 讯 科 D[19:16] Pixel2 限 D[35:20] Pixel1 公 blank 司 ， Figure 15. 18-bit RGB 4:4:4 dual-edge triggered val 深 圳 D[3:0] PCLK DE H/VSYNC Figure 16. 12-bit RGB 4:4:4 dual-edge triggered www.ite.com.tw Oct-2010 Rev:0.9 30/36 IT6613 RGB 4:4:4 and YCbCr 4:4:4 Triggered with 0.5X PCLK at Dual Edges Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Rpix6 val val val val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 D[23:12] val val val val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 D[11:0] val val val val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Gpix6 Bpix6 blank .... val .... val .... val QQ ： 71 D[35:24] ... 81 Pixel1 51 Pixel0 44 blank 9 The bus mapping in this format is the same as that of RGB 4:4:4 and YCbCr 4:4:4 with Separate Syncs. The only difference is that the input video clock (PCLK) is now halved in frequency. The data are in turn to be latched in with both the rising and falling edges of the 0.5X PCLK. Figure 17 and Figure 18 give two examples of such timing format. 85 ， PCLK DE 43 41 5 H/VSYNC 18 66 Figure 17. 36-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK val val val val Pixel4 Pixel5 Pixel6 ... val blank Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 .... val 限 技 有 val val val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 .... val val val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6 .... val 市 金 D[1:0] Pixel3 合 D[13:12] D[11:2] Pixel2 司 val D[25:24] D[23:14] Pixel1 公 val 讯 科 D[35:26] Pixel0 ， blank 圳 PCLK 深 DE H/VSYNC Figure 18. 30-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK www.ite.com.tw Oct-2010 Rev:0.9 31/36 IT6613 System Design Consideration 51 81 9 The IT6613 is a very high-speed interface chip. It takes in TTL signals at up to 148.5MHz with 36-bit data bus and transmits TMDS differential signals at as high as 2.25Gbps and s. At such speeds any PCB design imperfection could lead to compromised signal integrity and hence degraded performance. To get the optimum performance the system designers sould follow the guideline below when designing the application circuits and PCB layout. QQ ： 71 44 1. Pin 28 (PVCC1) should be supplied with clean power: ferrite-decoupled and capacitively- bypassed, since this is the power for the transmitter PLL, which is crucial in determining the TMDS output signal quality . Excess power noise might degrade the system performance. 18 66 43 41 5 85 ， 2. It is highly recommended that all power pins are decoupled to ground pins via capacitors of 0.01uF and 0.1uF. Low-ESL capacitors are prefered. Generally these capacitors should be placed on the same side of the PCB with the IT6613 and as close to the pins as possible, preferably within 0.5cm from the pins. It is also recommended that the power and ground traces run relatively short distances and are connected directly to respecitve power and ground planes through via holes. ， 0.01uF 公 限 Power 司 (Low ESL) Via to ground plane < 0.5cm Figure 19. Layout example for decoupling capacitors. 深 圳 市 金 合 讯 科 技 有 Ground Via to power plane 3. The IT6613 supports 36-bit input bus running at as high as 148.5MHz. To maintain signal integrity and lower EMI, the following guidelines should be followed: A. Employ 4-layer PCB design, where a ground or power plane is directly placed under the signal buses at middle layes. The ground and power planes underneath these buses should be continuous in order to provide a solid return path for EM-wave introduced currents. B. Whenever possible, keep all TTL signal traces on the same layer with the IT6613 and the www.ite.com.tw Oct-2010 Rev:0.9 32/36 IT6613 71 44 51 81 9 frontend decoder. C. TTL input traces from the decoder should be kept as short as possible D. Depending on the TTL output specifications of the frontend decoder, 33Ω resistors might be placed in series to its output pins. This slow down the signal rising edges, reduces current spikes and lower the reflections. E. The PCLK signal should be kept away from other signal traces to avoid crosstalk interference. A general guideline is 2X the dielectric thickness. For example, if the dielectric layer between the signal layer and the immediate power/ground layer is 7 mil, then the PCLK trace should be kept at least 14 mil away from all other signal traces. 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 4. The characteristic impedance of all differential PCB traces should be kept at 100Ω all the way from the HDMI connector to the IT6613. This is crucial to the system performance at high speeds. When layouting these differential transmission lines, the following guidelines should be followed: A. The signals traces should be on the outside layers (TOP layer or BOTTOM layer) while beneath it there should be a continuous ground plane in order to maintain the so-called micro-strip transmission line structure, giving stable and well-defined characteristic impedances. B. Carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various parameters of the PCB: trace width, trace spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM simulation is the best way to derive a correct dimension that enables a nominal 100Ω differential impedance. C. Cornering, through holes, crossing and any irregular signal routing should be minimized so as to prevent from disrupting the EM field and creating discontinuity in characteristic impedance. D. The IT6613 should be placed as close to the HDMI connector as possible. As a rule of thumb, the lengths of the TMDS differential traces (from the TMDS output pins of the IT6613 to the 深 圳 市 金 合 HDMI connector) should be smaller than 1 cm (refer to Figure 20), especially for applications that support TMDS data rates at more than 1.62 Gbps. This is because at such high transmission rates, the source-side reflections would seriously impact the output data eyes. Since PCB traces, even when carefully designed, suffer from large impedance variations, it's a must that the reflection route be kept as short as possible. 5. Special care should be taken when adding discrete ESD devices to all differential PCB traces (TX2P/M, TX1P/M, TX0P/M, TXCP/M). The IT6613 is designed to provide ESD protection for up to 2kV at these pins, which is good enough to prevent damages during assembly. To meet the system EMC specification, external discrete ESD diodes might be added. But note that adding discrete ESD diodes inevitably add capacitive loads, therefore degrade the electrical performance at high speeds. If not chosen carefully, these diodes coupled with less-than-optimal layout would degrade the output www.ite.com.tw Oct-2010 Rev:0.9 33/36 IT6613 DATA2+ GND DATA2- 71 GND 44 RClamp0524p 51 81 9 data eyes, which might fail to pass the SOURCE Data Eye Diagram test in the HDMI Compliance Test (Test ID 7-10). One should only use low-capacitance ESD diode to protect these high-speed pins. Commercially available devices such as Semtech's RClamp0524p that take into consideration of all aspects of designing and protecting high-speed transmission lines are recommended. (http://www.semtech.com/products/product-detail.jsp?navId=H0,C2,C222,P3028). ： DATA1+ GND QQ DATA1- 85 ， DATA0+ 43 41 5 GND 18 66 RClamp0524p 100ohm differentially, L < 1 cm 技 有 限 ， 公 司 S er=4.3 DATA0CLOCK+ GND CLOCKCEC reserved SCL SDA EXAMPLE: 100 ohm: W=9mil, S=11mil W GND W GND +5V 1.8mil HPD 8mil 1.4mil 讯 科 Figure 20. Layout example for high-speed TMDS differential signals 圳 市 金 合 4. Pin 27 (REXT) should be connected to AVCC18 via a 698Ω/1% precision SMD resistor. This resistor is used to calibrate the TMDS output current level and should be placed as close as possible to the IT6613. 深 5. The IT6613 comes embedded with optionally programmable source terminations. It is recommended by HDMI Specifications v1.3a that source terminations be turned on when the operating link rate is over 1.65Gbps. User of the IT6613 may refer to IT6613 Programming Guide for proper control of source terminations through register setting. www.ite.com.tw Oct-2010 Rev:0.9 34/36 IT6613 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Package Dimensions Figure 21. 100-pin LQFP Package Dimensions www.ite.com.tw Oct-2010 Rev:0.9 35/36 IT6613 Classification Reflow Profiles Reflow Profile Pb-Free Assembly 3℃/second max. Preheat -Temperature Min(Tsmin) -Temperature Max(Tsmax) -Time(tsmin to ts tsmax) 9 150℃ 200℃ Time maintained above: -Temperature(TL) -Time(tL) 71 217℃ 44 51 60-180 seconds 81 Average Ramp-Up Rate (Tsmax to Tp) QQ ： 60-150 seconds 260 +0 /-5℃ 85 ， Peak Temperature(Tp) Time within 5 ℃ of actual Peak 20-40 seconds 43 41 5 Temperature(tp) Ramp-Down Rate 8 minutes max. 18 66 Time 25℃ to Peak Temperature 6℃/second max. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Note: All Temperature refer to topside of the package, measured on the package body surface. www.ite.com.tw Oct-2010 Rev:0.9 36/36