3.3 V Upstream Cable Line Driver AD8324 FEATURES FUNCTIONAL BLOCK DIAGRAM BYP VIN+ VOUT+ DIFF OR SINGLE INPUT AMP VIN– VERNIER ATTENUATION CORE OUTPUT STAGE VOUT– ZIN (SINGLE) = 550Ω ZIN (DIFF) = 1100Ω ZOUT DIFF = 75Ω 8 DECODE 8 AD8324 POWERDOWN LOGIC RAMP DATA LATCH 8 SHIFT REGISTER 04339-0-001 Supports DOCSIS 2.0 and Euro-DOCSIS standards for reverse path transmission systems Gain programmable in 1 dB steps over a 59 dB range Low distortion at 61 dBmV output: –59 dBc SFDR at 21 MHz –54 dBc SFDR at 65 MHz Output noise level @ minimum gain 1.3 nV/√Hz Maintains 75 Ω output impedance in TX-enable and Transmit-disable condition Upper bandwidth: 100 MHz (full gain range) 3.3 V supply operation Supports SPI® interfaces APPLICATIONS GND DOCSIS 2.0 and Euro-DOCSIS cable modems CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers –40 GENERAL DESCRIPTION –50 DATEN DATA CLK TXEN SLEEP Figure 1. Functional Block Diagram 1 DISTORTION (dBc) The AD8324 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8324 ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications. The gain of the AD8324 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB. VOUT = 61dBmV @ DEC 60 THIRD HARMONIC –60 VOUT = 61dBmV @ DEC 60 SECOND HARMONIC The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 transformer. 04339-0-002 –70 –80 5 15 25 35 45 FREQUENCY (MHz) 55 65 Figure 2. Worst Harmonic Distortion vs. Frequency Distortion performance of –54 dBc is achieved with an output level up to 61 dBmV at 65 MHz bandwidth. This device has a sleep mode function that reduces the quiescent current to 30 µA and a full power-down function that reduces power-down current to 2.5 mA. The AD8324 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8324 operates from a single 3.3 V supply. 1 Patent pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD8324 TABLE OF CONTENTS Specifications..................................................................................... 3 Power Saving Features ............................................................... 12 Logic Inputs (TTL/CMOS Compatible Logic)......................... 4 Distortion, Adjacent Channel Power, and DOCSIS............... 12 Timing Requirements .................................................................. 4 Utilizing Diplex Filters............................................................... 12 Absolute Maximum Ratings............................................................ 5 Noise and DOCSIS..................................................................... 12 ESD Caution.................................................................................. 5 Evaluation Board Features and Operation.............................. 13 Pin Configurations and Functional Descriptions ........................ 6 Differential Signal Source.......................................................... 13 Typical Performance Characteristics ............................................. 7 Differential Signal from Single-Ended Source ....................... 13 Applications..................................................................................... 10 Single-Ended Source.................................................................. 13 General Applications.................................................................. 10 Overshoot on PC Printer Ports ................................................ 14 Circuit Description..................................................................... 10 Installing Visual Basic Control Software................................. 14 Gain Programming for the AD8324 ........................................ 10 Running AD8324 Software ....................................................... 14 Input Bias, Impedance, and Termination ................................ 10 Controlling Gain/Attenuation of the AD8324 ...................... 14 Output Bias, Impedance, and Termination ............................. 10 Transmit Enable and Sleep Mode............................................. 14 Power Supply............................................................................... 11 Memory Functions..................................................................... 14 Signal Integrity Layout Considerations ................................... 11 Outline Dimensions ....................................................................... 16 Initial Power-Up ......................................................................... 11 Ordering Guide .......................................................................... 16 RAMP Pin and BYP Pin Features ............................................ 11 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8324 SPECIFICATIONS Table 1. TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1 transformer1 at the device output. Parameter INPUT CHARACTERISTICS Specified AC Voltage Input Resistance Conditions Min Output = 61 dBmV, Max Gain Single-Ended Input Differential Input Input Capacitance GAIN CONTROL INTERFACE Voltage Gain Range Max Gain Min Gain Output Step Size2 Output Step Size Temperature Coefficient OUTPUT CHARACTERISTICS Bandwidth (–3 dB) Bandwidth Roll-Off 1 dB Compression Point3 Output Noise Max Gain Min Gain Transmit Disable Noise Figure Max Gain Differential Output Impedance OVERALL PERFORMANCE Second-Order Harmonic Distortion5, 3 Typ 27.5 550 1100 2 TA = –40°C to +85°C 59.0 33.5 –25.5 1.0 ±0.004 All Gain Codes (1–60 Decimal Codes) f = 65 MHz Max Gain, f = 10 MHz, Output Referred Min Gain, f = 10 MHz, Input Referred 100 1.7 21 3.7 Gain Code = 60 Dec Gain Code = 1 Dec Max 58 32.5 –26.5 0.6 19.6 2.1 Unit dBmV Ω Ω pF 60 34.5 –24.5 1.4 dB dB dB dB/LSB dB/°C MHz dB dBm dBm 2 f = 10 MHz f = 10 MHz f = 10 MHz 157 1.3 1.1 166 1.5 1.2 nV/√Hz nV/√Hz nV/√Hz f = 10 MHz TX Enable and TX Disable 15.5 75 ± 30%4 16.0 dB Ω f = 33 MHz, VOUT = 61 dBmV @ Max Gain f = 65 MHz, VOUT = 61 dBmV @ Max Gain f = 21 MHz, VOUT = 61 dBmV @ Max Gain f = 65 MHz, VOUT = 61 dBmV @ Max Gain Max Gain, f = 65 MHz –66 –58 –59 –54 –61 –75 –60 –53 –57.5 –52.5 –58 –70 dBc dBc dBc dBc dBc dB Max Gain, VIN = 0 Max Gain, VIN = 0 Equivalent Output = 31 dBmV Equivalent Output = 61 dBmV 2.5 3.8 2.5 27 6 71 µs µs mV p-p mV p-p Min to Max Gain Max Gain, VIN = 27.5 dBmV 60 30 2 Third-Order Harmonic Distortion5, 3 ACPR 2, 6 Isolation (Transmit Disable) POWER CONTROL TX Enable Settling Time TX Disable Settling Time Output Switching Transients 2 3 Output Settling Due to Gain Change Due to Input Step Change POWER SUPPLY Operating Range Quiescent Current OPERATING TEMPERATURE RANGE Max Gain Min Gain Transmit Disable (TXEN = 0) SLEEP Mode (Power-Down) LFCSP QSOP Rev. 0 | Page 3 of 16 3.13 195 25 1 –40 –25 3.3 207 39 2.5 30 ns ns 3.47 235 50 4 500 V mA mA mA µA +85 +70 °C °C AD8324 1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz. Guaranteed by design and characterization to ±6 sigma for TA = 25°C. 3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 4 Measured through a 1:1 transformer. 5 Specification is worst case over all gain codes. 6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate. 2 LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC) Table 2. DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN Logic 1 Current (VINH = 3.3 V), TXEN Logic 0 Current (VINL = 0 V), TXEN Logic 1 Current (VINH = 3.3 V), SLEEP Logic 0 Current (VINL = 0 V), SLEEP Min 2.1 0 0 −600 50 −250 50 −250 Typ Max 3.3 0.8 20 −100 190 −30 190 −30 Unit V V nA nA µA µA µA µA Min 16.0 32.0 5.0 15.0 5.0 3.0 Typ Max Unit ns ns ns ns ns ns ns TIMING REQUIREMENTS Table 3. VCC = 3.3 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted Parameter Clock Pulse Width (tWH) Clock Period (tC) Setup Time SDATA vs. Clock (tDS) Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) Hold Time DATEN vs. Clock (tEH) Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) 10 tDS SDATA VALID DATA BIT VALID DATA WORD G1 MSB . . . LSB VALID DATA WORD G2 tC tVUH SDATA MSB MSB-1 MSB-2 CLK tES tEH tDS tDH 8 CLOCK CYCLES GAIN TRANSFER (G1) GAIN TRANSFER (G2) 04339-0-004 DATEN CLK tOFF TXEN Figure 4. SDATA Timng tGS SIGNAL AMPLITUDE (p-p) 04339-0-0030 tCN ANALOG OUTPUT Figure 3. Serial Interface Timing Rev. 0 | Page 4 of 16 AD8324 ABSOLUTE MAXIMUM RATINGS Table 4. AD8324 Stress Ratings Parameter Supply Voltage VCC Input Voltage VIN+, VIN– DATEN, SDATA, CLK, SLEEP, TXEN Internal Power Dissipation QSOP, LFCSP Operating Temperature Range LFCSP QSOP Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 3.63 V 1.5 V p-p –0.5 V to +3.63 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 776 mW –40°C to +85°C –25°C to +70°C –65°C to +150°C 300°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 AD8324 20 19 18 17 16 19 VCC GND 3 18 TXEN GND 4 GND 1 GND 2 AD8324 14 VOUT+ VIN+ 3 13 VOUT– VIN– 4 TOP VIEW (Not to Scale) GND 5 15 RAMP 12 BYP GND 8 9 10 SDATA CLK GND SLEEP 04339-0-006 7 DATEN 11 NC 6 AD8324 17 RAMP 16 VOUT+ TOP VIEW VIN– 6 (Not to Scale) 15 VOUT– VIN+ 5 7 14 BYP DATEN 8 13 NC SDATA 9 12 SLEEP CLK 10 11 GND NC = NO CONNECT Figure 5. 20-Lead LFCSP 04339-0-005 VCC 20 GND 2 GND 1 VCC GND GND VCC TXEN PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS Figure 6. 20-Lead QSOP Table 5. Pin Function Descriptions Pin No. 20-Lead LFCSP 1, 2, 5, 9, 18, 19 17, 20 3 Pin No. 20-Lead QSOP 1, 3, 4, 7, 11, 20 2, 19 5 4 6 6 8 VIN– DATEN 7 9 SDATA 8 10 CLK 10 12 SLEEP 12 13 14 15 16 14 15 16 17 18 BYP VOUT– VOUT+ RAMP TXEN Mnemonic GND Description Common External Ground Reference. VCC VIN+ Common Positive External Supply Voltage. Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous and simultaneously enables the register for serial data load). Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit masterslave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 µA. A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part. Internal Bypass. This pin must be externally decoupled (0.1 µF capacitor). Negative Output Signal. Must be biased to VCC. See Figure 23. Positive Output Signal. Must be biased to VCC. See Figure 23. External RAMP Capacitor (Optional). Logic 0 disables forward transmission. Logic 1 enables forward transmission. Rev. 0 | Page 6 of 16 AD8324 TYPICAL PERFORMANCE CHARACTERISTICS –40 –40 VOUT = 62dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 –50 DISTORTION (dBc) VOUT = 62dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 –60 –60 VOUT = 60dBmV @ DEC 60 –70 04339-0-007 –70 VOUT = 60dBmV @ DEC 60 –80 5 15 25 35 45 FREQUENCY (MHz) 55 04339-0-010 DISTORTION (dBc) –50 –80 5 65 Figure 7. Second-Order Harmonic Distortion vs. Frequency for Various Output Powers 15 25 35 45 FREQUENCY (MHz) 55 65 Figure 10. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers –40 –40 VOUT = 61dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 TA = +25°C TA = +85°C –50 DISTORTION (dBc) TA = –40°C –60 TA = +25°C –70 TA = –40°C –60 04339-0-008 –70 TA = +85°C –80 5 15 25 35 45 55 04339-0-011 DISTORTION (dBc) –50 –80 65 5 15 FREQUENCY (MHz) Figure 8. LFSCP Second-Order Harmonic Distortion vs. Frequency vs. Temperature 55 65 Figure 11. LFCSP Third-Order Harmonic Distortion vs. Frequency vs. Temperature –40 –40 VOUT = 61dBmV @ DEC 60 VOUT = 61dBmV @ DEC 60 TA = +25°C TA = +70°C –50 DISTORTION (dBc) –50 TA = +25°C TA = –25°C –60 –70 TA = –25°C –60 TA = +70°C –80 5 15 25 35 45 55 04339-0-012 –70 04339-0-009 DISTORTION (dBc) 25 35 45 FREQUENCY (MHz) –80 65 5 FREQUENCY (MHz) Figure 9. QSOP Second-Order Harmonic Distortion vs. Frequency vs. Temperature 15 25 35 45 FREQUENCY (MHz) 55 Figure 12. QSOP Third-Order Harmonic Distortion vs. Frequency vs. Temperature Rev. 0 | Page 7 of 16 65 AD8324 0 60 CH PWR 12dBm WORST ACP –61dBc VOUT = 57dBmV/TONE @ MAX GAIN 50 –20 40 –30 30 –40 20 VOUT (dBmV) –50 –60 –70 10 0 –10 CU1 C0 C0 –90 –20 CU1 04339-0-013 –80 CL1 CL1 –100 CENTER 21 MHz 100 kHz/DIV 04339-0-016 POUT (dBm) –10 –30 –40 41.6 SPAN 1 MHz Figure 13. Adjacent Channel Power 41.7 41.8 41.9 42.0 42.1 42.2 FREQUENCY (MHz) 42.3 42.4 42.5 Figure 16. Two-Tone Intermodulation Distortion 40 0 TXEN = 0 VIN = 27.5dBmV –10 30 DEC60 –20 DEC54 –30 GAIN (dB) 0 ISOLATION (dB) DEC48 10 DEC42 DEC36 DEC30 –10 DEC24 –50 –60 –70 DEC18 DEC12 –80 –30 DEC 1 TO DEC 6 –40 0.1 1 10 FREQUENCY (MHz) MAX GAIN 04339-0-014 –20 –40 100 04339-0-017 20 –90 MIN GAIN –100 1000 100 10 FREQUENCY (MHz) 0 Figure 14. AC Response 1000 Figure 17. Isolation in Transmit Disable Mode vs. Frequency 1.4 2.0 1.5 1.2 1.0 GAIN ERROR (dB) 1.3 1.1 1.0 0.9 0.8 0.5 f = 5MHz 0 f = 10MHz f = 42MHz –0.5 –1.0 0.7 0.6 0 6 12 18 24 30 36 42 48 54 f = 65MHz –1.5 04339-0-018 04339-0-015 OUTPUT STEP SIZE (dB) f = 10MHz –2.0 60 0 GAIN CONTROL (Decimal Code) 6 12 18 24 30 36 42 48 GAIN CONTROL (Decimal Code) Figure 15. Output Step Size vs. Gain Control Figure 18. Gain Error vs. Gain Control Rev. 0 | Page 8 of 16 54 60 180 110 TXEN = 1 140 120 100 80 60 40 20 0 0 6 12 18 24 30 36 42 48 54 100 90 80 70 60 50 DOCSIS 2.0 BETWEEN BURST TRANSIENT SPECIFICATION 40 30 AD8324 20 04339-0-021 160 BETWEEN BURSTS TRANSIENTS (mV p-p) f = 10MHz 04339-0-019 10 0 60 0 6 GAIN CONTROL (Decimal Code) 12 18 Figure 19. Output Referred Voltage Noise vs. Gain Control 30 36 42 48 54 60 Figure 21. Between Burst Transient vs. Gain Control 3.3V 210 TA = 25°C 190 0.1µF 10µF 170 18.7Ω 150 VCC VIN+ 130 110 18.7Ω 90 1/2 VIN 1/2 VIN OUT+ 1:1 AD8324 39.5Ω VIN– 75Ω 50 30 0 6 12 OUT– 0.1µF 0.1µF 18 24 30 36 42 48 54 Figure 22. Typical Characterization Circuit 60 GAIN CONTROL (Decimal Code) Figure 20. Supply Current vs. Gain Control Rev. 0 | Page 9 of 16 RL BYP GND 70 04339-0-020 QUIESCENT SUPPLY CURRENT (mA) 24 GAIN CONTROL (Decimal Code) 04339-0-022 OUTPUT REFERRED VOLTAGE NOISE (nV/ Hz) AD8324 AD8324 APPLICATIONS GENERAL APPLICATIONS The AD8324 is primarily intended for use as the upstream power amplifier (PA) in DOCSIS (data over cable service interface specification) certified cable modems and CATV settop boxes. The upstream signal is either a QPSK or QAM signal generated by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all cases, the signal must be low-pass filtered before being applied to the PA in order to filter out-of-band noise and higher order harmonics from the amplified signal. Due to the varying distances between the cable modem and the head-end, the upstream PA must be capable of varying the output power by applying gain or attenuation. The ability to vary the output power of the AD8324 ensures that the signal from the cable modem will have the proper level once it arrives at the head-end. The upstream signal path commonly includes a diplexer and cable splitters. The AD8324 has been designed to overcome losses associated with these passive components in the upstream cable path. CIRCUIT DESCRIPTION The AD8324 is composed of three analog functions in the transmit-enable mode. The input amplifier (preamp) can be used in a single-ended or differential configuration. If the input is used in the differential configuration, the input signals should be 180 degrees out of phase and of equal amplitude. A vernier is used in the input stage for controlling the fine 1 dB gain steps. This stage then drives a DAC, which provides the bulk of the AD8324’s attenuation. The signals in the preamp and DAC blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage. The output stage maintains 75 Ω differential output impedance in all power modes. that uses 8-bits to program the cable driver, the 2 MSBs will be ignored. This allows the AD8324 to be compatible with some existing system designs. The AD8324 recognizes gain codes 1 through 60 (all gain codes are in decimal, unless otherwise noted). When the AD8324 is programmed with 61 to 63, it will internally default to max gain (gain code 60). If the programmed gain code is above 63, the AD8324 will recognize only the 6 LSBs. For example, gain code 75 (01001011 binary) will be interpreted as gain code 11 (001011 binary) since the 2 MSBs are ignored. The programming range of the AD8324 is from –25.5 dB (gain code 1) to +33.5 dB (gain code 60). The 60 dB gain range is linear with a 1 dB change in a 1 LSB change in gain code. Figure 15 illustrates the gain step size of the AD8324 versus gain code. The AD8324 was characterized with a differential input signal and a TOKO 458PT-1457 1:1 transformer at the output. INPUT BIAS, IMPEDANCE, AND TERMINATION The VIN+ and VIN– inputs have a dc bias level of VCC/2; therefore the input signal should be ac-coupled as seen in the typical application circuit (Figure 23). The differential input impedance of the AD8324 is approximately 1.1 kΩ, while the single-ended input is 550 Ω. The high input impedance of the AD8324 allows flexibility in termination and properly matching filter networks. The AD8324 will exhibit optimum performance when driven with a pure differential signal. OUTPUT BIAS, IMPEDANCE, AND TERMINATION. The output stage of the AD8324 requires a bias of 3.3 V. The 3.3 V power supply should be connected to the center tap of the output transformer. Also, the VCC that is being applied to the center tap of the transformer should be decoupled as seen in the typical application circuit (Figure 23). GAIN PROGRAMMING FOR THE AD8324 The AD8324 features a serial peripheral interface (SPI) for programming the gain code settings. The SPI interface consists of three digital data lines: CLK, DATEN, and SDATA. The DATEN pin should be held low while the AD8324 is being programmed. The SDATA pin accepts the serial data stream for programming the AD8324 gain code. The CLK pin accepts the clock signal to latch in the data from the SDATA line. The AD8324 utilizes a 6-bit shift register for clocking in the data. The shift register is designed to be programmed MSB first. The timing interface for programming the AD8324 can be seen in Table 2, Table 3, Figure 3, and Figure 4. While the DATEN pin is held low, the serial bits on the SDATA line are shifted into the register on the rising edge of the CLK pin. For existing software The output impedance of the AD8324 is 75 Ω, regardless of whether the amplifier is in transmit enable, transmit disable, or sleep mode. This, when combined with a 1:1 voltage ratio transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must be used to provide the test circuit with the proper impedance match. The AD8324 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder will allow testing on a 50 Ω system. When using a matching attenuator, it should be noted that there will be 5.7 dB of power loss (7.5 dB voltage) through the network. Rev. 0 | Page 10 of 16 AD8324 VCC 10µF AD8324-JRQ 1 2 0.1µF 3 VIN+ 4 5 ZIN = 150Ω 174Ω 6 7 8 VIN– 9 0.1µF 10 GND GND VCC VCC GND TXEN GND RAMP VIN+ VOUT+ VIN– VOUT– GND BYP DATEN NC SDATA SLEEP GND CLK 20 19 18 0.1µF 17 TO DIPLEXER ZIN = 75Ω 1:1 16 15 TOKO 458PT-1556 14 13 0.1µF 12 11 1kΩ DATEN 1kΩ SDATA 1kΩ CLK 04339-0-023 1kΩ TXEN 1kΩ SLEEP Figure 23. Typical Application Circuit Table 6. Adjacent Channel Power Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 160 –63 –63 –64 –67 –70 –72 320 –64 –64 –64 –65 –67 –70 POWER SUPPLY The 3.3 V supply should be delivered to each of the VCC pins via a low impedance power bus. This ensures that each pin is at the same potential. The power bus should be decoupled to ground using a 10 µF tantalum capacitor located close to the AD8324. In addition to the 10 µF capacitor, VCC pins should be decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, labeled BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the AD8324 and the output transformer. All AD8324 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. Adjacent Channel Symbol Rate (kSym/s) 640 1280 2560 –68 –71 –72 –66 –70 –72 –65 –67 –71 –65 –66 –68 –66 –66 –67 –67 –67 –64 5120 –66 –67 –67 –67 –65 –64 and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guidelines will optimize the overall performance of the AD8324 in all applications. INITIAL POWER-UP When the supply voltage is first applied to the AD8324, the gain of the amplifier is initially set to gain code 1. As power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. After power has been applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the Gain Programming for the AD8324 section. The TXEN pin can then be brought from Logic 0 to Logic 1, enabling forward signal transmission at the desired gain level. SIGNAL INTEGRITY LAYOUT CONSIDERATIONS RAMP PIN AND BYP PIN FEATURES Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short will minimize parasitic capacitance and inductance, which is most critical between the outputs of the AD8324 and the 1:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input The RAMP pin (Pin 15) is used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected will result in a transient that is fully compliant with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients. DOCSIS requires that all between burst transients must be dissipated no faster than 2 µs. Adding capacitance to the RAMP pin will slow the dissipation even more. Rev. 0 | Page 11 of 16 AD8324 The BYP pin is used to decouple the output stage to ground. Typically, for normal DOCSIS operation, the BYP pin should be decoupled to ground with a 0.1 µF capacitor. However, in applications that may require transient on/off times faster than 2 µs, smaller capacitors may be used, but it should be noted that the BYP pin should always be decoupled to ground. POWER SAVING FEATURES The AD8324 incorporates three distinct methods of reducing power consumption: transmit disable and sleep modes for between-burst and shutdown modes, as well as gain dependent quiescent current for transmit enable mode. The asynchronous TXEN pin is used to place the AD8324 into between-burst mode. In this reduced current state, the 75 Ω output impedance is maintained. Applying Logic 0 to the TXEN pin deactivates the on-chip amplifier, providing a 98.8% reduction in consumed power. For 3.3 V operation, the supply current is typically reduced from 207 mA to 2.5 mA. In this mode of operation, between-burst noise is minimized and high input to output isolation is achieved. In addition to the TXEN pin, the AD8324 also incorporates an asynchronous SLEEP pin, which may be used to further reduce the supply current to approximately 30 µA. Applying Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode may result in a transient voltage at the output of the amplifier. In addition to the sleep and transmit disable functions, the AD8324 provides yet another means of reducing system power consumption. While in the transmit enable state, the AD8324 incorporates supply current scaling, which allows for lower power consumption at lower gain codes. Figure 20 shows the typical relationship between supply current and gain code. DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS To deliver the DOCSIS required 58 dBmV of QPSK signal and 55 dBmV of 16 QAM signal, the PA is required to deliver up to 61 dBmV. This added power is required to compensate for losses associated with the diplex filter or other passive components that may be included in the upstream path of cable modems or set-top boxes. It should be noted that the AD8324 was characterized with a differential input signal. Figures 7 to 10 show the AD8324 second and third harmonic distortion performance versus the fundamental frequency for various output power levels. These figures are useful for determining the inband harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for Euro-DOCSIS) will be sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power, commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1 states, “Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.” Figure 13 shows the typical ACP for a 61 dBmV (approximately 12 dBm) QPSK signal taken at the output of the AD8324 evaluation board. The transmit channel width and adjacent channel width in Figure 13 correspond to the symbol rates of 160 kSym/s. Table 6 shows the ACP results for the AD8324 driving a QPSK, 61 dBmV signal for all conditions in DOCSIS Table 6-9, Adjacent Channel Spurious Emissions. UTILIZING DIPLEX FILTERS The AD8324 was designed to drive 61 dBmV without any external filtering and still meet DOCSIS spurious emissions and distortion requirements. However, in most upstream CATV applications, a diplex filter is used to separate the upstream and downstream signal paths from one another. The diplex filter does have insertion loss that the upstream driver needs to overcome, but it also provides a low-pass filter. The addition of this low-pass filter to the signal chain can greatly attenuate second harmonic products of channels above 21 MHz and third harmonic products of channels at or above 14 MHz up for diplexers with a 42 MHz upstream cutoff. Similar performance gains can be achieved using European-specified diplexers to filter second harmonics for channels above 33 MHz and third harmonics for channels above 22 MHz (65 MHz upstream cutoff). This filtering allows the AD8324 to drive up to 63 dBmV of QPSK (this level can vary by application and modulation type). NOISE AND DOCSIS At minimum gain, the AD8324 output noise spectral density is 1.3 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious Emissions in 5 MHz to 42 MHz, specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 kSym/s is 20 × log [√(1.3 nV/√Hz)2 × 160 kHz] + 60 = –65.7 dBmV Comparing the computed noise power of –65.7 dBmV to the +8 dBmV signal yields –73.7 dBc, which meets the required level set forth in DOCSIS Table 6-10. As the AD8324 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal-tonoise ratio that improves with gain. In transmit disable mode, the output noise spectral density is 1.1 nV/√Hz, which results in –67 dBmV when computed over 160 kSym/s. The noise power was measured directly at the AD8324AR-EVAL’s output. Rev. 0 | Page 12 of 16 AD8324 EVALUATION BOARD FEATURES AND OPERATION DIFFERENTIAL SIGNAL SOURCE Typical applications for the AD8324 use a differential input signal from a modulator or a DAC. Refer to Table 7 for common values of R4, or calculate other input configurations using the equation in Figure 24. This circuit configuration will give optimal distortion results due to the symmetric input signals. It should be noted that this is the configuration that was used to characterize the AD8324. R4 = ZIN × 1100Ω 1100Ω – ZIN VIN+ ZIN AD8324 VIN+ ZIN VIN– AD8324 R4 Figure 25. Single-to-Differential Circuit SINGLE-ENDED SOURCE Although the AD8324 was designed to have optimal DOCSIS performance when used with a differential input signal, the AD8324 may also be used as a single-ended receiver, or as an IF digitally controlled amplifier. However, as with the single-ended to differential configuration noted previously, even order harmonic distortion will be slightly degraded. When operating the AD8324 in a single-ended input mode, terminate the part as illustrated in Figure 26. On the AD8324 evaluation boards, this termination method requires the removal and shorting of R2 and R3, the removal of R4, as well as the addition of 86.6 Ω at R1 and 40.2 Ω at R17 for 75 Ω termination. Table 7 shows the correct values for R11 and R12 for some common input configurations. Other input impedance configurations may be accommodated using the equations in Figure 26. 04339-0-024 R4 ZIN × 1100Ω 1100Ω – ZIN 04339-0-025 The AD8324 evaluation board and control software can be used to control the AD8324 upstream cable driver via the parallel port of a personal computer. A standard printer cable connected to the parallel port of the PC is used to feed all the necessary data to the AD8324 using the Windows® based control software. This package provides a means of controlling the gain and the power mode of the AD8324. With this evaluation kit, the AD8324 can be evaluated in either a single-ended or differential input configuration. A schematic of the evaluation board is provided in Figure 29. R4 = R1 = Figure 24. Differential Circuit ZIN × 550 550 – ZIN R17 = ZIN × R1 R1 – ZIN VIN+ R1 AD8324 ZIN The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. This configuration uses a 1:1 balun transformer to approximate a differential signal. Because of the non-ideal nature of real transformers, the differential signal is not purely equal and opposite in amplitude. Although this circuit slightly sacrifices even order harmonic distortion due to asymmetry, it does provide a convenient way to evaluate the AD8324 with a singleended source. The AD8324 evaluation board is populated with a TOKO 617DB-A0070 1:1 for this purpose (T1). Table 7. Common Matching Resistors Table 7 provides typical R4 values for common input configurations. R16 must be removed, and R2 and R3 should be shorted. Other input impedances may be calculated using the equation in Figure 25. Refer to Figure 29 for an evaluation board schematic. To use the transformer for converting a single ended source into a differential signal, the input signal must be applied to VIN+. ZIN (Ω) 50 75 R17 04339-0-026 DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE Figure 26. Single-Ended Circuit ZIN (Ω) 50 75 100 150 Rev. 0 | Page 13 of 16 Differential Input Termination R2/R3 (Ω) R4 (Ω) Open 52.3 Open 80.6 Open 110 Open 174 Single-Ended Input Termination R2/R3 (Ω) R4 (Ω) 0/0 Open 0/0 Open R1/R17 (Ω) Open/Open Open/Open Open/Open Open/Open R1/R17 (Ω) 54.9/26.1 86.6/40.2 AD8324 OVERSHOOT ON PC PRINTER PORTS The data lines on some PC parallel printer ports have excessive overshoot, which may cause communications problems when presented to the CLK pin of the AD8324. The evaluation board was designed to accommodate a series resistor and shunt capacitor (R9 and C5 in Figure 29) to filter the CLK signal if required. For parallel ports with logic levels above 3.3 V, R9 and C5 may be used as an attenuator. CONTROLLING GAIN/ATTENUATION OF THE AD8324 The slide bar controls the gain/attenuation of the AD8324, which is displayed in dB and in V/V. The gain scales 1 dB per LSB. The gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (Figure 28). INSTALLING VISUAL BASIC CONTROL SOFTWARE Install the CabDrive_24 software by running the setup.exe file on disk one of the AD8324 evaluation software. Follow the onscreen directions and insert disk two when prompted. Choose the installation directory and then select the icon in the upper left to complete the installation. RUNNING AD8324 SOFTWARE 04339-0-028 To load the control software, go to START, PROGRAMS, CABDRIVE_24 or select the AD8324.exe file from the installed directory. Once loaded, select the proper parallel port to communicate with the AD8324 (Figure 27). Figure 28. Control Software Interface 04339-0-027 TRANSMIT ENABLE AND SLEEP MODE Figure 27. Parallel Port Selection The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8324 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmission. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8324 for forward transmission. Checking the Enable SLEEP Mode checkbox applies Logic 0 to the asynchronous SLEEP pin, setting the AD8324 for SLEEP mode. MEMORY FUNCTIONS The Memory section of the software provides a way to alternate between two gain settings. The X–>M1 button stores the current value of the gain slide bar into memory, while the RM1 button recalls the stored value, returning the gain slide bar to the stored level. The same applies to the X–>M2 and RM2 buttons. Rev. 0 | Page 14 of 16 AD8324 2 6 4 TOKO1 VIN–_A R3A OPEN R17A OPEN R4A 73.4Ω VCC1 C2A 0.1µF 1 3 R5A 1kΩ R6A 0Ω C3A OPEN 4 5 6 7 8 9 TP2A P1 3 R7A 1kΩ 10 R8A 0Ω AD8324 GND GND VCC VCC GND TXEN 20 19 18 17 GND RAMP VIN+ VOUT+ 16 VIN– VOUT– 15 GND BYP DATAEN SDATA CLK C8A 10µF C9A OPEN DUT1 2 TP1A 2 TP9A 3 T1A 1 R1A OPEN P1 C1A 0.1µF R2A OPEN VIN+_A NC SLEEP GND C10A 0.1µF C11A OPEN 1 T2A 14 13 12 11 C12A 0.1µF VCC1 2 R15A 0Ω 6 4 3 TOKOB5F CABLE_0A R16A OPEN C13A 0.1µF C4A OPEN P1 19 P1 20 TP3A P1 5 R9A 1kΩ P1 21 R10A 0Ω P1 22 P1 23 C5A OPEN P1 24 P1 25 TP4A P1 6 R11A 1kΩ P1 26 R12A 0Ω P1 27 TP10A C6A OPEN TP11A TP12A TP5A R13A 1kΩ P1 P1 28 P1 29 P1 30 TP_AGND1 TP_VCC1 AGND1 VCC1 R14A 0Ω P1 31 7 04339-0-029 C7A OPEN P1 16 Figure 29. AD8324 Evaluation Board Schematic Rev. 0 | Page 15 of 16 AD8324 OUTLINE DIMENSIONS 0.60 MAX 4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR 16 15 3.75 BSC SQ TOP VIEW 11 10 0.20 REF 0.50 BSC 5 0.30 0.23 0.18 0.05 MAX 0.02 NOM SEATING PLANE 6 0.25 MIN 0.80 MAX 0.65 TYP 1.00 0.85 0.80 2.25 2.10 SQ 1.95 BOTTOM VIEW 0.75 0.55 0.35 12° MAX 20 1 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body (CP-20) Dimensions shown in millimeters 0.341 BSC 20 11 0.154 BSC 1 0.236 BSC 10 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AD Figure 31. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches ORDERING GUIDE Model AD8324JRQ AD8324JRQ-REEL AD8324JRQ-REEL7 AD8324JRQ-EVAL AD8324ACP AD8324ACP-REEL7 AD8324ACP-EVAL 1 2 Temperature Range –25°C to +70°C –25°C to +70°C –25°C to +70°C –40°C to +85°C –40°C to +85°C Package Description 20-Lead QSOP 20-Lead QSOP 20-Lead QSOP Evaluation Board 20-Lead LFCSP 20-Lead LFCSP Evaluation Board Thermal resistance measured on SEMI standard 4-layer board. Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04339–0–10/03(0) Rev. 0 | Page 16 of 16 θJA (°C/W) 83.21 83.2 83.2 Package Option RQ-20 RQ-20 RQ-20 30.42 30.4 CP-20 CP-20 1 1 2