MDTIC 10P75

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【1】
10P57AD REVIEW
1.1 General Description
The 10P57AD is an 8-bit microprocessor embedded dev ice. It includes an 8-bit RISC MCU core, 64 bytes SRAM,
4XPWM,ADC and a 2.0K internal program OTP-ROM.
1.2 Features
8-bit RISC microprocessor
System Clock
Internal Oscillator
Internal +/- 2% 16MHz Oscillator.
Internal oscillator 32KHz free run clock for suspend mode.
External crystal Oscillator
One Operating Frequency Range of Oscillator/crystal is 32k~16 MHz.
One RC type up to 10MHz
Optional external ceramic resonator or internal clock mode for MCU clock.
10+2 I/O ports
On chip 2.0K x 14 program OTP Memory .
6 level stack.
64 bytes internal SRAM.
Optional Fosc/(1,2,4,8,16) MCU clock.
MCU can switch to work on External clock / internal slow 32K Hz clock.
Four 12-bit Timers/Counters are PTM0,PTM1,PTM2,PTM3 individually.
Watch dog Timer.
High current dive on any GPIO pin :15mA pin current drive and sink.
Each GPIO pin supports high-impedance input, internal pull-ups,
open drains output, or CMOS outputs.
External interrupt on all GPIO pin.
5+1 Channel 12-bit ADC.
Optional Continues or Trigger mode to sample.
Support 5 channel external ADC input and a internal VDD/4 ADC input.
Build in AD reference voltage (VDD, 4V, 3V, 2V).
Support One channel DAC output.
Power on Manager
Power on reset (POR) is 1.8V
Chip can work on greater than 2.0V power.
Three level Low Voltage Detect : LVDH(3.6V),LVDM(2.4V),LVDL(2.0V).
Build in PWM function.
Support 4 channels PWM
GPIO supply 1.8V~5V interface.
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P.1
Rev13 January 18, 2011
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10P57AD
1.3 Block Diagram
OTP
8-bit
RISC
CPU
64 Bytes
SRAM
M
U
X
XTAL
XIN
XOUT
IRC
SIRC
LVD
WDT
PORTA
PORTB
PWM0
PWM2
CHIRP0
CHIRP2
PWM1
PWM3
CHIRP1
CHIRP3
12-BIT
ADC
B-VD
1.4 Pin Definitions
VDD
XIN/PA[0]
XOUT/PA[1]
RSTN/VPP/PA[2]
PWM0/PA[3]
PWM1/PA[4]
T0CK/PA[5]
1
2
3
4
5
6
7
14-PIN
14
13
12
11
10
9
8
VSS
PB[0]/AIN0
PB[1]/AIN1
PB[2]/AIN2
PB[3]/AIN3
PB[4]/AIN4/VREFH
PB[5]/T1CK
10P57AD
PDIP/SOP
10P57AD
PDIP/SSOP
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P.2
Rev13 January 18, 2011
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10P57AD
1.5 Pin Description
PIN
Name
PA[0]
I/O
XIN
PA[1]
I
IO
XOUT
PA[2]
I
I
IO
14-pin
P
2
3
4
16-pin
S
2
3
4
VPP
Description
GPIO Port A [0]capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
Up to 16Mhz ceramic resonator or external clock input when external
Crystal enable.
GPIO Port A [1]capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
Up to 16Mhz ceramic resonator or external clock output when external
Crystal enable.
GPIO Port A [2] input and a resistive pull-up.
Programming voltage supply, VCC for normal operation
RSTN
PA[3]
I
IO
5
5
PWM0
PA[4]
O
IO
6
6
PWM1
PA[5]
O
O
IO
7
7
T0CK
PA[6]
I
IO
--
8
PWM2
PA[7]
I
IO
--
9
PWM3
PB[5]
I
IO
8
10
T1CK
PB[4]
I
IO
9
11
AIN4
VREFH
PB[3]
I
IO
10
12
External reset pin , active low..
GPIO Port A [3] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
PWM0 signal output pin when PWM0 enable.
GPIO Port A [4]c apable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
PWM1 signal output pin when PWM1 enable.
GPIO Port A [5] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
Timer 0 or PWM0 timer or PWM2 timer external clock input pin
GPIO Port A [6]capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
PWM2 signal output pin when PWM2 enable
GPIO Port A [7] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
PWM3 signal output pin when PWM3 enable
GPIO Port B [5] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
Timer 1 or PWM1 timer or OWM3 timer external clock input pin
GPIO Port B [4 ]capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
ADC input channel-4.
External high reference voltage input of ADC
GPIO Port B [3] capable of sinking up to 25mA/pin, or sinking controlled low
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P.3
Rev13 January 18, 2011
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10P57AD
PIN
Name
I/O
14-pin
P
16-pin
S
Description
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
AIN3
PB[2]
I
IO
11
13
AIN2
PB[1]
I
IO
12
14
AIN1
PB[0]
O
O
IO
13
15
AIN0
VSS
I
G
14
16
ADC input channel-3.
GPIO Port B [2] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
ADC input channel-2.
GPIO Port B [1] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
ADC input channel-1.
GPIO Port B [0] capable of sinking up to 25mA/pin, or sinking controlled low
or high programmable current. Can also source 25 mA drive current or
provide a resistive pull-up, or serve as a high-impedance input.
ADC input channel-0.
Ground
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P.4
Rev13 January 18, 2011