深圳市美芯微电子有限公司 麦肯单片机授权一级代理商 电话：０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 1.General Description MDT10P622 while PED is Disable This OTP-Based 8-bit micro-controller ◆ Power Edge-detector Reset (PED) uses a fully static CMOS technology ◆ Interrupt capability process to achieve higher speed and ◆ Timer0:8-bit timer with 8-bit prescaler smaller size with the low power consumption and high noise immunity. On chip memory includes 3K words of EPROM, and 128bytes of static RAM. (RTCC) ◆ Timer1:16bit timer with 16bit compare register. This timer can be used as carrier generator. ◆ 4 Channel comparator ◆ Sleep mode for power saving. 2.Features ◆ PB with port change wake- up interrupt ◆ RISC CPU ◆ Fully static design ◆ 37 single word instructions ◆ 3K × 14 program memory 3.Applications ◆ 128 bytes RAM for data range from appliance motor control and high ◆ 23 bi-directional I/O speed automotive to low power remote ◆ Eight level hardware stacks transmitters/receivers and ◆ Watchdog timer (WDT) with on-chip RC telecommunications processors, such as The application areas of this NEW MCU Remote controller, small instruments, toy , oscillator ◆ Power-On Reset (POR) ,only available automobile and keyboard…etc. This specification are subject to be changed without notice. Any latest information please preview http;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.1 2006/7 Ver1.0 MDT10P622 4. Pin Diagram DIP/SOP SSOP PA4/RTCC 1 28 /MCLR VSS 1 28 /MCLR VDD 2 27 OSC1 PA4/RTCC 2 27 OSC1 PA5 3 26 OSC2 VDD 3 26 OSC2 VSS 4 25 PC7 PA6/INT 4 25 PC7 PA6/INT 5 24 PC6/ VREF PA0 5 24 PC6/ VREF PA0 6 23 PC5/CIC3 PA1 6 23 PC5/CIC3 PA1 7 22 PC4/CIC2 PA2 7 22 PC4/CIC2 PA2 8 21 PC3/CIC1 PA3 8 21 PC3/CIC1 PA3 9 20 PC2/CIC0 PB0 9 20 PC2/CIC0 PB0 10 19 PC1/T1OSI PB1 10 19 PC1/T1OSI PB1 11 18 PC0/T1OSO/T1SKI PB2 11 18 PC0/T1OSO/T1SKI PB2 12 17 PB7 PB3 12 17 PB7 PB3 13 16 PB6 PB4 13 16 PB6 PB4 14 15 PB5 VSS 14 15 PB5 This specification are subject to be changed without notice. Any latest information please pleasepreview previewhttp;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.2 2006/7 Ver1.0 MDT10P622 5. Pin function description Pin name Type Buffer type Description OSC1 I Oscillator input OSC2 O Oscillator out /MCLR I ST Reset input Bi-directional I/O port A. PA6 internal pull-high PA0 I/O TTL PA1 I/O TTL PA2 I/O TTL PA3 I/O TTL PA4 I/O ST PA5 I/O TTL PA6(/INT) I/O ST/TTL 80K ohm . PA4 Can be clock input to RTCC input Can be change pin function to be external interrupt pin /int Bi-directional I/O port B. Port B can be software programmed for internal 100K ohm pull-up on all pins. PB0-PB7 can generate interrupt on pin state change. PB0 I/O ST/TTL PB0 serial programming clock PB1 I/O ST/TTL PB1 serial programming data PB2 I/O TTL PB3 I/O TTL PB4 I/O TTL PB5 I/O TTL PB6 I/O TTL PB7 I/O TTL Bi-directional I/O port C.. PC0 I/O ST Can be Timer1 oscillator output or Timer1 clock input. PC1 I/O ST Can be Timer1 oscillator input. PC2 I/O TTL TTL input level or Comparator input PC3 I/O TTL TTL input level or Comparator input PC4 I/O TTL TTL input level or Comparator input PC5 I/O TTL TTL input level or Comparator input PC6 I/O TTL TTL input level or Comparator VREF input PC7 I/O TTL Vdd Power input Vss Ground pin This specification are subject to be changed without notice. Any latest information please pleasepreview preview http;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.3 2006/7 Ver1.0 MDT10P622 6. Memory Mapping 6.2Register file map : 6.1Program memory : BANK 0 BANK 1 00h IAR IAR 80h 0001h 01h RTCC TMR 81h 0002h 02h PCL PCL 82h 0003h 03h STATUS STATUS 83h 0004h Peripheral interrupt Vector 04h MSR MSR 84h 0005h 05h PORT A CPIO A 85h 06h PORT B CPIO B 86h 07h PORT C CPIO C 87h 0000h Reset Vector Program memory (Page 0) 07FFh 08h 88h 0800h 09h 89h Program memory 0Ah PCHLAT PCHLAT 8Ah (Page 1) 0Bh INTS INTS 8Bh 0Ch PIFB1 PIEB1 8Ch 0BFFh 0Dh 8Dh 0Eh TMR1L PSTA 8Eh 0Fh TMR1H 8Fh 10h T1CON OPTION2 90h 11h 91h 12h 92h 13h 93h 14h 94h 15h CCPR1L 95h 16h CCPR1H 96h 17h CCPR1C 97h 18h 98h 1Fh 9Fh 20h A0h General Purpose Register General Purpose Register BFH 7Fh Unimplemented memory location. This specification are subject to be changed without notice. Any latest information please pleasepreview previewhttp;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.4 2006/7 Ver1.0 MDT10P622 BANK0 00 01 02 03 IAR (Indirect addressing register) RTCC (Timer0) register Program counter low byte Status register Bit Symbol 0 1 2 3 4 5 C DC Z PF TF Bank 6:7 04 05 06 07 08 09 0A 0B Function Carry Digit carry Zero flag Power-down flag WDT time-out flag Register bank select (For direct addressing) =0 Bank 0 (00h-7Fh) =1 Bank 1 (80h-BFh) General purpose bit MSR (Memory select register) PORTA (Port A data register) PORTB (Port B data register) PORTC (Port C data register) Unimplemented. Unimplemented. PCHLAT (Program memory segment register) INTS (Interrupt control register) Bit 0 1 2 3 4 5 6 7 0C 0D 0E Function PB port change interrupt flag bit. /INT external interrupt flag bit. RTCC(Timer0) overflow interrupt flag bit. PB port change interrupt enable bit. /INT external interrupt enable bit. Timer0 overflow interrupt enable bit. Peripheral interrupt enable bit. Global interrupt enable bit. PIFB1 (Peripheral interrupt flag register 1.) Bit Function 0 7-1 Timer1 overflow interrupt flag bit Unimplemented. Always read as 0. Unimplemented. TMR1L (Timer1 data register low byte.) This specification are subject to be changed without notice. Any latest information please pleasepreview preview http;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.5 2006/7 Ver1.0 MDT10P622 0F 10 TMR1H (Timer1 data register high byte.) T1CON (Timer1 control register) Bit 11-14 15 16 17 Function 0 Timer1 enable bit (0:disable 1:enable) 1 Timer1 clock source select (0:internal clock 1:external input) 2 Timer1 external clock synchronization control bit (0:synchronization 1: asynchronous) 3 Timer1 oscillator enable control bit (0:disable 1:enable) 4-7 Unimplemented. Always read as 0. Unimplemented. CCPR1L (Timer1 compare low register.)(8BIT) CCPR1H (Timer1 compar high register.)(8BIT) CCPR1C (Timer1 compare control register) Bit 7-1 –Unimplemented. Always set as 0. Bit 0 – compare enable bit (0:disable 1:enable) Unimplemented. General purpose register 18-1F 20-7F BANK1 80 81 Same as register 00. TMR (Time mode register) Bit Symbol Function Prescaler 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Value RTCC 0 1 0 1 0 1 0 1 rate WDT 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 2–0 PS 2–0 3 PSC Prescaler assign bit 4 TCE RTCC edge select bit 0:Increment on low to high 5 TCS RTCC clock source select bit 0:Internal clock 1:RTCC Pin 0:RTCC rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1:WDT 1:Increment on high to low This specification are subject to be changed without notice. Any latest information please pleasepreview previewhttp;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.6 2006/7 Ver1.0 MDT10P622 Bit 82-84 85 86 87 88 89 8A-8B 8C 8D 8E Symbol Function 6 /INT interrupt edge select bit 7 Port B pull-up enable bit. (0:enable 1:disable) Same as 02H-04H. Port A data direction register.(CPIO A) Port B data direction register.(CPIO B) Port C data direction register.(CPIO C) Unimplemented. Unimplemented. Same as 0AH-0BH. Peripheral interrupt control register 1. Bit 0 – Timer1 overflow interrupt enable bit. 7-1 – Unimplemented. Always set these bits to 0. Unimplemented. PSTA (Power control register and Comparator control register.) BIT Function 0 The comparator function enable bit 1 Power-on reset status bit 2 0:Define PC2 as TTL input (CMR0) 1:Define PC2 as comparator input. 3 0:Define PC3 as TTL input (CMR1) 1:Define PC3 as comparator input. 4 0:Define PC4 as TTL input (CMR2) 1:Define PC4 as comparator input. 5 0:Define PC5 as TTL input (CMR3) 1:Define PC5 as comparator input. 7:6 (0:disable 1:enable) Reference Voltage select(CMR5~CMR4) 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF(External pin and PC6 must set to input) 8F 90 Unimplemented. Option register 2. ( “ 0 ” Enable ; “ 1 ” Disable ) Bit 0–3 5–7 : Unimplemented. 4 – PA 6 pull-up enable bit. 91-9F A0-BF Unimplemented. General purpose register. This specification are subject to be changed without notice. Any latest information please pleasepreview previewhttp;//www.mx http;//www.mdtic.com.tw mcu.com.cn P.7 2006/7 Ver1.0 MDT10P622 7.Reset Condition for all Registers Address Power-On Reset, Power range detector Reset /MCLR or WDT Reset Wake-up from SLEEP IAR 00h(80h) 0000 0000 0000 0000 uuuu uuuu RTCC 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h(82h) 0000 0000 0000 0000 0000 0100 STATUS 03h(83h) 0001 1xxx 000# #uuu 000# #uuu MSR 04h(84h) xxxx xxxx uuuu uuuu uuuu uuuu PORT A 05h xxxx xxxx uuuu uuuu uuuu uuuu PORT B 06h xxxx xxxx uuuu uuuu uuuu uuuu PORT C 07h xxxx xxxx uuuu uuuu uuuu uuuu PCHLAT 0Ah(8Ah) ---- 0000 ---- 0000 ---- uuuu INTS 0Bh(8Bh) 0000 0001 0000 0001 uuuu uuuu PIFB1 0Ch ---- ---x ---- ---u ---- ---u TMR1L 0Eh xxxx xxxx Uuuu uuuu Uuuu uuuu TMR1H 0FH xxxx xxxx Uuuu uuuu Uuuu uuuu T1STA 10h ---- 0000 ---- 0000 ---- uuuu CCP1L 15h xxxx xxxx uuuu uuuu --uu uuuu CCP1H 16h xxxx xxxx Uuuu uuuu --uu uuuu CCP1CTL 17h ---- ---0 ---- ---0 ---- ---u TMR 81h 1111 1111 1111 1111 uuuu uuuu CPIOA 85h 1111 1111 1111 1111 uuuu uuuu CPIOB 86h 1111 1111 1111 1111 uuuu uuuu CPIOC 87h 1111 1111 1111 1111 uuuu uuuu PIEB1 8Ch ---- ---0 ---- ---0 ---- ---u PSTA 8Eh 0000 00#0 0000 00u0 0000 00u0 OPTION2 90h ---1 ---- ---1 ---- ---u ---- Register Note ： u＝unchanged， x＝unknown， - ＝unimplemented， read as “0” This specification are subject to be changed without notice. Any latest information P.8 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 #＝value depends on the condition of the following table Condition Status bit 4 Status bit 3 PSTA bit 1 POWR ON RESET 1 1 0 /MCLR reset (not during SLEEP) u u u /MCLR reset during SLEEP 1 0 u WDT reset (not during SLEEP) 0 1 u WDT reset during SLEEP 0 0 u Interrupt Wake-up during SLEEP 1 0 u 8. Instruction Set Instruction Code Mnemonic Operands Function Operation Status 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT, TF, PF stop OSC 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000rrr CPIO Control I/O port register W→CPIO r None 010001 1rrrrrrr STWR Store W to register W→R None 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None Swap halves register [R(0~3) ↔ None 010111 trrrrrrr R R SWAPR R, t R(4~7)]→t Increment register R + 1→t Z INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t C, HC, Z 011001 trrrrrrr INCR 011010 trrrrrrr R, t (R+/W+1→t) Decrement register R ﹣1→t Z DECRSZ R, t Decrement register, skip if zero R ﹣1→t None ANDWR R, t AND W and register R ∩ W→t Z ANDWI i AND W and immediate i ∩ W→W Z IORWR R, t Inclu. OR W and register R ∪ W→t Z 011101 trrrrrrr DECR 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr R, t This specification are subject to be changed without notice. Any latest information P.9 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 Instruction Code Mnemonic Operands Function Operation Status IORWI i Inclu. OR W and immediate i ∪ W→W Z XORWR R, t Exclu. OR W and register R ♁ W→t Z XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR Complement register /R→t Z 010110 trrrrrrr RRR Rotate right register R(n)→R(n-1), C 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii R, t R, t C→R(7), R(0)→C 010101 trrrrrrr RLR R, t R(n)→r(n+1), Rotate left register C C→R(0), R(7)→C Clear working register 0→W Z Clear register 0→R Z R, b Bit clear 0→R(b) None BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 100nnn nnnnnnnn LCALL n Long CALL subroutine n→PC, None 010000 1xxxxxxx CLRW 010001 0rrrrrrr CLRR 0000bb brrrrrrr BCR 0010bb brrrrrrr R PC+1→Stack 101nnn nnnnnnnn LJUMP 110001 iiiiiiii RTIW i n Long JUMP to address n→PC None Return, place immediate to W Stack→PC, None i→W 110111 iiiiiiii ADDWI PC+1→PC, Add immediate to W C,HC,Z W+i→W 111000 iiiiiiii 010000 00001001 SUBWI Subtract W from immediate i-W→W RTFI Return from interrupt Stack→PC, C,HC,Z None 1→GIS 010000 00000100 Note : W WT TMODE CPIO : : : : RET Stack→PC Return from subroutine Working register Watchdog timer TMODE mode register Control I/O port register b t : : 0 1 This specification are subject to be changed without notice. Any latest information P.10 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn None Bit position Target : Working register : General register please preview 2006/7 Ver1.0 MDT10P622 TF PF PC OSC Inclu. Exclu. AND ( PA, PB, PC Only ) Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ : : : : : : : R C HC Z / x i n : : : : : : : : General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 9. Electrical Characteristics (A)Operation Voltage & Frequency Vdd : 2.3V~6.3V Frequency: 0Hz~20MHz (B)Input Voltage Vil Vih Port MIN MAX PA , PB Vss 1.0V RTCC /MCLR Vss 1.0V PA , PB 2.0V Vdd RTCC /MCLR 3.4V Vdd *Threshold Voltage PortA PortB PortC Vth = 1.6V RTCC,/MCLR Vil=1.2V Vih=3.1V (Schmitt Trigger) (C) Output Voltage @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : PA, PB, PC Port Ioh＝－20.0 mA Voh＝3.8 V Iol＝20.0 mA Vol＝0.6V Ioh＝－5.0 mA Voh＝4.7V Iol＝5.0 mA Vol＝0.2V This specification are subject to be changed without notice. Any latest information P.11 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 (D)Leakage Current @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : Iil － 1.0 µA (Max.) Iih ＋ 1.0 µA (Max.) (E) Sleep Current @WDT－Enable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd=1uA Vdd＝3.0 V Idd=2.0 µA Vdd＝4.0 V Idd=5.0µA Vdd＝5.0 V Idd=10.0µA Vdd＝6.3 V Idd=18.0µA @WDT－Disable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V ~ 6.3 V, Idd＜0.1 µA (F) Operating Current / Voltage Temperature＝25℃, the typical value as followings : (i) OSC Type＝RC (OSC1&OSC2 internal CAP about 10P) ; WDT－Enable; The IC may not oscillate properly if the resistance of rext less than 4.7K The minimum resistance of rext must be more than 4.7K @ Vdd＝5.0 V Cext. (F) 3P 20P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 7.7M 780u 10.0 K 4.0M 480u 47.0 K 890K 200u 100.0 K 425K 155u 300.0 K 140K 135u 470.0 K 96K 126u 4.7 K 4.8M 535u 10.0 K 2.5M 340u 47.0 K 540K 150u 100.0 K 265K 130u 300.0 K 87K 126u 470.0 K 55.6K 124u This specification are subject to be changed without notice. Any latest information P.12 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 Cext. (F) 100P 300P Rext. (Ohm) Frequency (Hz) Current (A) 4.7 K 2.0M 279u 10.0 K 1.0M 186u 47.0 K 220K 122u 100.0 K 103K 109u 300.0 K 34.6K 107u 470.0 K 22.K 88u 4.7 K 850 K 365u 10.0 K 370 K 301u 47.0 K 90 K 270u 100.0 K 43 K 265u 300.0 K 15K 256u 470.0 K 9.0 K 250u (ii) OSC Type＝LF;(OSC1&OSC2 Internal cap) LF WDT - disable, PED – disable IC1: 32K(C=50P) 455K 1M Sleep 2.3V 4uA 20uA 29uA <0.1uA 3.0V 8uA 37uA- 50uA <0.1uA 4.0V 20uA 86uA 95uA <0.1uA 5.0V 43uA 143uA 127uA <0.1uA 6.0v 88uA 237uA 185uA <0.1uA 6.4V 111uA 280uA 215uA 0.1uA (iii) OSC Type=XT (OSC1&OSC2 Internal cap) , WDT - enable, PED – disable IC1: 1M 4M 10M Sleep 2.3V 42uA 110uA 251uA 1uA 3.0V 71uA 177uA 381uA 2uA 4.0V 141uA 302uA 583uA 5uA 5.0V 314uA 460uA 869uA 10uA 6.0V 558uA 581uA 1.2mA 15uA 6.4V 702uA 760uA 1.25mA 18uA This specification are subject to be changed without notice. Any latest information P.13 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 (iv) OSC Type＝HF (OSC1&OSC2 Internal cap) WDT - enable, PED – disable IC1 4M 10M 20M Sleep 2.3V 106uA 288uA --- 1uA 3.0V 171uA 403uA 775uA 2uA 4.0V 353uA 682uA 1.3mA 5uA 5.0V 569uA 966uA 1.85mA 10uA 6.0V 830uA 1.4mA 2.5mA 15uA 6.4V 937uA 1.5mA 2.8mA 18uA (G)Power Edge-detector Reset Voltage (Not in Sleep Mode) @Vdd=5.0V(PED=Enable) Vpr≦1.6V~1.80V Vpr ﹕Vdd (Power Supply) PS: If PED_Enable then Internal Power-On Reset will be off (H) The basic WDT time-out cycle time @Temperature＝25 ℃, the typical value as followings : Voltage (V) Basic WDT time-out cycle time (ms) 2.3 26.4ms 3.0 24.6ms 4.0 22ms 5.0 20ms 6.3 19.4ms This specification are subject to be changed without notice. Any latest information P.14 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 (I) Pull_High Resistance @ Input Mode : Vdd＝5.0 V PB 7~0 PA6 5V=90k 5V=45k p.s. : It is only a reference value for the Pull High Resistance, and the accurate value of the Resistance depends on the various parameter of the Process. But the variation of the value will be not more than 20%. 10. TIMER1 timer/counter 1 2 Timer1 is a 16bit timer/counter consisting two 8-bit register (TMR1H and TMR1L) increment from 0000h to FFFFh.Timer1 can operate two mode (time mode and counter mode).Used the TICON register to control Timer1 mode Timer1 ccp mode: timer1 can internal “reset “ by CCP mode,CCP register consisting two 8bit register ccp1L and ccp1H and control the register(17H-bit0) enable the comparator to reset timer1 CC P1C TL Enable CC P1H CC P1L Input CO M PA RA TO R TM R1L TM R1H 1/2 O utput PA 5 TRISA < 5 > O utput Enable Clear TM R1L PA 5 Input O utput D efault This specification are subject to be changed without notice. Any latest information P.15 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 11. Port A ,Port B and Port C Equivalent Circuit PA0~3 ,PA5 ,PB0~PB7 ,PC7 Working Register D Data I/P QB PORTB USED PULL-HIGH enable bit I/O Control Latch I/O Control CK 80K ohm Q Port I/O Pin D Data O/P Latch Write CK Q Data Bus D QB Input Resistor Data I/P Latch Read TTL Input Level CK PA4/RTCC Working Register D Data I/P QB I/O Control Latch I/O Control CK Q Port I/O Pin D Data O/P Latch Write CK Q Data Bus D QB Read Data I/P Latch Input Resistor TTL Input Level CK Time0 input Schmitt Input Level This specification are subject to be changed without notice. Any latest information P.16 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 PA6/INT Working Register D Data I/P QB PA6 PULL-HIGH enable bit I/O Control Latch I/O Control CK 80K ohm Q Port I/O Pin D Data O/P Latch Write CK Q TTL Input Level Input Resistor Data Bus D QB Read Data I/P Latch CK PA6/INT Schmitt trigger buffer PC6/VREF This specification are subject to be changed without notice. Any latest information P.17 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 PC2~PC5 12. MCLRB Input Equivalent Circuit R≒1K MCLRB Schmitt Trigger This specification are subject to be changed without notice. Any latest information P.18 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0 MDT10P622 13. Block Diagram RAM 128 bytes ROM 3K X 14 Stack 8 Levels Port PA0~PA6 7 bits Port A 12 bits 12 bits Program Counters 14 bits Instruction Register Special Register Port PB0~PB7 8 bits OSC1 OSC2 MCLR Oscillator Circuit D0~D7 Instruction Decoder Port B Control Circuit Port PC0~PC7 8 bits Data 8-bit Power on Reset Power Down Reset Port C Working Register ALU Status Register CMR0~CMR5 WDT/OST Timer 8-bit Timer/Counter Prescale Comparator mode Register 16bit timer1 PC0 ~PC1 PA4 / RTCC This specification are subject to be changed without notice. Any latest information P.19 http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn please preview 2006/7 Ver1.0