a 16-Channel, 8-Bit Multiplying DAC AD8600* FUNCTIONAL BLOCK DIAGRAM FEATURES 16 Independently Addressable Voltage Outputs Full-Scale Set by External Reference 2 µs Settling Time Double Buffered 8-Bit Parallel Input High Speed Data Load Rate Data Readback Operates from Single +5 V Optional ±6 V Supply Extends Output Range EN A3 A2 A1 A0 The AD8600 contains 16 independent voltage output digital-toanalog converters that share a common external reference input voltage. Each DAC has its own DAC register and input register to allow double buffering. An 8-bit parallel data input, four address pins, a CS select, a LD, EN, R/W, and RS provide the digital interface. Data is preloaded into the input registers one at a time after the internal address decoder selects the input register. In the write mode (R/W low) data is latched into the input register during the positive edge of the EN pulse. Pulses as short as 40 ns can be used to load the data. After changes have been submitted to the input registers, the DAC registers are simultaneously updated by a common load EN × LD strobe. The new analog output voltages simultaneously appear on all 16 outputs. LD VDD2 VREF VCC O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 CONTROL LOGIC 16 x 8 DAC REGISTERS 16 8-BIT DAC S 16 x 8 INPUT REGISTERS AD8600 DGND1 DGND2 DACGND VEE At system power up or during fault recovery the reset (RS) pin forces all DAC registers into the zero state which places zero volts at all DAC outputs. The AD8600 is offered in the PLCC-44 package. The device is designed and tested for operation over the extended industrial temperature range of –40°C to +85°C. R/W•CS•ADDR•EN The AD8600 is constructed in a monolithic CBCMOS process which optimizes use of CMOS for logic and bipolar for speed and precision. The digital-to-analog converter design uses voltage mode operation ideally suited to single supply operation. The internal DAC voltage range is fixed at DACGND to VREF. The voltage buffers provide an output voltage range that approaches ground and extends to 1.0 V below VCC. Changes in reference voltage values and digital inputs will settle within ± 1 LSB in 2 µs. VDD1 ADDRESS DECODE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 APPLICATIONS Phased Array Ultrasound & Sonar Power Level Setting Receiver Gain Setting Automatic Test Equipment LCD Clock Level Setting GENERAL DESCRIPTION RS R/W CS VDD1 VDD2 LD•EN VREF VCC DB7...DB0 INPUT REGISTER DAC REGISTER R-2R DAC OX RS DGND2 RS DACGND VEE D GND1 R/W•CS•ADDRESS Figure 1. Equivalent DAC Channel *Patent pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8600–SPECIFICATIONS SINGLE SUPPLY (@ V DD1 Parameter STATIC PERFORMANCE1 Resolution Relative Accuracy2 Differential Nonlinearity2 Full-Scale Voltage Full-Scale Tempco Zero Scale Error = VDD2 = VCC = +5 V ± 5%, VEE = 0 V, VREF = +2.500 V, –40°C ≤ TA ≤ +85°C, unless otherwise noted) Symbol Condition Min N INL DNL VFS TCVFS VZSE VZSE RREF Guaranteed Monotonic Data = FFH Data = FFH Data = 00H, RS = “0,” TA = +25°C Data = 00H, RS = “0” Data = ABH ANALOG OUTPUT Output Voltage Range 2 Output Current Capacitive Load OVRSS IOUT CL VREF = +2.5 V Data = 80H No Oscillation LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Logic Input Current Logic Input Capacitance 3 VIL VIH IIL CIL LOGIC OUTPUTS Logic Out High Voltage Logic Out Low Voltage VOH VOL Reference Input Resistance AC CHARACTERISTICS3 Slew Rate SR Voltage Output Settling Time2 tS1 Voltage Output Settling Time2 tS2 POWER SUPPLIES Positive Supply Current Logic Supply Currents Power Dissipation Power Supply Sensitivity Logic Power Supply Range Positive Power Supply Range 3 ICC IDD1&2 PDISS PSS VDDR VCCR 8 –1 –1 2.480 1.2 Typ Max ± 1/2 +1 ± 1/4 +1 2.490 2.500 ± 20 +3.5 +5 2 0.000 V mA pF 0.8 10 10 V V µA pF 0.4 V V 2.4 3.5 For ∆VREF or FS Code Change ± 1 LSB of Final Value, Full-Scale Data Change ± 1 LSB of Final Value, ∆VREF = 1 V, Data = FFH 4 VIH = 5 V, VIL = 0 V, No Load VIH = 5 V, VIL = 0 V, No Load VIH = 5 V, VIL = 0 V, No Load ∆VCC = ± 5% 7 2 2 24 120 4.75 VDD Bits LSB LSB V ppm/°C LSB LSB kΩ 2.500 ±2 50 IOH = –0.4 mA IOL = 1.6 mA Units V/µs µs µs 35 0.1 175 0.007 5.25 7.0 mA mA mW %/% V V NOTES 1 When VREF = 2.500 V, 1 LSB = 9.76 mV. 2 Single supply operation does not include the final 2 LSBs near analog ground. If this performance is critical, use a negative supply (V EE) pin of at least –0.7 V to –5.25 V. Note that for the INL measurement zero-scale voltage is extrapolated using codes 7 10 to 8010. 3 Guaranteed by design not subject to production test. Specifications subject to change without notice. –2– REV. 0 AD8600 DUAL SUPPLY (@ V DD1 = VDD2 = VCC = +5 V ± 5%, VEE = –5 V ± 5%, VREF = +3.500 V, –40°C ≤ TA ≤ +85°C, unless otherwise noted) Parameter Symbol Condition Min Typ Max 8 –1 –1 –1 3.473 –1 ± 3/4 ± 1/2 ± 1/4 3.486 +1 +1 +1 3.500 +1 Units 1 STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Voltage Full-Scale Voltage Error Full-Scale Tempco Zero Scale Error Zero Scale Error Zero Scale Error Zero Scale Tempco Reference Input Resistance Reference Input Capacitance 2 N TUE INL DNL VFS VFSE TCVFS VZSE VZSE VZSE TCVZS RREF CREF ANALOG OUTPUT Output Voltage Range Output Voltage Range 2 Output Current Capacitive Load2 OVR1 OVR2 IOUT CL LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Logic Input Current Logic Input Capacitance 2 VIL VIH IIL CIL LOGIC OUTPUTS Logic Out High Voltage Logic Out Low Voltage VOH VOL IOH = –0.4 mA IOL = 1.6 mA 3.5 AC CHARACTERISTICS2 Reference In Bandwidth Slew Rate Voltage Noise Density Digital Feedthrough Voltage Output Settling Time3 Voltage Output Settling Time3 BW SR eN FT tS1 tS2 –3 dB Frequency, VREF = 2.5 VDC + 0.1 VAC For ∆VREF or FS Code Change f = 1 kHz, VREF = 0 V Digital Inputs to DAC Outputs ± 1 LSB of Final Value, FS Data Change ± 1 LSB of Final Value, ∆VREF = 1 V, Data = FFH 500 4 POWER SUPPLIES Positive Supply Current Negative Supply Current Logic Supply Currents Power Dissipation4 Power Supply Sensitivity Logic Power Supply Range Pos Power Supply Range2 Neg Power Supply Range2 ICC IEE IDD1&2 PDISS PSS VDDR VCCR VEER VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load VIH = 5 V, VIL = 0 V, VEE = –5 V, No Load ∆VCC & ∆VEE = ± 5% All Other DACs Loaded with Data = 55 H Guaranteed Monotonic Data = FFH, VREF = +3.5 V Data = FFH, VREF = +3.5 V Data = FFH, VREF = +3.5 V Data = 00H, RS = “0,” TA = +25°C Data = 00H, All Other DACs Data = 00 H Data = 00H, All Other DACs Data = 55 H Data = 00H, VCC = +5 V, VEE = –5 V Data = ABH Data = ABH VREF = +3.5 V VCC = VDD2 = +7 V, VEE = –0.7 V, VREF = 5 V Data = 80H No Oscillation 1.2 ± 20 ±1 +2 +1 ± 1/2 ± 10 2 240 0.000 0.000 3.500 5.000 V V mA pF 0.8 10 10 V V µA pF 0.4 V V 2 2 kHz V/µs nV/√Hz nVs µs µs 35 35 0.1 350 0.007 5.25 7.0 0.0 mA mA mA mW %/% V V V ±2 50 2.4 –3– 7 46 10 1 1 22 22 225 4.75 VDD –5.25 NOTES 1 When VREF = +3.500 V, 1 LSB = 13.67 mV. 2 Guaranteed by design not subject to production test. 3 Settling time test is performed using R L = 50 kΩ and CL = 35 pF. 4 Power Dissipation is calculated using 5 V × (IDD + |ISS| + IDD1 + IDD2). Specifications subject to change without notice. REV. 0 –2 –1 Bits LSB LSB LSB V LSB ppm/°C mV LSB LSB µV/°C kΩ pF AD8600 (@ VDD1 = VDD2 = VCC = +5 V ± 5%, VEE = –5 V, VREF = +3.500 V, –40°C ≤ TA ≤ +85°C, ELECTRICAL CHARACTERISTICS unless otherwise noted) Parameter Symbol Condition Min fCLK tCH tCL tDS tDH tAS tAH tAD tLS tLH tRWC tRWZ tRWD tTWH tTCH tCSC tCSD tCSZ tRS Data Loading Typ Max Units 12.5 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1, 2 INTERFACE TIMING Clock (EN) Frequency Clock (EN) High Pulse Width Clock (EN) LowPulse Width Data Setup Time Data Hold Time Address Setup Time Address Hold Time Valid Address to Data Valid Load Enable Setup Time Load Enable Hold Time Read/Write to Clock (EN) Read/Write to DataBus Hi-Z Read/Write to DataBus Active Clock (EN) to Read/Write Clock (EN) to Chip Select Chip Select to Clock (EN) Chip Select to Data Valid Chip Select to DataBus Hi-Z Reset Pulse Width 40 40 40 10 0 0 160 0 0 30 120 120 0 0 30 120 150 25 NOTES 1 Guaranteed by design not subject to production test. 2 All logic input signals have maximum rise and fall times of 2 ns. Specifications subject to change without notice. R/W R/W tRWZ tTWH tDS tRWD tDH HIGH-Z DATA tAS DATA HIGH -Z tAD tAH ADDR ADDR tCH EN EN tTCH CS tCSD tCSZ tCL tRWC tCSC CS Figure 2. Write Timing Figure 3. Readback Timing LD tLS tLH EN tRS RS OUT tS1 tS1 Figure 4. Write to DAC Register & Voltage Output Settling Timing (CS= High, Prevents Input Register Changes) –4– REV. 0 AD8600 ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION (TA= +25°C unless otherwise noted) VDD1 (Digital Supply) to GND . . . . . . . . . . . . . . –0.3 V, +7 V VDD2 (DAC Buffer/Driver Supply) . . . . . . . . . . . . –0.3 V, +7 V VCC (Analog Supply) to GND . . . . . . . . . . . . . . . –0.3 V, +7 V VEE (Analog Supply) to GND . . . . . . . . . . . . . . . +0.3 V, –7 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V VDD2 to VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V VOUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC Short Circuit Duration VOUT to GND or Power Supplies1 . . . . . . . . . . . . . . . Continuous Digital Input/Output Voltage to GND . . . –0.3 V, VDD + 0.3 V Thermal Resistance–Theta Junction-to-Ambient (θJA) PLCC-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Package Power Dissipation . . . . . . . . . . . . . . . . (TJ – TA)/θJA Maximum Junction Temperature TJ max . . . . . . . . . . . 150°C Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C NOTE 1 No more than four outputs may be shorted to power or GND simultaneously. 44 43 42 41 40 VEE 1 O8 2 DGND2 3 VCC NC 4 VDD2 5 DACGND VCC 6 VREF O7 VEE PIN CONFIGURATION O6 7 39 O9 O5 8 38 O10 O4 9 37 O11 O3 10 36 O12 O2 11 AD8600 35 O13 O1 12 TOP VIEW (Not to Scale) 34 O14 O0 13 33 O15 VDD1 14 32 DGND1 RS 15 31 LD DB0 16 30 CS DB1 17 29 EN A3 R/W A2 A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 18 19 20 21 22 23 24 25 26 27 28 NC = NO CONNECT ORDERING GUIDE Package Description Model Temperature AD8600AP AD8600Chips –40°C to +85°C 44-Lead PLCC +25°C Die* Package Option P-44A *For die specifications contact your local Analog Devices sales office. The AD8600 contains 5782 transistors. Pin No. Name Description 1 2 NC VREF 3 DACGND 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 VCC VEE O7 O6 O5 O4 O3 O2 O1 O0 VDD1 RS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A0 A1 A2 A3 R/W EN CS LD DGND1 O15 O14 O13 O12 O11 O10 O9 O8 VEE VCC DGND2 VDD2 No Connection Reference input voltage common to all DACs. DAC Analog Ground Return. Sets analog zero-scale voltage. Output Amplifier Positive Supply Output Amplifier Negative Supply DAC Channel Output No. 7 DAC Channel Output No. 6 DAC Channel Output No. 5 DAC Channel Output No. 4 DAC Channel Output No. 3 DAC Channel Output No. 2 DAC Channel Output No. 1 DAC Channel Output No. 0 Digital Logic Power Supply Active Low Reset Input Pin Data Bit Zero I/O (LSB) Data Bit I/O Data Bit I/O Data Bit I/O Data Bit I/O Data Bit I/O Data Bit I/O Most Significant Data Bit I/O (MSB) Address Bit Zero (LSB) Address Bit Address Bit Most Significant Addr Bit (MSB) Read/Write Select Control Input Active Low Enable Clock Strobe Chip Select Input DAC Register Load Strobe Digital Ground Input No. 1 DAC Channel Output No. 15 DAC Channel Output No. 14 DAC Channel Output No. 13 DAC Channel Output No. 12 DAC Channel Output No. 11 DAC Channel Output No. 10 DAC Channel Output No. 9 DAC Channel Output No. 8 Output Amplifier Negative Supply Output Amplifier Positive Supply Digital Ground Input No. 2 DAC Analog Supply Voltage CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8600 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– WARNING! ESD SENSITIVE DEVICE AD8600 TRANSFER EQUATIONS Output Voltage Decoded DAC Register Oi = D × Oi = A VREF 256 where A is the decimal value of the decoded address bits A3, A2, A1, A0 (LSB). where i is the DAC channel number and D is the decimal value of the DAC register data. Address, CS, R/W and data inputs should be stable prior to activation of the active low EN input. Input registers are transparent when EN is low. When EN returns high, data is latched into the decoded input register. When the load strobe LD and EN pins are active low, all input register data is transferred to the DAC registers. The DAC registers are transparent while they are enabled. Table I. Truth Table EN R/W CS LD RS – L + L L X X X X L H H H H L L – L + L H H H H H L L L H H + L L H H L L + H H X H L H H X H + H H X X H X X X X X X L X L X X H L H H + + Operation Write to DAC Register Update DAC Register Update DAC Register Latches DAC Register Latches DAC Register DAC Register Transparent Write to Input Register Load Data to Input Register at Decoded Address Latches Data in Input Register at Decoded Address Latches Data in Input Register at Decoded Address Readback Input Registers Input Register Readback (Data Access) Hi-Z Readback Disconnects from Bus Hi-Z on Data Bus Reset Clear All Registers to Zero, VOUT = 0 V Latches All Registers to Zero CS = Low; Input Register Ready for R/W, DAC Register Latched to Zero Table II. Address Decode Table A3 (MSB) A2 A1 A0 (LSB) Addr Code (Hex) DAC Updated 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 (Binary) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 NOTES 1 + symbol means positive edge of control input line. 2 – symbol means negative edge of control input line. –6– REV. 0 Typical Performances Characteristics–AD8600 8 FULL-SCALE OUTPUT – Volts LINEARITY ERROR – LSB 3.50 0 V CC = +5V V EE = –5V V REF = +3.5V T A = +25°C –1/2 +1/2 0 DACs 08–015 SUPERIMPOSED –1/2 VCC = +5V VEE = –5V VREF = 3.5V ZERO-SCALE – mV DACs 00–07 SUPERIMPOSED +1/2 3.49 3.48 64 128 192 DIGITAL INPUT CODE – Decimal 0 –2 256 –50 Figure 5. Linearity Error vs. Digital Code –25 0 25 50 75 TEMPERATURE – °C 100 –4 –50 125 Figure 6. Full-Scale Voltage vs. Temperature 5 0 –5 –10 –15 3 2 V CC = +5V V EE = –5V V REF = 3.5V 1 –3 –2 –1 0 1 VOUT – Volts 2 3 4 Figure 9. Full-Scale Settling Time –45 –5 –90 –10 PHASE –15 1k 10k 100k 1M FREQUENCY – Hz Figure 11. Gain & Phase vs. Frequency REV. 0 10M 20 10 1k 100 FREQUENCY – Hz V IN = 2V p-p + 1V DC RS = 0 TA = +25°C ∆V CC = 100mV p-p T A = +25°C CODE = 00H V EE = –5V 50 –40 –60 40 30 –80 –100 100 10k 60 PSRR – dB 0 FEEDTHROUGH – dB GAIN PHASE – Degrees –20 0 40 Figure 10. Voltage Noise Density vs. Frequency 0 V IN = 100mV p-p + 2.5V DC CODE = FF H T A = +25°C 125 60 TIME – 250ns/DIV Figure 8. Output Current vs. Voltage 100 V CC = +5V V EE = –5V V REF = 0V T A = +25°C 80 0 0 –4 0 25 50 75 TEMPERATURE – °C 100 NOISE VOLTAGE DENSITY – nV/√Hz 10 V CC = +5V V EE = –5V RS = 0 OUTPUT AMPLITUDE – Volts 15 –25 Figure 7. Zero-Scale Voltage vs. Temperature 4 IOUT – mA 4 3.47 0 GAIN – dB V CC = +5V V EE = –5V V REF = 3.5V 1k 10k FREQUENCY – Hz 100k Figure 12. AC Feedthrough vs. Frequency –7– 20 10 100 1k 10k FREQUENCY – Hz 100k Figure 13. PSRR vs. Frequency AD8600 5 20 V CC = +5V V EE = –5V V REF = 3.5V CODE = 00 H 19 CHANGE IN ZERO SCALE – mV SUPPLY CURRENT – mA 4 V CC = +5V V EE = –5V V REF = 3.5V 18 17 χ + 3σ χ 16 χ − 3σ 15 –75 –50 –25 0 25 50 75 TEMPERATURE – °C 3 2 χ + 3σ χ 1 0 χ − 3σ –1 –2 –3 –4 –5 0 100 125 Figure 14. Supply Current vs. Temperature 200 400 600 800 1000 1200 T = HOURS OF OPERATION AT +125°C Figure 15. Output Voltage Drift Accelerated by Burn-In Operation Amplifier Section The AD8600 is a 16-channel voltage output, 8-bit digital to analog converter. The AD8600 operates from a single +5 V supply, or for a wider output swing range, the part can operate from dual supplies of ± 5 V or ± 6 V or a single supply of +7 V. The DACs are based upon a unique R-2R ladder structure* that removes the possibility of current injection from the reference to ground during code switching. Each of the 8-bit DACs has an output amplifier to provide 16 low impedance outputs. With a single external reference, 16 independent dc output levels can be programmed through a parallel digital interface. The interface includes 4 bits of address (A0–A3), 8 bits of data (DB0–DB7), a read/write select pin (R/W), an enable clock strobe (EN), a DAC register load strobe (LD), and a chip select pin (CS). Additionally a reset pin (RS) is provided to asynchronously reset all 16 DACs to 0 V output. The output of the DAC ladder is buffered by a rail-to-rail output amplifier. This amplifier is configured as a unity gain follower as shown in Figure 16. The input stage of the amplifier contains a PNP differential pair to provide low offset drift and noise. The output stage is shown in Figure 17. It employs complementary bipolar transistors with their collectors connected to the output to provide rail-to-rail operation. The NPN transistor enters into saturation as the output approaches the negative rail. Thus, in single supply, the output low voltage is limited by the saturation voltage of the transistor. For the transistors used in the AD8600, this is approximately 40 mV. The AD8600 was not designed to swing to the positive rail in contrast to some of ADI’s other DACs (for example, the AD8582). The output stage of the amplifier is actually capable of swinging to the positive rail, but the input stage limits this swing to approximately 1.0 V below VCC. D/A Converter Section The internal DAC is an 8-bit voltage mode device with an output that swings from DACGND to the external reference voltage, VREF. The equivalent schematic of one of the DACs is shown in Figure 16. The DAC uses an R-2R ladder to ensure accuracy and linearity over the full temperature range of the part. The switches shown are actually N and P-channel MOSFETs to allow maximum flexibility and range in the choice of reference VREF R VOUT R VOUT R R R R R VEE R TO 15 DACs R VCC Figure 17. Equivalent Analog Output Circuit R During normal operation, the output stage can typically source and sink ± 1 mA of current. However, the actual short circuit current is much higher. In fact, each DAC is capable of sourcing 20 mA and sinking 8 mA during a short condition. The absolute maximum ratings state that, at most, four DACs can be shorted simultaneously. This restriction is due to current densities in the metal traces. If the current density is too high, voltage drops in the traces will cause a loss in linearity performance for the other DACs in the package. Thus to ensure longterm reliability, no more than four DACs should be shorted simultaneously. *R = 30kΩ TYPICALLY R 2R DACGND Figure 16. Equivalent Schematic of Analog Channel voltage. The switches’ low ON resistance and matching is important in maintaining the accuracy of the R-2R ladder. *Patent Pending. –8– REV. 0 AD8600 Power Supply and Grounding Considerations VCC The low power consumption of the AD8600 is a direct result of circuit design optimizing using a CBCMOS process. The overall power dissipation of 120 mW translates to a total supply current of only 24 mA for 16 DACs. Thus, each DAC consumes only 1.5 mA. Because the digital interface is comprised entirely of CMOS logic, the power dissipation is dependent upon the logic input levels. As expected for CMOS, the lowest power dissipation is achieved when the input level is either close to ground or +5 V. Thus, to minimize the power consumption, CMOS logic should be used to interface to the AD8600. VDD2 ALL DIGITAL INPUTS (A0–A3, DB0–DB7) (R/W, CS, EN, LD, RS) DGND1 VREF DACGND The AD8600 has multiple supply pins. VCC (Pins 4 and 42) is the output amplifiers’ positive supply, and VEE (Pins 5 and 41) the amplifiers’ negative supply. The digital input circuitry is powered by VDD1 (Pin 14), and finally the DAC register and R2R ladder switches are powered by VDD2 (Pin 44). To minimize noise feedthrough from the supplies, each supply pin should be decoupled with a 0.1 µF ceramic capacitor close to the pin. When applying power to the device, it is important for the digital supply, VDD2, to power on before the reference voltage and for VREF to remain less than 0.3 V above VDD2 during normal operation. Otherwise, an inherent diode will energize, and it could damage the AD8600. Attention should be paid to the ground pins of the AD8600 to ensure that noise is not introduced to the output. The pin labeled DACGND (Pin 3) is actually the ground for the R-2R ladder, and because of this, it is important to connect this pin to a high quality analog ground. Ideally, the analog ground should be an actual ground plane. This helps create a low impedance, low noise ground to maintain accuracy in the analog circuitry. In order to improve ESD resistance, the AD8600 has several ESD protection diodes on its various pins. These diodes shunt ESD energy to the power supplies and protect the sensitive active circuitry. During normal operation, all the ESD diodes are reversed biased and do not affect the part. However, if overvoltages occur on the various inputs, these diodes will energize. If the overvoltage is due to ESD, the electrical spike is typically short enough so that the part is not damaged. However, if the overvoltage is continuous and has sufficient current, the part could be damaged. To protect the part, it is important not to forward bias any of the ESD protection diodes during normal operation or during power up. Figure 18 shows the location of these diodes. For example, the digital inputs have diodes connected to VCC and from DGND1. Thus, the voltage on any digital input should never exceed the analog supply or drop below ground, which is also indicated in the absolute maximum ratings. 5 V Output Swing REV. 0 Figure 18. ESD Protection Diode Locations The digital ground pins (DGND1 at Pin 32 and DGND2 at Pin 43) provide the ground reference for the internal digital circuitry and latches. The first thought may be to connect both of these pins to the system digital ground. However, this is not the best choice because of the high noise typically found on a system’s digital ground. This noise can feed through to the output through the DAC’s ground pins. Instead, DGND1 and DGND2 should be connected to the analog ground plane. The actual switching current in these pins is small and should not degrade the analog ground. The output swing is limited to 1.0 V below the positive supply. This gives a maximum output of +4.0 V on a +5 V supply. To increase the output range, the analog supply, VCC, and the DAC ladder supply, VDD2, can be increased to +7 V. This allows an output of +5 V with a 5 V reference. VDD1 should remain at +5 V to ensure that the input logic levels do not change. Reference Input Considerations The AD8600 is designed for one reference to drive all 16 DACs. The reference pin (VREF) is connected directly to the R-2R ladders of each DAC. With 16 DACs in parallel, the input impedance is typically 2 kΩ and a minimum of 1.2 kΩ. The input resistance is code dependent. Thus, the chosen reference device must be able to drive this load. Some examples of +2.5 V references that easily interface to the AD8600 are the REF43, AD680, and AD780. The unique architecture ensures that the reference does not have to supply “shoot through” current, which is a condition in some voltage mode DACs where the reference is momentarily connected to ground through the CMOS switches. By eliminating this possibility, all 16 DACs in the AD8600 can easily be driven from a single reference. –9– AD8600 Interface Timing and Control The AD8600 employs a double buffered DAC structure with each DAC channel having a unique input register and DAC register as shown in the diagram entitled “Equivalent DAC Channel” on the first page of the data sheet. This structure allows maximum flexibility in loading the DACs. For example, each DAC can be updated independently, or, if desired, all 16 input registers can be loaded, followed by a single LD strobe to update all 16 DACs simultaneously. An additional feature is the ability to read back from the input register to verify the DAC’s data. A0 A1 A2 A3 N1 R/W EN CS N2 N5 R/W CS N3 LD EN N4 D7–D0 After all the input registers have been loaded, a single load strobe will transfer the contents of the input registers to the DAC registers. EN must also be low during this time. If the address or data on the inputs could change, then CS should be high during this time to ensure that new data is not loaded into an input register. Alternatively, a single DAC can be updated by first loading its input register and then transferring that to the DAC register without loading the other 15 input registers. N6 8 INPUT REGISTER 8 8 DAC REGISTER To load multiple input registers in the fastest time possible, both R/W and CS should remain low, and the EN line be used to “clock” in the data. As the write timing diagram shows, the address should be updated at the same time as EN goes low. Before EN returns high, valid data must be present for a time equal to the data setup time (tDS), and after EN returns high, the data Hold Time (tDH) must be maintained. If these minimum times are violated, invalid data may be latched into the input register. This cycle can be repeated 16 times to load all of the DACs. The fastest interface time is equal to the sum of the low and high times (tCL and tCH) for the EN input, which gives a minimum of 80 ns. Because the EN input is used to clock in the data, it is often referred to as the clock input, and the timing specifications give a maximum clock frequency of 12.5 MHz, which is just the reciprocal of 80 ns. R-2R LADDER READ BACK Figure 19. Logic Interface Circuit for DAC Channel 0 The interface logic for a single DAC channel is shown in Figure 19. This figure specifically shows the logic for Channel 0; however, by changing the address input configuration to gate N1, the other 15 channels are achieved. All of the logic for the AD8600 is level sensitive and not edge triggered. For example, if all the control inputs (CS, R/W, EN, LD) are low, the input and DAC registers are transparent and any change in the digital inputs will immediately change the DAC’s R-2R ladder. Table I details the different logic combinations and their effects. Chip Select (CS), Enable (EN) and R/W must be low to write the input register. During this time that all three are low, any data on DB7–DB0 changes the contents of the input register. This data is not latched until either EN or CS returns high. The data setup and hold times shown in the timing diagrams must be observed to ensure that the proper data is latched into the input register. The final interface option is to read data from the DAC’s input registers, which is accomplished by setting R/W high and bringing CS low. Read back allows the microprocessor to verify that correct data has been loaded into the DACs. During this time EN and LD should be high. After a delay equal to tRWD, the data bus becomes active and the contents of the input register are read back to the data pins, DB0–DB7. The address can be changed to look at the contents of all the input registers. Note that after an address change, the valid data is not available for a time equal to tAD. The delay time is due to the internal readback buffers needing to charge up the data bus (measured with a 35 pF load). These buffers are low power and do not have high current to charge the bus quickly. When CS returns high, the data pins assume a high impedance state and control of the data lines or bus passes back to the microprocessor. –10– REV. 0 AD8600 Unipolar Output Operation Table IV. Bipolar Code Table The AD8600 is configured to give unipolar operation. The fullscale output voltage is equivalent to the reference input voltage minus 1 LSB. The output is dependent upon the digital code and follows Table III. The actual numbers given for the analog output are calculated assuming a +2.5 V reference. Table III. Unipolar Code Table DAC Binary Input MSB LSB Analog Output 1111 1000 1000 0111 0000 0000 +VREF (255/256) = +2.49 V +VREF (129/256) = +1.26 V +VREF (128/256) = +1.25 V +VREF (127/256) = +1.24 V +VREF (001/256) = +0.01 V +VREF (000/256) = +0.00 V 1111 0001 0000 1111 0001 0000 The AD8600 can be configured for bipolar operation with the addition of an op amp for each output as shown in Figure 20. The output will now have a swing of ± VREF, as detailed in Table IV. This modification is only needed on those channels that require bipolar outputs. For channels which only require unipolar output, no external amplifier is needed. The OP495 quad amplifier is chosen for the external amplifier because of its low power, rail-to-rail output swing, and DC accuracy. Again, the values calculated for the analog output are based upon an assumed +2.5 V reference. R1 10k Analog Output 1111 1000 1000 0111 0000 0000 +2 VREF (255/256) – VREF = +2.49 V +2 VREF (129/256) – VREF = +0.02 V +2 VREF (128/256) – VREF = +0.00 V +2 VREF (127/256) – VREF = –0.02 V +2 VREF (001/256) – VREF = –2.48 V +2 VREF (000/256) – VREF = –2.50 V 1111 0001 0000 1111 0001 0000 Interfacing to the 68HC11 Microcontroller Bipolar Output Operation VREF DAC Binary Input MSB LSB The 68HC11 is a popular microcontroller from Motorola, which is easily interfaced to the AD8600. The connections between the two components are shown in Figure 21. Port C of the 68HC11 is used as a bidirectional input/output data port to write to and read from the AD8600. Port B is used for addressing and control information. The bottom 4 LSBs of Port B are the address, and the top 4 MSBs are the control lines (LD, CS, EN, and R/W). The microcode for the 68 HC11 is shown in Figure 22. The comments in the program explain the function of each step. Three routines are included in this listing: read from the AD8600, write to the AD8600, and a continuous loop that generates a saw-tooth waveform. This loop is used in the application below. 8 PC0–PC7 4 PB0–PB3 PB4 MOTOROLA PB5 68HC11 R1 10k GND PB6 PB7 DB0–DB7 A0–A3 LD EN R/W CS AD8600 DGND1, DGND2 DACGND +5V DIGITAL GROUND VREF OUT ø 1/4 OP495 Figure 21. Interfacing the 68HC11 to the AD8600 AD8600 –5V Figure 20. Circuit for Bipolar Output Operation REV. 0 ANALOG GROUND VOUT –11– AD8600 * This program contains subroutines to read and write * to the AD8600 from the 68HC11. Additionally, a ramp * program has been included, to continuously ramp the * output giving a triangle wave output. * * The following connections need to be made: * 68HC11 AD8600 * GND DGND1,2 * PC0-PC7 DB0–DB7 respectively, data port * PB0-PB3 A0–A3 respectively, address port * PB4 LD * PB5 EN * PB6 R/W * PB7 CS * portc equ $1003 define port addresses portb equ $1004 ddrc equ $1007 * org $C000 read lds #$CFFF subroutine to read from AD8600 * ldaa #$00 initialize port c to 00000000 staa ddrc configures PC0-PC7 as inputs. * ldx #$00 points to DAC address in 68HC11 memory ldaa 0,x put the address in the accumulator adda #$70 add the control bits to the address * R/W, LD, EN are high, CS is low. staa portb output control and address on port b. * inx points to memory location to store the data ldaa portc read data from DAC staa 0,x Store this data in memory at address “x” * ldy #$1000 bset portb,y $f0 Set CS, LD, EN high jmp $e000 Return to BUFFALO * * write lds #$cfff routine to write to AD8600 ldaa #$ff initialize port c to 11111111 staa ddrc configures PC0-PC7 as outputs. * ldx #$00 points to DAC address in 68HC11 mem ldaa 0,x puts the address in the accumulator adda #$30 set CS, R/W low and LD, EN high staa portb output to portb for control and address * inx points to memory location to store the data ldaa 0,x load the data into the accumulator staa portc write the data to the DAC * ldy #$1000 bclr portb,y $30 Set LD, EN low to latch data bset portb,y $b0 Bring LD, EN, CS high, write is complete * jmp $e000 Return to BUFFALO * * ramp lds #$cfff routine to generate a triangle wave ldaa #$ff configure port c as outputs –12– REV. 0 AD8600 staa ddrc ldx ldaa staa #$00 0,x portb ldab #$ff set x to point to the DAC address load the address from 68HC11 mem set the address on portb LD, CS, EN, R/W are all low for transparent DAC loading set accumulator b to 255 ldaa staa #$00 portc start the triangle wave at zero write the data to the AD8600 * * * * loop * load inca staa cba bne jmp portc load loop increase the data by one send the new data to the AD8600 compare a to b we haven’t reached 255 yet we have reached 255, so start over Figure 22. 68HC11 Microcode to Interface to the AD8600. Time Dependent Variable Gain Amplifier Using the AD600 The AD8600 is ideal for generating a control signal to set the gain of the AD600, a wideband, low noise variable gain amplifier. The AD600 (and similar parts such as the AD602 and AD603) is often used in ultrasound applications, which require the gain to vary with time. When a burst of ultrasound is applied, the reflections from near objects are much stronger than from far objects. To accurately resolve the far objects, the gain must be greater than for the near objects. Additionally, the signals take longer to reach the ultrasound sensor when reflected from a distant object. Thus, the gain must increase as the time increases. needs to be 1.25 V. In this application, the C1LO input is set at the midscale voltage of 0.625 V, which is generated by a simple voltage divider from the REF43. The AD8600’s output is divided in half, generating a 0 V to 1.25 V ramp, and then applied to C1HI. This ramp sweeps the gain from 0 dB to 40 dB. +5V VCC, V DD1 , VDD2 DIGITAL CONTROL VREF REV. 0 13 0V – 1.25V R2 10k C1 100pF 2 The AD600 requires a dc voltage to adjust its gain over a 40 dB range. Since it is a dual, the two variable gain amplifiers can be cascaded to achieve 80 dB of gain. The AD8600 is used to generate a ramped output to control the gain of the AD600. The slope of the ramp should correspond to the time delay of the ultrasound signal. Since ultrasound applications often require multiple channels, the AD8600 is ideal for this application. The circuit to achieve a time dependent variable gain amp is shown in Figure 23. The AD600’s gain is controlled by differential inputs, C1LO and C1HI, with a gain constant of 32 dB/V. Thus for 40 dB of gain, the differential control input AD8600 R1 Oø 10k VIN (FROM ULTRASOUND SENSOR) +5V VPOS 13 2 A1HI AD600 3 A1LO 4 1 GAT1 C1LO 2 4 +5V C1HI 16 VOUT A1OP 15 A1CM –5V 0.625V REF43 6 +2.5V 12 14 R3 30k R4 10k Figure 23. Ultrasound Amplifier with Digitally Controlled Variable Gain –13– AD8600 The functionality of this circuit is shown in the scope photo in Figure 24 The top trace is the control ramp, which goes from 0 V to 1.25 V. The bottom trace is the output of the AD600. The input is actually a 12 mV p-p, 10 kHz sine wave. Thus, the bottom trace shows the envelop of this waveform to illustrate the increase in gain as time progresses. This ramp was generated under control of the 68HC11 using the “ramp” subroutine as mentioned above. The slope of the ramp can easily be lengthened by adding some delay in the loop, or the slope can be increased by stepping by 2 or more LSBs instead of the current 1 LSB changes. Glitch Impulse A specification of interest in many DAC applications is the glitch impulse. This is the amount of energy contained in any overshoot when a DAC changes at its major carry transition, in other words, when the DAC switches from code 01111111 to code 10000000. This point is the most demanding because all of the R-2R ladder switches are changing state. The AD8600’s glitch impulse is shown in Figure 25. Calculating the value of the glitch is accomplished by calculating the area of the pulse, which for the AD8600 is: Glitch Impulse = (1/2) × (100 mV) × (200 ns) = 10 nV sec. GAIN CONTROL 1V/DIV VOUT 50mV/DIV AD600 OUTPUT 0.2V/DIV 200ns/DIV 200µs/DIV Figure 24. Time Dependent Gain of the AD600 Figure 25. Glitch Impulse –14– REV. 0 AD8600 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Lead Chip Carrier (PLCC) Package (P-44A) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 0.025 (0.63) 0.015 (0.38) 40 PIN 1 IDENTIFIER 7 0.048 (1.21) 0.042 (1.07) 0.180 (4.57) 0.165 (4.19) 39 0.021 (0.53) 0.013 (0.33) 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) TOP VIEW 0.050 (1.27) BSC 29 17 18 0.020 (0.50) R 28 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.110 (2.79) 0.085 (2.16) 0.695 (17.65) SQ 0.685 (17.40) REV. 0 –15– PRINTED IN U.S.A. C1921–18–7/94 AD8600 –16– REV. 0