12-Bit 65 MSPS Quad A/D Converter with Integrated Signal Conditioning AD15452 FEATURES PRODUCT HIGHLIGHTS 12-bit, 65 MSPS, quad, analog-to-digital converter Differential input with 100 Ω input impedance Full-scale analog input: 296 mV p-p 200 MHz, 3 dB bandwidth SNR @ −9 dBFS 64 dBFS (70 MHz AIN) 64 dBFS (140 MHz AIN) SFDR @ −9 dBFS 81 dBFS (70 MHz AIN) 73 dBFS (140 MHz AIN) 475 mW per channel Quad LVDS outputs Data clock output provided Offset binary output data format 1. Quad, 12-bit, 65 MSPS, analog-to-digital converter with integrated analog signal conditioning optimized for antijam global positioning system receiver (AJ-GPS) applications. 2. Packaged in a space saving 81-lead, 10 mm x 10 mm chip scale package ball grid array (CSP_BGA) and specified over the industrial temperature range (−40°C to +85°C). GENERAL DESCRIPTION The AD15452 is a quad, 12-bit, 65 MSPS, analog-to-digital converter (ADC). It features a differential front-end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline analog-to-digital converter. It is designed to operate with a 3.3 V analog supply and a 3.3 V digital supply. Each input is fully differential. The input signals are ac-coupled and terminated in 100 Ω input impedances. The full-scale differential signal input range is 296 mV p-p. APPLICATIONS Antijam GPS receivers Wireless and wired broadband communications Communications test equipment Four separate 12-bit digital output signals provide data flow from the ADCs. The digital output data is presented in offset binary format. A single-ended clock input is used to control all internal conversion cycles. The AD15452 is optimized for applications in antijam global positioning receivers and is suited for communications applications. FUNCTIONAL BLOCK DIAGRAM D+A D+C D–A D–C D+B D+D D–B D–D IN_A IN_C LPF LPF PDOWN IN_B IN_D LPF LPF 05155-001 CLK Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD15452 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 10 Applications....................................................................................... 1 Theory of Operation ...................................................................... 13 Product Highlights ........................................................................... 1 Analog Inputs ............................................................................. 13 General Description ......................................................................... 1 Voltage Reference ....................................................................... 13 Functional Block Diagram .............................................................. 1 Clock Input and Considerations .............................................. 13 Revision History ............................................................................... 2 Digital Outputs ........................................................................... 13 Specifications..................................................................................... 3 Timing ......................................................................................... 14 Electrical Characteristics............................................................. 3 DTP Pin ....................................................................................... 14 Timing Diagram ........................................................................... 5 Power-Down Mode.................................................................... 14 Absolute Maximum Ratings............................................................ 6 Power Supplies ............................................................................ 14 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 15 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 15 Terminology ...................................................................................... 8 REVISION HISTORY 10/05—Rev. 0: Initial Version Rev. 0 | Page 2 of 16 AD15452 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ AVDD = DRVDD = PLLVDD = 3.3 V, Encode = 65 MSPS, AIN = −9 dBFS differential input, TA = 25°C, unless otherwise noted. Table 1. Parameter Temp Test Level Min RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error MATCHING CHARACTERISTICS Offset Error Gain Error INPUT REFERRED NOISE ANALOG INPUT Input Range Input Resistance 1 Input Capacitance1 CLOCK INPUTS High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Capacitance (CIN) POWER-DOWN INPUT Logic 1 Voltage Logic 0 Voltage Input Capacitance DIGITAL OUTPUTS (LVDS) Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding CLOCK Maximum Conversion Rate Minimum Conversion Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS Propagation Delay (tpd) Rise Time (tR) 2 Fall Time (tF)2 FCO Propagation Delay (tFCO) DCO Propagation Delay (tDCO) DCO to Data Delay (tDATA) DCO − FCO Delay (tFRAME) Data to Data Skew Wake-Up Time Pipeline Latency Typ Max 12 Full 25°C 25°C Full Full IV I I V V Full Full Unit Bits Guaranteed ±0.35 ±0.5 % FSR % FSR LSB LSB V V ±10 ±290 ppm/oC ppm/oC Full Full Full V V V ±2 ±1.2 0.82 % FSR % FSR LSB rms Full 25°C 25°C IV V V 296 100 2.5 mV p-p Ω pF Full Full Full Full Full IV IV IV IV V Full IV Full Full IV V Full Full VI VI −5 −12.5 +5 +12.5 2 0.8 +10 +10 −10 −10 2 2 V V μA μA pF V 0.8 V pF 440 1.35 mV V 2 260 1.15 Offset binary Full Full Full Full VI IV VI VI 65 Full Full Full VI V V 3.3 Full Full Full Full Full 25°C Full V V IV IV IV V IV 10 6.2 6.2 tSAMPLE/24 − 250 tSAMPLE/24 − 250 Rev. 0 | Page 3 of 16 6.5 250 250 6.5 tFCO + tSAMPLE/24 tSAMPLE/24 tSAMPLE/24 ±100 250 10 7.9 tSAMPLE/24 + 250 tSAMPLE/24 + 250 ±250 MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns Cycles AD15452 Parameter APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Currents IAVDD IDRVDD Total Power Dissipation Power-Down Dissipation SIGNAL-TO-NOISE RATIO fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SINAD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz THD fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz SPURIOUS-FREE DYNAMIC RANGE fINPUT = 70 MHz fINPUT = 110 MHz fINPUT = 140 MHz CROSSTALK 1 2 Temp Test Level 25°C 25°C V Full Full IV IV Full Full 25°C 25°C I I V V 25°C Full 25°C I V I 25°C Full 25°C I V I Full Full Full V V V 25°C Full 25°C Full I V I V Min Typ Max 1.8 <1 3 3 62.7 62.5 62.4 61.9 73.0 68.5 Input resistance and capacitance are listed as differential values. Rise and fall times are defined from 20% to 80%. Rev. 0 | Page 4 of 16 Unit ns ps rms 3.3 3.3 3.6 3.6 V V 540 28 1.9 0.36 592 33 2.0 mA mA W W 64.8 64.7 64.6 dBFS dBFS dBFS 64.7 64.4 64.0 dBFS dBFS dBFS −80.0 −77.0 −73.0 dBFS dBFS dBFS 81 77 73 −60 dBFS dBFS dBFS dB AD15452 Table 2. Test Levels Test Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C, and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at 25°C, guaranteed by design and characterization testing for industrial temperature range, 100% production tested at temperature extremes for military devices. TIMING DIAGRAM N–1 AIN N tA tEH tEL CLK tCPD DCO– DCO+ tFCO tFRAME FCO– FCO+ D+ MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10 (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9) Figure 2. Timing Diagram Rev. 0 | Page 5 of 16 05155-016 tDATA tPD D– AD15452 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter AVDD to AGND DRVDD to DRGND DRGND to AGND DRVDD to AVDD Analog Inputs Digital Outputs CLK LVDSBIAS PDWN, DTP Operational Case Temperature Storage Temperature Range Lead Temperature: Infrared, 15 seconds Rating −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +0.3 V −3.9 V to +3.9 V −0.3 V to AVDD −0.3 V to DRVDD −0.3 V to AVDD −0.3 V to DRVDD −0.3 V to AVDD −40°C to +85°C 65°C to 150°C 230°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 16 AD15452 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 9 8 7 6 5 4 3 2 1 A B C D E F G H BOTTOM VIEW (Not to Scale) 05155-002 J Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. A2 Mnemonic VIN+A Description Channel A Positive Analog Input. A1 VIN−A Channel A Negative Analog Input. B2 VIN+B Channel B Positive Analog Input. B1 VIN−B Channel B Negative Analog Input. H2 VIN+C Channel C Positive Analog Input. H1 VIN−C Channel C Negative Analog Input. J2 VIN+D Channel D Positive Analog Input. J1 VIN−D Channel D Negative Analog Input. E8 D+A ADC A True Digital Out. E9 D−A ADC A Complement Digital Out. F8 D+B ADC B True Digital Out. F9 D−B ADC B Complement Digital Out. G8 D+C ADC C True Digital Out. G9 D−C ADC C Complement Digital Out. H8 D+D ADC D True Digital Out. H9 D−D ADC D Complement Digital Out. J6 CLK Clock Input. A7 PDWN Power-Down Function Selection. B3, C3, D2, E1, E2, F2, F3, F4, G3, G4, H3 H7, J7 A3, A4, A5, A6, B4, B5, B6, C1, C2, C4, C5, D1, D5, E5, F1, F5 G1, G2, G5, H4, H5, H6, J3, J4, J5 A8, A9, B8, B9, AVDD Analog Power Supply Connection. AGND Analog Ground Connection. DRVDD Digital Output Driver Supply Connection. C6, C7, D6, D7, E6, E7, F6, F7, G6, G7, J8 DRGND Digital Output Ground Connection. D3 VREF Voltage Reference Input/Output. D4 SENSE Reference Mode Selection. E4 REFT Differential Reference (Top). E3 REFB Differential Reference (Bottom). C8 DCO+ Data Clock Output; True. C9 DCO− Data Clock Output; Complement. D8 FCO+ Frame Clock Indicator; True. D9 FCO− Frame Clock Indicator Output; Complement. B7 DTP Digital Test Pattern Enable. J9 LVDSBIAS LVDS Output Current Set Resistor Pin. Rev. 0 | Page 7 of 16 AD15452 TERMINOLOGY Analog Bandwidth Analog bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB from full scale. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples and can be manifested as frequency dependent noise on the ADC input. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve a rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the amount of rejection on the differential analog inputs over the entire full-scale signal range. Crosstalk Crosstalk is defined as the coupling onto any other channel when one channel is driven by a full-scale signal. Gain Flatness Gain flatness is the measured amount of fluctuation in the analog front-end input response to the bandwidth measured. Differential Analog Input Capacitance The complex impedance simulated at each analog input port. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a pin and subtracting the voltage from a second pin that is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. The difference is computed between both peak measurements. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to an n-bit resolution indicates that all 2n codes, respectively, must be present over all operating ranges. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a measure of performance expressed as N, the effective number of bits: N = (SINAD – 1.76)/6.02 Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Gain Error The largest gain error is specified and is considered the difference between the measured and ideal full-scale input voltage range. Gain Matching Expressed in %FSR. Computed using the following equation: Gain Matching = FSR max − FSR min × 100% ⎛ FSR max + FSR min ⎞ ⎜ ⎟ 2 ⎝ ⎠ where: FSRMAX is the most positive gain error of the ADCs. FSRMIN is the most negative gain error of the ADCs. Second and Third Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the second or third harmonic component, reported in dBc. Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Noise Power Ratio (NPR) NPR is the rms noise power injected into the ADC vs. the rejected band of interest (notch depth measured). Offset Error The largest offset error is specified and is considered the difference between the measured and ideal voltage at the analog input that produces the midscale code at the outputs. Rev. 0 | Page 8 of 16 AD15452 Offset Matching Expressed in mV. Computed using the following equation: Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. OffsetMatching = OFFMAX − OFFMIN where: OFFMAX is the most positive offset error. OFFMIN is the most negative offset error. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Out-of-Range Recovery Time Out-of-range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Output Propagation Delay The delay between the clock logic threshold and the time when all bits are within valid logic levels. Power Supply Rejection Ratio (PSRR) PSRR is the measure of change in a given supply relative to the amount of error seen on the ADC reconstructed output. This is measured in decibels based on the spurious feedthrough of the device. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component can be an IMD product. It may be reported in dBc (that is, degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Signal-to-Noise and Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Rev. 0 | Page 9 of 16 AD15452 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 1 10 –1 20 30 –3 MAGNITUDE (dB) ROLL-OFF (dB) –2 –4 –5 –6 40 50 60 70 2 80 90 5 6 3 4 100 –7 110 –8 100 1000 FREQUENCY (MHz) 130 05155-003 –9 10 0 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 4. Analog Input Bandwidth 05155-014 120 Figure 7. FFT Plot with fIN = 140 MHz 11.00 0 1 10 10.75 20 10.50 40 ATTENUATION (dB) MAGNITUDE (dB) 30 50 60 70 80 2 90 3 5 4 6 100 IF = 70 10.25 10.00 9.75 IF = 110 9.50 9.25 9.00 IF = 140 110 0 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) 8.50 –5 05155-012 130 0 5 10 15 20 25 30 35 FREQUENCY (MHz) Figure 5. FFT Plot with fIN = 70 MHz 05155-004 8.75 120 Figure 8. Gain Flatness 30 MHz Centered @ IF 0 0 1 10 –10 20 –20 CROSSTALK (dB) 40 50 60 70 80 3 90 6 4 2 5 100 –30 –40 –50 –60 –70 110 130 0 3.25 6.50 9.75 13.00 16.25 19.50 22.75 26.00 29.25 32.50 FREQUENCY (MHz) Figure 6. FFT Plot with fIN = 110 MHz –90 10 100 FREQUENCY (MHz) Figure 9. Typical Crosstalk Rev. 0 | Page 10 of 16 1000 05155-005 –80 120 05155-013 MAGNITUDE (dB) 30 AD15452 90 86 SFDR = 70MHz 84 85 82 SNR/SFDR (dBFS) 80 SFDR (dBFS) SFDR = 110MHz 80 75 70 78 SFDR = 140MHz 76 74 72 70 65 68 66 60 SNR = 70MHz/110MHz/140MHz 64 –40 25 05155-009 BACK-OFF (dBFS) 62 05155-006 55 –16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 85 TEMPERATURE (°C) Figure 10. SFDR vs. Backoff @ AIN with fIN = 70 MHz Figure 13. SNR/SFDR vs. Temperature with FIN @ −9 dBFS 90 0.5 0.4 85 0.3 0.2 INL (LSB) SFDR (dBFS) 80 75 70 0.1 0 –0.1 –0.2 65 –0.3 60 BACK-OFF (dBFS) Figure 11. SFDR vs. Backoff @ AIN with fIN = 110 MHz 85 75 70 65 60 05155-008 SFDR (dBFS) 80 BACK-OFF (dBFS) 0 512 1024 1536 2048 2560 CODE Figure 14. Typical INL 90 55 –16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 –0.5 Figure 12. SFDR vs. Backoff @ AIN with fIN = 140 MHz Rev. 0 | Page 11 of 16 3072 3584 4096 05155-010 55 –16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 05155-007 –0.4 AD15452 75 70 0.2 65 CMRR (dB) 60 0 –0.1 55 50 45 40 –0.2 0 512 1024 1536 2048 2560 CODE 3072 3584 4096 Figure 15. Typical DNL 30 10 100 FREQUENCY (MHz) Figure 16. Common-Mode Rejection Ratio Rev. 0 | Page 12 of 16 1000 05155-015 35 05155-011 DNL (LSB) 0.1 AD15452 THEORY OF OPERATION The AD15452 consists of four high performance ADC channels. Each channel is independent of each other with the exception of a shared internal reference source, VREF, and sample clock. The channels consist of a differential front-end amplification circuit followed by a low-pass filter and a multistage pipeline ADC. The quantized outputs from each stage are combined into a 12-bit result. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers; the data is then serialized and aligned to the frame and output clock. ANALOG INPUTS Each analog input is fully differential, allowing sampling of differential input signals. The differential input signals are accoupled and terminated in 100 Ω input impedances. The fullscale differential signal input range is 296 mV p-p. VOLTAGE REFERENCE The AD15452 reference voltage is set internally to 0.5 V. The VREF pin and SENSE pin are used to decouple the 0.5 V reference. The VREF pin and SENSE pin must be shorted together and then decoupled with a 10 μF capacitor to AGND. Ideally, this capacitor should be placed as close to the pins as possible. The REFT pin and the REFB pin must have a 10 μF capacitor placed between the two pins. The clock input is treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD15452. Power supplies for clock drivers are separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods) then the original clock at the last step should retime it. DIGITAL OUTPUTS The AD15452 differential outputs conform to the ANSI-644 LVDS standard. To set the LVDS bias current, place a resistor (RSET is nominally equal to 4.0 kΩ) to ground at the LVDSBIAS pin. The RSET resistor current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. To adjust the differential signal swing, simply change the resistor to a different value, as shown in Table 5. Table 5. LVDSBIAS Differential Output Swing CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Typically, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD15452 has a self-contained clock duty cycle stabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD15452. An on-board phase-locked loop (PLL) multiplies the input clock rate for shifting the serial data out. Consequently, any change to the sampling frequency requires a minimum of 100 clock periods to allow the PLL to reacquire and lock to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fA) due only to aperture jitter (tA) can be calculated with the following equation: SNR degradation = 20 × log10 [1/2 × π × fA × tA] In the equation, the rms aperture jitter, tA, represents the root sum square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Applications that require undersampling are particularly sensitive to jitter. RSET 3.6 kΩ 3.9 kΩ (Default) 4.3 kΩ Differential Output Swing 375 mV p-p 350 mV p-p 325 mV p-p The AD15452 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. It is recommended to keep the trace length no longer than 12 inches and to keep differential output traces close together and at equal lengths. The format of the output data can be selected as offset binary. A quick example of the output coding format can be found in Table 6. Table 6. Digital Output Coding Code 4095 2048 2047 0 Rev. 0 | Page 13 of 16 (VIN+) − (VIN−) Input Span = 296 V p-p (V) Digital Output Offset Binary (D11...D0) 0.147 0 −0.000072 −0.148 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 AD15452 TIMING POWER-DOWN MODE Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 MHz (12 bits × 65 MSPS = 780 MHz). The lowest typical conversion rate is 10 MSPS. By asserting the PDWN pin high, the AD15452 is placed in power-down mode with a typical power dissipation of 360 mW. During power-down, the LVDS output drivers are placed in a high impedance state. To return the AD15452 to normal operating mode, reassert the PDWN pin low. Two output clocks are provided to assist in capturing data from the AD15452. The DCO is used to clock the output data and is equal to six times the sampling clock (CLK) rate. Data is clocked out of the AD15452 and can be captured on the rising and falling edges of the DCO that supports double-data rate (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode and shorter cycles result in proportionally shorter wakeup times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately one second to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation. DTP PIN The digital test pattern (DTP) pin can be enabled for two different types of test patterns. When the DTP is tied to AVDD/3, all the ADC channel outputs shift out the 1000 0000 0000 pattern. When the DTP is tied to 2 × AVDD/3, all the ADC channel outputs shift out the 1010 1010 1010 pattern. The FCO and DCO outputs still work as usual while all channels shift out the test pattern. This pattern allows the user to perform timing alignment adjustments between the DCO and the output data. For normal operation, this pin should be grounded to AGND. POWER SUPPLIES The nominal setting for the AVDD, PLLVDD, and DRVDD supplies is 3.3 V. The AVDD and PLLVDD supplies (analog) should be kept separate from the DRVDD supply (digital). AVDD and PLLVDD can be tied together as long as clean supplies are used. Power supply decoupling capacitors should be used to decouple the supplies at the board connections. Internal decoupling is present in the AD15452 and any external decoupling capacitors should be placed as close to the AD15452 supply pins as possible. Both the analog and digital ground pins are used to dissipate power from the AD15452’s package. These ground pins should be brought to a ground plane in order to maximize the thermal dissipation designed into the package. Table 7. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP1 DTP2 Restricted DTP Voltage AGND AVDD/3 2 × AVDD/3 AVDD Resulting D1+, D1– Normal operation 1000 0000 0000 1010 1010 1010 NA Rev. 0 | Page 14 of 16 Resulting FCO and DCO Normal operation Normal operation Normal operation NA AD15452 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 10.00 BSC SQ 9 8 7 6 5 4 3 2 1 A BALL A1 INDICATOR B C 8.00 BSC SQ D TOP VIEW E F G 1.00 BSC H J BOTTOM VIEW DETAIL A 1.70 MAX DETAILA 0.30 MIN 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER 1.10 0.25 0.20 COPLANARITY COMPLIANT WITH JEDEC STANDARDS MO-192-ABC-1. Figure 17. 81-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-81-1) Dimensions shown in millimeters ORDERING GUIDE Model AD15452BBC AD15452/PCB Temperature Range −40°C to +85°C Package Description 81-Lead Chip Scale Package Ball Grid Array (CSPBGA) Evaluation Board Rev. 0 | Page 15 of 16 Package Option BC-81-1 AD15452 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05155-0-10/05(0) Rev. 0 | Page 16 of 16