MICROTUNE MT45W4MW16B

64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Features
Async/Page/Burst CellularRAMTM 1.0 Memory
MT45W4MW16B*
*Note: Not recommended for new designs.
For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/products/psram/
Features
Figure 1:
• Single device supports asynchronous, page, and
burst operations
• Random access time: 70ns
• VCC, VCCQ voltages
1.70V–1.95V VCC
1.70V–3.30V VCCQ
• Page mode read access
Sixteen-word page size
Interpage read access: 70ns
Intrapage read access: 20ns
• Burst mode write access
Continuous burst
• Burst mode read access
4, 8, or 16 words, or continuous burst
MAX clock rate: 80 MHz (tCLK = 12.5ns)
Burst initial latency: 50ns (4 clocks) @ 80 MHz
t
ACLK: 9ns @ 80 MHz
• Low power consumption
Asynchronous READ: <25mA
Intrapage READ: <15mA
Initial access, burst READ:
(50ns [4 clocks] @ 80 MHz) < 35mA
Continuous burst READ: <15mA
Standby: 120µA – standard
100µA – low-power option
Deep power-down: <10µA (TYP @ 25°C)
• Low-power features
Temperature-compensated refresh (TCR)
Partial-array refresh (PAR)
Deep power-down (DPD) mode
Options
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_1.fm - Rev. G 10/05 EN
1
2
3
4
5
6
A
LB#
OE#
A0
A1
A2
CRE
B
DQ8
UB#
A3
A4
CE#
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSSQ
DQ11
A17
A7
DQ3
VCC
E
VCCQ
DQ12
A21
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
A19
A12
A13
WE#
DQ7
H
A18
A8
A9
A10
A11
A20
J
WAIT
CLK
ADV#
NC
NC
NC
Top View
(Ball Down)
Options (continued)
Designator
• Frequency
66 MHz
80 MHz
• Standby power
Standard
Low-power
• Operating temperature range
Wireless (-30°C to +85°C)
Industrial (-40°C to +85°C)
Designator
• Configuration:
4 Meg x 16
• Package
54-ball VFBGA (standard)
54-ball VFBGA (lead-free)
• Timing
70ns access
85ns access
Ball Assignment – 54-Ball VFBGA
MT45W4MW16B1
6
8
None
L
WT3
IT2
Notes: 1. Not recommended for new designs.
2. Contact factory.
FB
BB2
3. -30°C exceeds the CellularRAM Working
Group 1.0 specification of -25°C.
-70
-85
Part Number Example:
MT45W4MW16BFB-708LWT
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Table of Contents
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part-Numbering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Software Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Burst Wrap (BCR[3]) Default = Burst No Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .23
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Temperature-Compensated Refresh (RCR[6:5]) Default = +85°C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAMTOC.fm - Rev. G 10/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Ball Assignment – 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram – 4 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Burst Mode READ (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Burst Mode WRITE (4-word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Wired or WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY Operation . . . .17
Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY Operation . . . . .18
Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WAIT Configuration During Burst Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Typical Refresh Current vs. Temperature (ITCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Asynchronous READ Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Single-Access Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4-Word Burst READ Operation (with LB#/UB#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . . .45
CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
LB#/UB#-Controlled Asynchronous WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Burst WRITE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row Condition . .51
Burst WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Asynchronous WRITE Followed By Burst READ – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Burst READ Followed by Asynchronous WRITE Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . .57
Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAMLOF.fm - Rev. G 10/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
List of Tables
List of Tables
Table 1:
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VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Bus Operations – Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Operations – Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
64Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Maximum Standby Currents for Applying PAR and TCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Maximum Standby Currents for Applying PAR and TCR Settings – Low-Power (L) . . . . . . . . . . . . . .30
Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Asynchronous READ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Asynchronous READ Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Asynchronous READ Timing Parameters – Page Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Burst READ Timing Parameters – Single Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Burst READ Timing Parameters – 4-Word Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Burst READ Timing Parameters – 4-Word Burst with LB#/UB#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Burst READ Timing Parameters – Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Burst READ Timing Parameters – BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Asynchronous WRITE Timing Parameters – CE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Asynchronous WRITE Timing Parameters – LB#/UB#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Asynchronous WRITE Timing Parameters – WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Burst WRITE Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Burst WRITE Timing Parameters – BCR[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
WRITE Timing Parameters – Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . .52
READ Timing Parameters – Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
WRITE Timing Parameters – Async WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . .53
READ Timing Parameters – Async WRITE Followed by Burst READ. . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Asynchronous WRITE Timing Parameters – ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Asynchronous WRITE Timing Parameters – WE#-Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Burst READ Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Asynchronous WRITE Timing Parameters Using ADV#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
WRITE Timing Parameters – ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
READ Timing Parameters – ADV# LOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
WRITE Timing Parameters – Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . .58
READ Timing Parameters – Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . .58
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Burst CellularRAMLOT.fm - Rev. G 10/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
General Description
General Description
Micron® CellularRAM™ products are high-speed, CMOS PSRAM memories developed
for low-power, portable applications. The MT45W4MW16BFB is a 64Mb DRAM core
device organized as 4 Meg x 16 bits. This device includes an industry-standard burst
mode Flash interface that dramatically increases read/write bandwidth compared with
other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device read/write performance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three system-accessible mechanisms used to minimize
standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) is used to
adjust the refresh rate according to the case temperature. The refresh rate can be
decreased at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) halts the refresh operation altogether and is used when no
vital information is stored in the device. These three refresh mechanisms are accessed
through the RCR.
Figure 2:
Functional Block Diagram – 4 Meg x 16
A[21:0]
Address Decode
Logic
4,096K x 16
DRAM
Memory
Array
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
Control
Logic
Note:
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
General Description
Table 1:
VFBGA Ball Descriptions
VFBGA
Assignment
Symbol
Type
Description
E3, H6, G2, H1,
D3, E4, F4, F3,
G4, G3, H5, H4,
H3, H2, D4, C4,
C3, B4, B3, A5,
A4, A3
J2
A[21:0]
Input
Address Inputs: Inputs for addresses during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR.
CLK
Input
J3
ADV#
Input
A6
CRE
Input
B5
CE#
Input
A2
OE#
Input
G5
WE#
Input
A1
B2
G1, F1, F2, E2,
D2, C2, C1, B1,
G6, F6, F5, E5,
D5, C6, C5, B6
J1
LB#
UB#
DQ[15:0]
Input
Input
Input/
Output
Clock: Synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK is static (HIGH or
LOW) during asynchronous access READ and WRITE operations and during PAGE
READ ACCESS operations.
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses can be latched on the rising edge of ADV# during asynchronous READ
and WRITE operations. ADV# may be held LOW during asynchronous READ and
WRITE operations.
Control Register Enable: When CRE is HIGH, WRITE operations load the RCR or
BCR.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle
is a WRITE to either a configuration register or to the memory array.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
WAIT
Output
J4, J5, J6
D6
E1
E6
D1
NC
VCC
VCCQ
VSS
VSSQ
–
Supply
Supply
Supply
Supply
Note:
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between refresh and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with opening a new internal page.
WAIT is asserted and should be ignored during asynchronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
Not internally connected.
Device Power Supply: (1.70V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.70V–3.30V) Power supply for input/output buffers.
VSS must be connected to ground.
VSSQ must be connected to ground.
The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted but should be ignored during asynchronous and
page mode operations.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operations
Bus Operations
Table 2:
Bus Operations – Asynchronous Mode
Mode
Power
CLK1
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT2
DQ[15:0]3
Notes
Read
Write
Standby
No Operation
Configuration
Register
DPD
Active
Active
Standby
Idle
Active
X
X
X
X
X
L
L
X
X
L
L
L
H
L
L
L
X
X
X
H
H
L
X
X
L
L
L
L
L
H
L
L
X
X
X
Low-Z
Low-Z
High-Z
Low-Z
Low-Z
Data-Out
Data-In
High-Z
X
High-Z
4
4
5, 6
4, 6
Deep
Power-Down
X
X
H
X
X
X
X
High-Z
High-Z
7
Table 3:
Bus Operations – Burst Mode
Mode
Power
CLK1
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT2
DQ[15:0]3
Notes
Async Read
Async Write
Standby
No Operation
Initial Burst
Read
Active
Active
Standby
Idle
Active
X
X
X
X
L
L
X
X
L
L
L
H
L
L
L
X
X
X
X
H
L
X
X
H
L
L
L
L
L
L
L
X
X
L
Low-Z
Low-Z
High-Z
Low-Z
Low-Z
Data-Out
Data-In
High-Z
X
Data-Out
4
4
5, 6
4, 6
4, 8
Initial Burst
Write
Active
L
L
H
L
L
X
Low-Z
Data-In
4, 8
Burst
Continue
Active
H
L
X
X
X
L
Low-Z
Data-In or
Data-Out
4, 8
Burst Suspend
Configuration
Register
Active
Active
X
X
L
L
L
H
H
X
L
L
H
X
X
Low-Z
Low-Z
High-Z
High-Z
4, 8
8
Deep
Power-Down
X
X
H
X
X
X
X
High-Z
High-Z
7
DPD
Notes: 1. CLK may be HIGH or LOW, but must be static, during async read and async write modes
and to achieve standby and DPD modes. CLK must be static (HIGH or LOW) during burst
suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are
affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby
current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Part-Numbering Information
Part-Numbering Information
Micron CellularRAM devices are available in several different configurations and densities (see Figure 3).
Figure 3:
Part Number Chart
MT 45
W 4M W 16
B
FB -70
6
WT ES
Production Status
Micron Technology
Blank = Production
Product Family
ES = Engineering Sample
45 = PSRAM/CellularRAM Memory
MS = Mechanical Sample
Operating Core Voltage
Operating Temperature
W = 1.70V–1.95V
WT = -30°C to +85°C (see Note 1)
IT = -40° to +85°C (contact factory)
Address Locations
Standby Power Options
M = Megabits
Blank = Standard
Operating Voltage
L = Low Power
W = 1.70V–3.30V
Frequency
Bus Configuration
6 = 66 MHz
16 = x16
8 = 80 MHz
READ/WRITE Operation Mode
Access/Cycle Time
B = Asynchronous/Page/Burst
70 = 70ns
85 = 85ns
Package Codes
FB = VFBGA (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball
BB = Lead-free VFBGA (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) 54-ball (contact factory)
Note:
-30°C exceeds the CellularRAM Working Group 1.0 specification of -25°C.
Valid Part Number Combinations
After building the part number from the part numbering chart, please go to the Micron
Part Marking Decoder Web site at http://www.micron.com/partsearch to verify that the
part number is offered and valid. If the device required is not on this list, please contact
the factory.
Device Marking
Due to the size of the package, the Micron standard part number is not printed on the
top of the device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at http://www.micron.com/partsearch. To view the location of the abbreviated mark on the device, please refer to customer service note, CSN-11, “Product
Mark/Label," at http://www.micron.com/csn.
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Functional Description
Functional Description
In general, the MT45W4MW16BFB device is a high-density alternative to SRAM and
Pseudo SRAM products, popular in low-power, portable applications.
The MT45W4MW16BFB device contains a 67,108,864-bit DRAM core, organized as
4,194,304 addresses by 16 bits. The device implements the same high-speed bus interface found on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their default
settings (see Table 17 on page 21 and Table 22 on page 26). VCC and VCCQ must be
applied simultaneously. When they reach a stable level at or above 1.70V, the device will
require 150µs to complete its self-initialization process. During the initialization period,
CE# should remain HIGH. When initialization is complete, the device is ready for normal operation.
Figure 4:
Power-Up Initialization Timing
Vcc = 1.70V
Vcc
VccQ
tPU > 150µs
Device ready for
Device Initialization normal operation
Bus Operating Modes
The MT45W4MW16BFB CellularRAM product incorporates a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode, and burst mode read and write transfers. The specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5) are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE#
HIGH. Valid data will be driven out of the I/Os after the specified access time has
elapsed. WRITE operations (Figure 6) occur when CE#, WE#, and LB#/UB# are driven
LOW. During asynchronous WRITE operations, the OE# level is a “Don’t Care,” and WE#
will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or
LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can
either use the ADV input to latch the address, or ADV can be driven LOW during the
entire READ/WRITE operation.
During asynchronous operation, the CLK input must be static (HIGH or LOW—no transitions). WAIT will be driven while the device is enabled and its state should be ignored.
WE# LOW time must be limited to tCEM.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
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©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 5:
READ Operation (ADV = LOW)
CE#
OE#
WE#
ADDRESS
ADDRESS VALID
DATA
DATA VALID
LB#/UB#
tRC = READ Cycle Time
DON’T CARE
Note:
Figure 6:
ADV must remain LOW for page mode operation.
WRITE Operation (ADV = LOW)
CE#
OE#
< tCEM
WE#
ADDRESS
DATA
ADDRESS VALID
DATA VALID
LB#/UB#
tWC = WRITE Cycle Time
DON’T CARE
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order
address. Addresses A[3:0] are used to determine the members of the 16-address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time.
Figure 7 shows the timing for a page mode access. Page mode takes advantage of the fact
that adjacent addresses can be read in a shorter period of time than random addresses.
WRITE operations do not include comparable page mode functionality.
During asynchronous page mode operation, the CLK input must be static (HIGH or LOW
– no transitions). CE# must be driven HIGH upon completion of a page mode access.
WAIT will be driven while the device is enabled and its state should be ignored. Page
mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page
mode read accesses.
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
10
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©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than tCEM.
Figure 7:
Page Mode READ Operation (ADV = LOW)
< tCEM
CE#
OE#
WE#
ADDRESS
Add[0]
tAA
DATA
Add[1]
tAPA
D[0]
Add[2]
tAPA
D[1]
Add[3]
tAPA
D[2]
D[3]
LB#/UB#
DON’T CARE
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consist of a multi-clock sequence that must be performed in an
ordered fashion. After CE# goes LOW, the address to access is latched on the next rising
edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether
the operation is going to be a READ (WE# = HIGH, Figure 8 on page 12) or WRITE (WE#
= LOW, Figure 9 on page 12).
The size of a burst can be specified in the BCR as either fixed-length or continuous.
Fixed-length bursts consist of four, eight, or sixteen words. Continuous bursts have the
ability to start at a specified address and burst through the entire memory. The latency
count stored in the BCR defines the number of clock cycles that elapse before the initial
data value is transferred between the processor and CellularRAM device.
The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to
indicate when data is to be transferred into (or out of ) the memory. WAIT will again be
asserted if the burst crosses the boundary between 128-word rows. Once the CellularRAM device has restored the previous row’s data and accessed the next row, WAIT will be
de-asserted and the burst can continue (see Figure 34 on page 45).
The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. Bursts are suspended by stopping
CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the
burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and as a
result no other devices should directly share the WAIT connection to the controller. To
continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is
available on the bus.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension
will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the
burst restarted with a new CE# LOW/ADV# LOW cycle.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 8:
Burst Mode READ (4-word Burst)
CLK
ADDRESS
VALID
A[21:0]
ADV#
Latency Code 2 (3 clocks)
CE#
OE#
WE#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
LB#/UB#
DON’T CARE
READ Burst Identified
(WE# = HIGH)
Note:
Figure 9:
UNDEFINED
Non-default BCR settings for burst mode READ (4-word burst): Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
Burst Mode WRITE (4-word Burst)
CLK
ADDRESS
VALID
A[21:0]
ADV#
Latency Code 2 (3 clocks)
CE#
OE#
WE#
WAIT
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
LB#/UB#
DON’T CARE
WRITE Burst Identified
(WE# = LOW)
Note:
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Non-default BCR settings for burst mode WRITE (4-word burst): Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
12
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Bus Operating Modes
Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous WRITE
operations when the BCR is configured for synchronous operation. The asynchronous
READ and WRITE operations require that the clock (CLK) remain static (HIGH or LOW)
during the entire sequence. The ADV# signal can be used to latch the target address, or it
can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a
READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode
operation facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 42 on page 53 for the “Asynchronous WRITE Followed by Burst READ”
timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, systemlevel WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus.
Figure 10:
Wired or WAIT Configuration
CellularRAM
WAIT
External
Pull-Up/
Pull-Down
Resistor
READY
Processor
WAIT
WAIT
Other
Device
Other
Device
Once a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
CE# must remain asserted during WAIT cycles (WAIT asserted and WAIT configuration
BCR[8] = 1). Bringing CE# HIGH during WAIT cycles may cause data corruption. (Note
that for BCR[8] = 0, the actual WAIT cycles end one cycle after WAIT de-asserts, and for
row boundary crossings, start one cycle after the WAIT signal asserts.)
The WAIT output also performs an arbitration role when a READ or WRITE operation is
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted
for additional clock cycles until the refresh has completed (see Figures 11 and 12 on
page 15). When the REFRESH operation has completed, the READ or WRITE operation
will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary.
The WAIT assertion allows time for the new row to be accessed, and permits any pending REFRESH operations to be performed.
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Bus Operating Modes
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE operations, any disabled bytes will not be transferred to the RAM array and the internal value
will remain unchanged. During an asynchronous WRITE cycle, the data to be written is
latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Figure 11:
CLK
A[21:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
Refresh Collision During READ Operation
VIH
VIL
VIH
VIL
VALID
ADDRESS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
High-Z
VOH
D[0]
VOL
Additional WAIT states inserted to allow refresh completion.
Note:
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D[1]
D[2]
D[3]
UNDEFINED
DON’T CARE
Non-default BCR settings for refresh collision during READ operation: Latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay.
14
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Bus Operating Modes
Figure 12:
CLK
A[21:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
Refresh Collision During WRITE Operation
VIH
VIL
VIH
VIL
VALID
ADDRESS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
High-Z
VOH
D[0]
VOL
Additional WAIT states inserted to allow refresh completion.
Note:
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D[1]
D[2]
D[3]
DON’T CARE
Non-default BCR settings for refresh collision during WRITE operation: Latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay.
15
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Low-Power Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature-Compensated Refresh
Temperature-compensated refresh (TCR) is used to adjust the refresh rate depending on
the device operating temperature. DRAM technology requires increasingly frequent
REFRESH operations to maintain data integrity as temperatures increase. More frequent
refresh is required due to increased leakage of the DRAM capacitive storage elements as
temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings
in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C, +45°C,
+70°C, and +85°C). The setting selected must be for a temperature higher than the case
temperature of the CellularRAM device. For example, if the case temperature is +50°C,
the system can minimize self refresh current consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause data
corruption.
Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of
these partitions can start at either the beginning or the end of the address map (see
Table 6 on page 27). READ and WRITE operations to address ranges receiving refresh will
not be affected. Data stored in addresses not receiving refresh will become corrupted.
When re-enabling additional portions of the array, the new portions are available immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM device will require 150µs to perform
an initialization procedure before normal operations can resume. During this 150µs
period, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access
sequence; the RCR should be accessed using CRE instead.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up, and can
be updated any time the devices are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a synchronous or an asynchronous
WRITE operation when the control register enable (CRE) input is HIGH (see Figure 13
below and Figure 14 on page 18). When CRE is LOW, a READ or WRITE operation will
access the memory array. The register values are placed on addresses A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising
edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care.” Access
using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed
when A[19] is LOW.
Figure 13:
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY
Operation
CLK
A[21:0]
(except A19)
OPCODE
ADDRESS
tAVH
tAVS
Select Control Register
A191
ADDRESS
tAVS
CRE
tAVH
tVPH
ADV#
tVP
tCBPH
Initiate Control Register Access
CE#
tCW
OE#
tWP
Write Address Bus Value
to Control Register
WE#
LB#/UB#
DQ[15:0]
DATA VALID
DON’T CARE
Note:
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
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Configuration Registers
Figure 14:
Configuration Register WRITE in Synchronous Mode Followed by READ ARRAY
Operation
CLK
Latch Control Register Value
A[21:0]
(except A19)
OPCODE
tHD
tSP
ADDRESS
Latch Control Register Address
A192
ADDRESS
tSP
CRE
tSP
ADV#
tHD
tHD
tCBPH3
tCSP
CE#
OE#
tSP
WE#
tHD
LB#/UB#
WAIT
tCW
High-Z
High-Z
DATA
VALID
DQ[15:0]
DON’T CARE
Notes: 1. Non-default BCR settings for configuration register WRITE in synchronous mode followed
by READ ARRAY operation: Latency code two (three clocks); WAIT active LOW; WAIT
asserted during delay.
2. A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Software Access
Software access of the configuration registers uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the configuration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 15). The read sequence is virtually identical except that an asynchronous READ is
performed during the fourth operation (see Figure 16 on page 20). Note that a third
READ cycle of the highest address cancels the access sequence until a different address
is read.
The address used during all READ and WRITE operations is the highest address of the
CellularRAM device being accessed (3FFFFFh for 64Mb); the content at this address is
changed by using this sequence (note that this is a deviation from the CellularRAM specification).
The data value presented during the third operation (WRITE) in the sequence defines
whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will
access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth
operation, DQ[15:0] is used to transfer data into or out of bits 15–0 of the configuration
registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for the control register enable
(CRE) ball. If the software mechanism is used, the CRE ball can simply be tied to VSS. The
port line often used for CRE control purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
Figure 15:
Load Configuration Register
ADDRESS
1
READ
READ
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
XXXXh
XXXXh
WRITE
ADDRESS
(MAX)
CE#
OE#
WE#
LB#/UB#
DATA
CR VALUE
IN
RCR: 0000h
BCR: 0001h
DON'T CARE
Note:
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The WRITE on the third cycle must be CE#-controlled.
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Configuration Registers
Figure 16:
Read Configuration Register
ADDRESS
1
READ
READ
WRITE
ADDRESS
(MAX)
ADDRESS
(MAX)
ADDRESS
(MAX)
CE#
READ
ADDRESS
(MAX)
NOTE2
OE#
WE#
LB#/UB#
DATA
XXXXh
CR VALUE
OUT
XXXXh
RCR: 0000h
BCR: 0001h
DON'T CARE
Notes: 1. The WRITE on the third cycle must be CE#-controlled.
2. CE# must be HIGH for 150ns before performing the cycle that reads a configuration register.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] HIGH, or through the configuration register
software sequence with DQ = 0001h on the third cycle.
Figure 17:
Bus Configuration Register Definition
A15
A[21:20] A19 A[18:16]
21–20
Reserved
18–16
19
Register
Select
Reserved
15
14
Operating
Mode
Must be set to "0"
All must be set to "0"
A14 A13 A12A11 A10
Reserved
13 12 11
Latency
Counter
Must be set to "0"
BCR[13] BCR[12] BCR[11]
9
WAIT
Polarity
A7
Reserved
A5
A6
7
8
WAIT
Configuration (WC)
Reserved
Must be set to "0"
A4
4
5
6
Clock
Configuration (CC)
Output
Impedance
Must be set to "0"
Reserved
A3
A2 A1 A0
3
2
1
0
Burst
Burst
Wrap (BW)* Length (BL)*
Must be set to "0"
Latency Counter
0
0
0
Code 0–Reserved
0
0
1
Code 1–Reserved
0
1
0
Code 2
0
1
1
Code 3 (Default)
1
0
0
Code 4–Reserved
1
0
1
Code 5–Reserved
1
1
0
Code 6–Reserved
1
1
1
Code 7–Reserved
BCR[10]
Burst Wrap (Note 1)
BCR[3]
0
Burst wraps within the burst length
1
Burst no wrap (default)
WAIT Polarity
0
Active LOW
1
Active HIGH (default)
BCR[8]
BCR[15]
10
A8
A9
Output Impedance
BCR[5]
0
Full Drive (default)
1
1/4 Drive
WAIT Configuration
BCR[6]
0
Asserted during delay
1
Asserted one data cycle before delay (default)
Clock Configuration
0
Not supported
1
Rising edge (default)
Operation Mode
0
Synchronous burst access mode
1
Asynchronous access mode (default)
BCR[2]
Register Select
BCR[19]
0
Select RCR
1
Select BCR
Note:
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BCR[1] BCR[0]
Burst Length (Note 1)
0
0
1
4 words
0
1
0
8 words
0
1
1
16 words
1
1
1
Continuous burst (default)
All burst WRITEs are continuous.
21
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Configuration Registers
Table 4:
Sequence and Burst Length
Burst Wrap
Starting
Address
BCR[3] Wrap (Decimal)
0
Yes
0
1
2
3
4
5
6
7
...
14
4-Word
Burst
Length
8-Word
Burst Length
16-Word Burst Length
Continuous Burst
Linear
Linear
Linear
Linear
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
...
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11-…
6-7-8-9-10-11-127-8-9-10-11-12-13-…
...
14-15-16-17-18-1920-...
15-16-17-18-19-2021...
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
15
1
No
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0
1
2
0-1-2-3
1-2-3-4
2-3-4-5
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3
3-4-5-6
3-4-5-6-7-8-9-10
4
4-5-6-7-8-9-10-11
5
5-6-7-8-9-10-11-12
6
6-7-8-9-10-11-1213
7-8-9-10-11-12-1314
7
...
14
15
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-1617
3-4-5-6-7-8-9-10-11-12-13-14-15-16-1718
4-5-6-7-8-9-10-11-12-13-14-15-16-1718-19
5-6-7-8-9-10-11-12-13-...-15-16-17-1819-20
6-7-8-9-10-11-12-13-14-...-16-17-18-1920-21
7-8-9-10-11-12-13-14-...-17-18-19-2021-22
...
14-15-16-17-18-19-...-23-24-25-26-2728-29
15-16-17-18-19-20-...-24-25-26-27-2829-30
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12…
7-8-9-10-11-12-13…
...
14-15-16-17-18-1920-…
15-16-17-18-19-2021-…
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set
in continuous burst mode where data is output sequentially without regard to address
boundaries; the internal address wraps to 000000h if the device is read past the last
address. WRITE bursts are always performed using continuous burst mode.
Burst Wrap (BCR[3]) Default = Burst No Wrap
The burst wrap option determines if a 4-, 8-, or 16-word burst READ wraps within the
burst length, or steps through sequential addresses. If the wrap option is not enabled,
the device outputs data from sequential addresses without regard to burst boundaries;
the internal address wraps to 000000h if the device is read past the last address.
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Configuration Registers
Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength
The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option will be more than adequate in stacked chip (Flash +
CellularRAM) environments when there is a dedicated memory bus. The reduced-drivestrength option is included to minimize noise generated on the data bus during READ
operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength
during testing.
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on
the clock edge immediately after WAIT transitions to the de-asserted or asserted state,
respectively (see Figure 18 and Figure 20). When A8 = 1, the WAIT signal transitions one
clock period prior to the data bus going valid or invalid (see Figure 19 and Figure 20).
Figure 18:
WAIT Configuration (BCR[8] = 0)
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data[1]
Data immediately valid (or invalid)
Note:
Figure 19:
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 20 on
page 24.
WAIT Configuration (BCR[8] = 1)
CLK
WAIT
DQ[15:0]
High-Z
Data[0]
Data valid (or invalid) after one clock delay
Note:
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
Note: Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See
Figure 20 on page 24.
23
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 20:
WAIT Configuration During Burst Operation
CLK
BCR[8] = 0
Data valid in current cycle.
WAIT
BCR[8] = 1
Data valid in next cycle.
WAIT
DQ[15:0]
D[1]
D[0]
D[2]
D[3]
D[4]
DON’T CARE
Note:
Non-default BCR setting for WAIT configuration during burst operation: WAIT active LOW.
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code two
(three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure 21)
Table 5:
Latency Configuration
Max Input CLK Frequency (MHz)
Latency Configuration Code
2 (3 clocks)
3 (4 clocks) – default
-708
-706/-856
53 (18.75ns)
80 (12.50ns)
441 (22.7ns)
66 (15.20ns)
Notes: 1. Clock rates below 50 MHz are allowed as long as tCSP specifications are met.
Figure 21:
CLK
A[21:0]
ADV#
Latency Counter
VIH
VIL
VIH
VIL
VALID
ADDRESS
VIH
VIL
Code 2
DQ[15:0]
VOH
VALID
OUTPUT
VOL
Code 3
DQ[15:0]
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
(Default)
VOH
VOL
DON’T CARE
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
24
UNDEFINED
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the
RCR. Figure 22 describes the control bits used in the RCR. At power-up, the RCR is set to
0070h.
The RCR is accessed using CRE and A[19] LOW; or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Registers” on page 17.)
Figure 22:
Refresh Configuration Register Mapping
A[21:20]
21–20
RESERVED
A19
19
Register
Select
A[18:8]
A7
18–8
RESERVED
7
PAGE
A6
6
A5
A4
5
TCR
4
Select RCR
1
Select BCR
RCR[7]
A0
0
1
2
RESERVED
Address Bus
Read Configuration
Register
PAR
Must be set to "0"
Refresh Coverage
RCR[2]
RCR[1]
RCR[0]
0
0
0
0
0
1
Bottom 1/2 array
Bottom 1/4 array
Register Select
0
A1
A2
3
DPD
All must be set to "0" All must be set to "0"
RCR[19]
A3
Page Mode Enable/Disable
Full array (default)
0
1
0
0
1
1
Bottom 1/8 array
1
0
0
None of array
1
0
1
Top 1/2 array
0
Page Mode Disabled (default)
1
1
0
Top 1/4 array
1
Page Mode Enable
1
1
1
Top 1/8 array
RCR[6] RCR[5]
Maximum Case Temp.
RCR[4]
Deep Power-Down
1
1
+85˚C (default)
0
DPD Enable
0
0
+70˚C
1
DPD Disable (default)
0
1
+45˚C
1
0
+15˚C
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map.
Table 6:
64Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Full die
One-half of die
One-quarter of die
One-eighth of die
None of die
One-half of die
One-quarter of die
One-eighth of die
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
000000h–07FFFFh
0
200000h–3FFFFFh
300000h–3FFFFFh
380000h–3FFFFFh
4 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
521K x 16
64Mb
32Mb
16Mb
8Mb
0Mb
32Mb
16Mb
8Mb
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150µs to perform an initialization procedure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to
“1.” DPD should not be enabled or disabled with the software access sequence; instead,
use CRE to access the RCR.
Temperature-Compensated Refresh (RCR[6:5]) Default = +85°C Operation
The TCR bits allow for adequate refresh at four different temperature thresholds (+15°C,
+45°C, +70°C, and +85°C). The setting selected must be for a temperature higher than
the case temperature of the CellularRAM device. If the case temperature is +50°C, the
system can minimize self refresh current consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in inadequate refreshing and cause
data corruption.
Page Mode Operation (RCR[7]) Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled.
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Electrical Characteristics
Electrical Characteristics
Table 7:
Absolute Maximum Ratings
Parameter
Rating
-0.50V to (4.0V or VCCQ + 0.3V, whichever is less)
-0.2V to +2.45V
-0.2V to +4.0V
-55°C to +150°C
Voltage to Any Ball Except VCC, VCCQ Relative to VSS
Voltage on VCC Supply Relative to VSS
Voltage on VCCQ Supply Relative to VSS
Storage Temperature (plastic)
Operating Temperature (case)
Wireless (see Note 1)
Industrial
-30°C to +85°C
-40°C to +85°C
Soldering Temperature and Time
10s (solder ball only)
+260°C
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Notes: 1. -30°C exceeds the CellularRAM Working Group 1.0 specification of -25°C.
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Electrical Characteristics
Table 8:
Electrical Characteristics and Operating Conditions
Wireless Temperature1 (-30ºC < TC < +85ºC); Industrial Temperature (-40ºC < TC < +85ºC)
Description
Conditions
Supply Voltage
I/O Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Asynchronous Random READ/
WRITE
Asynchronous Page READ
IOH = -0.2mA
IOL = +0.2mA
VIN = 0 to VCCQ
OE# = VIH or
Chip Disabled
VIN = VCCQ or 0V
Chip Enabled,
IOUT = 0
Symbol
VCC
VCCQ
VIH
VIL
VOH
VOL
ILI
ILO
ICC1
ICC1P
ICC2
Initial Access, Burst READ/WRITE
Continuous Burst READ
ICC3R
Continuous Burst WRITE
ICC3W
VIN = VCCQ or 0V
CE# = VCCQ
Standby Current
ISB
Min
Max
Units
Notes
1.70
1.70
1.4
-0.20
0.80 VCCQ
1.95
3.30
VCCQ + 0.2
0.4
V
V
V
V
V
V
µA
µA
2, 3
4
5
5
mA
6
mA
6
mA
6
mA
6
mA
6
µA
7
0.20 VCCQ
1
1
-70
-85
-70
-85
80 MHz
66 MHz
80 MHz
66 MHz
80 MHz
66 MHz
Standard
Low-Power (L)
25
20
15
12
35
30
18
15
35
30
120
100
Notes: 1. -30°C exceeds the CellularRAM Working Group 1.0 specification of -25°C.
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. VIH (MIN) value is not aligned with CellularRAM Working Group 1.0 specification of VCCQ 0.4V.
4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions
5. BCR[5:4] = 00b.
6. This parameter is specified with the outputs disabled to avoid external loading effects. The
user must add the current required to drive output capacitance expected in the actual system.
7. ISB (MAX) values measured with PAR set to FULL ARRAY and TCR set to +85°C. In order to
achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB may be
slightly higher for up to 500ms after power-up or when entering standby mode.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Maximum and Typical Standby Currents
The following tables and figures refer to the maximum and typical standby currents for
the MT45W4MW16BFB device. The typical values shown in Figure 23 on page 31 are
measured with the appropriate PAR and TCR settings. The maximum values shown in
Table 9 and Table 11 are measured with the relevant TCR bits set in the configuration
register.
Table 9:
Maximum Standby Currents for Applying PAR and TCR Settings
TCR
PAR
+15°C (RCR[6:5] = 10b)
+45°C (RCR[6:5] = 01b)
+70°C (RCR[6:5] = 00b)
+85°C (RCR[6:5] = 11b)
70
65
60
57
50
85
80
75
70
55
105
100
95
90
60
120
115
110
105
70
Full Array
1/2 Array
1/4 Array
1/8 Array
0 Array
Notes: 1. For RCR[6:5] = 00b (default), refer to Figure 23, Typical Refresh Current vs. Temperature
(Itcr), on page 31 for typical values.
2. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB
may be slightly higher for up to 500ms after power-up or when entering standby mode.
3. TCR values for 85°C are 100 percent tested. TCR values for 15°C , 45°C, and 70°C are sampled only.
Table 10:
Maximum Standby Currents for Applying PAR and TCR Settings – Low-Power (L)
TCR
PAR
+15°C (RCR[6:5] = 10b)
+45°C (RCR[6:5] = 01b)
+70°C (RCR[6:5] = 00b)
+85°C (RCR[6:5] = 11b)
60
57
54
52
50
70
65
61
58
55
85
80
75
70
60
100
95
90
85
70
Full Array
1/2 Array
1/4 Array
1/8 Array
0 Array
Notes: 1. For RCR[6:5] = 00b (default), refer to Figure 23, Typical Refresh Current vs. Temperature
(Itcr), on page 31 for typical values.
2. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB
may be slightly higher for up to 500ms after power-up or when entering standby mode.
3. TCR values for 85°C are 100 percent tested. TCR values for 15°C, 45°C, and 70°C are sampled only.
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64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Figure 23:
Typical Refresh Current vs. Temperature (ITCR)
70
60
I SB (µA)
50
PAR = Full Array
PAR = 1/2 of Array
40
PAR = 1/4 of Array
PAR = 1/8 of Array
PAR = None of Array
30
20
10
0
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (°C)
Note:
Table 11:
Typical ISB currents for each PAR setting with the appropriate TCR selected.
Deep Power-Down Specifications
Description
Deep Power-Down
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
Conditions
Symbol
Typ
Units
VIN = VCCQ or 0V; +25°C
IZZ
10
µA
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Electrical Characteristics
Table 12:
Capacitance
Description
Input Capacitance
Input/Output Capacitance (DQ)
Conditions
Symbol
Min
Max
Units
Notes
TC = +25ºC; f = 1 MHz;
VIN = 0V
CIN
CIO
2.0
2.5
6
6
pF
pF
1
1
Notes: 1. These parameters are verified in device characterization and are not 100 percent tested.
Figure 24:
AC Input/Output Reference Waveform
VCCQ
Input
1
2
VCC/2
Test Points
3
VCCQ/2
Output
VSSQ
Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall
times (10% to 90%) < 1.6ns.
2. Input timing begins at VCC/2. Due to the possibility of a difference between VCC and VCCQ,
the input test point may not be shown to scale.
3. Output timing ends at VCCQ/2.
Figure 25:
Output Load Circuit
VccQ
R1
Test Point
DUT
30pF
Note:
Table 13:
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
R2
All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
Output Load Circuit
VCCQ
R1/R2
1.8V
2.5V
3.0V
2.7KΩ
3.7KΩ
4.5KΩ
32
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Electrical Characteristics
Table 14:
Asynchronous READ Cycle Timing Requirements
-70x
Parameter1
Symbol
Address Access Time
ADV# Access Time
Page Access Time
Address Hold from ADV# HIGH
Address Setup to ADV# HIGH
LB#/UB# Access Time
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
Chip Select Access Time
CE# LOW to ADV# HIGH
Chip Disable to DQ and WAIT High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
READ Cycle Time
ADV# Pulse Width LOW
ADV# Pulse Width HIGH
tAA
Min
Max
Min
70
70
20
t
AADV
APA
tAVH
t
AVS
tBA
t
BHZ
t
BLZ
tCEM
tCEW
tCO
tCVS
tHZ
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
tRC
tVP
tVPH
-856
t
5
10
10
85
85
25
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
8
10
8
7.5
70
10
1
8
7.5
85
10
8
10
8
10
20
5
20
5
8
5
20
70
10
10
Units
5
10
70
8
1
Max
8
5
25
85
10
10
Notes
4
3
2
4
3
4
3
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Page-mode enabled only.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The
Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward
either VOH or VOL.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
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Electrical Characteristics
Table 15:
Burst READ Cycle Timing Requirements
-708
Parameter1
Symbol
Burst to READ Access Time
CLK to Output Delay
Burst OE# LOW to Output Delay
CE# HIGH between Subsequent Mixed-Mode
Operations
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
CLK Period
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT High-Z Output
CLK Rise or Fall Time
CLK to WAIT Valid
CLK to DQ High-Z Output
CLK to Low-Z Output
Output HOLD from CLK
CLK HIGH or LOW Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tABA
Min
ACLK
BOE
tCBPH
t
5
t
CEM
CEW
t
CLK
tCSP
tHD
tHZ
tKHKL
tKHTL
tKHZ
tKLZ
tKOH
tKP
tOHZ
tOLZ
tSP
Max
Min
46.5
9
20
t
t
-706/-856
1
12.5
4.5
2
3
2
2
4
Units
Notes
56
11
20
ns
ns
ns
ns
2
5
8
7.5
20
20
8
1.8
9
8
5
1
15
5
2
3
2
2
5
8
5
3
Max
8
7.5
20
20
8
2.0
11
8
5
8
5
3
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3
4
4
5
4
5
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
5. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The
Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward
either VOH or VOL.
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Electrical Characteristics
Table 16:
Asynchronous WRITE Cycle Timing Requirements
-70x
Parameter
Symbol
Address and ADV# LOW Setup Time
Address Hold from ADV# Going HIGH
Address Setup to ADV# Going HIGH
Address Valid to End of WRITE
LB#/UB# Select to End of WRITE
CE# LOW to WAIT Valid
Async Address-to-Burst Transition Time
CE# HIGH between Subsequent Asynchronous Operations
CE# LOW to ADV# HIGH
Chip Enable to End of WRITE
Data Hold from WRITE Time
Data WRITE Setup Time
Chip Disable to WAIT High-Z Output
Chip Enable to Low-Z Output
End WRITE to Low-Z Output
ADV# Pulse Width
ADV# Pulse Width HIGH
ADV# Setup to End of WRITE
WRITE Cycle Time
WRITE to DQ High-Z Output
WRITE Pulse Width
WRITE Pulse Width HIGH
WRITE Recovery Time
tAS
t
AVH
AVS
tAW
t
BW
tCEW
t
CKA
t
CPH
tCVS
tCW
tDH
tDW
tHZ
tLZ
tOW
tVP
tVPH
tVS
tWC
tWHZ
tWP
tWPH
tWR
t
Min
0
5
10
70
70
1
70
5
10
70
0
23
-856
Max
7.5
Min
0
5
10
85
85
1
85
5
10
85
0
23
8
10
5
10
10
70
70
7.5
8
10
5
10
10
85
85
8
46
10
0
Max
8
55
10
0
Units
νσ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
3
Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The
Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward
either VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
3. WE# LOW time must be limited to tCEM (8µs).
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Table 17:
Burst WRITE Cycle Timing Requirements
-708
Parameter
Symbol
CE# HIGH between Subsequent Mixed-Mode
Operations
Minimum CE# Pulse Width
CE# LOW to WAIT Valid
Clock Period
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to WAIT High-Z Output
CLK Rise or Fall Time
Clock to WAIT Valid
CLK HIGH or LOW Time
Setup Time to Activate CLK Edge
tCBPH
Min
CEM
CEW
tCLK
t
CSP
t
HD
t
HZ
tKHKL
tKHTL
tKP
tSP
Max
5
t
t
-706/-856
1
12.5
4.5
2
Min
5
8
7.5
20
20
1
15
5
2
8
1.8
9
4
3
Max
8
7.5
20
20
8
2.0
11
5
3
Units
Notes
ns
1
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
3
Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Timing Diagrams
Figure 26:
Initialization Period
Vcc (MIN)
Vcc, VccQ = 1.70V
Table 18:
tPU
Device ready for
normal operation
Initialization Timing Parameters
-70x
Parameter
Symbol
Initialization Period (required before normal operations)
tPU
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
37
Min
-856
Max
150
Min
Max
Units
150
µs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 27:
Asynchronous READ
tRC
VIH
A[21:0]
VALID ADDRESS
VIL
tAA
ADV#
VIH
VIL
tHZ
CE#
VIH
VIL
LB#/UB#
tCO
tBA
VIH
tBHZ
VIL
tOE
OE#
WE#
tOHZ
VIH
VIL
VIH
VIL
tBLZ
tOLZ
tLZ
VOH
DQ[15:0]
High-Z
VOL
VALID OUTPUT
tCEW
tHZ
VIH
WAIT
High-Z
VIL
High-Z
DON’T CARE
Table 19:
Asynchronous READ Timing Parameters
-70x
Symbol
Min
tAA
t
BHZ
BLZ
tCEW
tCO
-856
Max
Min
70
70
8
tBA
t
UNDEFINED
10
1
7.5
70
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
-70x
Max
85
85
8
10
1
7.5
85
Units
Symbol
Min
tHZ
ns
ns
ns
ns
ns
ns
tLZ
Min
8
5
70
Max
Units
8
ns
ns
ns
ns
ns
ns
10
20
8
t
38
Max
10
t
OE
OHZ
tOLZ
tRC
-856
20
8
5
85
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 28:
Asynchronous READ Using ADV#
A[21:0]
VIH
VALID ADDRESS
VIL
tAA
tAVS
tVPH
tAVH
VIH
ADV#
VIL
tAADV
tVP
tCVS
tHZ
VIH
CE#
VIL
tCO
tBA
tBHZ
VIH
LB#/UB#
VIL
tOE
tOHZ
VIH
OE#
VIL
VIH
WE#
tOLZ
tBLZ
VIL
tLZ
DQ[15:0]
VOH
High-Z
VALID OUTPUT
VOL
tCEW
WAIT
tHZ
VIH
High-Z
VIL
High-Z
DON’T CARE
Table 20:
Asynchronous READ Timing Parameters Using ADV#
-70x
Symbol
t
Min
tAVS
Max
5
10
t
BA
t
BHZ
tBLZ
tCEW
tCO
-856
Min
70
70
AA
tAADV
tAVH
UNDEFINED
Max
85
85
5
10
70
8
10
1
-70x
7.5
70
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
85
8
10
1
7.5
85
Units
Symbol
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
CVS
Min
8
10
20
8
5
10
10
Max
10
10
t
39
Min
8
tOE
OHZ
t
OLZ
tVP
tVPH
Max
10
tHZ
tLZ
-856
20
8
5
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 29:
Page Mode READ
tRC
A[21:4]
VIH
VALID ADDRESS
VIL
VIH
A[3:0]
ADV#
VALID ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
tPC
tAA
VIH
VALID
ADDRESS
VIL
tCEM
tCO
VIH
tHZ
CE# VIL
LB#/UB#
tBA
VIH
tBHZ
VIL
tOHZ
tOE
VIH
OE#
VIL
VIH
WE#
tOLZ
tBLZ
VIL
VOH
DQ[15:0]
tAPA
tOH
tLZ
VALID
OUTPUT
High-Z
VOL
VALID
OUTPUT
tCEW
VALID
OUTPUT
tHZ
VIH
WAIT
VALID
OUTPUT
High-Z
VIL
High-Z
DON’T CARE
Table 21:
Asynchronous READ Timing Parameters – Page Mode Operation
-70x
Symbol
Min
tAA
-856
Max
Min
70
20
70
8
tAPA
t
BA
t
BHZ
tBLZ
tCEM
tCEW
t
CO
UNDEFINED
10
1
-70x
Max
85
25
85
8
10
8
7.5
70
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
1
8
7.5
85
Units
Symbol
Min
tHZ
ns
ns
ns
ns
ns
µs
ns
ns
tLZ
OE
OH
tOHZ
tOLZ
tPC
t
RC
40
Max
Min
8
10
t
t
-856
Units
8
ns
ns
ns
ns
ns
ns
ns
ns
10
20
5
20
5
8
5
20
70
Max
8
5
25
85
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 30:
Single-Access Burst READ Operation
tCLK
tKP
tKP
tKHKL
VIH
CLK
VIL
tSP
VIH
A[21:0]
VALID
ADDRESS
VIL
tSP
VIH
ADV#
tHD
tHD
VIL
tHD
tCEM
CE#
tCSP
VIH
tHZ
tABA
VIL
tBOE
tOHZ
VIH
OE#
VIL
tSP
tHD
tOLZ
VIH
WE#
VIL
tSP
tHD
VIH
LB#/UB#
VIL
tCEW
VOH
WAIT
tKHTL
High-Z
High-Z
VOL
DQ[15:0]
tKOH
tACLK
VOH
VALID
OUTPUT
High-Z
VOL
READ Burst Identified
(WE# = HIGH)
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for single-access burst READ operation: Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 22:
Burst READ Timing Parameters – Single Access
-708
Symbol
Min
tABA
tACLK
tBOE
t
CEM
t
CEW
tCLK
t
CSP
tHD
1
12.5
4.5
2
Max
46.5
9
20
8
7.5
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
-706/-856
Min
1
15
5
2
Max
56
11
20
8
7.5
20
20
-708
Units
Symbol
Min
tHZ
ns
ns
ns
µs
ns
ns
ns
ns
tKHTL
KOH
KP
tOHZ
t
OLZ
tSP
t
41
Max
Min
8
1.8
9
tKHKL
t
-706/-856
2
4
Units
8
2.0
11
ns
ns
ns
ns
ns
ns
ns
ns
2
5
8
5
3
Max
8
5
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 31:
4-Word Burst READ Operation
tKHKL
CLK
A[21:0]
tKP
VIL
tSP
VIH
tHD
VALID
ADDRESS
VIL
tSP
ADV#
tKP
tCLK
VIH
tHD
VIH
VIL
tCEM
CE#
VIH
tHD
tABA
tCSP
VIL
tCBPH
tHZ
tBOE
OE#
WE#
LB#/UB#
VIH
VIL
tOHZ
tSP
tHD
tSP
tHD
tOLZ
VIH
VIL
VIH
VIL
tKHTL
tCEW
WAIT
VOH
High-Z
VOL
High-Z
tACLK
DQ[15:0]
VOH
VALID
OUTPUT
High-Z
VOL
tKOH
VALID
OUTPUT
VALID
OUTPUT
READ Burst Identified
(WE# = HIGH)
VALID
OUTPUT
UNDEFINED
DON’T CARE
Notes: 1. Non-default BCR settings for 4-word burst READ operation: Latency code two (three
clocks); WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 23:
Burst READ Timing Parameters – 4-Word Burst
-708
Symbol
Min
t
ABA
tACLK
tBOE
tCBPH
t
CEM
t
CEW
tCLK
tCSP
tHD
-706/-856
Max
Min
46.5
9
20
5
1
12.5
4.5
2
Max
Units
56
11
20
ns
ns
ns
ns
µs
ns
ns
ns
ns
5
8
7.5
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
1
15
5
2
-708
8
7.5
20
20
Symbol
Min
t
HZ
tKHKL
tKHTL
tKOH
t
KP
t
OHZ
tOLZ
tSP
42
-706/-856
Max
Min
8
1.8
9
2
4
Units
8
2.0
11
ns
ns
ns
ns
ns
ns
ns
ns
2
5
8
5
3
Max
8
5
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 32:
4-Word Burst READ Operation (with LB#/UB#)
tCLK
CLK
A[21:0]
VIH
VIL
tHD
tSP
VIH
VALID
ADDRESS
VIL
tSP
ADV#
tHD
VIH
VIL
tCEM
CE#
VIH
tHD
tABA
tCSP
VIL
tCBPH
tHZ
tBOE
OE#
WE#
LB#/UB#
VIH
VIL
tOHZ
tSP
tHD
tSP
tHD
tOLZ
VIH
VIL
VIH
VIL
tCEW
WAIT
tKHTL
VOH
High-Z
VOL
High-Z
tKOH
tACLK
DQ[15:0]
VOH
VALID
OUTPUT
High-Z
VOL
tKHZ
tKHZ
tKLZ
VALID
OUTPUT
High-Z
READ Burst Identified
(WE# = HIGH)
VALID
OUTPUT
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for 4-word burst READ operation with LB#/UB#: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met. BCR
configured with a burst length of four.
Table 24:
Burst READ Timing Parameters – 4-Word Burst with LB#/UB#
-708
Symbol
Min
tABA
t
BOE
CBPH
tCEM
tCEW
tCLK
t
CSP
tHD
Max
Min
46.5
9
20
tACLK
t
-706/-856
5
1
12.5
4.5
2
Max
Units
56
11
20
ns
ns
ns
ns
µs
ns
ns
ns
ns
5
8
7.5
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
1
15
5
2
-708
8
7.5
20
20
Symbol
Min
tHZ
tKHTL
t
KHZ
KLZ
tKOH
tOHZ
tOLZ
t
SP
t
43
3
2
2
-706/-856
Max
8
9
8
5
Min
3
2
2
8
5
3
Max
Units
8
11
8
5
ns
ns
ns
ns
ns
ns
ns
ns
8
5
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 33:
READ Burst Suspend
tCLK
VIH
CLK VIL
tSP
VIH
tHD
VALID
ADDRESS
VALID
ADDRESS
A[21:0] VIL
tSP
tHD
VIH
ADV# VIL
tCEM
tCBPH
tHZ
tCSP
VIH
CE# VIL
tOHZ
tOHZ
VIH
OE#
VIL
tSP
VIH
tHD
WE# VIL
tSP tHD
VIH
LB#/UB# VIL
tBOE
VOH
tOLZ
WAIT VOL High-Z
High-Z
tKOH
VOH
DQ[15:0] VOL
VALID
OUTPUT
High-Z
tBOE
tOLZ
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tACLK
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for READ burst suspend: Latency code two (three clocks); WAIT
active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 25:
Burst READ Timing Parameters – Burst Suspend
-708
Symbol
Min
tACLK
5
tCEM
t
CLK
tCSP
Max
Min
9
20
tBOE
tCBPH
-706/-856
12.5
4.5
Max
11
20
5
8
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
15
5
8
20
20
-708
Units
Symbol
tHD
ns
ns
ns
µs
ns
ns
Min
8
2
8
5
3
Max
2
2
tOHZ
44
Min
8
tKOH
OLZ
tSP
Max
2
tHZ
t
-706/-856
8
5
3
Units
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 34:
CLK
Continuous Burst READ Showing an Output Delay with BCR[8] = 0 for End-of-Row
Condition
VIH
VIL
tCLK
A[21:0]
VIH
VIL
ADV#
VIH
VIL
LB#/UB#
VIH
VIL
CE#
VIH
NOTE 4
VIL
OE#
VIH
VIL
WE#
VIH
VIL
tKHTL
tKHTL
WAIT
VOH
NOTE 3
VOL
DQ[15:0]
VOH
VALID
OUTPUT
VALID
OUTPUT
VOL
VALID
OUTPUT
VALID
OUTPUT
tKOH
tACLK
DON’T CARE
Notes: 1. Non-default BCR settings for continuous burst READ, showing an output delay, with
BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
3. WAIT will be asserted a maximum of (2 x LC) cycles (BCR[8] = 0; WAIT asserted during
delay). LC = Latency Code (BCR[13:11]).
4. CE# must not remain LOW longer than tCEM.
Table 26:
Burst READ Timing Parameters – BCR[8] = 0
-708
Symbol
t
t
ACLK
CLK
Min
12.5
-706/-856
Max
9
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
15
Max
11
20
-708
Units
Symbol
t
ns
ns
t
45
KHTL
KOH
Min
-706/-856
Max
Min
9
2
2
Max
Units
11
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 35:
CE#-Controlled Asynchronous WRITE
tWC
A[21:0]
VIH
VALID ADDRESS
VIL
tAW
tWR
tAS
VIH
ADV#
VIL
tCW
CE#
tCPH
VIH
VIL
tBW
VIH
LB#/UB#
OE#
VIL
VIH
VIL
tWPH
tWP
VIH
WE#
VIL
tDH
tDW
DQ[15:0]
IN
VIH
DQ[15:0]
OUT
VOH
High-Z
VIL
tWHZ
tLZ
WAIT
VALID INPUT
VOL
tCEW
VIH
tHZ
High-Z
VIL
High-Z
DON’T CARE
Table 27:
Asynchronous WRITE Timing Parameters – CE#-Controlled
-70x
Symbol
tAS
tAW
tBW
t
CEW
tCPH
tCW
tDH
tDW
Min
0
70
70
1
5
70
0
23
-856
Max
7.5
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
0
85
85
1
5
85
0
23
-70x
Max
7.5
Units
Symbol
νσ
ns
ns
ns
ns
ns
ns
ns
Min
tHZ
10
70
tWC
tWPH
46
Min
46
10
0
Max
Units
8
ns
ns
ns
ns
ns
ns
ns
10
85
8
WHZ
tWP
tWR
Max
8
tLZ
t
-856
8
55
10
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 36:
LB#/UB#-Controlled Asynchronous WRITE
tWC
A[21:0]
VIH
VALID ADDRESS
VIL
tAW
tAS
ADV#
tWR
VIH
VIL
tCW
CE#
LB#/UB#
OE#
VIH
VIL
tBW
VIH
VIL
VIH
VIL
tWP
tWPH
VIH
WE#
VIL
tDW
DQ[15:0]
IN
VIH
DQ[15:0]
OUT
VOH
High-Z
VIL
VALID INPUT
tWHZ
tLZ
VOL
tCEW
WAIT
tDH
tHZ
VIH
High-Z
VIL
High-Z
DON’T CARE
Table 28:
Asynchronous WRITE Timing Parameters – LB#/UB#-Controlled
-70x
Symbol
t
AS
tAW
tBW
tCEW
t
CW
tDH
tDW
Min
0
70
70
1
70
0
23
-856
Max
7.5
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
0
85
85
1
85
0
23
-70x
Max
7.5
Units
Symbol
t
ns
ns
ns
ns
ns
ns
ns
Min
10
70
tWC
tWHZ
WP
tWPH
tWR
47
Max
Min
8
HZ
tLZ
t
-856
Units
8
ns
ns
ns
ns
ns
ns
ns
10
85
8
46
10
0
Max
8
55
10
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 37:
WE#-Controlled Asynchronous WRITE
tWC
VIH
A[21:0]
VALID ADDRESS
VIL
tAW
tWR
VIH
ADV#
VIL
tCW
VIH
CE#
VIL
tBW
VIH
LB#/UB#
VIL
VIH
OE#
VIL
tAS
tWP
tWPH
VIH
WE#
VIL
tDH
tDW
DQ[15:0]
IN
VIH
High-Z
VIL
tOW
tWHZ
tLZ
DQ[15:0]
OUT
VALID INPUT
VOH
VOL
tCEW
tHZ
VIH
WAIT
High-Z
VIL
High-Z
DON’T CARE
Table 29:
Asynchronous WRITE Timing Parameters – WE#-Controlled
-70x
Symbol
tAS
tAW
tBW
t
CEW
t
CW
tDH
tDW
tHZ
Min
0
70
70
1
70
0
23
-856
Max
Min
7.5
0
85
85
1
85
0
23
8
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
-70x
Max
7.5
8
Units
Symbol
tLZ
ns
ns
ns
ns
ns
ns
ns
ns
Min
tWC
t
WHZ
WP
tWPH
tWR
48
Max
10
5
70
tOW
t
-856
Min
8
46
10
0
Max
Units
8
ns
ns
ns
ns
ns
ns
ns
10
5
85
55
10
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 38:
Asynchronous WRITE Using ADV#
A[21:0]
VIH
VALID ADDRESS
VIL
tAVS
tVS
tVPH
ADV#
tAVH
tVP
tAS
VIH
VIL
tAS
tAW
tCW
VIH
CE#
VIL
tBW
VIH
LB#/UB#
OE#
VIL
VIH
VIL
tWPH
tWP
WE#
VIH
VIL
tDW
DQ[15:0] VIH
IN VIL
DQ[15:0] VOH
OUT VOL
High-Z
VALID INPUT
tWHZ
tLZ
tOW
tCEW
WAIT
tDH
tHZ
VIH
High-Z
VIL
High-Z
DON’T CARE
Table 30:
Asynchronous WRITE Timing Parameters Using ADV#
-70x
Symbol
tAS
tAVH
t
AVS
AW
tBW
tCEW
tCW
tDH
t
DW
t
Min
0
5
10
70
70
1
70
0
23
-856
Max
7.5
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
0
5
10
85
85
1
85
0
23
-70x
Max
7.5
Units
Symbol
Min
tHZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
OW
VP
tVPH
tVS
tWHZ
tWP
t
WPH
t
49
Max
Min
8
tLZ
t
-856
10
5
10
10
70
Units
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
10
10
85
8
46
10
Max
8
55
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 39:
Burst WRITE Operation
tCLK
CLK
tKP
tKP
tKHKL
VIH
VIL
tSP
A[21:0]
VALID
ADDRESS
VIL
ADV#
tHD
VIH
tSP
VIH
tHD
VIL
LB#/UB#
tSP tHD
VIH
VIL
tHD
tCSP
CE#
tCBPH
tCEM
VIH
VIL
OE#
VIH
VIL
tSP
WE#
tHD
VIH
VIL
tKHTL
tCEW
VOH
WAIT
tHZ
High-Z
VOL
High-Z
tHD
tSP
VIH
DQ[15:0]
D[0]
VIL
D[1]
D[2]
D[3]
WRITE Burst Identified
(WE# = LOW)
DON’T CARE
Notes: 1. Non-default BCR settings for burst WRITE operation: Latency code two (three clocks);
WAIT active LOW; WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 31:
Burst WRITE Timing Parameters
-708
Symbol
t
CBPH
tCEM
tCEW
tCLK
t
CSP
t
HD
Min
-706/-856
Max
5
1
12.5
4.5
2
Min
Max
Units
8
7.5
20
20
ns
µs
ns
ns
ns
ns
5
8
7.5
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
1
15
5
2
-708
Symbol
Min
t
HZ
tKHKL
tKHTL
tKP
t
SP
50
-706/-856
Max
Min
8
1.8
9
4
3
5
3
Max
Units
8
2.0
11
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 40:
CLK
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row
Condition
VIH
VIL
tCLK
A[21:0]
VIH
VIL
ADV#
VIH
VIL
LB#/UB#
VIH
VIL
CE#
VIH
NOTE 4
VIL
VIH
WE#
VIL
VIH
OE#
VIL
tKHTL
tKHTL
WAIT
VOH
NOTE 3
VOL
tSP
VIH
DQ[15:0]
tHD
VALID
INPUT D[n]
VIL
VALID
INPUT D[n+1]
END OF ROW
VALID
INPUT D[n+2]
START OF ROW
(NOTE 4)
VALID
INPUT D[n+3]
DON’T CARE
Notes: 1. Non-default BCR settings for continuous burst WRITE, showing an output delay, with
BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
2. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
3. WAIT will be asserted a maximum of (2 x LC) + 1 cycles (BCR[8] = 0; WAIT asserted during
delay). LC = Latency Code (BCR[13:11]).
4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write
the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that
the start-of-row data is input just before (as shown) or just after WAIT asserts. This difference in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to
abort on the start-of-row input cycle.
Table 32:
Burst WRITE Timing Parameters – BCR[8] = 0
-708
Symbol
tCLK
t
HD
Min
12.5
2
-706/-856
Max
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
15
2
Max
20
-708
Units
Symbol
Min
tKHTL
ns
ns
t
51
SP
-706/-856
Max
Min
9
3
3
Max
Units
11
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 41:
Burst WRITE Followed by Burst READ
tCLK
CLK
VIH
VIL
A[21:0]
VIH
VIL
ADV#
VIH
VIL
tSP
tSP tHD
LB#/UB#
VALID
ADDRESS
tSP tHD
tSP tHD
tSP tHD
VIH
VIL
tCSP
CE#
OE#
WE#
WAIT
tHD
VALID
ADDRESS
tHD
VIH
VIL
tCBPH2
tABA
tCSP
VIH
VIL
tOHZ
tSP tHD
VIH
VIL
tSP tHD
VOH
VOL
tBOE
High-Z
tSP tHD
DQ[15:0] VIH
IN/OUT VIL
VOH
High-Z
D[0]
D[1]
D[2]
D[3]
VOL
High-Z
tKOH
tACLK
VALID
OUTPUT
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for burst WRITE followed by burst READ: Latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay.
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 33:
WRITE Timing Parameters – Burst WRITE Followed by Burst READ
-708
Symbol
Min
tCBPH
5
12.5
4.5
t
t
CLK
CSP
Table 34:
-706/-856
Max
Min
20
20
5
15
5
Min
t
ABA
ACLK
tBOE
tCLK
tCSP
Max
Units
20
20
ns
ns
ns
Symbol
tHD
t
Min
-706/-856
Max
2
3
SP
Min
Max
2
3
Units
ns
ns
READ Timing Parameters – Burst WRITE Followed by Burst READ
-708
Symbol
-708
t
12.5
4.5
Max
46.5
9
20
20
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
-706/-856
Min
15
5
Max
56
11
20
20
20
-708
Units
Symbol
t
ns
ns
ns
ns
ns
HD
KOH
tOHZ
tSP
t
52
Min
-706/-856
Max
2
2
Min
2
2
8
3
Max
8
3
Units
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 42:
Asynchronous WRITE Followed by Burst READ
tCLK
VIH
CLK VIL
VIH
VIL
A[21:0]
VIH
ADV#
VIL
tWC
VALID ADDRESS
tAVS
tAW
tWR
tSP
tVP
tCVS
VIH
tVS
tBW
tHD
tSP tHD
tCBPH2
tCW
VIH
VIL
tHD
VALID
ADDRESS
tVPH
LB#/UB# VIL
CE#
tAVH
tSP
tCKA
tWC
VALID ADDRESS
tABA
tCSP
tOHZ
tAS
VIH
OE# VIL
tWC
tAS
VIH
tWP
tSP tHD
tWPH
WE# VIL
tCEW
VOH
VOL
WAIT
tBOE
tWHZ
DQ[15:0] VIH
IN/OUT VIL
High-Z
VOH
DATA
DATA
tDH
VOL
tDW
High-Z
tKOH
tACLK
VALID
OUTPUT
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DON’T CARE
UNDEFINED
Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 35:
WRITE Timing Parameters – Async WRITE Followed by Burst READ
-70x
Symbol
tAS
tAVH
tAVS
tAW
tBW
tCKA
t
CVS
tCW
tDH
Table 36:
Min
-856
Max
0
5
10
70
70
70
10
70
0
Min
ACLK
tCEW
tCLK
Symbol
tDW
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
20
10
10
70
70
tVP
tVPH
tVS
tWC
t
WP
tWPH
tWR
Min
Max
23
10
10
85
85
tWHZ
8
46
10
0
-706/-856
Max
Min
46.5
9
20
tBOE
tCBPH
Units
-856
8
55
10
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ Timing Parameters – Async WRITE Followed by Burst READ
tABA
t
Max
0
5
10
85
85
85
10
85
0
-708
Symbol
Min
-70x
5
1
12.5
7.5
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
5
1
15
-708
Max
Units
56
11
20
ns
ns
ns
ns
ns
ns
7.5
20
Symbol
tCSP
t
HD
tKOH
Min
Max
Min
Max
Units
4.5
2
2
20
5
2
2
20
ns
ns
ns
ns
ns
tOHZ
tSP
53
-706/-856
8
3
8
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 43:
Asynchronous WRITE Followed By Burst READ – ADV# LOW
CLK
VIH
VIL
A[21:0]
VIH
VIL
ADV#
VIH
VIL
tCLK
tWC
LB#/UB#
CE#
OE#
WE#
WAIT
VALID ADDRESS
tSP
tCKA
tHD
VALID
ADDRESS
VALID ADDRESS
tWR
tAW
tSP
tBW
VIH
tHD
tSP tHD
VIL
tCBPH2
tCW
VIH
tCSP
tABA
VIL
tOHZ
VIH
tWC
tWPH
VIL
tWP
VIH
tSP tHD
VIL
VOH
tCEW
tBOE
tWHZ
VIL
High-Z
DATA
tDH
VOH
DATA
VOL
tDW
High-Z
tKOH
VOL
VIH
DQ[15:0]
IN/OUT
tWC
tACLK
VALID
OUTPUT
High-Z
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
UNDEFINED
DON’T CARE
Notes: 1. Non-default BCR settings for asynchronous WRITE followed by burst READ—ADV# LOW:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
Table 37:
Asynchronous WRITE Timing Parameters – ADV# LOW
-70x
Symbol
t
AW
tBW
tCKA
tCW
t
t
DH
DW
Table 38:
Min
-856
Max
70
70
70
70
0
23
Min
ACLK
tCEW
tCLK
Symbol
t
ns
ns
ns
ns
ns
ns
Min
Max
70
WC
tWP
tWPH
t
WR
Min
Max
85
tWHZ
8
46
10
0
-706/-856
Max
Min
46.5
9
20
tBOE
tCBPH
Units
-856
8
55
10
0
Units
ns
ns
ns
ns
ns
Burst READ Timing Parameters
tABA
t
Max
85
85
85
85
0
23
-708
Symbol
Min
-70x
5
1
12.5
7.5
20
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
5
1
15
-708
Max
Units
56
11
20
ns
ns
ns
ns
ns
ns
7.5
20
Symbol
tCSP
t
HD
tKOH
Min
Max
Min
Max
Units
4.5
2
2
20
5
2
2
20
ns
ns
ns
ns
ns
tOHZ
tSP
54
-706/-856
8
3
8
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 44:
Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
tCLK
VIH
CLK
A[21:0]
VIL
tSP
VIH
VIL
tSP
VIH
ADV#
CE#
tWC
tHD
VALID
ADDRESS
VALID
ADDRESS
VIL
tHD
tCSP
VIH
tCW
tCBPH1
VIL
tBOE
tOHZ
tAS
VIL
tSP
WE#
tHZ
tABA
VIH
OE#
tWR
tAW
tHD
tHD
tOLZ
tWP
tWPH
VIH
VIL
tSP
VIH
tHD
tBW
LB#/UB#
VIL
tCEW
tKHTL
tCEW
tHZ
VOH
WAIT
High-Z
High-Z
VOL
DQ[15:0]
tKOH
tACLK
VOH
VALID
INPUT
VALID
OUTPUT
High-Z
VOL
tDH
tDW
READ Burst Identified
(WE# = HIGH)
DON’T CARE
UNDEFINED
Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
Table 39:
Burst READ Timing Parameters
-708
Symbol
Min
tABA
t
Table 40:
Max
Min
5
1
12.5
4.5
7.5
20
20
t
AS
tAW
tBW
tCW
tDH
t
DW
Units
56
11
20
ns
ns
ns
ns
ns
ns
ns
5
1
15
5
7.5
20
20
Symbol
tHD
Min
-706/-856
Max
2
Max
2
tHZ
8
9
t
KHTL
t
KOH
tOHZ
tSP
Min
2
8
11
2
8
3
8
3
Units
ns
ns
ns
ns
ns
ns
Asynchronous WRITE Timing Parameters – WE#-Controlled
-70x
Symbol
-708
Max
46.5
9
20
tACLK
BOE
t
CBPH
tCEW
tCLK
tCSP
-706/-856
Min
Max
0
70
70
70
0
23
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
-856
Min
85
85
85
0
23
-70x
Max
Units
0
ns
ns
ns
ns
ns
ns
Symbol
Min
t
HZ
tWC
tWP
tWPH
tWR
55
-856
Max
Min
8
70
46
10
0
85
55
10
0
Max
Units
8
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 45:
CLK
A[21:0]
Burst READ Followed by Asynchronous WRITE Using ADV#
tCLK
VIH
VIL
VIH
tSP
VIL
tSP
VIH
ADV#
CE#
tHD
VALID
ADDRESS
VALID
ADDRESS
tVPH
tHD
WE#
tAVH
tVS
tVP
VIL
tCSP
VIH
tAW
tHD
tABA
tAS
tHZ
tCW
tCBPH1
VIL
tOHZ
tBOE
VIH
OE#
tAVS
VIL
tSP
VIH
tHD
tAS
tOLZ
tWP
tWPH
VIL
tSP
VIH
tHD
tBW
LB#/UB#
VIL
tCEW
tKHTL
tCEW
tHZ
VOH
WAIT
High-Z
VOL
High-Z
tACLK
DQ[15:0]
VOH
tDH
tDW
VALID
INPUT
VALID
OUTPUT
High-Z
VOL
tKOH
READ Burst Identified
(WE# = HIGH)
DON’T CARE
UNDEFINED
Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns. Note that CellularRAM
Working Group 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
Table 41:
Burst READ Timing Parameters
-708
Symbol
Min
tABA
tBOE
tCEW
tCLK
t
CSP
Table 42:
Max
Min
5
1
12.5
4.5
7.5
20
20
56
11
20
5
1
15
5
tAS
t
AVH
t
AVS
tAW
tBW
tCEW
t
CW
tDH
7.5
20
20
-708
Units
Symbol
tHD
ns
ns
ns
ns
ns
ns
ns
Min
-706/-856
Max
2
8
9
tKHTL
2
8
11
2
tOHZ
tSP
Max
2
tHZ
tKOH
Min
8
3
8
3
Units
ns
ns
ns
ns
ns
ns
Asynchronous WRITE Timing Parameters Using ADV#
-70x
Symbol
Max
46.5
9
20
tACLK
tCBPH
-706/-856
Min
0
5
10
70
70
1
70
0
-856
Max
7.5
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Min
0
5
10
85
85
1
85
0
-70x
Max
7.5
Units
Symbol
tDW
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
23
t
HZ
t
VP
tVPH
tVS
tWP
t
WPH
56
-856
Min
23
8
10
10
70
46
10
Max
8
10
10
85
55
10
Units
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 46:
A[21:0]
Asynchronous WRITE Followed by Asynchronous READ – ADV# LOW
VIH
VALID ADDRESS
VIL
VALID ADDRESS
VALID ADDRESS
tAA
tWR
tAW
VIH
ADV#
LB#/UB#
VIL
VIL
tCW
CE#
tBHZ
tBLZ
tBW
VIH
tCPH1
tCO
tHZ
VIH
VIL
tOHZ
tLZ
OE#
tOE
VIH
VIL
tWC
tWPH
tWP
WE#
WAIT
VIH
VIL
tHZ
tHZ
VOH
VOL
DQ[15:0] VIH
IN/OUT VIL
tWHZ
High-Z
tOLZ
DATA
VOH
High-Z
DATA
tDW
tDH
VALID
OUTPUT
VOL
UNDEFINED
DON’T CARE
Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only
required after CE#-controlled WRITEs.
Table 43:
WRITE Timing Parameters – ADV# LOW
-70x
Symbol
tAW
tBW
tCPH
t
CW
tDH
tDW
Table 44:
Min
-856
Max
70
70
5
70
0
23
Min
Min
Symbol
Min
Max
tHZ
ns
ns
ns
ns
ns
ns
Min
Max
Units
8
ns
ns
ns
ns
ns
ns
8
tWC
70
85
tWHZ
t
WP
tWPH
tWR
8
46
10
0
-856
Max
Min
70
8
t
BHZ
BLZ
tCO
tHZ
Units
-856
8
55
10
0
READ Timing Parameters – ADV# LOW
tAA
t
Max
85
85
5
85
0
23
-70x
Symbol
-70x
10
-70x
Max
Units
85
8
ns
ns
ns
νσ
ns
10
70
8
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
85
8
Symbol
tLZ
Min
t
57
Max
10
t
OE
OHZ
tOLZ
-856
5
Min
Max
Units
20
8
ns
ns
ns
ns
10
20
8
8
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 47:
Asynchronous WRITE Followed by Asynchronous READ
A[21:0]
VIH
VALID ADDRESS
VIL
ADV#
LB#/UB#
CE#
tAVS
tVPH
VIH
VALID ADDRESS
tAVH
VALID ADDRESS
tAA
tWR
tAW
tAVS
tVS
tVP
tVP
VIL
VIH
VIL
tCW
VIH
tCPH1
tCVS
WE#
WAIT
tHZ
tCO
VIL
tLZ
tAS
OE#
tBHZ
tAADV
tBLZ
tBW
tCVS
tAVH
tOHZ
VIH
VIL
tAS
VIH
tWC
tWPH
tWP
tOLZ
VIL
VOH
VOL
tOE
tWHZ
DQ[15:0] VIH
IN/OUT VIL
High-Z
DATA
VOH
DATA
VOL
tDW
tDH
VALID
OUTPUT
High-Z
DON’T CARE
UNDEFINED
Notes: 1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only
required after CE#-controlled WRITEs.
Table 45:
WRITE Timing Parameters – Async WRITE Followed by Async READ
-70x
Symbol
tAS
tAVH
tAVS
t
AW
tBW
tCBPH
tCVS
tCW
tDH
Table 46:
Min
-856
Max
0
5
10
70
70
5
10
70
0
Min
Units
Symbol
tDW
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
-856
Max
23
10
10
70
70
tVP
tVPH
t
VS
tWC
tWPH
tWR
Max
23
10
10
85
85
tWHZ
tWP
Min
8
46
10
0
8
55
10
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ Timing Parameters – Async WRITE Followed by Async READ
Min
tAA
-856
Max
Min
70
70
t
AADV
tAVH
tAVS
tBHZ
tBLZ
t
CO
Max
0
5
10
85
85
5
10
85
0
-70x
Symbol
-70x
5
10
-70x
Max
85
85
5
10
8
10
8
10
70
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
85
Units
Symbol
tCVS
ns
ns
ns
ns
ns
ns
νs
Min
58
Max
10
t
HZ
tLZ
tOE
tOHZ
tOLZ
t
VP
-856
Min
10
8
10
8
10
20
8
5
10
Max
20
8
5
10
Units
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 48:
54-Ball VFBGA
0.70 ±0.05
SEATING PLANE
C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag or
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø0.30 SOLDER MASK DEFINED
SUBSTRATE MATERIAL: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
0.10 C
54X Ø0.37
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-REFLOW
DIAMETER IS Ø0.35.
3.75
0.75
TYP
BALL A1 ID
BALL A1 ID
4.00 ±0.05
BALL A6
BALL A1
8.00 ±0.10
6.00
3.00
0.75 TYP
1.875
3.00 ±0.05
1.00 MAX
6.00 ±0.10
Notes: 1. All dimensions in millimeters; MAX/MIN, or typical, as noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron
Technology, Inc., inside the U.S. and a trademark of Infineon Technologies outside the U.S.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Revision History
Revision History
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/05
• Added new P25A-specific note on the first page.
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04/05
• Removed 60ns and 104 MHz support.
• Clarified Note 2, clock state on page 7.
• Clarified data values in Figure 40 on page 51.
• Corrected typographic errors.
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/04
• Removed all references to 32Mb density.
• Added Table 9, Maximum Standby Currents for Applying PAR and TCR Settings, on
page 30.
• Added Table 10, Maximum Standby Currents for Applying PAR and TCR Settings –
Low-Power (L), on page 30.
• Added Figure 23, Typical Refresh Current vs. Temperature (Itcr), on page 31.
• Added “Maximum and Typical Standby Currents” on page 30.
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/04
• WE# LOW limited to tCEM for async WRITES.
• Last address changed by software access sequence.
• Noted software access third cycle must be CE#-controlled WRITE.
• Separated ICC3 for READ and WRITE.
• Moved tCPH to follow CE#-controlled async WRITE cycles only.
• CRE is “Don’t Care” during burst continue.
• Clarified TCR temperatures and setting in Table 9.
• Changed VccQ to 1.7V–3.3V.
• Changed wireless temperature range to -30°C.
• Noted input HIGH voltage not aligned with the workgroup specification of VCCQ - 0.4.
• Noted wireless temp exceeds the workgroup spec.
• Clarified WAIT assertion for continuous burst with output delay.
• Noted workgroup spec for burst termination compliance.
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04
• Added software access.
• CR WRITE diagram titles updated to reflect WRITEs followed by READ ARRAY operation.
• Added 80 MHz burst clock (-708).
• Changed PAR options to full, one-half, one-quarter, one-eight, or none.
• Corrected Table 17 typo.
• Added Note 3 to Fig. 34 and 40.
• Added tCO to Fig. 46 and Table 44.
• Clarified READ/WRITE operating currents.
• Added clarifying notes for required refresh opportunity for BCR[15], depending on
BCR setting.
• Changed tCEM MAX to 8.
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Revision History
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated ICC values and symbols.
Added ADV# timing parameters and tCO to Fig. 47 and Table 46.
Clarified CE# LOW time limited by refresh—must not stay LOW longer than tCEM.
Aligned tACLK, tKHTL, tABA, and tCSP with Workgroup values.
Added tCEM to Asynchronous WRITE, Page Mode READ Operation, and Burst Mode
Operation descriptions and timing diagrams.
Deleted Appendix A (extended timings and all references).
Added -708 timing specifications.
Added CIN and CIO MIN values.
Clarified burst latency at row-boundary crossings.
Replaced Abbreviated Component Marks with Part Numbering chart.
Added measurement time clarification to ISB and IPAR notes.
Changed tCBPH to tCPH for async–async transitions.
Corrected package nomenclature to VFBGA.
Clarified address A[4] and higher in page mode.
Clarified CRE in Figure 14.
Updated tKP to 4ns for the -708, and 5ns for -706 and -856 parts.
Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03
• Changed BCR[6] = 0 to “not supported,” and deleted all references to falling clock
edges.
• Clarified mixed-mode operation.
• 104MHz part now “contact factory.”
• Changed tHD MIN in all speed grades to 2.
• Prohibited DPD via software access sequence.
• Changed tCSP (MIN) to 5ns for -706 and -856 in all burst timing tables (18, 20, 25, 26,
27, 28, 34, 36, 37, 39, 41).
• Added “and ADV# LOW” to tAS in Async WRITE Timing Req. table; added tAS as
appropriate in Figures 34, 38, 41, 43, and corollary Tables 38, 44, 48.
• Added Note 6 to Tables 2 and 3 for Standby Mode, and clarified standby description
under Low-Power Operation.
• -701 latency code 2 (3 clocks) changed to 66 MHz (15.2ns).
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/03
• Added lead-free option.
• Differentiated standard and low-power standby and related annotation in/for figures
and tables.
• CLK in Tables 2 & 3 changed; can be either HIGH or LOW. Data and figures added to
cover software access to the configuration registers.
• L, V and -60 now “contact factory.”
• Added V & L options. Modified WAIT in bus operations. Indicated wrap factors.
• Added -706 part information where applicable.
• Removed tSP and tHD from CE# in Burst diagrams.
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Burst CellularRAM_2.fm - Rev. G 10/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.