RT8206A/B High-Efficiency, Main Power Supply Controllers for Notebook Computers General Description Features The RT8206A/B dual step-down, switch-mode powersupply (SMPS) controller generates logic-supply voltages in battery-powered systems. The RT8206A/B includes two pulse-width modulation (PWM) controllers fixed at 5V/ 3.3V or adjustable from 2V to 5.5V. An optional external charge pump can be monitored through SECFB (RT8206A). This device also features a linear regulator providing a fixed 5V output. The linear regulator provides up to 70mA output current with automatic linear-regulator bootstrapping to the BYP input. The RT8206A/B includes on-board power-up sequencing, the power-good outputs, internal soft-start, and internal soft-discharge output that prevents negative voltages on shutdown. z A constant on-time PWM control scheme operates without sense resistors and provides 100ns response to load transients while maintaining a relatively constant switching frequency. The unique ultrasonic mode maintains the switching frequency above 25kHz, which eliminates noise in audio applications. Other features include diodeemulation mode (DEM), which maximizes efficiency in light-load applications, and fixed-frequency PWM mode, which reduces RF interference in sensitive application. The RT8206A/B is available in the WQFN-32L 5x5 package. z z z z z z z z z z z z z z Wide Input Voltage Range 6V to 25V Dual Fixed 5V/3.3V Outputs or Adjustable from 2V to 5.5V, 1.5% Accuracy Secondary Feedback Input Maintains Charge Pump Voltage (RT8206A) Independent Enable and Power Good 5V Fixed LDO Output : 70mA 2V Reference Voltage ±1% : 50uA Constant ON-Time Control with 100ns Load Step Response Frequency Selectable via TON Setting RDS(ON) Current Sensing and Programmable Current Limit Selectable PWM, DEM or Ultrasonic Mode Internal Soft-Start with 5 Steps Current Limiting and Soft-Discharge High Efficiency Up to 97% 5mW Quiescent Power Dissipation Thermal Shutdown RoHS Compliant and Halogen Free Ordering Information RT8206 Package Type QW : WQFN-32L 5x5 (W-Type) Operating Temperature Range G : Green (Halogen Free with Commercial Standard) Applications z z Notebook and Sub-Notebook Computers 3-Cell and 4-Cell Li+ Battery-Powered Devices A : With SECFB B : Without SECFB Note : Richtek Green products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` DS8206A/B-03 December 2009 Suitable for use in SnPb or Pb-free soldering processes. www.richtek.com 1 RT8206A/B Pin Configurations 25 24 2 23 3 22 ENLDO NC VIN LDO NC 4 21 GND 5 BOOT2 LGATE2 PGND GND SECFB PVCC LGATE1 BOOT1 20 6 19 7 18 33 17 32 31 30 29 28 27 26 25 REF TON VCC 1 24 2 23 3 22 ENLDO NC VIN LDO NC 4 21 GND 5 20 6 19 7 18 33 17 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 BYP FB1 ILIM1 PGOOD1 EN1 UGATE1 PHASE1 BYP VOUT1 FB1 ILIM1 PGOOD1 EN1 UGATE1 PHASE1 8 VOUT1 8 PHASE2 PHASE2 26 UGATE2 UGATE2 27 EN2 EN2 28 PGOOD2 PGOOD2 29 SKIP SKIP 30 VOUT2 VOUT2 31 1 ILIM2 ILIM2 32 REF TON VCC FB2 FB2 (TOP VIEW) WQFN-32L 5x5 WQFN-32L 5x5 RT8206A RT8206B BOOT2 LGATE2 PGND GND NC PVCC LGATE1 BOOT1 Typical Application Circuit VIN 6V to 25V R14 3.9 C1 10µF RT8206A/B 6 VIN C18 0.1µF Q1 VOUT1 5V C3 220µF PHASE2 25 R3 0 17 LGATE2 23 18 LGATE1 9 C8 C9 1µF C7 0.1µF 3 VCC 0.1µF VOUT2 30 REF 1 PGOOD1 C11 0.1µF 20 SECFB/NC R12 39k R7 0 C16 1µF 11 FB1 32 FB2 ILIM2 19 PVCC SKIP 7 LDO VOUT2 3.3V C17 220µF R10 C14 C15 0.22µF R6 100k R13 100k PVCC PVCC 5V Enable ON 3.3V Enable OFF LDO Control 31 TON 2 GND C12 10µF L2 4.7µH Q4 13 EN1 14 EN2 27 C13 10µF R8 0 ILIM1 12 R11 200k C19 Q2 PGND 22 ENLDO 4 D4 CP R9 0 PGOOD2 28 D2 D3 BYP 10 VOUT1 C5 0.1µF D1 BOOT1 16 PHASE1 C4 C6 0.1µF 24 15 UGATE1 Q3 R5 BOOT2 R4 0 C2 0.1µF L1 6.8µH UGATE2 26 29 VIN R1 180k R2 180k Frequency Control PWM/DEM/Ultrasonic 21, Exposed Pad (33) C10 4.7µF Figure 1. Fixed Voltage Regulator www.richtek.com 2 DS8206A/B-03 December 2009 RT8206A/B VIN 6V to 25V R14 3.9 C1 10µF RT8206A/B 6 VIN C18 0.1µF R4 0 Q1 R3 0 C2 0.1µF L1 6.8µH VOUT1 5V C3 220µF R5 BOOT2 15 UGATE1 17 18 LGATE1 9 C4 D1 C6 0.1µF BYP C9 1µF 3 VCC C8 0.1µF C23 C20 0.1µF R15 15k R16 10k CP C19 20 SECFB/NC R12 39k 11 FB1 R7 0 C16 1µF C10 4.7µF 19 PVCC 7 LDO L2 4.7µH Q4 C17 220µF R10 R17 11.5k C15 0.22µF SKIP GND C22 C21 0.1µF PVCC PVCC ON 3.3V Enable OFF LDO Control VIN R1 180k R2 180k 31 29 R18 10k 5V Enable ILIM1 12 TON 2 R6 100k R13 100k PGOOD2 28 ILIM2 VOUT2 3.3V C14 13 ENLDO 4 R11 200k C11 0.1µF VOUT2 30 FB2 32 REF 1 C12 10µF R8 0 PGND 22 EN1 14 EN2 27 D4 C13 10µF Q2 LGATE2 23 PGOOD1 C7 0.1µF 24 R9 0 PHASE2 25 10 VOUT1 C5 0.1µF D2 D3 BOOT1 16 PHASE1 Q3 UGATE2 26 Frequency Control PWM/DEM/Ultrasonic 21, Exposed Pad (33) Figure 2. Adjustable Voltage Regulator DS8206A/B-03 December 2009 www.richtek.com 3 RT8206A/B Function Block Diagram TON SKIP BOOT1 BOOT2 UGATE1 UGATE2 PHASE1 PV CC PHASE2 PV CC SMPS1 PWM Buck Controller LGATE1 PGND SMPS2 PWM Buck Controller LGATE2 VOUT2 FB2 ILIM2 PGOOD2 VOUT1 FB1 ILIM1 PGOOD1 GND SW Threshold VCC PVCC ENLDO EN1 EN2 BYP Internal Logic LDO Power-On Sequence Clear Fault Latch Thermal Shutdown LDO REF REF VIN Function Block Diagram TON VIN UGATE On-Time Compute VOUT T ON Q 1-Shot R T OFF TRIG 1-Shot Q TRIG REF + + - Comp + - LGATE FB 1.1 x V REF Over-Voltage + Fault Latch - 0.7 x V REF + Under-Voltage V CC Blanking Time + - 0.9 x V REF PGOOD + ILIM - SS Time + 25kHz Detector Zero Detector + Current Limit - PHASE - SKIP PWM Controller (One Side) www.richtek.com 4 DS8206A/B-03 December 2009 RT8206A/B Functional Pin Description REF (Pin 1) VOUT1 (Pin 10) 2V Reference Output. Bypass to GND with a 0.22uF capacitor. REF can source up to 50uA for external loads. Loading REF degrades FBx and output accuracy according to the REF load-regulation error. SMPS1 Output Voltage-Sense Input. Connect this pin to the SMPS1 output. VOUT1 is an input to the Constant on-time-PWM one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode. TON (Pin 2) FB1 (Pin 11) Frequency Select Input. (VOUT1/VOUT2 switching frequency, respectively) : SMPS1 Feedback Input. Connect FB1 to VCC or GND for fixed 5V operation. Connect FB1 to a resistive voltagedivider from VOUT1 to GND to adjust output from 2V to 5.5V. TON = VCC, (200kHz / 250kHz) TON = REF, (300kHz / 375kHz) TON = GND, (400kHz / 500kHz) VCC (Pin 3) Analog Supply Voltage Input for the PWM Core. Bypass to GND with a 1uF ceramic capacitor ENLDO (Pin 4) LDO Enable Input. The REF/LDO is enabled if ENLDO is within logic high level and disable if ENLDO is less than the logic low level. NC (Pin 5, 8) No Internal Connection. VIN (Pin 6) Power-supply Input. VIN is used for the constant on-time PWM one shot circuits. VIN is also used to power the linear regulators. The linear regulators are powered by SMPS1 if VOUT1 is set greater than 4.66V and BYP is tied to VOUT1. Connect VIN to the battery input and bypass with a 1uF capacitor. LDO (Pin 7) Linear-Regulator Output. LDO can provide a total of 70mA external loads. The LDO regulates a fixed 5V output. When the BYP is within 5V switchover threshold, the internal regulator shuts down and the LDO output pin connects to BYP through a 1.5Ω switch. Bypass LDO output with a minimum of 4.7uF ceramic. BYP (Pin 9) BYP is the switchover source voltage input for the LDO. DS8206A/B-03 December 2009 ILIM1 (Pin 12) SMPS1 Current-Limit Adjustment. The GND − PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a 0.5V to 2V range. There is an internal 5uA current source from VCC to ILIM1. The logic current limit threshold is default to 100mV if ILIM1 is higher than (VCC − 1V). PGOOD1 (Pin 13) SMPS1 Power-Good Open-Drain Output. PGOOD1 is low when the SMPS1 output voltage is more than 7.5% below the normal regulation point or during soft-start. PGOOD1 is high impedance when the output is in regulation and the soft-start circuit has terminated. PGOOD1 is low in shutdown. EN1 (Pin 14) SMPS1 Enable Input. The SMPS1 will be enabled if EN1 is greater than the logic high level and disabled if EN1 is less than the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive EN1 below 0.8V to clear fault level and reset the fault latches. UGATE1 (Pin 15) High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1. PHASE1 (Pin 16) Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver. PHASE1 is the current-sense input for the SMPS1. www.richtek.com 5 RT8206A/B BOOT1 (Pin 17) PHASE2 (Pin 25) Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application circuits. Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver. PHASE2 is the current-sense input for the SMPS2. LGATE1 (Pin 18) UGATE2 (Pin 26) SMPS1 Synchronous-Rectifier Gate-drive Output. LGATE1 swings between PGND and PVCC. High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE2 swings between PHASE2 and BOOT2. PVCC (Pin 19) EN2 (Pin 27) PVCC is the supply voltage for the low-side MOSFET driver LGATEx. Connect a 5V power source to the PVCC pin (bypass with 1uF MLCC capacitor to PGND if necessary). There is an internal 10Ω connecting from PVCC to VCC. Make sure that both VCC and PVCC are bypassed with 1uF MLCC capacitors. SMPS2 Enable Input. The SMPS2 will be enabled if EN2 is greater than the logic high level and be disabled if EN2 is less than the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive EN2 below 0.8V to clear fault level and reset the fault latches. SECFB (Pin 20) (RT8206A) PGOOD2 (Pin 28) The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from the 14V charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 will be turned on for 300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage. SMPS2 Power-Good Open-Drain Output. PGOOD2 is low when the SMPS2 output voltage is more than 7.5% below the normal regulation point or during soft-start. PGOOD2 is high impedance when the output is in regulation and the soft-start circuit has terminated. PGOOD2 is low in shutdown. SKIP (Pin 29) NC (Pin 20) (RT8206B) SMPS Operation Mode Control. No Internal Connection. SKIP = GND : DEM operation GND [Pin 21, Exposed Pad (33)] SKIP = REF : Ultrasonic Mode operation Analog Ground for both SMPS and LDO. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. SKIP = VCC : PWM operation. VOUT2 (Pin 30) Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad. SMPS2 Output Voltage-Sense Input. Connect this pin to the SMPS2 output. VOUT2 is an input to the constant on-time-PWM one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode. LGATE2 (Pin 23) ILIM2 (Pin 31) SMPS2 Synchronous-Rectifier Gate-drive Output. LGATE2 swings between PGND and PVCC. SMPS2 Current-Limit Adjustment. The GND − PHASE2 current-limit threshold is 1/10th the voltage seen at ILIM2 over a 0.5V to 2V range. There is an internal 5uA current source from VCC to ILIM2. The logic current limit threshold is default to 100mV value if ILIM2 is higher than (VCC − 1V). PGND (Pin 22) BOOT2 (Pin 24) Boost Flying Capacitor Connection for SMPS2. Connect this pin to an external capacitor according to the typical application circuits. www.richtek.com 6 DS8206A/B-03 December 2009 RT8206A/B FB2 (Pin 32) SMPS2 Feedback Input. Connect FB2 to VCC or GND for fixed 3.3V operation. Connect FB2 to a resistive voltagedivider from VOUT2 to GND to adjust output from 2V to 5.5V. DS8206A/B-03 December 2009 www.richtek.com 7 RT8206A/B Absolute Maximum Ratings z z z z z z z z z z z z z z z (Note 1) VIN, ENLDO to GND ---------------------------------------------------------------------------------------------- –0.3V to 30V BOOTx to GND ----------------------------------------------------------------------------------------------------- –0.3V to 36V PHASEx to GND DC --------------------------------------------------------------------------------------------------------------------- –0.3V to 30V <20ns ---------------------------------------------------------------------------------------------------------------- –8V to 38V BOOTx to PHASEx ----------------------------------------------------------------------------------------------- –0.3V to 6V VCC, ENx, SKIP, TON, PVCC, PGOODx, to GND ------------------------------------------------------- –0.3V to 6V LDO, FBx, VOUTx, SECFB, REF, ILIMx to GND ---------------------------------------------------------- –0.3V to (VCC + 0.3V) UGATEx to PHASEx DC --------------------------------------------------------------------------------------------------------------------- –0.3V to (PVCC + 0.3V) <20ns ---------------------------------------------------------------------------------------------------------------- –5V to 7.5V LGATEx, BYP to GND DC --------------------------------------------------------------------------------------------------------------------- –0.3V to (PVCC + 0.3V) <20ns ---------------------------------------------------------------------------------------------------------------- –2.5V to 7.5V PGND to GND ------------------------------------------------------------------------------------------------------ –0.3V to 0.3V Power Dissipation, PD @ TA = 25°C WQFN-32L 5x5 ---------------------------------------------------------------------------------------------------- 2.778W Package Thermal Resistance (Note 4) WQFN-32L 5x5, θJA ----------------------------------------------------------------------------------------------- 36°C/W WQFN-32L 5x5, θJC ---------------------------------------------------------------------------------------------- 7°C/W Junction Temperature --------------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C Storage Temperature Range ------------------------------------------------------------------------------------ –65°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z (Note 3) Input Voltage, VIN ------------------------------------------------------------------------------------------------------ 6V to 25V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C www.richtek.com 8 DS8206A/B-03 December 2009 To be continued RT8206A/B Electrical Characteristics (VIN = 12V, EN1 = EN2 = VCC, VBYP = 5V, PVCC = 5V, VENLDO = 5V, No Load on LDO, VOUT1, VOUT2 and REF, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit -- 180 250 μA -- 20 40 μA -- 5 7 mW 4.975 5.05 5.125 V Input Supply VIN = 6V to 25V, Both SMPS Off, ENLDO = 5V V = 6V to 25V, VIN Shutdown Supply I VIN_SHDH IN Current ENx = ENLDO = GND Both SMPSs On, Quiescent Power FB1 = SKIP = GND, FB2 = VCC, Consumption VOUT1 = BYP = 5.3V, (Note 5) VOUT2 = 3.5V SMPS Output and FB Voltage VIN = 6V to 25V, FB1= GND, VOUT1 Output Voltage in VOUT1 SKIP = 5V Fixed Mode VIN Standby Supply Current I VIN_SBY VOUT2 Output Voltage in Fixed Mode FBx in Output Adjustable Mode SECFB Voltage Output Voltage Adjust Range FBx Adjustable-mode Threshold Voltage DC Load Regulation Line Regulation VOUT2 VIN = 6V to 25V, FB2 = VCC , SKIP = 5V 3.285 3.33 3.375 V FBx VIN = 6V to 25V 1.975 2 2.025 V SECFB VIN = 6V to 25V (RT8206A) 1.92 2 2.08 V 2 -- 5.5 V 0.2 0.4 0.55 V -- −0.1 -- % Either SMPS, SKIP = REF, 0 to 5A -- −1.7 -- % Either SMPS, SKIP = GND, 0 to 5A -- −1.5 -- % Either SMPS, VIN = 6V to 25V -- 0.005 -- %/V SMPS1, SMPS2 Fixed or Adj-Mode comparator threshold Either SMPS, SKIP = VCC , 0 to 5A VLOAD VLINE On Time On-Time Pulse Width Minimum Off-Time t UGATEx TON = VCC SMPS1 = 5.05V (200kHz) 1895 2105 2315 SMPS2 = 3.33V (250kHz) 999 1110 1221 TON = REF SMPS1 = 5.05V (300kHz) 1227 1403 1579 SMPS2 = 3.33V (375kHz) 647 740 833 TON = GND SMPS1 = 5.05V (400kHz) 895 1052 1209 SMPS2 = 3.33V (500kHz) 475 555 635 200 300 400 ns SKIP = REF 25 33 -- kHz Zero to full limit from ENx Enable -- 2 -- ms ILIMx = VCC , GND − PHASEx 90 100 110 mV 4.75 5 5.25 μA t LGATEx Ultrasonic Mode Frequency ns Soft Start Soft-Start Time t SSx Current Sense Current Limit Threshold (Default) Current Limit Current Source I LIMX To be continued DS8206A/B-03 December 2009 www.richtek.com 9 RT8206A/B Parameter Symbol Conditions Min Typ Max Unit 0.5 -- 2 V VILIMx = 0.5V 40 50 60 mV VILIMx = 1V 90 100 110 mV VILIMx = 2V 180 200 220 mV -- 3 -- mV I LIM Adjustment Range VILIMx = I LIMx × RILIMx Current-Limit Threshold GND − PHASEx SKIP = GND or REF, GND − PHASEx Zero-Current Threshold Internal Regulator and Reference LDO Output Voltage VLDO BYP = GND, 6V < VIN < 25V, 0 < I LDO < 70mA 4.9 5 5.1 V LDO Output Current ILDO BYP = GND, VIN = 6V to 25V 70 -- -- mA LDO = GND, BYP = GND -- 200 300 mA 4.53 4.66 4.79 V -- 1.5 3 Ω LDO Short-Circuit Current LDO 5V Switchover Threshold to BYP VBYP Falling Edge, Rising Edge at BYP Regulation Point LDO Switchover Equivalent RSW Resistance LDO to BYP, 10mA REF Output Voltage No External Load 1.98 2 2.02 V REF Load Regulation IREF = 0 to 50uA -- 10 -- mV REF Sink Current REF in Regulation 10 -- -- μA Rising Edge -- 4.35 4.5 Falling Edge 3.9 4.05 -- −11 −7.5 −4 % -- 10 -- μs High State, Forced to 5.5V -- -- 1 μA ISINK = 4mA -- -- 0.3 V 108 111 115 % VREF UVLO PVCC UVLO Threshold PVCC V Power Good FBx with Respect to Internal Reference, Falling Edge, Hysteresis = 1% Falling Edge PGOODx Threshold PGOODx Propagation Delay PGOODx Leakage Current PGOODx Output Low Voltage Fault Detection OVP Trip Threshold VFB_OVP FBx with Respect to Internal Ref. OVP Propagation Delay FBx with 50mV Overdrive -- 10 -- μs UVP Trip Threshold FBx with Respect to Internal Ref. 65 70 75 % tSHDN_UVP From ENx Enable -- 3 -- ms TSHDN -- 150 -- °C -- 10 -- °C Low Level (Internal Fixed VOUTx) -- -- 0.2 V High Level (Internal Fixed VOUTx) VCC−1 -- -- V UVP Shutdown Blanking Time Thermal Shutdown Thermal Shutdown Thermal Shutdown Hysteresis Logic Input FB1/FB2 Input Voltage To be continued www.richtek.com 10 DS8206A/B-03 December 2009 RT8206A/B Parameter Symbol Conditions Min Typ Max -- -- 0.8 REF Level (Ultrasonic Mode) 1.8 -- 2.3 High Level (PWM Mode) 2.5 -- -- VOUT1 / VOUT2 (400kHz / 500kHz) -- -- 0.8 VOUT1 / VOUT2 (300kHz / 375kHz) 1.8 -- 2.3 VOUT1 / VOUT2 (200kHz / 250kHz) 2.5 -- -- Clear Fault Level / SMPS Off Level -- -- 0.8 Delay Start 1.8 -- 2.3 SMPS On Level 2.5 -- -- Rising Edge 1.2 1.6 2.0 Falling Edge 0.94 1 1.06 ENLDO = 0V or 25V −1 -- +3 ENx = 0V or 5V −1 -- +1 TON, SKIP = 0V or 5V −1 -- +1 FBx = 0V or 5V −1 -- +1 SECFB = 0V or 5V (RT8206A) −1 -- +1 PVCC to BOOTx -- 20 -- Ω UGATEx Driver Sink/Source Current UGATEx Forced to 2V -- 2 -- A LGATEx Driver Source Current LGATEx Forced to 2V -- 1.7 -- A LGATEx Driver Sink Current LGATEx Forced to 2V -- 3.3 -- A UGATEx On-Resistance BOOTx to PHASEx Forced to 5V -- 1.5 4 Ω LGATEx, High State -- 2.2 5 LGATEx, Low State -- 0.6 1.5 LG Rising -- 30 -- UG Rising -- 40 -- Low Level (DEM) SKIP Input Voltage TON Setting Voltage ENx Input Voltage ENLDO Input Voltage Input Leakage Current VENLDO Unit V V V V μA Internal BOOT Switch Internal Boost Charging Switch On-Resistance Power MOSFET Drivers LGATEx On-Resistance Dead Time Ω ns Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. Note 5. PVIN + PPVCC DS8206A/B-03 December 2009 www.richtek.com 11 RT8206A/B Typical Operating Characteristics VOUT1 Efficiency vs. Load Current VOUT1 Efficiency vs. Load Current 100 100 DEM Mode 90 80 80 70 70 60 Efficiency (%) Efficiency (%) 90 Ultrasonic Mode 50 PWM Mode 40 30 20 0 0.001 0.01 0.1 1 60 Ultrasonic Mode 50 40 PWM Mode 30 20 VIN = 7V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND 10 DEM Mode VIN = 12V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND 10 0 0.001 10 0.01 VOUT1 Efficiency vs. Load Current 90 DEM Mode 70 60 50 Ultrasonic Mode 40 PWM Mode 30 0 0.001 0.01 0.1 1 70 60 50 Ultrasonic Mode 40 PWM Mode 30 20 VIN = 25V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND 10 DEM Mode 80 Efficiency (%) Efficiency (%) 100 20 VIN = 7V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND 10 0 0.001 10 0.01 Load Current (A) VOUT2 Efficiency vs. Load Current 90 DEM Mode 80 Efficiency (%) 60 50 Ultrasonic Mode 40 PWM Mode 30 20 VIN = 12V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND 10 0.01 0.1 Load Current (A) www.richtek.com 12 10 VOUT2 Efficiency vs. Load Current 70 0 0.001 1 100 90 80 0.1 Load Current (A) 100 Efficiency (%) 10 VOUT2 Efficiency vs. Load Current 100 80 1 Load Current (A) Load Current (A) 90 0.1 1 10 70 DEM Mode 60 50 Ultrasonic Mode 40 PWM Mode 30 20 VIN = 25V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND 10 0 0.001 0.01 0.1 1 10 Load Current (A) DS8206A/B-03 December 2009 RT8206A/B VOUT1 Switching Frequency vs. Load Current VOUT1 Switching Frequency vs. Load Current 225 250 VIN = 7V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND Switching Frequency (kHz) Switching Frequency (kHz) 250 200 175 PWM Mode 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 DEM Mode 0.01 0.1 1 225 VIN = 12V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND 200 175 PWM Mode 150 125 100 75 50 Ultrasonic Mode 25 DEM Mode 0 0.001 10 0.01 VOUT1 Switching Frequency vs. Load Current 300 VIN = 25V, TON = VCC, EN2 = GND, EN1 = VCC, ENLDO = VIN, FB1 = GND 275 200 175 PWM Mode 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 DEM Mode 0.01 0.1 1 250 225 VIN = 7V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND PWM Mode 200 175 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 10 DEM Mode 0.01 225 300 VIN = 12V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND Switching Frequency (kHz) Switching Frequency (kHz) 250 PWM Mode 200 175 150 125 100 75 50 Ultrasonic Mode 25 0 0.001 0.1 Load Current (A) DS8206A/B-03 December 2009 275 10 250 225 VIN = 25V, TON = VCC, EN2 = VCC, EN1 = GND, ENLDO = VIN, FB2 = GND PWM Mode 200 175 150 125 100 75 50 Ultrasonic Mode 25 DEM Mode 0.01 1 VOUT2 Switching Frequency vs. Load Current VOUT2 Switching Frequency vs. Load Current 275 0.1 Load Current (A) Load Current (A) 300 10 VOUT2 Switching Frequency vs. Load Current Switching Frequency (kHz) Switching FrequencyY (kHz) 225 1 Load Current (A) Load Current (A) 250 0.1 1 10 0 0.001 DEM Mode 0.01 0.1 1 10 Load Current (A) www.richtek.com 13 RT8206A/B VREF vs. Output Current LDO Output Voltage vs. Output Current 5.04 2.00500 VIN = 12V, EN1 = EN2 = GND, ENLDO = VIN VIN = 12V, EN1 = EN2 = GND, ENLDO = VIN 2.00475 2.00450 5.032 V REF (V) Output Voltage (V) 5.036 5.028 2.00425 2.00400 2.00375 2.00350 5.024 2.00325 5.02 2.00300 0 10 20 30 40 50 60 -10 70 0 10 Output Current (mA) 30 40 50 Output Current (uA) No Load Battery Current vs. Input Voltage 100 20 Standby Current vs. Input Voltage 216 TON = VCC, EN1 = EN2 = VCC, ENLDO = VIN No Load, EN1 = EN2 = GND, ENLDO = VIN Standby Current (uA) Battery Current (mA) 214 PWM Mode 10 Ultrasonic Mode 1 DEM Mode 212 210 208 Standby Current 206 204 202 200 198 0.1 7 9 11 13 15 17 19 21 23 7 25 9 11 13 Input Voltage (V) Shutdown Current vs. Input Voltage 27 19 21 23 25 VREF vs. Temperature VIN = 12.6V 2.04 23 2.03 21 2.02 19 17 2.05 No Load on VOUT1, VOUT2, LDO and REF, EN1 = EN2 = GND, ENLDO = GND V REF (V) Shutdown Current (uA) 25 15 Input Voltage (V) Shutdown Current 17 15 2.01 2.00 1.99 1.98 13 1.97 11 1.96 9 1.95 7 9 11 13 15 17 19 Input Voltage (V) www.richtek.com 14 21 23 25 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) DS8206A/B-03 December 2009 RT8206A/B Power On from VIN Power On from EN1 DEM Mode VIN (10V/Div) EN1 (5V/Div) LDO (5V/Div) VOUT1 (5V/Div) REF (2V/Div) IL1 (2A/Div) CP (10V/Div) No Load, VIN = 12V, TON = VCC, EN1 = VCC, EN2 = GND, ENLDO = VIN PGOOD1 (5V/Div) No Load, VIN = 12V, TON = VCC, EN1 = VCC, EN2 = GND, ENLDO = VIN Time (400μs/Div) Time (1ms/Div) Power On from EN1 Power On from EN1 PWM Mode PWM Mode EN1 (5V/Div) EN1 (5V/Div) VOUT1 (5V/Div) VOUT1 (5V/Div) IL1 (2A/Div) IL1 (2A/Div) PGOOD1 (5V/Div) No Load, VIN = 12V, TON = VCC, EN1 = VCC, EN2 = GND, ENLDO = VIN PGOOD1 (5V/Div) Time (1ms/Div) Time (1ms/Div) Power On from EN2 Power On from EN2 DEM Mode PWM Mode EN2 (5V/Div) EN2 (5V/Div) VOUT2 (5V/Div) VOUT2 (5V/Div) IL2 (2A/Div) IL2 (2A/Div) PGOOD2 (5V/Div) No Load, VIN = 12V, TON = VCC, EN1 = GND, EN2 = VCC, ENLDO = VIN Time (1ms/Div) DS8206A/B-03 ILOAD = 4A, VIN = 12V, TON = VCC, EN1 = VCC, EN2 = GND, ENLDO = VIN December 2009 PGOOD2 (5V/Div) No Load, VIN = 12V, TON = VCC, EN1 = GND, EN2 = VCC, ENLDO = VIN Time (1ms/Div) www.richtek.com 15 RT8206A/B Power On from EN1 (Delay Start) Power On from EN2 EN2 = REF PWM Mode EN2 (5V/Div) EN1 (5V/Div) VOUT2 (5V/Div) EN2 (5V/Div) IL2 (2A/Div) PGOOD2 (5V/Div) ILOAD = 4A, VIN = 12V, TON = VCC, EN1 = GND, EN2 = VCC, ENLDO = VIN VOUT1 (2V/Div) VOUT2 (2V/Div) VIN = 12V, TON = VCC, ENLDO = VIN Time (1ms/Div) Time (400μs/Div) Power On from EN2 (Delay Start) Power Off from EN1 EN1 = REF EN1 (10V/Div) EN1 (5V/Div) VOUT1 (5V/Div) EN2 (5V/Div) VOUT1 (2V/Div) UGATE1 (20V/Div) VOUT2 (2V/Div) LGATE1 (5V/Div) VIN = 12V, TON = VCC, ENLDO = VIN VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = VIN Time (400μs/Div) Time (10ms/Div) VOUT1 Load Transient Response VOUT2 Load Transient Response PWM Mode, VIN = 12V PWM Mode, VIN = 12V VOUT2_ac- VOUT1_ac- coupled coupled (50mV/Div) (50mV/Div) IL1 (5A/Div) IL2 (2A/Div) LGATE1 (5V/Div) LGATE2 (5V/Div) TON = VCC, SKIP = VCC, ENLDO = VIN, FB1 = VCC Time (20μs/Div) www.richtek.com 16 TON = VCC, SKIP = VCC, ENLDO = VIN, FB2 = VCC Time (20μs/Div) DS8206A/B-03 December 2009 RT8206A/B OVP VOUT1 (5V/Div) UVP VOUT1 (5V/Div) IL1 (10A/Div) PGOOD1 (5V/Div) VOUT2 (5V/Div) UGATE1 (20V/Div) PGOOD2 (5V/Div) LGATE1 (5V/Div) VIN = 12V, TON = VCC, SKIP = GND, ENLDO = VIN Time (500μs/Div) VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = VIN Time (10μs/Div) Power On in Short Circuit VOUT1 (1V/Div) VOUT1 = Short IL1 (5A/Div) UGATE1 (20V/Div) LGATE1 (5V/Div) VIN = 12V, TON = VCC, SKIP = VCC, ENLDO = VIN Time (400μs/Div) DS8206A/B-03 December 2009 www.richtek.com 17 RT8206A/B Application Information The RT8206A/B is a dual, high efficiency, Mach ResponseTM DRVTM dual ramp valley mode synchronous buck controller. The controller is designed for low-voltage power supplies for notebook computers. Richtek Mach Response TM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a dual output application. The RT8206A/B achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs. The RT8206A/B includes 5V (LDO) linear regulator which can step down the battery voltage to supply both internal circuitry and gate drivers. When VOUT1 voltage is above 4.66V, an automatic circuit turns off the linear regulator and powers the device from VOUT1 through BYP pin connected to VOUT1. PWM Operation The Mach ResponseTM DRVTM mode controller relies on the output filter capacitor's effective series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. Refer to the function block diagram, the UGATE driver will be turned on at the beginning of each cycle. After the internal oneshot timer expires, the UGATE driver will be turned off. The pulse width of this one shot is determined by the converter's input voltage and the output voltage to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (300ns typ.). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the currentlimit threshold, and the minimum off-time one-shot has timed out. PWM Frequency and On-Time Control The Mach ResponseTM control architecture runs with pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The high-side switch on-time is inversely proportional to the www.richtek.com 18 input voltage as measured by the VIN, and proportional to the output voltage. The on-time is given by : On-Time= K (VOUT / VIN) There “K” is set by the TON pin-strap connector (Table 1). One-shot timing error increases for the shorter ontime setting due to fixed propagation delays that is approximately ±15% at high frequency and the ±10% at low frequency. The on-time guaranteed in the Electrical Characteristics tables is influenced by switching delays in the external high-side power MOSFET. Two external factors that influence switching-frequency accuracy are resistive drops in the two conduction loops (including inductor and PC board resistance) and the dead-time effect. These effects are the largest contributors to the change of frequency with changing load current. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times. It occurs only in PWM mode (SKIP = high) when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes PHASEX to go high earlier than normal, extending the ontime by a period equal to the low-to-high dead time. For loads above the critical conduction point, the actual switching frequency is : FS = (VOUT +VDROP1) / TON x (VIN + VDROP1 − VDROP2 ) The VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path; and TON is the ontime calculated by the RT8206A/B. Table 1. TON Setting and PWM Frequency Table TON TON TON TON = VCC = REF = GND VOUT1 5μs 3.33μs 2.5μs K-Factor VOUT1 200kHz 300kHz 400kHz Frequency VOUT2 4μs 2.67μs 2μs K-Factor VOUT2 250kHz 375kHz 500kHz Frequency Approximate ±10% ±12.5% ±15% K-Factor Error DS8206A/B-03 December 2009 RT8206A/B Operation Mode Selection The RT8206A/B supports three operation modes: DiodeEmulation Mode, Ultrasonic Mode, and Forced-CCM Mode. Users can set operation mode by SKIP pin. All of the three operation modes will be introduced as follows. Diode-Emulation Mode (SKIP = GND) In Diode-Emulation mode, the RT8206A/B automatically reduces switching frequency at light-load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without the increase of VOUTx ripple or load regulation. As the output current decreases from heavy-load condition, the inductor current is also reduced, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low-side MOSFET allows only partial of negative current when the inductor free-wheeling current reach negative. As the load current further decreases, it takes longer and longer to discharge the output capacitor to the level that requires for the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. The transition load point to the light-load operation can be calculated as following equation. ILOAD ≈ (VIN − VOUT ) × TON 2L where TON is the given On-time. IL Slope = (V IN -V OUT) / L iLoad = iL, peak / 2 t tON Figure 3. Boundary Condition of CCM/DEM DS8206A/B-03 December 2009 Ultrasonic Mode (SKIP = REF) Connecting SKIP to REF activates a unique DiodeEmulation mode with a minimum switching frequency above 25kHz. This ultrasonic mode eliminates audiofrequency modulation that would otherwise be present when a lightly loaded controller automatically skips pulses. In ultrasonic mode, the low-side switch gate-driver signal is OR with an internal oscillator (>25kHz). Once the internal oscillator is triggered, the ultrasonic controller forces the LGATEx high, turning on the low-side MOSFET to induce a negative inductor current. At the point that the output voltage is higher than that of REF, the controller turns off the low-side MOSFET (LGATEx pulled low) and triggers a constant on-time (UGATEx driven high). When the on-time has expired, the controller re-enables the lowside MOSFET until the controller detects that the inductor current dropped below the zero-crossing threshold. Forced-CCM Mode (SKIP = VCC) iL, peak 0 The switching waveforms may appear noisy and asynchronous when light loading causes Diode-Emulation operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). The low-noise, forced-CCM mode (SKIP = VCC) disables the zero-crossing comparator, which controls the low-side switch on-time. This causes the low-side gate-driver waveform to become the complement of the high-side gatedriver waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop strives to maintain a duty ratio of VOUT/VIN. The benefit of the forcedCCM mode is to keep the switching frequency fairly constant, but it comes at a cost : The no-load battery current can be 10mA to 40mA, depending on the external MOSFETs. www.richtek.com 19 RT8206A/B Reference and Linear Regulator (REF, LDO and 14V Charge Pump) The 2V reference (REF) is accurate within ±1% over temperature, making REF useful as a precision system reference. Bypass REF to GND with 0.22uF(MIN) capacitor. REF can supply up to 50uA for external loads. Loading REF degrades FBx and output accuracy according to the REF load-regulation error. An internal regulator produces a fixed output voltage 5V. The LDO regulator can supply up to 70mA for external loads. Bypass LDO with a minimum 4.7μF ceramic capacitor. When the output voltage of the VOUT1 is higher than the switchover threshold, an internal 1.5Ω N-Channel MOSFET switch connects VOUT1 to LDO through BYP while simultaneously shutting down the internal linear regulator. of Figure 3), will also increase the robustness of the charge pump. Current-Limit Setting (ILIMx) The RT8206A/B has a cycle-by-cycle current limiting control. The current-limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the currentsense signal at PHASEx is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 4). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the sense resistance, inductor value, battery voltage, and output voltage. IL IL, peak In typical application circuit figure, the external 14V charge pump is driven by LGATE1. When LGATE1 is low, D1 charge C5 sourced from VOUT1. C5 voltage is equal to VOUT1 minus a diode drop. When LGATE1 transitions to high, the charge from C5 will transfer to C6 through D2 and charge it to VLGATE1 plus VC5. As LGATE1 transients low on the next cycle, C6 will charge C7 to its voltage minus a diode drop through D3. Finally, C7 charges C8 through D4 when LGATE1 transi switched to high. CP output voltage is : CP = VOUT1 +2 x VLGATE1 − 4 x VD Where : ` VLGATE1 ` is the peak voltage of the LGATE1 driver VD is the forward diode dropped across the Schottkys SECFB (RT8206A) is used to monitor the charge pump through resistive divider. In an event when SECFB drops below 2V, the detection circuit forces the LGATE1 on for 300ns to allow CP to recharge and the SECFB rise above 2V. In the event of an overload on CP where SECFB can not reach more than 2V, the monitor will be deactivated. The SECFB pin has a 17mV of hysteresis so the ripple should be enough to bring the SECFB voltage above the threshold by ~3x the hysteresis, or (3 x 17mV) = 51mV. Reducing the CP decoupling capacitor and placing a small ceramic capacitor C19 (10pF to 47pF) in parallel will the upper leg of the SECFB resistor feedback network (R11 www.richtek.com 20 ILoad ILIM t 0 Figure 4. Valley Current-Limit The RT8206A/B uses the on-resistance of the synchronous rectifier as the current-sense element. Use the worsecase maximum value for RDS(ON) from the MOSFET datasheet, and add a margin of 0.5%/°C for the rise in RDS(ON) with temperature. The current-limit threshold is adjusted with an external resistor for the RT8206A/B at ILIMx. The current-limit threshold adjustment range is from 50mV to 200mV. In the adjustment mode, the current-limit threshold voltage is precise to 1/10 the voltage seen at ILIMx. The threshold defaults to 100mV when ILIMx is connected to VCC. The logic threshold for switchover to the 100mV default value is higher than VCC−1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signal at PHASEx and GND. Mount or place the IC close to the low-side MOSFET. DS8206A/B-03 December 2009 RT8206A/B MOSFET Gate Driver (UGATEx, LGATEx) The high-side driver is designed to drive high-current, low RDS(ON) N-MOSFET(s). When configured as a floating driver the instantaneous drive current is supplied by the flying capacitor between BOOTx and PHASEx pins. A dead time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and lowside MOSFET off to high-side MOSFET on. The low-side driver is designed to drive high current low RDS(ON) N-MOSFET(s). The internal pulldown transistor that drives LGATEx low is robust, with a 0.6Ω typical onresistance. A 5V bias voltage is typically delivered from PVCC through LDO supply. The instantaneous drive current is supplied by an input capacitor connected between PVCC and GND. For high-current applications, some combinations of highand low-side MOSFETs might be encountered that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents. This is often remedied by adding a resistor in series with BOOTx, which increases the turn-on time of the high-side MOSFET without degrading the turn-off time (Figure 5). switching by keeping UGATEx and LGATEx low when PVCC is below 4V. The PWM outputs begin to ramp up once PVCC exceeds its UVLO threshold and ENx is enable. Power-Good Output (PGOODx) The PGOODx is an open-drain type output. PGOODx is actively held low in soft-start, standby, and shutdown. It is released when the VOUTx voltage is above than 92.5% of the nominal regulation point. The PGOODx goes low if it is 7.5% below its nominal regulator point. Output Over voltage Protection (OVP) The output voltage can be continuously monitored for over voltage protection. When the output voltage of the VOUTx is 11% above the set voltage, over voltage protection will be enabled, if the output exceeds the over voltage threshold, over voltage fault protection will be triggered and the LGATEx low-side gate drivers are forced high. This activates the low-side MOSFET switch, which rapidly discharges the output capacitor and reduces the output voltage. Once an over-voltage fault condition is set, it can only be reset by toggling ENLDO, ENx, or cycling VIN (POR.) V IN BOOTx 10 UGATEx PHASEx Figure 5. Reducing the UGATEx Rise Time Soft-Start A built-in soft-start is used to prevent surge current from power supply input after ENx is enabled. The typical softstart duration is 2ms period. The maximum allowed current limit is segmented in 5 steps : 20%, 40%, 60%, 80% and 100% during this period. The current limit steps can eliminate the VOUT folded-back in the soft-start duration. POR and UVLO Power-on reset (POR) occurs when VIN rises above approximately 3.7V (typ.), resetting the fault latches. PVCC undervoltage-lockout (UVLO) circuitry inhibits DS8206A/B-03 December 2009 Output Under-Voltage Protection (UVP) The output voltage can be continuously monitored for under voltage protection. If the output is less than 70% of the error-amplifier trip voltage, under voltage protection will be triggered, and then both UGATEx and LGATEx gate drivers will be forced low. The UVP will be ignored for at least 3ms (typ.) after start-up or after a rising edge on ENx. Toggle ENx or cycle VIN (POR) to clear the under-voltage fault latch and restart the controller. The UVP only applies to the BUCK outputs. Thermal Protection The RT8206A/B has a thermal shutdown protection function to prevent it from overheating. Thermal shutdown occurs when the die temperature exceeds +150°C. All internal circuitry will be shut down during thermal shutdown. The RT8206A/B may trigger thermal shutdown if the LDO were not supplied from VOUTx, while input voltage is on VIN and drawing current that is too high from the LDO. Even if the LDO is supplied from VOUTx, overloading the www.richtek.com 21 RT8206A/B LDO causes large power dissipation on automatic switches, which may result in thermal shutdown. ⎡ ⎤ VOUTx = VFBx × ⎢1 + ⎛⎜ R1 ⎞⎟ ⎥ ⎣ ⎝ R2 ⎠ ⎦ Where VFBx is 2V (typ.). Discharge Mode V IN When standby or shutdown mode occurs, or the output under voltage fault latch is set, the outputs discharge mode is triggered. During discharge mode, the output capacitor will be discharged to GND through an internal 20Ω switch. V OUTx UGATEx PHASEx LGATEx R1 VOUTx FBx Shutdown Mode The RT8206A/B SMPS1, SMPS2 and LDO have independent enabling control. Drive ENLDO, EN1 and EN2 below the precise input falling-edge trip level to place the RT8206A/B in its low-power shutdown state. The RT8206A/B consumes only 20uA of quiescent current while in shutdown. When shutdown mode is activated, the reference turns off. The accurate 1V falling-edge threshold on the ENLDO can be used to detect a specific analog voltage level and shutdown the device. Once in shutdown, the 1.6V rising-edge threshold activates, providing sufficient hysteresis for most application. Power-Up Sequencing and On/Off Controls (ENx) EN1 and EN2 control SMPS power-up sequencing. When the RT8206A/B applies in the single channel mode, EN1 or EN2 enables the respective outputs when ENx voltage rising above 2.5V, and disables the respective outputs when ENx voltage falling below 1.8V. Connecting one of ENx to VCC and the other one to REF can force the latter one output starts after the former one regulates. If both of ENx forced to connect to REF, both outputs will always wait for the regulation of the other one. However, in this situation, neither of the two ENx will be in regulation. Output Voltage Setting (FBx) Connect FB1 directly to GND or VCC for a fixed 5V output (VOUT1). Connect FB2 directly to GND or VCC for a fixed 3.3V output (VOUT2). The output voltage can also be adjusted from 2V to 5.5V with a resistor-divider network (Figure 6). The following equation is for adjusting the output voltage. Choose R2 to be approximately 10kΩ, and solve for R1 using the following equation : www.richtek.com 22 R2 GND Figure 6. Setting VOUTx with a Resistor-Divider Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : L= TON × (VIN - VOUT ) LIR × ILOAD(MAX) Where LIR is the ratio of the peak-to-peak ripple current to the average inductor current. Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although the powdered iron is inexpensive and can work well at 200kHz. The core must be large enough to prevent it from saturating at the peak inductor current (IPEAK) : IPEAK = ILOAD(MAX) + [(LIR / 2) x ILOAD(MAX)] This inductor ripple current also impacts transient-response performance, especially at low VIN − VOUTx differences. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The peak amplitude of the output transient. The VSAG also features a function of the output transient (VSAG) is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time : V (ΔILOAD )2 × L × ⎛⎜ K OUTx + TOFF(MIN) ⎞⎟ VIN ⎝ ⎠ VSAG = ⎡ ⎛ VIN − VOUTx ⎞ ⎤ 2 × COUT × VOUTx × ⎢K ⎜ ⎟ − TOFF(MIN) ⎥ V IN ⎠ ⎣ ⎝ ⎦ Where minimun off-time (TOFF(MIN)) = 300ns (typ.) and K is from Table 1. DS8206A/B-03 December 2009 RT8206A/B Output Capacitor Selection The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements, it’s commanded to keep the feedback voltage between 6 to 12mV. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to noload condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : ESR ≤ VP-P ILOAD(MAX) In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple : ESR ≤ VP-P LIR × ILOAD(MAX) There VP-P is the peak-to-peak output voltage ripple. Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Output Capacitor Stability Stability is determined by the value of the ESR zero relative to the switching frequency. The point of instability is given by the following equation : fESR = f 1 ≤ SW 2 × π × ESR × COUT 4 Do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. Large ceramic capacitors can have a high- ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting VOUTx or the FBx divider close to the inductor. There are two related but distinct ways including doublepulsing and feedback loop instability in the unstable operation. Double-pulsing occurs due to noise on the output or because the ESR is too low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 300ns minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it may indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can trip the over-voltage protection latch or cause the output voltage to fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. It helps to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under- or overshoot. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8206, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-32L 5x5 packages, the thermal resistance θJA is 36°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (36°C/W) = 2.778W for WQFN-32L 5x5 packages DS8206A/B-03 December 2009 www.richtek.com 23 RT8206A/B The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal ` All sensitive analog traces and components such as VOUTx, FBx, GND, ENx, PGOODx, ILIMx, VCC, and TON should be placed away from high-voltage switching nodes such as PHASEx, LGATEx, UGATEx or BOOTx nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` Gather ground terminal of VIN capacitor(s), VOUTx capacitor(s), and source of low-side MOSFETs as close as possible. PCB trace defined as PHASEx node, which connects to source of high-side MOSFET, drain of lowside MOSFET and high-voltage side of the inductor, should be as short and wide as possible. Maximum Power Dissipation (W) resistance θJA. For RT8206A/B packages, the Figure 7 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Four Layers PCB WQFN -32L 5x5 0 25 50 75 100 125 Ambient Temperature (°C) Figure 7. Derating Curves for RT8206A/B Packages Layout Considerations Layout is very important in high frequency switching converter design. If the layout is designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. The following points must be followed for a proper layout of RT8206A/B. ` Connect RC low-pass filter from PVCC to VCC, the RC low-pass filter is composed of an external capacitor and an internal 10Ω resistor. Bypass VCC to GND with a capacitor 1uF is recommended. Place the capacitor close to the IC, within 12mm (0.5 inch) if possible. ` Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high-voltage switching node. ` Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65mm (25 mils) or wider trace. www.richtek.com 24 DS8206A/B-03 December 2009 RT8206A/B Table 2. Operation Mode Truth Table Mode Condition Comment Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO and REF remain active. RUN ENLDO = high, EN1 or EN2 enabled Normal Operation. Over voltage Either output > 111% of nominal LGATEx is forced high. LDO and REF active. Exited by Protection level. VIN POR or by toggling ENLDO. Both UGATEx and LGATEx are forced low until enter Either output<70% of nominal level Under voltage discharge mode terminates. LDO and REF are active. after 3ms time-out expires and output Protection Exited by VIN POR or by toggling ENLDO, EN1, or is enabled. EN2. Either SMPS output is still high in During discharge mode, the output capacitor Discharge either standby mode or shutdown discharges to GND through an internal 20Ω switch. mode. ENx < startup threshold, Standby LGATEx stays low. LDO and REF active. ENLDO = high. Shutdown EN1, EN2, ENLDO=low All circuitry off. Thermal Shutdown TJ > +150°C All circuitry off. Exit by VIN POR or by toggling ENLDO. Power-UP PVCC < UVLO threshold Table 3. Power-Up Sequencing VE N1 (V) X VEN2 (V) “>2V” High Low Low “>2V” High Low REF “>2V” High Low High “>2V” High REF Low “>2V” High REF REF “>2V” High REF High “>2V” High High Low “>2V” High High REF “>2V” High High High ENLDO (V) Low DS8206A/B-03 December 2009 LDO Off 5V SMPS1 Off 3V SMPS2 Off Off Off Off Off Off On Off Off Off Off On (after SMPS2 on) On On Off On (after REF powers up) On On (after SMPS1 on) On (after REF powers up) On On X (after (after (after (after (after (after (after On REF powers On REF powers On REF powers On REF powers On REF powers On REF powers On REF powers up) up) up) up) up) up) up) www.richtek.com 25 RT8206A/B Outline Dimension D2 D SEE DETAIL A L 1 E E2 e 1 1 2 2 b DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 A3 Symbol Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.400 3.750 0.134 0.148 E 4.950 5.050 0.195 0.199 E2 3.400 3.750 0.134 0.148 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 32L QFN 5x5 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 26 DS8206A/B-03 December 2009