SHARP RJ2411

BACK
RJ2411AA0PB
1/4-type Color CCD Area Sensors
with 270 k Pixels
RJ2411AA0PB
DESCRIPTION
PIN CONNECTIONS
The RJ2411AA0PB is a 1/4-type (4.5 mm) solidstate image sensor that consists of PN photo-diodes
and CCDs (charge-coupled devices). With
approximately 270 000 pixels (542 horizontal x 492
vertical), the sensor provides a stable high-resolution
color image.
14-PIN HALF-PITCH DIP
FEATURES
• Number of image pixels : 512 (H) x 492 (V)
• Number of optical black pixels
– Horizontal : 2 front and 28 rear
• Pixel pitch : 7.2 µm (H) x 5.6 µm (V)
• Mg, G, Cy, and Ye complementary color filters
• Low fixed-pattern noise and lag
• No burn-in and no image distortion
• Blooming suppression structure
• Built-in output amplifier
• Built-in overflow drain voltage circuit and reset
gate voltage circuit
• Horizontal shift register clock and reset gate clock
voltage : 3.3 V (TYP.)
• Variable electronic shutter (1/60 to 1/10 000 s)
• Compatible with NTSC standard
• Package :
14-pin half-pitch DIP [Plastic]
(P-DIP014-0400A)
Row space : 10.16 mm
TOP VIEW
OD 1
14 GND
ØRS 2
13 ØV4
NC 3
12 ØV3
OS 4
11 ØV2
OOFD 5
10 ØV1
ØH2 6
9 PW
ØH1 7
8 OFD
(P-DIP014-0400A)
PRECAUTIONS
• The exit pupil position of lens should be more
than 10 mm from the top surface of the CCD.
• Refer to "PRECAUTIONS FOR CCD AREA
SENSORS" for details.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
RJ2411AA0PB
PIN DESCRIPTION
OD
SYMBOL
PIN NAME
Output transistor drain
OS
ØRS
Output signals
Reset transistor clock
ØV1, ØV2, ØV3, ØV4
ØH1, ØH2
Vertical shift register clock
Horizontal shift register clock
OFD
Overflow drain
OOFD
PW
Overflow drain output
P-well
GND
NC
Ground
No connection
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Output transistor drain voltage
(TA = +25˚C)
SYMBOL
VOD
RATING
0 to +18
0 to +37
UNIT
V
V
VØRS
Internal output
Internal output
V
V
Overflow drain voltage
VOFD
Overflow drain output voltage
VOOFD
Reset gate clock voltage
VØV
VPW to +17.5
V
Horizontal shift register clock voltage
Voltage difference between P-well and vertical clock
VØH
VPW-VØV
–0.3 to +12
–28 to 0
V
V
Voltage difference between vertical clocks
Vertical shift register clock voltage
VØV-VØV
0 to +15
V
Storage temperature
TSTG
–40 to +85
˚C
Ambient operating temperature
TOPR
–20 to +70
˚C
NOTE
1
1
2
3
NOTES :
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage
directly. When OOFD is connected to GND, connect VOD to GND.
2. Do not connect to DC voltage directly. When ØRS is connected to GND, connect VOD to GND. Reset gate clock is
applied below 8 Vp-p.
3. When clock width is below 10 µs, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be
below 27 V.
2
RJ2411AA0PB
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Ambient operating temperature
SYMBOL
TOPR
MIN.
TYP.
25.0
MAX.
UNIT
˚C
Output transistor drain voltage
Overflow drain clock p-p level
VOD
VØOFD
14.55
21.5
15.0
(adj.)
15.45
23.5
V
V
1
Ground
P-well voltage
GND
VPW
VØVL
V
V
2
–7.5
V
LOW level
Vertical shift
register clock
Horizontal shift
register clock
INTERMEDIATE level
VØV1L, VØV2L
VØV3L, VØV4L
0.0
–9.0
–8.5
VØV1I, VØV2I
–8.0
0.0
V
HIGH level
VØV3I, VØV4I
VØV1H, VØV3H
14.55
15.0
15.45
V
LOW level
HIGH level
VØH1L, VØH2L
VØH1H, VØH2H
–0.05
3.0
0.0
3.3
+0.05
5.25
V
V
VØRS
3.0
3.3
5.25
V
Reset gate clock p-p level
Vertical shift register clock frequency
Horizontal shift register clock frequency
fØV1, fØV2
fØV3, fØV4
fØH1, fØH2
Reset gate clock frequency
fØRS
NOTE
15.73
kHz
9.53
9.53
MHz
MHz
1
NOTES :
• Connect NC to GND directly or through a capacitor larger than 0.047 µF.
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly.
2. VPW is set below VØVL that is low level of vertical shift register clock, or is used with the same power supply that is connected
to VL of V driver IC.
* To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on VPW first and then turn on other
powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
3
RJ2411AA0PB
CHARACTERISTICS (Drive method : Field accumulation)
(TA = +25˚C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS".
Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER
Standard output voltage
SYMBOL
VO
Photo response non-uniformity
Saturation output voltage
PRNU
VSAT
MIN.
TYP.
150
MAX.
UNIT
mV
NOTE
2
15
%
mV
3
4
700
Dark output voltage
VDARK
0.5
3.0
mV
1, 5
Dark signal non-uniformity
Sensitivity
DSNU
R
0.5
800
2.0
mV
mV
1, 6
7
–105
–95
1.0
dB
%
8
9
3.0
350
8.0
mA
$
Vector breakup
Line crawling
7.0
3.0
˚, %
%
11
12
Luminance flicker
2.0
%
13
Smear ratio
Image lag
SMR
AI
Blooming suppression ratio
ABL
Output transistor drain current
Output impedance
IOD
RO
550
1 000
10
NOTES :
• Within the recommended operating conditions of VOD,
VOFD of the internal output satisfies with ABL larger than
1 000 times exposure of the standard exposure conditions,
and VSAT larger than 700 mV.
1. TA = +60˚C
2. The average output voltage under uniform illumination.
The standard exposure conditions are defined as when
Vo is 150 mV.
3. The image area is divided into 10 x 10 segments under
the standard exposure conditions. Each segment's
voltage is the average output voltage of all pixels within
the segment. PRNU is defined by (Vmax – Vmin)/Vo,
where Vmax and Vmin are the maximum and minimum
values of each segment's voltage respectively.
4. The image area is divided into 10 x 10 segments. Each
segment's voltage is the average output voltage of all
pixels within the segment. VSAT is the minimum
segment's voltage under 10 times exposure of the
standard exposure conditions.
5. The average output voltage under non-exposure
conditions.
6. The image area is divided into 10 x 10 segments under
non-exposure conditions. DSNU is defined by (Vdmax –
Vdmin), where Vdmax and Vdmin are the maximum and
minimum values of each segment's voltage respectively.
7. The average output voltage when a 1 000 lux light
source with a 90% reflector is imaged by a lens of F4,
f50 mm.
8. The sensor is exposed only in the central area of V/10
square with a lens at F4, where V is the vertical image
size. SMR is defined by the ratio of the output voltage
detected during the vertical blanking period to the
maximum output voltage in the V/10 square.
9. The sensor is exposed at the exposure level
corresponding to the standard conditions. AI is defined
by the ratio of the output voltage measured at the 1st
field during the non-exposure period to the standard
output voltage.
10. The sensor is exposed only in the central area of V/10
square, where V is the vertical image size. ABL is
defined by the ratio of the exposure at the standard
conditions to the exposure at a point where blooming is
observed.
11. Observed with a vector scope when the color bar chart
is imaged under the standard exposure conditions.
12. The difference between the average output voltage of the
(Mg + Ye), (G + Cy) line and that of the (Mg + Cy), (G
+ Ye) line under the standard exposure conditions.
13. The difference between the average output voltage of
the odd field and that of the even field under the
standard exposure conditions.
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RJ2411AA0PB
PIXEL STRUCTURE
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OPTICAL BLACK
(2 PIXELS)
OPTICAL BLACK
(28 PIXELS)
512 (H) x 492 (V)
1 pin
COLOR FILTER ARRAY
(1, 492)
ODD
field
(512, 492)
Mg
G
Mg
G
Mg
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Mg
G
Mg
G
Mg
G
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
G
Mg
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
(1, 1)
EVEN
field
(512, 1)
5
RJ2411AA0PB
TIMING CHART
VERTICAL TRANSFER TIMING
Shutter speed
1/2 000 s
(ODD FIELD)
525 1
10
17
19
HD
VD
ØV1
ØV2
ØV3
ØV4
ØOFD
484 486 488 490 492
+
+
+
+
485 487 489 491
1
+
2
3
+
4
5
+
6
7
+
8
9
+
10
11
+
12
4
+
5
6
+
7
8
+
9
10
+
11
OS
(EVEN FIELD)
263
272
279
282
HD
VD
ØV1
ØV2
ØV3
ØV4
ØOFD
483 485 487 489 491
+
+
+
+
+
484 486 488 490 492
1
2
+
3
OS
HORIZONTAL TRANSFER TIMING
606
(0)
60
HD
ØH1
ØH2
ØRS
OS
…512
OB (2)
OUTPUT (512) 1πππππππ
OB (28)
29
49
ØV1
59
39
ØV2
24
54
ØV3
34
64
ØV4
62
ØOFD
6
72
RJ2411AA0PB
READOUT TIMING
(ODD FIELD)
0
606
(0)
60
60
HD
242
290
29 49
ØV1
29 49
39 59
161
449
39 59
ØV2
290
24
ØV3
54
34
338
180
54
34
64
64
ØV4
(EVEN FIELD)
0
606
(0)
60
60
HD
242
ØV1
290
29 49
39 59
59
161
ØV2
290
ØV3
24
34
54
338
180
54
450
64
ØV4
7
64
V2
NC
V4
V3B
V3A
V1B
VMa
V1A
VH
8
13 14 15 16 17 18 19 20 21 22 23 24
1
6
5
(*1)
4
3
2
(*1)
1
10 11 12 13 14
ØV2
ØV1
OFD
VDD
(*1) ØRS, OFD, OOFD :
Use the circuit parameter indicated in
this circuit example, and do not connect
to DC voltage directly.
9
PW
8
(*1)
1 M$
100 k$
CCD OUT
270 pF
RJ2411AA0PB
7
ØV3
+VDD
V3X
VH1AX
V1X
V2X
OFDX
VL
2
VMb
LR36685
+
3
POFD
4
ØH1
5
ØH2
6
OOFD
7
OS
8
0.01 µF
1 M$
NC
9
0.01 µF
100 k$
ØRS
12 11 10
100 $ 1.0 µF
OD
V4X
VH3AX
VH
ØH2
ØH1
VL (VPW)
ØRS
VOD
RJ2411AA0PB
SYSTEM CONFIGURATION EXAMPLE
+
GND
ØV4
VOFDH
VH3BX
OFDX
V2X
V1X
VH1AX
V3X
GND
+
VH3AX
V4X
VH1BX
+
RJ2411AA0PB
PACKAGE OUTLINES
14 DIP (P-DIP014-0400A)
(Unit : mm)
10±0.1
9±0.1 (◊)
Center of effective imaging area
and center of package
(◊ : Lid's size)
9±0.1 (◊)
8
CCD
1
0.5±0.5
7
Rotation error of die : ¬ = 1.0˚MAX
Refractive index : nd = 1.5
1.96±0.05
A'
14-0.3TYP.
14-0.46TYP.
3.35±0.1
5.02MAX.
A
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Glass Lid
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CCD
;;;;;;;;;;;;;;;;;
Package
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P-1.27TYP.
0.25±0.1
0.25
0.03
A
1.39±0.025
1.27±0.25
2.55±0.1
5±0.075
0.8±0.05 (◊)
0.5±0.5
5±0.075
¬
3.5±0.3 3.35±0.1
10±0.1
14
A'
0.03
0.03
+0.5
10.16–0
M
9
RJ2411AA0PB
(In the case of plastic packages)
– The leads of the package are fixed with
package body (plastic), so stress added to a
lead could cause a crack in the package
body (plastic) in the jointed part of the lead.
PRECAUTIONS FOR CCD AREA SENSORS
1. Package Breakage
In order to prevent the package from being broken,
observe the following instructions :
1) The CCD is a precise optical component and
the package material is ceramic or plastic.
Therefore,
ø Take care not to drop the device when
mounting, handling, or transporting.
ø Avoid giving a shock to the package.
Especially when leads are fixed to the socket
or the circuit board, small shock could break
the package more easily than when the
package isn’t fixed.
2) When applying force for mounting the device or
any other purposes, fix the leads between a
joint and a stand-off, so that no stress will be
given to the jointed part of the lead. In addition,
when applying force, do it at a point below the
stand-off part.
Glass cap
Package
Lead
Fixed
Stand-off
3) When mounting the package on the housing,
be sure that the package is not bent.
– If a bent package is forced into place
between a hard plate or the like, the package may be broken.
4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could
deteriorate.
Therefore,
ø Do not hit the glass cap.
ø Do not give a shock large enough to cause
distortion.
ø Do not scrub or scratch the glass surface.
– Even a soft cloth or applicator, if dry, could
cause flaws to scratch the glass.
(In the case of ceramic packages)
– The leads of the package are fixed with low
melting point glass, so stress added to a
lead could cause a crack in the low melting
point glass in the jointed part of the lead.
Low melting point glass
Lead
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has
lower ESD. Therefore, take the following antistatic
measures when handling the CCD :
1) Always discharge static electricity by grounding
the human body and the instrument to be used.
To ground the human body, provide resistance
of about 1 M$ between the human body and
the ground to be on the safe side.
2) When directly handling the device with the
fingers, hold the part without leads and do not
touch any lead.
Fixed
Stand-off
10
RJ2411AA0PB
3) To avoid generating static electricity,
a. do not scrub the glass surface with cloth or
plastic.
b. do not attach any tape or labels.
c. do not clean the glass surface with dustcleaning tape.
4) When storing or transporting the device, put it in
a container of conductive material.
4. Other
1) Soldering should be manually performed within
5 seconds at 350°C maximum at the tip of
soldering iron.
2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise
optical component. Do not give a mechanical
shock to the CCD.
3)* Do not expose the device to strong light. For
the color device, long exposure to strong light
will fade the color of the color filters.
3. Dust and Contamination
Dust or contamination on the glass surface could
deteriorate the output characteristics or cause a
scar. In order to minimize dust or contamination on
the glass surface, take the following precautions :
1) Handle the CCD in a clean environment such
as a cleaned booth. (The cleanliness level
should be, if possible, class 1 000 at least.)
2) Do not touch the glass surface with the fingers.
If dust or contamination gets on the glass
surface, the following cleaning method is
recommended :
ø Dust from static electricity should be blown
off with an ionized air blower. For antielectrostatic measures, however, ground all
the leads on the device before blowing off
the dust.
ø The contamination on the glass surface
should be wiped off with a clean applicator
soaked in isopropyl alcohol. Wipe slowly and
gently in one direction only.
– Frequently replace the applicator and do not
use the same applicator to clean more than
one device.
◊ Note : In most cases, dust and contamination
are unavoidable, even before the device
is first used. It is, therefore, recommended
that the above procedures should be
taken to wipe out dust and contamination
before using the device.
* Only for color devices
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