FUNCTIONAL BLOCK DIAGRAM FEATURES Dual 12-bit, 3-channel ADC Fast throughput rate: 2 MSPS Specified for VDD of 2.7 V to 5.25 V Low power: 12 mW max at 1.5 MSPS with 3 V supplies 30 mW max at 2 MSPS with 5 V supplies Wide input bandwidth 70 dB SNR at 100 kHz input frequency On-chip reference: 2.5 V –40°C to +125°C operation Flexible power/throughput rate management Simultaneous conversion/read No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible Shutdown mode: 1 µA max 32-lead LFCSP and TQFP packages REF SELECT DCAPA REF BUF MUX T/H The analog input range for the part can be selected to be a 0 V to VREF range or a 2VREF range with either straight binary or twos complement output coding. The AD7266 has an on-chip 2.5 V reference that can be overdriven if an external reference is preferred. This external reference range is 100 mV to 2.5 V. The AD7266 is available in 32-lead lead frame chip scale (LFCSP) and thin quad flat (TQFP) packages. 1 Protected by U.S. Patent No. 6,681,332. AD7266 VA2 VA3 VA4 12-BIT SUCCESSIVE APPROXIMATION ADC OUTPUT DRIVERS VA5 CONTROL LOGIC VB1 VB2 VB3 VB4 DOUTA SCLK CS RANGE SGL/DIFF A0 A1 A2 VA6 VDRIVE MUX T/H 12-BIT SUCCESSIVE APPROXIMATION ADC OUTPUT DRIVERS DOUTB VB6 GENERAL DESCRIPTION The conversion process and data acquisition are controlled using standard control inputs, allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CS; conversion is also initiated at this point. The conversion time is determined by the SCLK frequency. There are no pipelined delays associated with the part. The AD7266 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 5 V supplies and a 2 MSPS throughput rate, the part consumes 4 mA maximum. The part also offers flexible power/throughput rate management when operating in sleep mode. DVDD VA1 VB5 The AD72661 is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 10 MHz. AVDD 04603-PrA-001 Preliminary Technical Data Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC AD7266 BUF AGND AGND AGND DCAPB DGND DGND Figure 1 PRODUCT HIGHLIGHTS 1. The AD7266 features two complete ADC functions that allow simultaneous sampling and conversion of two channels. Each ADC has 2 analog inputs, 3 fully differential pairs, or 6 singleended channels as programmed. The conversion result of both channels is available simultaneously on separate data lines, or in succession on one data line if only one serial port is available. 2. High Throughput with Low Power Consumption The AD7266 offers a 1.5 MSPS throughput rate with 8 mW maximum power consumption when operating at 3 V. 3. Flexible Power/Throughput Rate Management The conversion rate is determined by the serial clock, allowing power consumption to be reduced as conversion time is reduced through an SCLK frequency increase. Power efficiency can be maximized at lower throughput rates if the part enters sleep between conversions. 4. No Pipeline Delay The part features two standard successive approximation ADCs with accurate control of the sampling instant via a CS input and once off conversion control. Rev. PrG Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7266 Preliminary Technical Data TABLE OF CONTENTS AD7266—Specifications.................................................................. 3 Output Coding............................................................................ 11 Timing Specifications .................................................................. 4 Transfer Functions ..................................................................... 12 Absolute Maximum Ratings............................................................ 5 Digital Inputs .............................................................................. 12 ESD Caution.................................................................................. 5 VDRIVE ............................................................................................ 12 Pin Configuration and Functional Descriptions.......................... 6 Modes of Operation ....................................................................... 13 Terminology ...................................................................................... 8 Normal Mode.............................................................................. 13 Theory of Operation ...................................................................... 10 Partial Power-Down Mode ....................................................... 13 Circuit Information.................................................................... 10 Full Power-Down Mode ............................................................ 14 Converter Operation.................................................................. 10 Outline Dimensions ....................................................................... 15 Analog Input ............................................................................... 11 Ordering Guide............................................................................... 17 REVISION HISTORY Revision PrG: Preliminary Version Rev. PrG | Page 2 of 17 Preliminary Technical Data AD7266 AD7266—SPECIFICATIONS1 Table 1. TA = TMIN to TMAX, VDD = 2.7 V to 3.3 V, fSCLK = 25 MHz, fS = 1.5 MSPS, VDRIVE = 2.7 V to 3.3 V; VDD = 4.75 V to 5.25 V, fSCLK = 32 MHz, fS = 2 MSPS, VDRIVE = 2.7 V to 5.25 V; Reference = 2.5 V ± 1%, unless otherwise noted Parameter DYNAMIC PERFORMANCE Specification Unit Test Conditions/Comments Signal-to-Noise + Distortion Ratio (SINAD)2 Total Harmonic Distortion (THD)2 Spurious Free Dynamic Range (SFDR)2 Intermodulation Distortion (IMD)2 Second Order Terms Third Order Terms Channel to Channel Isolation SAMPLE AND HOLD Aperture Delay3 Aperture Jitter3 Aperture Delay Matching3 Full Power Bandwidth 70 –75 –76 dB min dB max dB max fIN = 100 kHz sine wave fIN = 100 kHz sine wave fIN = 100 kHz sine wave –88 –88 –88 dB typ dB typ dB typ 10 50 200 20 2.5 ns max ps typ ps max MHz typ MHz typ 12 ±1 ±1.5 ±0.95 Bits LSB max LSB max LSB max ±3 ±0.5 ±2 ±0.6 LSB max LSB typ LSB max LSB typ ±2 ±3 ±1 ±1 LSB max LSB max LSB typ LSB max DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 0 V to VREF Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × VREF Input Range Positive Gain Error Zero Code Error Zero Code Error Match Negative Gain Error ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capactiance REFERENCE INPUT/OUTPUT Reference Output Voltage4 Reference Input Voltage Range DC Leakage Current Input Capactiance VREF Output Impedance5 Reference Temperature Coefficient LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 @ 3 dB @0.1 dB ±0.5 LSB typ; differential configuration ±0.5 LSB typ; single-ended configuration Guaranteed no missed codes to 12 bits Straight binary output coding Twos complement output coding 0 V to VREF V 0 V to 2 x VREF V ±500 ±1 30 10 nA max µA max pF typ pF typ 2.49/2.51 0.1/2.5 ±30 ±160 20 25 25 10 V min/V max V min/V max µA max µA max pF typ Ω typ ppm/°C max ppm/°C typ 2.8 0.4 ±1 10 V min V max µA max pF max Rev. PrG | Page 3 of 17 RANGE pin low upon CS falling edge RANGE pin high upon CS falling edge TA = –40°C to +85°C 85°C < TA ≤ 125°C When in track When in hold See Typical Performance plots VREF pin DCAPA, DCAPB pins Typically 15 nA, VIN = 0 V or VDRIVE AD7266 Preliminary Technical Data Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance3 Output Coding Specification Unit VDRIVE – 0.2 V min 0.4 V max ±1 µA max 10 pF max Straight (Natural) Binary Twos Complement CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD6 Normal Mode (Static) Operational, fs = 2 MSPS Test Conditions/Comments SGL/DIFF = 1 with 0 V to VREF range selected SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × VREF range 14 100 2 SCLK Cycles ns max MSPS max 437.5 ns with SCLK = 32 MHz 2.7/5.25 2.7/5.25 V min/V max V min/V max 2 6 4 TBD 500 1 mA max mA max mA max mA max µA max µA max VDD = 5 V VDD = 3 V fs = 200 kSPS Static 30 2.5 5 mW max mW max µW max VDD = 5 V VDD = 5 V VDD = 5 V Digital I/Ps = 0 V or VDRIVE Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation6 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down (Static) NOTES 1 Temperature ranges as follows: -40°C to +125°C 2 See Terminology section. 3 Sample tested during initial release to ensure compliance. 4 Relates to Pins DCAPA or DCAPB. 5 See Reference section for DCAPA, DCAPB output impedances. 6 See Power Versus Throughput Rate section. TIMING SPECIFICATIONS Table 2. AVDD = DVDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, TA = TMAX to TMIN, unless otherwise noted Parameter fSCLK tQUIET Limit at TMIN, TMAX 10 34 14 × tSCLK 437.5 560 35 Unit kHz min MHz max ns max ns max ns max ns max t2 10 ns min t3 25 ns max t4 t5 t6 t7 t8 25 0.4tSCLK 0.4tSCLK 5 25 ns max ns min ns min ns min ns max t9 60 ns min t10 5 30 ns min ns max tCONVERT Description tSCLK = 1/fSCLK fSCLK = 32 MHz, VDD = 5 V, FSAMPLE = 2 MSPS fSCLK = 25 MHz, VDD = 3 V, FSAMPLE = 1.5 MSPS Minimum time between end of serial read and next falling edge of CS CS to SCLK setup time Delay from CS until DOUTA and DOUTB are three-state disabled Data access time after SCLK falling edge. SCLK low pulse width SCLK high pulse width SCLK to data valid hold time CS rising edge to DOUTA, DOUTB, high impedance CS rising edge to falling edge pulsewidth SCLK falling edge to DOUTA, DOUTB, high impedance SCLK falling edge to DOUTA, DOUTB, high impedance All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. Rev. PrG | Page 4 of 17 Preliminary Technical Data AD7266 ABSOLUTE MAXIMUM RATINGS Table 3. AD7266 Stress Ratings Parameter VDD to AGND DVDD to DGND VDRIVE to DGND VDRIVE to AGND AVDD to DVDD AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND VREF to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow Temperature (10- 30 sec) ESD 1 Rating –0.3 V to +7 V –0.3 V to +7 V –0.3 V to DVDD –0.3 V to AVDD –0.3 V to +0.3 V –0.3 V to +0.3 V –0.3 V to AVDD +0.3 V –0.3 V to +7 V –0.3 V to VDRIVE +0.3 V –0.3 V to AVDD +0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. –40°C to +125°C –65°C to +150°C 150°C 108.2°C/W 32.71°C/W 255°C TBD Transient currents of up to 100 mA will not cause SCR latch up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrG | Page 5 of 17 AD7266 Preliminary Technical Data DVDD VDRIVE DOUTA DGND DOUTB SCLK CS A0 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS 32 31 30 29 28 27 26 25 DGND 1 24 A1 REF SELECT 2 23 A2 AVDD 3 22 SGL/DIFF DCAPA 4 AD7266 21 RANGE AGND 5 TOP VIEW (Not to Scale) 20 DCAPB 10 11 12 13 14 15 16 VB5 VB4 VB3 VA3 9 VB6 17 VB2 VA6 VA2 8 VA5 18 VB1 VA4 VA1 19 AGND 7 04603-PrA-002 AGND 6 Figure 2. AD7266 Pin Configuration Table 4. AD7266 Pin Function Descriptions Pin No. 4, 20 Mnemonic DCAPA, DCAPB 7–12 VA1–VA6 18–13 VB1–VB6 27 SCLK 5, 6, 19 AGND 32 DVDD 31 VDRIVE 1, 29 DGND 3 AVDD 26 CS 30, 28 DOUTA, DOUTB Description Decoupling capacitors (470nF recommended) are connected to these pins to decouple the reference buffer for each respective ADC. The on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the external reference is dependent on the analog input range selected. See the Reference Configuration Options section. Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog input channel pairs. See Table 6. Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7266. This clock is also used as the clock source for the conversion process. Analog Ground. Ground reference point for all analog circuitry on the AD7266. All analog input signals and any external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7266. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND. Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate. This pin should be decoupled to DGND. The voltage at this pin may be different to that at AVDD and DVDD but should never exceed either by more than 0.3 V. Digital Ground. This is the ground reference point for all digital circuitry on the AD7266. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7266. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7266 and frames the serial data transfer. Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins simultaneously from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits of data. If CS is held low for a further 16 SCLK cycles after this on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB alone using only one serial port. See the Serial Interface section. Rev. PrG | Page 6 of 17 Preliminary Technical Data Pin No. 21 Mnemonic RANGE 25–23 A0–A2 22 SGL/DIFF 2 REF SELECT AD7266 Description Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog input channels will have. On the falling edge of CS , the polarity of this pin is checked to determine the analog input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin is tied to a logic high when CS goes low, the analog input range is 2 × VREF. Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of channels selected may be two single ended channels or two differential pairs. The logic states of these pins are checked upon the falling edge of CS, and the multiplexer is set up for the next conversion. See Table 6 for multiplexer address decoding. Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic low selects differential operation while a logic high selects single ended operation. Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pins DCAPA and DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7266 through the DCAPA and/or DCAPB pins. Rev. PrG | Page 7 of 17 AD7266 Preliminary Technical Data TERMINOLOGY Differential Nonlinearity Track-and-Hold Acquisition Time This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. The track-and-hold amplifier returns into track mode after the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Offset Error This applies to Straight Binary output coding. It is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 1 LSB. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Offset Error Match Signal to (Noise + Distortion) = (6.02N + 1.76) dB This is the difference in Offset Error between the two channels. Thus for a 12-bit converter, this is 74 dB. Gain Error Total Harmonic Distortion This applies to Straight Binary output coding. It is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted out. Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7266 it is defined as: THD(dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 Gain Error Match This is the difference in Gain Error between the two channels. Zero Code Error This applies when using twos complement output coding in particular with the 2 x VREF input range as –VREF to +VREF biased about the VREF point. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, i.e., VREF - 1 LSB. Zero Code Error Match This refers to the difference in Zero Code Error between the two channels. V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Channel-to-Channel Isolation Positive Gain Error This applies when using twos complement output coding in particular with the 2 x VREF input range as –VREF to +VREF biased about the VREF point. It is the deviation of the last code transition (011…110) to (011…111) from the ideal (i.e., + VREF 1 LSB) after the Zero Code Error has been adjusted out. Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale (2 x VREF), 455kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 10 kHz signal (0 V to VREF). The figure given is the worst-case across all twelve channels for the AD7266. Rev. PrG | Page 8 of 17 Preliminary Technical Data AD7266 Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7266 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. PSR (Power Supply Rejection) Variations in power supply will affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See Typical Performance Curves. Rev. PrG | Page 9 of 17 AD7266 Preliminary Technical Data THEORY OF OPERATION CIRCUIT INFORMATION CAPACITIVE DAC The AD7266 is a fast, micropower, dual 12-bit, single supply, A/D converter that operates from a 2.7 V to 5.25 V supply. When operated from a 5 V supply, the AD7266 is capable of throughput rates of 2 MSPS when provided with a TBD MHz clock, and a throughput rate of 1.5 MSPS at 3 V. The AD7266 also features power-down options to allow power saving between conversions. The power-down feature is implemented across the standard serial interface, as described in the Modes of Operation section. VIN– A SW1 A SW2 CS COMPARATOR CONTROL LOGIC SW3 B VREF CAPACITIVE DAC 04603-PrA-003 The AD7266 contains two on-chip differential track-and-hold amplifiers, two successive approximation A/D converters, and a serial interface with two separate data output pins, and is housed in a 32-lead LFCSP package, which offers the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part but also provides the clock source for each successive approximation ADC. The analog input range for the part can be selected to be a 0 V to VREF input or a 2 × VREF input with the analog inputs configured as either single ended or differential. The AD7266 has an on-chip 2.5 V reference that can be overdriven if an external reference is preferred. CS B VIN+ Figure 3. ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW3 opens and SW1 and SW2 move to position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN– pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors. CONVERTER OPERATION CAPACITIVE DAC CS B VIN+ VIN– A SW1 A SW2 CS COMPARATOR CONTROL LOGIC SW3 B VREF CAPACITIVE DAC Figure 4. ADC Conversion Phase Rev. PrG | Page 10 of 17 04603-PrA-004 The AD7266 has two successive approximation analog-todigital converters, each based around two capacitive DACs. Figure 3 and Figure 4 show simplified schematics of one of these ADCs in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW3, is closed, SW1 and SW2 are in position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. Preliminary Technical Data AD7266 ANALOG INPUT The analog inputs of the AD7266 may be configured as single ended or true differential via the SGL/DIFF logic pin, as shown in Figure 5. On the falling edge of CS, point A, the logic level of the SGL/DIFF pin is checked to determine the configuration of the analog input channels for the next conversion. If this pin is tied to a logic low, the analog input channels to each on-chip ADC are set up as three true differential pairs. If this pin is at a logic high when CS goes low, the analog input channels to each on-chip ADC are set up as six single-ended analog inputs. In Figure 5 at point A, the SGL/DIFF pin is at a logic high so the analog inputs are configured as single-ended for the next conversion, i.e. sampling point B. At point B, the logic level of the SGL/DIFF pin has changed to low; there fore, the analog inputs are configured as differential for the next conversion after this one, even though this current conversion is on single ended configured inputs. CS 1 14 1 14 04603-PrA-005 SCLK SGL/DIFF The analog input range of the AD7266 can be selected as 0 V to VREF or 0 V to 2 × VREF via the RANGE pin. This selection is made in a similar fashion to that of the SGL/DIFF pin by checking the logic state of the RANGE pin upon the falling edge of CS. The analog input range is set up for the next conversion. If this pin is tied to a logic low upon the falling edge of CS, the analog input range for the next conversion is 0 V to VREF. If this pin is tied to a logic high upon the falling edge of CS, the analog input range for the next conversion is 0 V to 2 × VREF. OUTPUT CODING The AD7266 output coding is set to either twos complement or straight binary depending on which analog input configuration is selected for a conversion. Table 5 shows which output coding scheme is used for each possible analog input configuration. B A The channels to be converted on simultaneously are selected via the multiplexer address inputs A0 to A2. The logic states of these pins are also checked upon the falling edge of CS and the channels are chosen for the next conversion. The selected input channels are decoded as shown in Table 6. Figure 5. Selecting Differential or Single Ended Configuration Table 5 AD7266 Output Coding SGL/DIFF DIFF DIFF SGL SGL PSUEDO DIFF PSUEDO DIFF Range Output Coding 0 V to VREF 0 V to 2 × VREF 0 V to VREF 0 V to 2 × VREF 0 V to VREF 0 V to 2 × VREF Twos Complement Twos Complement Straight Binary Twos Complement Straight Binary Twos Complement Table 6. Analog Input Type and Channel Selection SGL/DIFF 1 1 1 1 1 1 0 0 0 0 0 0 A2 0 0 0 0 1 1 0 0 0 0 1 1 A1 0 0 1 1 0 0 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 VIN+ VA1 VA2 VA3 VA4 VA5 VA6 VA1 VA1 VA3 VA3 VA5 VA5 ADC A VIN– AGND AGND AGND AGND AGND AGND VA2 VA2 VA4 VA4 VA6 VA6 VIN+ VB1 VB2 VB3 VB4 VB5 VB6 VB1 VB1 VB3 VB3 VB5 VB5 Rev. PrG | Page 11 of 17 ADC B VIN– AGND AGND AGND AGND AGND AGND VB2 VB2 VB4 VB4 VB6 VB6 Comment Single Ended Single Ended Single Ended Single Ended Single Ended Single Ended Fully Differential Pseudodifferential Fully Differential Pseudodifferential Fully Differential Pseudodifferential AD7266 Preliminary Technical Data TRANSFER FUNCTIONS DIGITAL INPUTS The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristic for the AD7266 when straight binary coding is output is shown in Figure 6, and the ideal transfer characteristic for the AD7266 when twos complement coding is output is shown in Figure 7. The digital inputs applied to the AD7266 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. See the Absolute Maximum Ratings. Another advantage of SCLK, RANGE, A0–A2, and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If one of these digital inputs is applied before VDD, there is no risk of latch-up, as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to VDD. 111...111 ADC CODE 111...110 VDRIVE 111...000 1LSB = VREF/4096 011...111 000...010 000...000 VREF – 1LSB 0V 1LSB ANALOG INPUT 04603-PrA-006 000...001 The AD7266 also has the VDRIVE feature, which controls the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7266 was operated with a VDD of 5 V, the VDRIVE pin could be powered from a 3 V supply, allowing a large dynamic range with low voltage digital processors. For example, the AD7266 could be used with the 2 × VREF input range, with a VDD of 5 V while still being able to interface to 3 V digital parts. Figure 6. Straight Binary Transfer Characteristic 1LSB = 2 × VREF/4096 011...111 ADC CODE 011...110 000...001 000...000 111...111 100...010 100...000 –VREF + 1LSB VREF – 1LSB +VREF – 1 LSB ANALOG INPUT 04603-PrA-007 100...001 Figure 7. Twos Complement Transfer Characteristic with VREF ±VREF Input Range Rev. PrG | Page 12 of 17 Preliminary Technical Data AD7266 MODES OF OPERATION NORMAL MODE This mode is intended for fastest throughput rate performance since the user does not have to worry about any power-up times with the AD7266 remaining fully powered all the time. Figure 8 shows the general diagram of the operation of the AD7266 in this mode. CS 1 10 14 DOUTA DOUTB LEADING ZERO, I.D. BIT + CONVERSION RESULT 04603-PrA-008 SCLK Figure 8. Normal Mode Operation The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge but before the 14th SCLK falling edge, the part remains powered up but the conversion is terminated and DOUTA and DOUTB go back into three-state. Fourteen serial clock cycles are required to complete the conversion and access the conversion result. The DOUT line does not return to three-state after 14 SCLK cycles have elapsed, but instead does so when CS is brought high again. If CS is left low for another 2 SCLK cycles (e.g. if only a 16 SCLK burst is available), two trailing zeros are clocked out after the data. If CS is left low for a further 16 SCLK cycles again, the result from the other ADC on board is also accessed on the same DOUT line, as shown in Figure TBD (see the Serial Interface section). The identification bit provided prior to each conversion result identifies which on-board ADC the following result is from. Once 32 SCLK cycles have elapsed, the DOUT line returns to three-state on the 32nd SCLK falling edge. If CS is brought high prior to this, the DOUT line returns to three-state at that point. Thus, CS may idle low after 32 SCLK cycles until it is brought high again sometime prior to the next conversion (effectively idling CS low), if so desired, since the bus still returns to three-state upon completion of the dual result read. Once a data transfer is complete and DOUTA and DOUTB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. PARTIAL POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7266 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer. To enter partial power-down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 9. Once CS has been brought high in this window of SCLKs, the part enters partial power-down, the conversion that was initiated by the falling edge of CS is terminated, and DOUTA and DOUTB go back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. CS 1 2 10 14 SCLK DOUTA TRI-STATE DOUTB Rev. PrG | Page 13 of 17 Figure 9. Entering Partial Power-Down Mode 04603-PrA-009 The mode of operation of the AD7266 is selected by controlling the (logic) state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial powerdown mode, and full power-down mode. The point at which CS is pulled high after the conversion has been initiated determines which power-down mode, if any, the device enters. Similarly, if already in a power-down mode, CS can control whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. AD7266 Preliminary Technical Data AD7266 is in full power-down, all analog circuitry is powered down. Full power-down is entered in a similar way as partial power-down, except the timing sequence shown in Figure 9 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK. The device enters partial power-down at this point. To reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in Figure TBD. Once CS has been brought high in this window of SCLKs, the part powers down completely. To exit this mode of operation and power up the AD7266 again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after approximately 1 µs has elapsed, and valid data results from the next conversion, as shown in Figure 10. If CS is brought high before the second falling edge of SCLK, the AD7266 again goes into partial powerdown. This avoids accidental power-up due to glitches on the CS line. Although the device may begin to power up on the falling edge of CS, it powers down again on the rising edge of CS. If the AD7266 is already in partial power-down mode and CS is brought high between the second and 10th falling edges of SCLK, the device enters full power-down mode. Note that it is not necessary to complete the 14 SCLKs once CS has been brought high to enter a power-down mode. To exit full power-down and power the AD7266 up again, a dummy conversion is performed, as when powering up from partial power-down. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The power-up time required must elapse before a conversion can be initiated, as shown in Figure TBD. See the Power-Up Times section for the power-up times associated with the AD7266. FULL POWER-DOWN MODE This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substantially longer than that from partial power-down. This mode is more suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus power-down. When the THE PART BEGINS TO POWER-UP THE PART IS FULLY POWERED UP, SEE POWER-UP TIMES SECTION TPOWER-UP CS 1 10 14 1 14 A DOUTA DOUTB INVALID DATA VALID DATA Figure 10. Exiting Partial Power-Down Mode Rev. PrG | Page 14 of 17 04603-PrA-010 SCLK Preliminary Technical Data AD7266 SERIAL INTERFACE for DOUTA is shown. Note that in this case, the DOUT line in use will go back into three-state on the 32nd SCLK falling edge or the rising edge of CS, whichever occurs first. Figure 11 shows the detailed timing diagram for serial interfacing to the AD7266. The serial clock provides the conversion clock and controls the transfer of information from the AD7266 during conversion. A minimum of fourteen serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the AD7266. CS going low provides the leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with a second leading zero. Thus the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The 12 bit result then follows with the final bit in the data transfer valid on the fourteenth falling edge, having being clocked out on the previous (thirteenth) falling edge. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge depending on the SCLK frequency used, i.e., the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the thirteenth rising SCLK edge would have DB0 provided. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode and takes the bus out of three-state; the analog input is sampled at this point. The conversion is also initiated at this point and requires a minimum of 14 SCLKs to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold will go back into track on the next SCLK rising edge, as shown in Figure 11 at point B. If a 16 SCK transfer is used then 2 trailing zeros will appear after the final LSB. On the rising edge of CS, the conversion will be terminated and DOUTA and DOUTB will go back into three-state. If CS is not brought high but is instead held low for a further 14 (or 16) SCLK cycles on DOUTA, the data from conversion B will be output on DOUTA (followed by 2 trailing zeros). Likewise, if CS is held low for a further 14 (or 16) SCLK cycles on DOUTB, the data from conversion A will be output on DOUTB. This is illustrated in Figure 12 where the case +5 t2 SCLK t6 1 3 2 4 5 13 14 t5 DOUTA DOUTB 3-STATE 0 0 DB11 DB10 DB9 DB2 DB8 tquiet t8 t7 t4 t3 t9 B DB1 DB0 3-STATE 2 Leading Zeros Figure 11 Serial Interface Timing Diagram +5 t2 SCLK t6 1 3 2 4 5 14 17 16 15 32 t5 t4 t3 DOUTA 3-STATE 0 ZERO 2 Leading Zeros, DB11A DB10A DB9A t10 t7 ZERO ZERO 2 Traiing Zeros, ZERO ZERO DB11B 2 Leading Zeros, Figure 12. Reading data from Both ADCs on One DOUT Line with 32 SCLKs Rev. PrG | Page 15 of 17 ZERO ZERO 3-STATE 2 Traiing Zeros, AD7266 Preliminary Technical Data OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.60 MAX 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 1.00 0.85 0.80 17 16 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.30 0.23 0.18 3.25 3.10 SQ 2.95 9 0.05 MAX 0.02 NOM SEATING PLANE 1 BOTTOM VIEW 0.50 0.40 0.30 12° MAX 32 COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 13. 32-Lead Frame Chip Scale Package [LFCSP (CP-32) Dimensions shown in millimeters 1.20 MAX 9.00 SQ 0.75 0.60 0.45 24 17 16 25 TOP VIEW 7.00 SQ (PINS DOWN) 32 9 1 0.15 0.05 8 0.80 BSC 1.05 1.00 0.95 0.45 0.37 0.30 7° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-026ABA Figure 14. 32-Lead Thin Flat Quad Package [TQFP] (SU-32) Dimensions shown in millimeters Rev. PrG | Page 16 of 17 Preliminary Technical Data AD7266 ORDERING GUIDE AD7266 Products AD7266ACP AD7266BCP AD7266ASU AD7266BSU EVAL-AD7266CB1 EVAL-CONTROL BRD22 1 2 Temperature Package –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description Lead Frame Chip Scale Package Lead Frame Chip Scale Package Thin Quad Flat Package Thin Quad Flat Package Evaluation Board Controller Board Package Outline CP-32 CP-32 SU-32 SU-32 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes. This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7266CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation Board Technical note for more information. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04603–0–4/04(PrG) Rev. PrG | Page 17 of 17