AD ADV7196

a
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs,
10-Bit Data Input, and Macrovision
ADV7196A
FEATURES
INPUT FORMATS
YCrCb in 2 10-Bit (4:2:2) or 3 10-Bit (4:4:4) Format
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p) and
Any Other High Definition Standard Using Async
Timing Mode
RGB in 3 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit and Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay ()
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2 Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
I2C® Filter
VBI Open Control
Macrovision Rev. 1.0 (525p)
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
DVD Players
MPEG 2 at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7196A is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
FUNCTIONAL BLOCK DIAGRAM
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
ADV7196A
CGMS
MACROVISION
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
TEST PATTERN
GENERATOR
AND
DELAY
AND
GAMMA
CORRECTION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
LUMA
SSAF
2 INTERPOLATION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
11-BIT+
SYNC
DAC
DAC A (Y)
11-BIT
DAC
DAC B
11-BIT
DAC
DAC C
SYNC
GENERATOR
TIMING
GENERATOR
I2C MPU
PORT
DAC CONTROL
BLOCK
VREF
RESET
COMP
The ADV7196A has three separate 10-bit-wide input ports which
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE 293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can be
used to input data to the ADV7196A. For all standards, external
horizontal, vertical, and blanking signals or EAV/SAV codes control
the insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
The ADV7196A outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7196A requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used, allows
removal of ringing on the incoming Y data. The ADV7196A
supports CGMS-A data control generation and the Macrovision
Anticopy algorithm in 525p mode.
The ADV7196A is packaged in a 52-lead MQFP package.
I2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADV7196A
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 V DYNAMIC–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 4
3.3 V TIMING–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10
Y/CrCb Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
54 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PROGRAMMABLE SHARPNESS FILTER . . . . . . . . . . . 10
PROGRAMMABLE ADAPTIVE FILTER CONTROL . . 10
Input/Output Configuration . . . . . . . . . . . . . . . . . . . . . . . 11
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 11
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 13
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 13
Register Select (SR6–SR0) . . . . . . . . . . . . . . . . . . . . . . . . 13
PROGRESSIVE SCAN MODE . . . . . . . . . . . . . . . . . . . . . 14
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Standard Selection (MR00–MR01) . . . . . . . . . . . 14
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . . 14
Input Standard (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reserved (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Macrovision (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 16
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 16
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Undershoot Limiter (MR15–MR16) . . . . . . . . . . . . . . . . 16
Sharpness Filter (MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 16
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 17
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . . 17
CGMS Enable (MR26) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CGMS CRC (MR27) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
–2–
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . .
Interpolation (MR36) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . .
Gamma Curve (MR54) . . . . . . . . . . . . . . . . . . . . . . . . . .
Gamma Correction (MR55) . . . . . . . . . . . . . . . . . . . . . .
Adaptive Mode Control (MR56) . . . . . . . . . . . . . . . . . . .
Adaptive Filter Control (MR57) . . . . . . . . . . . . . . . . . . .
COLOR Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CY (CY7–CY0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COLOR CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCR (CCR7–CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COLOR CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCB (CCB7–CCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR6 (MR67–MR60) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR6 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
MR67–MR60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CGMS DATA REGISTERS 2–0 . . . . . . . . . . . . . . . . . . . .
CGMS2 (CGMS27–CGMS20) . . . . . . . . . . . . . . . . . . . .
CGMS1 (CGMS17–CGMS10) . . . . . . . . . . . . . . . . . . . .
CGMS0 (CGMS07–CGMS00) . . . . . . . . . . . . . . . . . . . .
FILTER GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FG (FG7–FG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FG BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Gain A (FG3–FG0) . . . . . . . . . . . . . . . . . . . . . . . .
Filter Gain B (FG4–FG7) . . . . . . . . . . . . . . . . . . . . . . . .
GAMMA CORRECTION REGISTERS 0–13 . . . . . . . . . .
(GAMMA CORRECTION 0–13) . . . . . . . . . . . . . . . . . .
SHARPNESS FILTER CONTROL AND
ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . .
SHARPNESS FILTER MODE . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER MODE . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER GAIN 1 . . . . . . . . . . . . . . . . . . . . . .
AFG1 (AFG1)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER GAIN 2 . . . . . . . . . . . . . . . . . . . . . .
AFG2 (AFG2)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
19
19
20
20
20
20
20
20
20
20
21
21
21
21
21
21
21
22
22
22
23
23
23
23
REV. 0
ADV7196A
ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . .
AFG3 (AFG3)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . .
AFTA (AFTA)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . .
AFTB (AFTB)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . .
AFTC (AFTC)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . .
Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . .
Adaptive Filter Control Application . . . . . . . . . . . . . . . . .
HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HEXMR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . .
Output Standard Selection (MR00–MR01) . . . . . . . . . . .
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . .
Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . .
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . .
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . .
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . .
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR15–MR17) . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . .
REV. 0
23
23
23
23
23
23
23
23
24
24
25
26
26
26
26
26
26
26
26
26
26
27
27
27
27
27
27
27
27
27
28
28
28
28
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR26–MR27) . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR36–MR37) . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . .
Reserved (MR54–MR57) . . . . . . . . . . . . . . . . . . . . . . . . .
DAC TERMINATION AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . .
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
Video Output Buffer and Optional Output Filter . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .
–3–
28
28
28
28
28
28
28
28
28
28
28
29
29
29
29
29
29
29
29
29
29
29
29
30
30
30
31
31
31
31
36
ADV7196A–SPECIFICATIONS
3.3 V SPECIFICATIONS
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications TMIN to TMAX
(0C to 70C) unless otherwise noted.)
Parameter
Min
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL OUTPUTS
Output High Voltage, VOL
Output Low Voltage, VOH
Three State Leakage Current
Three State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
Input Capacitance, CIN
Typ
11
1.5
0.9
Max
Unit
2.0
Bits
LSB
LSB
0.4
2.4
10
4
2
V
V
µA
pF
V
V
µA
pF
0.8
0
4
0.65
1
4.25
4.25
2.83
2.66
1.4
1.4
100
7
4.56
4.56
3.11
2.93
mA
mA
mA
mA
%
V
kΩ
pF
1.235
1.359
V
25
51
40
35
60
mA
mA
mA
IAA3, 4
11
15
mA
IPLL
6.0
12
mA
Power Supply Rejection Ratio
0.01
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
Full-Scale Output Current
Output Current Range
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE (External)
Reference Range, VREF
3.92
3.92
2.54
2.39
0
1.112
POWER REQUIREMENTS
IDD2
IDD2
IDD2
Test Conditions
ISINK = 3.2 mA
ISOURCE = 400 µA
VIN = 0.4 V
VIN = 0.0 V or VDD
DAC A
DAC A
DAC B, C
DAC B, C
1× Interpolation
2× Interpolation
HDTV Mode
(with fCLK = 74.25 MHz)
1× Interpolation, 2× Interpolation, and HDTV Mode
1× Interpolation, 2× Interpolation, and HDTV Mode
%/%
NOTES
1
Guaranteed by characterization.
2
IDD or the circuit current is the continuous current required to drive the digital core without I PLL.
3
IAA is the total current required to supply all DACs including the V REF circuitry.
4
All DACs on.
Specifications subject to change without notice.
3 V DYNAMIC–SPECIFICATIONS
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications
TMIN to TMAX (0C to 70C) unless otherwise noted.)
Parameter
Min
Luma Bandwidth
Chroma Bandwidth
Signal-to-Noise Ratio
Chroma/Luma Delay Inequality
Typ
13.5
6.75
64
0
Max
Unit
MHz
MHz
dB Luma Ramp Unweighted
ns
Specifications subject to change without notice.
–4–
REV. 0
ADV7196A
3.3 V TIMING–SPECIFICATIONS
Parameter
Min
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 , RLOAD = 300 . All specifications
TMIN to TMAX (0C to 70C) unless otherwise noted.)
Typ
Max
Unit
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
Conditions
1
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t 2
Hold Time (Start Condition), t 3
Setup Time (Start Condition), t 4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t 6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t 8
Reset Low Time
0
0.6
1.3
0.6
0.6
100
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay2
Analog Output Skew
CLOCK CONTROL AND PIXEL PORT 3
fCLK
fCLK
fCLK
Clock High Time t9
Clock Low Time t10
Data Setup Time t 11
Data Hold Time t12
Control Setup Time t 11
Control Hold Time t12
Pipeline Delay
Pipeline Delay
10
0.5
ns
ns
27
74.25
81
5.0
5.0
2.0
4.5
7.0
4.0
16
29
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
1.5
2.0
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
Progressive Scan Mode
HDTV Mode
Async Timing Mode and 1× Interpolation
For 4:4:4 Pixel Input Format at 1× Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at 2×
Oversampling
NOTES
1
Guaranteed by characterization.
2
Output delay measured from 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: Cb/Cr [9–0], Cr [9–0], Y [9:0]
Control: HSYNC/SYNC, VSYNC/TSYNC, DV
Specifications subject to change without notice.
REV. 0
–5–
ADV7196A
CLOCK
t9
PIXEL INPUT
DATA
t10
R0
R1
R2
•••
•••
Rxxx
Rxxx
G0
G1
G2
G3
•••
Gxxx
Gxxx
B0
B1
B2
B3
•••
Bxxx
Bxxx
t12
t9 – CLOCK HIGH TIME
t10 – CLOCK LOW TIME
t11 – DATA SETUP TIME
t12 – DATA HOLD TIME
t11
Figure 1. 4:4:4 RGB Input Data Format Timing Diagram
CLOCK
t9
PIXEL INPUT
DATA
t10
Y0
Y1
Y2
•••
•••
Yxxx
Yxxx
Cb0
Cr0
Cb1
Cr1
•••
Cbxxx
Crxxx
t12
t9 – CLOCK HIGH TIME
t10 – CLOCK LOW TIME
t11 – DATA SETUP TIME
t12 – DATA HOLD TIME
t11
Figure 2. 4:2:2 Input Data Format Timing Diagram
CLOCK
t9
PIXEL INPUT
DATA
t10
Y0
Y1
Y2
•••
•••
Yxxx
Yxxx
Cb0
Cb1
Cb2
Cb3
•••
Cbxxx
Cbxxx
Cr0
Cr1
Cr2
Cr3
•••
Crxxx
Crxxx
t12
t9 – CLOCK HIGH TIME
t10 – CLOCK LOW TIME
t11 – DATA SETUP TIME
t12 – DATA HOLD TIME
t11
Figure 3. 4:4:4 YCrCb Input Data Format Timing Diagram
–6–
REV. 0
ADV7196A
HSYNC
VSYNC
A
DV
PIXEL
DATA
Y
Y
Y
Y
Cr
Cr
Cr
Cr
Cb
Cb
Cb
Cb
B
AMIN = 16 CLKCYCLES (525P)
BMIN = 122 CLKCYCLES (525P)
AMIN = 12 CLKCYCLES (625P)
BMIN = 132 CLKCYCLES (625P)
AMIN = 44 CLKCYCLES (1080I)
BMIN = 236 CLKCYCLES (1080I)
AMIN = 70 CLKCYCLES (720P)
BMIN = 300 CLKCYCLES (720P)
Figure 4. Input Timing Diagram
t5
t3
t3
SDA
t6
t1
SCL
t2
t7
t4
Figure 5. MPU Port Timing Diagram
REV. 0
–7–
t8
ADV7196A
ABSOLUTE MAXIMUM RATINGS 1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . 225°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADV7196AKS
0°C to 70°C
Plastic Quad Flatpack (MQFP)
S-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADV7196A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
RESET
ALSB
Cb/Cr[9]
Cb/Cr[8]
Cb/Cr[7]
Cb/Cr[6]
Cb/Cr[5]
Cb/Cr[4]
Cb/Cr[3]
Cb/Cr[2]
Cb/Cr[1]
Cb/Cr[0]
GND
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
VDD
Y[0] 2
1
39 VREF
38 RSET
PIN 1
IDENTIFIER
Y[1] 3
37 COMP
Y[2] 4
36 DAC B
Y[3] 5
Y[4] 6
ADV7196A
Y[5] 7
TOP VIEW
(Not to Scale)
Y[6] 8
35 V
AA
34 DAC A
33 AGND
32 DAC C
Y[7] 9
31 SDA
Y[8] 10
30 SCL
Y[9] 11
29 HSYNC/SYNC
VDD 12
28 VSYNC/TSYNC
27 DV
GND 13
–8–
AGND
CLKIN
VAA
Cr[9]
Cr[8]
Cr[7]
Cr[6]
Cr[5]
Cr[4]
Cr[3]
Cr[2]
Cr[1]
Cr[0]
14 15 16 17 18 19 20 21 22 23 24 25 26
REV. 0
ADV7196A
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Input/Output
Function
1, 12
2–11
VDD
Y0–Y9
P
I
13, 52
14–23
GND
Cr0–Cr9
G
I
24, 35
25
VAA
CLKIN
P
I
26, 33
27
28
G
I
I
30
31
32
34
36
37
38
AGND
DV
VSYNC/
TSYNC
HSYNC/
SYNC
SCL
SDA
DAC C
DAC A
DAC B
COMP
RSET
Digital Power Supply
10-Bit Progressive Scan/HDTV Input Port for Y Data. Input for G data when
RGB data is input.
Digital Ground
10-Bit Progressive Scan/HDTV Input Port for Color Data in 4:4:4 Input Mode.
In 4:2:2 mode this input port is not used. Input port for R data when RGB data
is input.
Analog Power Supply
Pixel Clock Input. Requires a 27 MHz reference clock for standard operation in
Progressive Scan Mode or a 74.25 MHz (74.1758 MHz) reference clock in
HDTV mode.
Analog Ground
Video Blanking Control Signal Input
VSYNC, Vertical Sync Control Signal Input or TSYNC Input Control Signal in
Async Timing Mode
HSYNC, Horizontal Sync Control Signal Input or SYNC Input Control Signal in
39
VREF
I/O
40
RESET
I
41
ALSB
I
42–51
Cb/Cr9–0
I
29
REV. 0
I
Async Timing Mode
I
I/O
O
O
O
O
I
MPU Port Serial Interface Clock Input
MPU Port Serial Data Input/Output
Color Component Analog Output of Input Data on Cb/Cr9–0 Input Pins
Y Analog Output
Color Component Analog Output of Input Data on Cr9–Cr0 Input Pins
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA.
A 2470 Ω resistor (for input ranges 64–940 and 64–960; output standards
EIA-770.1–EIA-770.3) must be connected from this pin to ground and is used to
control the amplitudes of the DAC outputs. For input ranges 0–1023 (output
standards RS-170, RS-343A) the RSET value must be 2820 Ω.
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
This input resets the on-chip timing generator and sets the ADV7196A into
Default Register setting. Reset is an active low signal.
TTL Address Input. This signal sets up the LSB of the MPU address. When this
pin is tied high, the I2C filter is activated which reduces noise on the I2C interface.
When this pin is tied low, the input bandwidth on the I2C interface is increased.
10-Bit Progressive Scan/HDTV Input Port for Color Data. In 4:2:2 mode the
multiplexed CrCb data must be input on these pins. Input port for B data when
RGB is input.
–9–
ADV7196A
FUNCTIONAL DESCRIPTION
Digital Inputs
Analog Outputs
The digital inputs of the ADV7196A are TTL compatible. 30-bit
YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel
data in 4:2:2 format is latched into the device on the rising edge
of each clock cycle at 74.25 MHz or 74.1758 in HDTV mode.
It is also possible to input 3 × 10 bit RGB data in 4:4:4 to the
ADV7196A. It is recommended to input data in 4:2:2 mode to
make use of the Chroma SSAFs on the ADV7196A. As can be
seen in the figure below, this filter has a 0 dB pass band response
and prevents signal components being folded back in to the frequency band. In 4:4:4: input mode, the video data is already
interpolated by the external input device and the Chroma SSAFs
of the ADV7196A are bypassed.
ATTEN 10dB
RL –10.0dBm
VAVG
1
10dB/
The analog Y signal is output on the 11-Bit + Sync DAC A,
the color component analog signals on the 11-Bit DACs B, C
conforming to EIA-770.1 or EIA-770.2 standards in PS mode
or EIA-770.3 in HDTV mode. RSET has a value of 2470 Ω
(EIA-770.1, EIA-770.2, EIA-770.3), RLOAD has a value of 300 Ω.
For RGB outputs conforming to RS-170/RS-343A output standards
RSET must have a value of 2820 Ω.
I2C Filters
A selectable internal I2C filter allows significant noise reduction
on the I2C interface. In setting ALSB high, the input bandwidth
on the I2C lines is reduced and pulses of less than 50 ns are not
passed to the I2C controller. Setting ALSB low allows greater
input bandwidth on the I2C lines.
Undershoot Limiter
MKR
0dB
3.18MHz
A limiter can be applied to the Y data before it is applied to the DACs.
Available limit values are –1.5 IRE, –6 IRE, –11 IRE below blanking. This functionality is available in Progressive Scan mode only.
Internal Test Pattern Generator
The ADV7196A can generate a cross-hatch pattern (white lines
against a black background). Additionally, the ADV7196A can
output a uniform color pattern. The color of the lines or uniform
field/frame can be programmed by the user.
Y/CrCb Delay
The Y output and the color component outputs can be delayed
wrt the falling edge of the horizontal sync signal by up to four
clock cycles.
Gamma Correction
START 100kHz
RBW 10kHz
STOP
VBW 300Hz
20.00MHz
SWP 17.0SEC
Figure 6. ADV7196A SSAF Response to a 2.5 MHz Chroma
Sweep Using 4:2:2 Input Mode
ATTEN 10dB
RL –10.0dBm
VAVG
4
10dB/
Gamma correction may be performed on the luma data. The
user has the choice to use either of two different gamma curves,
A or B. At any one time one of these curves is operational if gamma
correction is enabled. Gamma correction allows the mapping of
the luma data to a user-defined function.
54 MHz Operation
MKR
–3.00dB
3.12MHz
In Progressive Scan mode, it is possible to operate the three output DACs at 54 MHz or 27 MHz. The ADV7196A is supplied
with a 27 MHz clock synced with the incoming data. If required, a
second stage interpolation filter interpolates the data to 54 MHz
before it is applied to the three output DACs. The second stage
interpolation filter is controlled by MR36. After applying a
Reset it is recommended to toggle this bit. Before toggling this bit,
3Ehex must be written to address 09hex.
PROGRAMMABLE SHARPNESS FILTER
START 100kHz
RBW 10kHz
STOP
VBW
300Hz
Sharpness Filter Mode is applicable to the Y data only in Progressive Scan mode. The desired frequency response can be chosen
by the user in programming the correct value via the I2C. The
variation of frequency responses can be seen in the figures on the
following pages.
20.00MHz
SWP
17.0SEC
Figure 7. Conventional Filter Response to a 2.5 MHz Chroma
Sweep Using 4:4:4 Input Mode
Control Signals
The ADV7196A accepts sync control signals accompanied by
valid 4:2:2 or 4:4:4 data. These external horizontal, vertical and
blanking pulses (or EAV/SAV codes) control the insertion of
appropriate sync information into the output signals.
PROGRAMMABLE ADAPTIVE FILTER CONTROL
If the Adaptive Filter Mode is enabled (Progressive Scan mode only),
it is possible to compensate for large edge transitions on the
incoming Y data. Sensitivity and attenuation are all programmable over the I2C. For further information refer to Sharpness
Filter Control and Adaptive Filter Control section.
–10–
REV. 0
ADV7196A
10
Input/Output Configuration
Table I shows possible input/output configurations when using
the ADV7196A.
0
–10
Table I.
Input Format
–20
Output
YCrCb Progressive Scan
4:2:2
4:4:4
YCrCb HDTV
4:2:2
4:4:4
RGB Progressive Scan
4:4:4
RGB HDTV
4:4:4
Async Timing Mode
All Inputs
–30
–40
2×
1× or 2×
–50
–60
1×
1×
–70
–80
–10
–20
–30
–40
–50
–60
–70
5
10
15
15
20
25
30
MPU PORT DESCRIPTION
1×
0
0
10
Figure 10. Interpolation Filter – CrCb Channels for 4:4:4
Input Data
1×
10
–80
5
0
2×
20
25
30
The ADV7196A support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data
(SDA) and Serial Clock (SCL), carry information between any
device connected to the bus. Each slave device is recognized by a
unique address. The ADV7196A has four possible slave addresses
for both read and write operations. These are unique addresses
for each device and illustrated in Figure 11. The LSB sets either
a read or write operation. Logic Level “1” corresponds to a read
operation while Logic Level “0” corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7196A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “0,” there is
greater input bandwidth on the I2C lines, which allows highspeed data transfers on this bus. When ALSB is set to “1,” there
is reduced input bandwidth on the I2C lines, which means that
pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
Figure 8. 2× Interpolation Filter – Y-Channel
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
10
0
–10
READ/WRITE
CONTROL
–20
0
1
WRITE
READ
–30
Figure 11. Slave Address
–40
–50
–60
–70
–80
0
5
10
15
20
25
30
Figure 9. Interpolation Filter – CrCb Channels for 4:2:2
Input Data
REV. 0
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a Start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Start condition and shift the next eight bits (7-bit address + R/W
bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the Start condition and the correct transmitted address.
The R/W bit determines the direction of the data.
–11–
ADV7196A
A Logic “0” on the LSB of the first byte means that the master will
write information to the peripheral. A Logic “1” on the LSB of
the first byte means that the master will read information from
the peripheral.
The ADV7196A acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses plus
the R/W bit. It interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses autoincrement allowing data to be written to or read from the starting
subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register
on a one by one basis without having to update all the registers.
SDATA
SCLOCK
SLAVE ADDR A(S)
SUB ADDR
A(S)
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
8
9
1–7
8
9
1–7
DATA
8
9
P
ACK
STOP
Figure 12 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
Figure 13 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7196A except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register the
next read or write operation accesses.
All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is performed from/to the target address which then increments to the
next address until a Stop command on the bus is performed.
DATA
A(S)
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
1–7
Figure 12. Bus Data Transfer
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the
ninth pulse.
S
S
START ADDR R/W ACK SUBADDRESS ACK
Stop and Start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, then these cause an immediate jump to the idle condition. During a given SCL high period
the user should only issue one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition.
If an invalid subaddress is issued by the user, the ADV7196A will
not issue an acknowledge and will return to the idle condition. If
in autoincrement mode, the user exceeds the highest subaddress
then the following action will be taken:
WRITE
SEQUENCE
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7196A and the part will return to the
idle condition.
SUB ADDR
A(S) S
SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 13. Write and Read Sequence
–12–
REV. 0
ADV7196A
REGISTER PROGRAMMING
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation takes place.
The following section describes the functionality of each register.
All registers can be read from as well as written to unless otherwise stated.
Figure 14 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Subaddress Register (SR7–SR0)
Register Select (SR6–SR0)
The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
SR7
SR6
SR5
These bits are set up to point to the required starting address.
SR3
SR4
SR2
SR1
SR0
SR7
ZERO SHOULD
BE WRITTEN
HERE
ADV7196A SUBADDRESS REGISTER
ADDRESS
SR6 SR5
SR4
SR3
SR2
SR1
SR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
COLOR Y
COLOR CR
COLOR CB
MODE REGISTER 6
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FILTER GAIN
CGMS DATA REGISTER 0
CGMS DATA REGISTER 1
CGMS DATA REGISTER 2
GAMMA CORRECTION REGISTER 0
GAMMA CORRECTION REGISTER 1
GAMMA CORRECTION REGISTER 2
GAMMA CORRECTION REGISTER 3
GAMMA CORRECTION REGISTER 4
GAMMA CORRECTION REGISTER 5
GAMMA CORRECTION REGISTER 6
GAMMA CORRECTION REGISTER 7
GAMMA CORRECTION REGISTER 8
GAMMA CORRECTION REGISTER 9
GAMMA CORRECTION REGISTER 10
GAMMA CORRECTION REGISTER 11
GAMMA CORRECTION REGISTER 12
GAMMA CORRECTION REGISTER 13
ADAPTIVE FILTER GAIN 1
ADAPTIVE FILTER GAIN 2
ADAPTIVE FILTER GAIN 3
ADAPTIVE FILTER THRESHOLD A
ADAPTIVE FILTER THRESHOLD B
ADAPTIVE FILTER THRESHOLD C
Figure 14. Subaddress Registers in Progressive Scan Mode
SR7
SR6
SR5
SR7
ZERO SHOULD
BE WRITTEN
HERE
SR3
SR4
SR2
SR1
ADV7196A SUBADDRESS REGISTER
ADDRESS
SR6 SR5
SR4
SR3
SR2
SR1
SR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
COLOR Y
COLOR CR
COLOR CB
Figure 15. Subaddress Registers in HDTV Mode
REV. 0
–13–
SR0
ADV7196A
PROGRESSIVE SCAN MODE
Input Control Signals (MR02–MR03)
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
These control bits are used to select whether data is input with
external horizontal, vertical and blanking sync signals or if the data
is input with embedded EAV/SAV codes.
Figure 16 shows the various operations under the control of
Mode Register 0.
An Asynchronous timing mode is also available using TSYNC,
SYNC and DV as input control signals. These control signals
have to be programmed by the user.
MR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)
Figure 17 shows an example of how to program the ADV7196A to
accept a different high definition standard but SMPTE293M,
SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
These bits are used to select the output levels for the ADV7196A.
If EIA-770.2 (MR01–00 = “00”) is selected the output levels will
be: 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional.
Input Standard (MR04)
Select between 525p progressive scan input or 625p progressive
scan input.
Reserved (MR05)
If EIA-770.1 (MR01–00 = “01”) is selected the output levels will
be: 0 mV for blanking level, 714 mV for peak white for the Y channel, ± 350 mV for Pr, Pb outputs and –286 mV for Sync. Optional
sync insertion on the Pr, Pb channels is not possible.
A “0” must be written to this bit.
DV Polarity (MR06)
This control bit allows to select the polarity of the DV input
control signal to be either active high or active low. This is in
order to facilitate interfacing from I to P Converters which use
an active low blanking signal output.
If Full I/P Range (MR01–00 = “10”) is selected the output levels
will be 0 mV for blanking level, 700 mV for peak white for the Y
channel, ±350 mV for Pr, Pb outputs and –300 mV for Sync. Sync
insertion on the Pr, Pb channels is optional. This mode is used
for RS-170, RS-343A standard output compatibility. Refer to
Appendix for output level plots.
MR07
MR06
MACROVISION
MR07
0
1
DISABLED
ENABLED
MR05
MR05
ZERO MUST
BE WRITTEN
TO THIS BIT
Macrovision (MR07)
To enable Macrovision this bit must be set to “1.”
MR04
MR02
INPUT STANDARD
MR04
0
1
MR01
MR00
INPUT CONTROL SIGNALS
MR03 MR02
525P
625P
HSYNC\VSYNC/DV
EAV/SAV
TSYNC/SYND/DV
RESERVED
0
1
0
1
0
0
1
1
OUTPUT STANDARD SELECTION
DV POLARITY
MR01 MR00
MR06
0
1
MR03
0
0
1
1
ACTIVE HIGH
ACTIVE LOW
0
1
0
1
EIA-770.2
EIA-770.1
FULL I/P RANGE
RESERVED
Figure 16. Mode Register 0
–14–
REV. 0
ADV7196A
Table II must be followed when programming the control signals in Async Timing Mode.
Table II. Truth Table
SYNC
TSYNC
DV
1 –> 0
0
0 or 1
0
0 –> 1
0 or 1
0 –> 1
0 or 1
0
1
1
0 or 1
0 or 1
0 –> 1
1 –> 0
50% Point of Falling Edge of
Tri-Level Horizontal Sync
Signal, A
25% Point of Rising Edge of
Tri-Level Horizontal Sync
Signal, B
50% Point of Falling Edge of
Tri-Level Horizontal Sync
Signal, C
50% Start of Active Video, D
50% End of Active Video, E
CLK
SYNC
PROGRAMMABLE
INPUT TIMING
TSYNC
DV SET
MR06 = 1
HORIZONTAL SYNC
81
66
66
A
B
ACTIVE VIDEO
243
C
ANALOG
OUTPUT
1920
D
E
Figure 17. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility
525
1
12
13
42
VIDEO
OUTPUT
HSYNC
VSYNC
DV
Figure 18. DV Input Control Signal in Relation to Video Output Signal
REV. 0
–15–
43
ADV7196A
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
VBI Open (MR14)
Figure 20 shows the various operations under the control of Mode
Register 1.
For this purpose Lines 13 to 42 of each frame can be used for VBI
when SMPTE293M standard is used, or Lines 6 to 43 when
ITU-R.BT1358 standard is used.
This bit enables or disables the facility of VBI data insertion during
the Vertical Blanking Interval.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
Undershoot Limiter (MR15–MR16)
When this bit is set to “0,” the pixel data input to the ADV7196A
is blanked such that a black screen is output from the DACs. When
this bit is set to “1,” pixel data is accepted at the input pins and
the ADV7196A outputs the standard set in “Output Standard
Selection” (MR01–00). This bit must be set to “1” to enable output of the test pattern signals.
This control limits the Y signal to a programmable level in the active
video region.
Available limit levels are –1.5 IRE, –6 IRE, –11 IRE.
Note that this facility is only available when Interpolation is enabled
(MR36 = “1”).
Input Format (MR11)
Sharpness Filter (MR17)
It is possible to input data in 4:2:2 format or at 4:4:4 format at
27 MHz.
Enables or disables the internal test pattern generator.
This control bit enables or disables the Sharpness Filter mode. This
bit must be set to “1” for any values programmed into the Filter
Gain 1 Register to take effect. It must also be set to “1” when
Adaptive Filter mode is used.
Test Pattern Hatch/Frame (MR13)
Refer to Sharpness Filter control and Adaptive Filter control section.
Test Pattern Enable (MR12)
If this bit is set to “0,” a cross-hatch test pattern is output from the
ADV7196A (for example, in SMPTE293M 11 horizontal and 11
vertical white lines, four pixels wide are displayed against a black
background). The cross-hatch test pattern can be used to test
monitor convergence.
100IRE
0IRE
–6IRE
–40IRE
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7196A.
Figure 19. Undershoot Limiter, Programmed to –6 IRE
The color of the lines or the frame/field is by default white but can
be programmed to be any color using the Color Y, Color Cr,
Color Cb registers.
MR17
MR16
MR15
MR14
SHARPNESS
FILTER
0
1
0
1
0
1
MR13
DISABLED
–11IRE
–6IRE
–1.5IRE
0
1
PIXEL DATA
ENABLE
MR10
DISABLED
ENABLED
TEST PATTERN
HATCH/FRAME
MR16 MR15
0
0
1
1
0
1
DISABLED
ENABLED
UNDERSHOOT
LIMITER
MR10
MR11
MR12
MR14
DISABLED
ENABLED
MR12
TEST PATTERN
ENABLE
VBI OPEN
MR17
0
1
MR13
0
1
DISABLED
ENABLED
INPUT FORMAT
MR11
HATCH
FIELD/FRAME
0
1
4:4:4 YCRCB
4:2:2 YCRCB
Figure 20. Mode Register 1
–16–
REV. 0
ADV7196A
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
The CGMS data bits are programmed into the CGMS Data
Registers 0–2. For more information refer to CGMS Data
Registers section.
Figure 22 shows the various operations under the control of Mode
Register 2.
CGMS CRC (MR27)
This bit enables the automatic Cyclic Redundancy Check when
CGMS is enabled.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
This control bit delays the Y signal with respect to the falling edge
of the horizontal sync signal by up to four pixel clock cycles.
Figure 21 demonstrates this facility.
NO DELAY
Y DELAY
Y OUTPUT
MAX DELAY
Color Delay (MR23–MR25)
This control allows delay of the color signals with respect to the
falling edge of the horizontal sync signal by up to four pixel clock
cycles. Figure 21 demonstrates this facility.
NO DELAY
CGMS Enable (MR26)
PrPb DELAY
When this bit is set to “1,” CGMS data is inserted on Line 41 in
525p mode. The CGMS conforms: to CGMS-A EIA-J CPR1204-1,
Transfer Method of Video ID information using vertical blanking
interval (525p System), March 1998 and IEC61880, 1998, video
systems (525/60)—video and accompanied data using the vertical
blanking interval—analogue interface.
MR27
MR26
MR25
CGMS ENABLE
CGMS CRC
MAX DELAY
Figure 21. Y and Color Delay
MR24
MR23
MR22
MR25 MR24
DISABLED
ENABLED
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
DISABLED
ENABLED
Figure 22. Mode Register 2
REV. 0
–17–
MR20
Y DELAY
MR22 MR21
MR23
MR27
0
1
MR21
COLOR DELAY
MR26
0
1
PrPb OUTPUTS
0
0
0
0
1
0
0
1
1
0
MR20
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
ADV7196A
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 23 shows the various operations under the control of Mode
Register 3.
Figure 24 shows the various operations under the control of Mode
Register 4.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
MR4 BIT DESCRIPTION
Timing Reset (MR40)
When this bit is set to “1” the ADV7196A reverts to HDTV mode
(refer to HDTV mode section). When set to “0” the ADV7196A
is set up in Progressive Scan Mode (PS Mode).
Toggling MR40 from low to high and low again resets the internal horizontal and vertical timing counters.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
Figure 25 shows the various operations under the control of
Mode Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
This bit is reserved for the revision code.
DAC C Control (MR35)
RGB Mode (MR51)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts
unsigned binary RGB data at its input port. This control is also
available in Async Timing Mode.
Interpolation (MR36)
This bit enables the second stage interpolation filters. When this
bit is enabled (MR36 = “1”). data is send at 54 MHz to the DAC
output stage. After Reset it is recommended to toggle this bit.
Before toggling this bit 3Ehex must be written to address 09hex
to guarantee correct operations.
Reserved (MR37)
By default the color component output signals Pr, Pb do not
contain any horizontal sync pulses. They can be inserted when
MR52 = “1.” This facility is only available when Output Standard
Selection has been set to EIA-770.2 (MR01–00 = “00”) or Full
Input Range (MR01–00 = “10”).
This control is not available in RGB mode.
A zero must be written to this bit.
MR37
MR36
MR35
MR34
MR33
MR34
0
1
INTERPOLATION
MR36
POWER-DOWN
NORMAL
DAC C CONTROL
0
1
HDTV ENABLE
MR30
ZERO MUST BE
WRITTEN TO
THIS BIT
MR33
POWER-DOWN
NORMAL
MR30
MR31
0
1
DAC A CONTROL
MR35
DISABLE
ENABLE
MR32
MR32
DAC B CONTROL
MR37
ZERO MUST BE
WRITTEN TO
THIS BIT
0
1
Sync on PrPb (MR52)
0
1
POWER-DOWN
NORMAL
DISABLE
ENABLE
MR31
ZERO MUST BE
WRITTEN TO
THIS BIT
Figure 23. Mode Register 3
MR47
MR46
MR45
MR44
MR43
MR42
MR40
MR41
TIMING RESET
MR47–MR41
ZERO MUST BE
WRITTEN TO
THESE REGISTERS
MR40
Figure 24. Model Register 4
–18–
REV. 0
ADV7196A
MR57
MR56
ADAPTIVE MODE
CONTROL
MR56
0
MODE A
1
MODE B
ADAPTIVE FILTER
CONTROL
MR57
0
DISABLE
1
ENABLE
MR54
MR55
MR53
GAMMA CURVE
MR54
0
1
MR51
MR50
SYNC ON PrPb
MR52
0
1
CURVE A
CURVE B
GAMMA
CORRECTION
MR55
0
DISABLE
1
ENABLE
MR52
MR50
RESERVED FOR
REVISION CODE
DISABLE
ENABLE
COLOR OUTPUT
SWAP
MR53
0
DAC B = Pr
1
DAC C = Pr
RGB MODE
MR51
0
1
DISABLE
ENABLE
Figure 25. Mode Register 5
Color Output Swap (MR53)
Adaptive Filter Control (MR57)
By default DAC B is configured as the Pr output and DAC C
as the Pb output. In setting this bit to “1” the DAC outputs can
be swapped around so that DAC B outputs Pb and DAC C
outputs Pr. Table III demonstrates this in more detail. This control
is also available in RGB mode.
This bit enables the Adaptive Filter Control when set to “1.”
Sharpness Filter must be enabled as well (MR17 = “1”). The
Adaptive Filter Controls is explained in more detail under
Sharpness Filter Control and Adaptive Filter Control section.
Table III. Relationship Between Color Input Pixel Port,
MR53 and DAC B, DAC C Outputs
COLOR Y
CY (CY7–CY0)
(Address (SR4–SR0) = 06H
In 4:4:4 Input Mode
Color Data
Input on Pins
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
CY7
MR53
CY6
0
0
1
1
DAC B
DAC C
DAC C
DAC B
Color Data
Input on Pins
MR53
Analog Output
Signal
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
0 or 1
0
1
Not Operational
DAC C (Pb)
DAC C (Pr)
In 4:2:2 Input Mode
CY4
This bit selects which of the two programmable gamma curves is to
be used. When setting MR54 to “0,” the gamma correction curve
selected is Curve A. Otherwise Curve B is selected. Each curve
will have to be programmed by the user as explained in the Gamma
Correction Registers section.
Adaptive Mode Control (MR56)
For this control to be effective, Adaptive Filter Control must be
enabled (MR57 = “1”) as well as the Sharpness Filter (MR17 =
“1”). For filter plots refer to Sharpness Filter Control and
Adaptive Filter Control section.
CY2
CY1
CY0
CCR1
CCR0
CCB1
CCB0
CY7–CY0
Figure 26. Color Y Register
COLOR CR
CCR (CCR7–CCR0)
(Address (SR4–SR0) = 07H
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR7–CCR0
COLOR CR VALUE
Figure 27. Color Cr Register
COLOR CB
CCB (CCB7–CCB0)
(Address (SR4–SR0) = 08H)
CCB7
Gamma Correction (MR55)
To enable Gamma Correction and therefore activate the gamma
curve programmed by the user, this bit must be set to “1.” Otherwise
the programmable Gamma Correction facility is bypassed. Programming of the gamma correction curves is explained in the
Gamma Correction Registers section.
CY3
COLOR Y VALUE
Gamma Curve (MR54)
REV. 0
CY5
Analog Output
Signal
CCB6
CCB5
CCB4
CCB3
CCB2
CCB7–CCB0
COLOR CB VALUE
Figure 28. Color Cb Register
These three 8-bit-wide registers are used to program the output
color of the internal test pattern generator, be it the lines of the
cross-hatch pattern or the uniform field test pattern and are
available in PS mode and HDTV mode.
The standard used for the values for Y and the color difference
signals to obtain white, black and the saturated primary and
complementary colors conforms to the ITU-R BT 601-4 standard.
–19–
ADV7196A
The Table IV shows sample color values to be programmed into
the color registers when Output Standard Selection is set to
EIA-770.2 (MR01–00 = “00”).
CGMS DATA REGISTERS 2–0
CGMS2 (CGMS27–CGMS20)
(Address (SR4–SR0) = 13H)
This 8-bit-wide register contains the last four CGMS data bits,
(C16–C19) of the CGMS data stream.
Table IV. Sample Color Values for EIA 770.2 Output
Standard Selection
Sample
Color
Color Y
Value
Color Cr
Value
Color Cb
Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128 (80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
CGMS27 CGMS26
CGMS25
CGMS27–CGMS24
CGMS23–CGMS20
ZERO MUST BE WRITTEN
TO THESE BITS
CGMS2
CGMS1 (CGMS17–CGMS10)
(Address (SR4–SR0) = 12H)
This 8-bit-wide register contains (C8–C15) of the CGMS
data stream.
CGMS17 CGMS16
CGMS15
Figure 29 shows the various operations under the control of
Mode Register 6.
CGMS12 CGMS11 CGMS10
CGMS1
Figure 31. CGMS1 Data Register
CGMS0 (CGMS07–CGMS00)
(Address (SR4–SR0) = 11H)
The value 3Ehex must be written to this register before the
PLL is reset (reset MR36) to guarantee correct operation of
the ADV7196A.
MR65
CGMS14 CGMS13
CGMS17–CGMS10
MR6 BIT DESCRIPTION
MR67–MR60
MR66
CGMS22 CGMS21 CGMS20
Figure 30. CGMS2 Data Register
MODE REGISTER 6
MR6 (MR67–MR60)
(Address (SR4–SR0) = 09H)
MR67
CGMS24 CGMS23
MR64
MR63
MR62
MR61
This 8-bit-wide register contains the first eight CGMS data
bits, (C0–C7) of the CGMS data stream.
MR60
CGMS07 CGMS06
MR66
MR64
MR62
MR60
ZERO MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
CGMS05
CGMS04 CGMS03
CGMS02 CGMS01 CGMS00
CGMS07–CGMS00
CGMS0
Figure 32. CGMS0 Data Register
MR67
MR65
MR63
MR61
ZERO MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THIS BIT
ONE MUST BE
WRITTEN TO
THIS BIT
Figure 29. Mode Register 6
CRC SEQUENCE
700mV
REF
(70
10)%
BIT1 BIT2................................................................................................................................................BIT20
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
5.8s
21.2s 0.22s
22T
0.15s
6T
T = 1/(fH 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T 30ns
Figure 33. CGMS Waveform
–20–
REV. 0
ADV7196A
FILTER GAIN
FG (FG7–FG0)
(Address (SR4–SR0) = 10H)
Figure 34 shows the various operations under the control of the
Filter Gain register.
FG7
FG6
FG5
FG4
FG3
FG2
FG0
FILTER GAIN B
0
1
2
3
4
5
6
7
–8
–7
–6
–5
–4
–3
–2
–1
Location 0, 16, 240, and 255 are fixed and can not be changed.
For the length of 16 to 240 the gamma correction curve has to be
calculated as below:
FG3–FG0
FG7–FG4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FG1
The response of the curve is programmed at seven predefined
locations. In changing the values at these locations the gamma
curve can be modified. Between these points linear interpolation
is used to generate intermediate values. Considering the curve to
have a total length of 256 points, the seven locations are at: 32,
64, 96, 128, 160, 192, 224.
y = xγ
FILTER GAIN A
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
–8
–7
–6
–5
–4
–3
–2
–1
Figure 34. Filter Gain Register
FG BIT DESCRIPTION
Filter Gain A (FG3–FG0)
These bits are used to program the gain A value, which varies
from response –8 to response +7 and are applied to Filter A.
Filter Gain B (FG4–FG7)
These bits are used to program the gain B value, which varies
from response –8 to response +7 and are applied to Filter B.
Refer to Sharpness Filter Control and Adaptive Filter Control
section for more detail.
where:
y = gamma corrected output.
x = linear input signal.
γ = gamma power factor.
To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:
yn = [x(n–16)/(240 – 16)]γ ⫻ (240) – 16) + 16
where:
x(n–16) = Value for x along x-axis at points:
n
= 32, 64, 96, 128, 160, 192, or 224.
= Value for y along the y-axis, which has to be written into
yn
the gamma correction register.
Example:
y32
y64
y96
y128
[(16/224)0.5 ⫻ 2 24] + 16 = 76*
[(48/224)0.5 ⫻ 224] + 16 =120*
[(80/224)0.5 ⫻ 224] + 16 = 150*
[(112/224)0.5 ⫻ 224] + 16 = 147*
*Rounded to the nearest integer.
The above will result in a gamma curve shown below, assuming a
ramp signal as an input.
300
GAMMA CORRECTION REGISTERS 0–13
(GAMMA CORRECTION 0–13)
(Address (SR5–SR0) = 14H–21H)
GAMMA-CORRECTED AMPLITUDE
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT
The Gamma Correction Registers are fourteen 8-bit-wide register.
They are used to program the gamma correction Curves A and B.
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever
nonlinear processing is used.
Gamma correction uses the function:
SignalOUT = (SignalIN ) γ
where γ = gamma power factor.
250
SIGNAL OUTPUT
200
0.5
150
100
SIGNAL INPUT
50
0
Gamma correction is performed on the luma data only.
The user has the choice to use two different curves, Curve A or
Curve B. At any one time only one of these curves can be used.
REV. 0
=
=
=
=
0
50
100
150
LOCATION
200
250
Figure 35. Signal Input (Ramp) and Signal Output for
Gamma 0.5
–21–
ADV7196A
INPUT SIGNAL: STEP
300
250
SIGNAL OUTPUTS
SHARPNESS AND ADAPTIVE FILTER CONTROL MODE
1.5
200
0.3
7
0.5
150
UT
NP
LI
A
1.5
GN
SI
100
6
5
1.3
4
3
2
1.8
50
0
1.4
1.2
MAGNITUDE
GAMMA-CORRECTED AMPLITUDE
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
1.1
1
0
1.0
–1
0.9
–2
–3
0
50
100
150
LOCATION
200
250
Figure 36. Signal Input (Ramp) and Selectable Gamma
Output Curves
0.8
–4
0.7
–5
0.6
–6
–7
0.5
The gamma curves shown above are examples only, any user
defined curve is acceptable in the range of 16–240.
SHARPNESS FILTER CONTROL AND ADAPTIVE
FILTER CONTROL
–8
0
2
4
6
8
FREQUENCY – MHz
10
12
1.5
To enhance or attenuate the Y signal in the frequency ranges shown
in Figure 37, the following register settings must be used:
Sharpness Filter must be enabled (MR17 = “1”) and Adaptive
Filter Control must be disabled (MR57 = “0”).
6
5
1.3
MAGNITUDE
SHARPNESS FILTER MODE
7
1.4
There are three Filter modes available on the ADV7196A: one
Sharpness Filter mode and two Adaptive Filter modes.
4
1.2
3
1.1
1
2
0
–1
1.0
–2
0.9
–3
0.8
To select one of the 256 individual responses, the according gain
values for each filter, which range from –8 to +7, must be programmed into the Filter Gain register.
–4
–5
0.7
–6
0.6
–7
–8
0.5
0
2
4
6
8
FREQUENCY – MHz
10
12
14
0
2
4
6
8
FREQUENCY – MHz
10
12
14
ADAPTIVE FILTER MODE
The derivative of the incoming signal is compared to the three programmable threshold values: Adaptive Filter Threshold A, B, C.
The edges can then be attenuated with the settings in Adaptive
Filter Gain 1, 2, 3 registers and Filter Gain register.
According to the settings of the Adaptive Mode control (MR56),
there are two Adaptive Filter Modes available:
1. Mode A: is used when Adaptive Filter Mode (MR56) is set
to “0.” In this case, Filter B (LPF) will be used in the adaptive
filter block. Also, only the programmed values for Gain B in
the Filter Gain, Adaptive Filter Gain 1, 2, 3 are applied when
needed. The Gain A values are fixed and can not be changed.
2. Mode B: is used when Adaptive Filter Mode (MR56) is set to
“1.” In this mode a cascade of Filter A and Filter B is used. Both
settings for Gain A and Gain B in the Filter Gain, Adaptive
Filter Gain 1, 2, 3 become active when needed.
–22–
1.6
MAGNITUDE RESPONSE – Linear Scale
The Adaptive Filter Threshold A, B, C registers, the Adaptive
Filter Gain 1, 2, 3 registers and the Filter Gain register are used
in Adaptive Filter mode. To activate the Adaptive Filter control,
Sharpness Filter must be enabled (MR17 = “1”) and Adaptive
Filter Control must be enabled (MR57 = “1”).
14
1.5
1.4
1.3
1.2
1.1
1.0
FREQUENCY RESPONSE IN SHARPNESS FILTER MODE
WITH KA = 3 and KB = 7
Figure 37. Sharpness and Adaptive Filter Control Mode
REV. 0
ADV7196A
ADAPTIVE FILTER GAIN 1
AFG1 (AFG1)7–0
(Address (SR5–SR0) = 22H)
AFG37
This 8-bit-wide register is used to program the gain applied to signals
which lie above Adaptive Filter Threshold A but are smaller than
Adaptive Filter Threshold B.
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG1)3–0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = “1”).
AFG17
AFG16
AFG15
AFG14
AFG13
AFG12
AFG11
AFG17–AFG14
AFG13–AFG10
GAIN B
GAIN A
AFG10
AFG36
AFG35
AFG34
AFG33
AFG32
AFG31
AFG37–AFG34
AFG33–AFG30
GAIN B
GAIN A
AFG30
Figure 40. Adaptive Filter Gain 3 Register
ADAPTIVE FILTER THRESHOLD A
AFTA (AFTA)7–0
(Address (SR5–SR0) = 25H)
This 8-bit-wide register is used to program the threshold value for
small edges. The recommended programmable threshold range is
from 16–235, although any value in the range of 0–255 can be used.
AFTA7
AFTA6
AFTA5
AFTA4
AFTA3
AFTA2
AFTA1
AFTA0
Figure 38. Adaptive Filter Gain 1 Register
AFTA7–AFTA0
ADAPTIVE FILTER
THRESHOLD A
ADAPTIVE FILTER GAIN 2
AFG2 (AFG2)7–0
(Address (SR5–SR0) = 23H)
This 8-bit-wide register is used to program the gain applied
to signals which lie above Adaptive Filter Threshold B but are
smaller than Adaptive Filter Threshold C.
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG2)3–0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = “1”).
AFG27
AFG26
AFG25
AFG24
AFG23
AFG22
AFG21
Figure 41. Adaptive Filter Threshold A Register
ADAPTIVE FILTER THRESHOLD B
AFTB (AFTB)7–0
(Address (SR5–SR0) = 26H)
This 8-bit-wide register is used to program the threshold value for
medium edges and has priority over Adaptive Threshold A. The
recommended programmable threshold range is from 16–235,
although any value in the range of 0–255 can be used.
AFG20
AFTB7
AFG27–AFG24
AFG23–AFG20
GAIN B
GAIN A
AFTB6
AFTB5
AFTB4
This 8-bit-wide register is used to program the gain applied to signals
which lie above Adaptive Filter Threshold C
Gain A and Gain B values vary from –8 to +7. The individual
responses are shown in the figures below.
Settings for (AFG3)3–0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = “1”).
AFTB1
AFTB0
AFTB7–AFTB0
Figure 42. Adaptive Filter Threshold B Register
ADAPTIVE FILTER THRESHOLD C
AFTC (AFTC)7–0
(Address (SR5–SR0) = 27H)
This 8-bit-wide register is used to program the threshold value
for large edges and has priority over Adaptive Threshold A and B.
The recommended programmable threshold range is from 16–235,
although any value in the range of 0–255 can be used.
AFTC7
The gain applied to signals which lie below Adaptive Threshold A
are programmed in the Filter Gain register.
AFTC6
AFTC5
AFTC4
AFTC3
AFTC2
AFTC1
AFTC0
AFTC7–AFTC0
At any one time only one of the following registers is active: AFG1,
AFG2, AFG3, FG. The gain values can be preprogrammed and
become active whenever the threshold conditions for the according register is met. To program the Adaptive Filter Gain registers
the source register settings are used as for the Filter Gain register.
REV. 0
AFTB2
ADAPTIVE FILTER
THRESHOLD B
Figure 39. Adaptive Filter Gain 2 Register
ADAPTIVE FILTER GAIN 3
AFG3 (AFG3)7–0
(Address (SR5–SR0) = 24H)
AFTB3
ADAPTIVE FILTER
THRESHOLD C
Figure 43. Adaptive Filter Threshold C Register
–23–
ADV7196A
The effect of the sharpness filter can also be seen when using the
internally generated cross hatch pattern:
SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES
Sharpness Filter Application
The sharpness filter can be used to enhance or attenuate the Y
video output signal.
The following register settings were used to achieve the results
shown in the figures below:
Input data was generated by an external signal source.
Table V.
Address
Register Setting
00hex
01hex
02hex
03hex
04hex
05hex
09hex
10hex
10hex
10hex
10hex
10hex
10hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Filter Gain
Filter Gain
Filter Gain
Filter Gain
Filter Gain
Filter Gain
TEK RUN
40hex
81hex
00hex
78hex
00hex
00hex
3Ehex
00hex
08hex
04hex
40hex
80hex
22hex
Table VI.
Address
00hex
01hex
02hex
03hex
04hex
05hex
09hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
00hex
85hex
00hex
38hex
00hex
00hex
3Ehex
(a)
(b)
(c)
(d)
(e)
(f)
TEK RUN
TRIG’D
T
Register Setting
TRIG’D
T
T
T
(D)
(A)
1
R2
(E)
(B)
R1
R4
(F)
(C)
R2
1
CH1 500mV
REF4
500mV
CH1 500mV
M 4.00s
CH1
ALL FIELDS
4.00s T
9.99976ms
REF2
500mV
M 4.00s
CH1
ALL FIELDS
4.00s T
9.99976ms
(b)
(a)
Figure 44. Sharpness Filter Control with Different Gain Settings for Filter Gain
–24–
REV. 0
ADV7196A
In toggling MR17 (Sharpness Filter Enable/Disable) and setting
the Filter Gain register value to 99hex it can be seen that the line
contours of the cross hatch pattern change their sharpness.
The figure below shows the output signal when changing the Adaptive Filter mode to Mode B (MR56 = “1”).
TEK RUN
Adaptive Filter Control Application
The figure below shows a typical signal to be processed by the
Adaptive Filter Control block.
TEK RUN
TRIG’D
T
T
TRIG’D
T
T
4
M 100ns
CH4
CH4 100mV
ALL FIELDS
12.8222ms
T
4
Figure 46. Output Signal from Adaptive Filter Control
The Adaptive Filter control can also be demonstrated using the
internally generated crosshatch test pattern and toggling the Adaptive Filter Control bit (MR57) using the following register settings:
M 100ns
CH4
CH4 100mV
ALL FIELDS
12.8222ms
T
Figure 45. Input Signal to Adaptive Filter Control
The following register settings where used to obtain the
results shown in the figure below, i.e., to remove the ringing
on the Y signal:
Input data was generated by an external signal source.
Table VII.
Address
00hex
01hex
02hex
03hex
04hex
05hex
09hex
10hex
22hex
23hex
24hex
25hex
26hex
27hex
Register Setting
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Mode Register 6
Filter Gain
Adaptive Filter Gain 1
Adaptive Filter Gain 2
Adaptive Filter Gain 3
Adaptive Filter Threshold A
Adaptive Filter Threshold B
Adaptive Filter Threshold C
40hex
81hex
00hex
78hex
00hex
80hex
3Ehex
00hex
AChex
9Ahex
88hex
28hex
3Fhex
64hex
TEK RUN
Table VIII.
Address
00hex
01hex
02hex
03hex
04hex
05hex
06hex
07hex
08hex
09hex
10hex
22hex
23hex
24hex
25hex
26hex
27hex
Register Setting
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Color Y
Color Cr
Color Cb
Mode Register 6
Filter Gain
Adaptive Filter Gain 1
Adaptive Filter Gain 2
Adaptive Filter Gain 3
Adaptive Filter Threshold A
Adaptive Filter Threshold B
Adaptive Filter Threshold C
TRIG’D
T
T
4
M 100ns
CH4
CH4 100mV
ALL FIELDS
12.8222ms
T
Figure 47. Output Signal from Adaptive Filter Control
REV. 0
–25–
40hex
85hex
00hex
78hex
00hex
80hex
6Chex
52hex
52hex
3Ehex
00hex
AChex
9Ahex
88hex
28hex
3Fhex
64hex
ADV7196A
HDTV MODE
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 48 shows an example of how to program the ADV7196A
to accept a different high definition standard but SMPTE293M,
SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Figure 50 shows the various operations under the control of Mode
Register 0.
A “0” must be written to this bit.
Reserved (MR04)
Input Standard (MR05)
HEXMR0 BIT DESCRIPTION
Output Standard Selection (MR00–MR01)
Select between 1080i or 720p input.
These bits are used to select the output levels from the ADV7196A.
This control bit allows to select the polarity of the DV input control
signal to be either active high or active low.
DV Polarity (MR06)
If EIA 770.3 (MR01–00 = “00”) is selected, the output levels will be:
0 mV for blanking level, 700 mV for peak white (Y channel),
± 350 mV for Pr, Pb outputs and –300 mV for tri-level sync.
If Full Input Range (MR01–00 = “10”) is selected, the output
levels will be 700 mV for peak white for the Y channel, ± 350 mV
for Pr, Pb outputs and –300 mV for Sync. This mode is used for
RS-170, RS-343A standard output compatibility.
Sync insertion on the Pr, Pb channels is optional.
For output levels, refer to the Appendix.
Input Control Signals (MR02–MR03)
These control bits are used to select whether data is input with
external horizontal, vertical and blanking sync signals or if the data
is input with embedded EAV/SAV code An Asynchronous timing
mode is also available using TSYNC, SYNC and DV as input
control signals. These timing control signals have to be programmed
by the user.
Reserved (MR07)
A “0” must be written to this bit.
Table IX. Truth Table
SYNC
TSYNC
DV
1 –> 0
0
0 or 1
0
0 –> 1
0 or 1
0 –> 1
0 or 1
0
1
1
0 or 1
0 or 1
0 –> 1
1 –> 0
50% Point of Falling Edge of
Tri-Level Horizontal Signal, A
25% Point of Rising Edge of
Tri-Level Horizontal Signal, B
50% Point of Falling Edge of
Tri-Level Horizontal Signal, C
50% Start of Active Video, D
50% End of Active Video, E
CLK
SYNC
PROGRAMMABLE
INPUT TIMING
TSYNC
DV SET
MR06 = ‘1’
ACTIVE VIDEO
HORIZONTAL SYNC
ANALOG
OUTPUT
81
66
A
66
B
243
C
1920
D
E
Figure 48. Async Timing Mode—Programming Input Control Signals for SMPTE295M Compatibility
525
VIDEO
OUTPUT
1
7
12
13
42
43
HSYNC
VSYNC
DV
Figure 49. DV Input Control Signal in Relation to Video Output Signal
–26–
REV. 0
ADV7196A
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4-SR0) = 01H)
Test Pattern Hatch/Frame (MR13)
If this bit is set to “0,” a cross-hatch test pattern is output from
the ADV7196A. The cross-hatch test pattern can be used to test
monitor convergence.
Figure 51 shows the various operations under the control of Mode
Register 1.
If this bit is set to “1,” a uniform colored frame/field test pattern
is output from the ADV7196A.
MR1 BIT DESCRIPTION
Pixel Data Enable (MR10)
The color of the lines or the frame/field is by default white but
can be programmed to be any color using the Color Y, Color
Cr, Color Cb registers.
When this bit is set to “0,” the pixel data input to the ADV7196A
is blanked such that a black screen is output from the DACs. When
this bit is set to “1,” pixel data is accepted at the input pins and
the ADV7196A outputs to the standard set in “Output Standard
Selection” (MR01–00). This bit also must be set to “1” to enable
output pattern signals.
VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion during
the Vertical Blanking Interval.
For this purpose Lines 7–20 in 1080i and Lines 6–25 in 720p can
be used for VBI data insertion.
Input Format (MR11)
It is possible to input data in 4:2:2 format or in 4:4:4
HDTV format.
Reserved (MR15–MR17)
A “0” must be written to these bits.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
MR06
MR07
MR07
MR05
MR04
MR03
INPUT STANDARD
0
1
MR04
DV POLARITY
0
1
0
0
1
1
1080I
720P
MR06
HSYNC/VSYNC/DV
EAV/SAV
TSYNC/SYNC/DV
RESERVED
0
1
0
1
ZERO MUST BE
WRITTEN TO
THIS BIT
ACTIVE HIGH
ACTIVE LOW
MR00
MR01
INPUT CONTROL SIGNALS
MR03 MR02
MR05
ZERO MUST BE
WRITTEN TO
THIS BIT
MR02
OUTPUT STANDARDS SELECTION
MR01 MR00
0
0
1
1
0
1
0
1
EIA770.3
RESERVED
FULL I/P RANGE
RESERVED
Figure 50. Mode Register 0
MR17
MR16
MR15
MR14
MR12
0
1
DISABLED
ENABLED
DISABLED
ENABLED
TEST PATTERN
HATCH/FRAME
MR13
0
1
0
1
INPUT FORMAT
MR11
HATCH
FIELD/FRAME
Figure 51. Mode Register 1
REV. 0
PIXEL DATA
ENABLE
MR10
MR12
MR14
0
1
MR10
MR11
TEST PATTERN
ENABLE
VBI OPEN
MR17–MR15
ZERO MUST BE
WRITTEN TO
THESE BITS
MR13
–27–
0
1
4:4:4 YCRCB
4:2:2 YCRCB
DISABLED
ENABLED
ADV7196A
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4-SR0) = 03H)
Figure 53 shows the various operations under the control of Mode
Register 2.
Figure 54 shows the various operations under the control of Mode
Register 3.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
When this bit is set to “1” the ADV7196A reverts to HDTV
mode. When set to “0” the ADV7196A reverts to Progressive
Scan mode (PS mode).
Color Delay (MR23–MR25)
With theses bits it is possible to delay the color signals with respect
to the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Reserved (MR31–MR32)
Reserved (MR26–MR27)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
A “0” must be written to these bits.
DAC A Control (MR33)
A “0” must be written to these bits.
DAC B Control (MR34)
Y DELAY
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
NO DELAY
Y OUTPUT
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
MAX DELAY
Reserved (MR36–MR37)
NO DELAY
A “0” must be written to these bits.
PrPb DELAY
PrPb OUTPUTS
MAX DELAY
Figure 52. Y and Color Delay
MR27
MR26
MR25
MR24
MR27–MR26
MR23
MR22
Y DELAY
COLOR DELAY
MR25 MR24
ZERO MUST BE
WRITTEN TO
THESE BITS
0
0
0
0
1
0
0
1
1
0
MR20
MR21
MR22 MR21
MR23
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
0
0
0
0
1
0
0
1
1
0
MR20
0
1
0
1
0
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
Figure 53. Mode Register 2
MR37
MR36
MR35
MR34
MR33
MR34
0
1
POWER-DOWN
NORMAL
DAC C CONTROL
MR35
0
1
MR30
MR31
MR32–MR31
DAC B CONTROL
MR37–MR36
ZERO MUST BE
WRITTEN TO
THESE BITS
MR32
ZERO MUST BE
WRITTEN TO
THESE BITS
HDTV ENABLE
MR30
0
1
DISABLE
ENABLE
DAC A CONTROL
MR33
POWER-DOWN
NORMAL
0
1
POWER-DOWN
NORMAL
Figure 54. Mode Register 3
–28–
REV. 0
ADV7196A
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Color Output Swap (MR53)
By default DAC B is configured as the Pr output and DAC C as
the Pb output. In setting this bit to “1” the DAC outputs can be
swapped around so that DAC B outputs Pb and DAC C outputs
Pr. Table X demonstrates this in more detail.
Figure 55 shows the various operations under the control of Mode
Register 4.
Reserved (MR54–MR57)
MR4 BIT DESCRIPTION
Timing Reset (MR40)
“0” must be written to these bits.
Toggling MR40 from low to high and low again resets the internal horizontal and vertical timing counters.
Table X. Relationship Between Input Pixel Port, MR53
and DAC B, DAC C Outputs
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
In 4:4:4 Input Mode
Figure 56 shows the various operations under the control of Mode
Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
These bit is reserved for the revision code.
When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts
unsigned binary RGB data at its input port. This control is also
available in Async Timing Mode.
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not contain
any horizontal sync pulses. If required they can be inserted when
MR52 = “1.” This control is not available in RGB mode.
MR46
MR53
Analog Output
Signal
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
0
0
1
1
DAC B
DAC C
DAC C
DAC B
Color Data
Input on Pins
MR53
Analog Output
Signal
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
0 or 1
0
1
Not Operational
DAC C (Pb)
DAC C (Pr)
In 4:2:2 Input Mode
RGB Mode (MR51)
MR47
Color Data
Input on Pins
MR45
MR44
MR43
MR42
MR40
MR41
TIMING RESET
MR47–MR41
ZERO MUST BE
WRITTEN TO
THESE BITS
MR40
Figure 55. Mode Register 4
MR57
MR56
MR55
MR54
MR53
MR52
SYNC ON PrPb
MR57–MR54
MR52
ZERO MUST BE
WRITTEN TO
THESE BITS
0
1
DISABLE
ENABLE
COLOR OUTPUT
SWAP
MR53
0
1
MR50
RESERVED FOR
REVISION CODE
RGB MODE
MR51
DAC B = Pr
DAC C = Pr
Figure 56. Mode Register 5
REV. 0
MR50
MR51
–29–
0
1
DISABLE
ENABLE
ADV7196A
DAC TERMINATION AND LAYOUT CONSIDERATIONS
Voltage Reference
PC BOARD LAYOUT CONSIDERATIONS
The ADV7196A is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excellent
noise performance of the ADV7196A, it is imperative that great
care be given to the PC board layout.
The ADV7196A contains an on-board voltage reference. The
VREF pin is normally terminated to VAA through a 0.1 µF capacitor
when the internal VREF is used. Alternatively, the ADV7196A
can be used with an external VREF (AD589).
The layout should be optimized for lowest noise on the ADV7196A
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and AGND and VDD and DGND pins
should be kept as short as possible to minimized inductive ringing.
Resistor RSET is connected between the RSET pin and AGND and
is used to control the full-scale output current and therefore the
DAC voltage output levels. For full-scale output RSET must have
a value of 2470 Ω. RLOAD has a value of 300 Ω. When an input
range of 0–1023 is selected the value of RSET must be 2820 Ω.
The ADV7196A has three analog outputs, corresponding to Y, Pr,
Pb video signals. The DACs must be used with external buffer circuits
in order to provide sufficient current to drive an output device.
Suitable op amps are the AD8009, AD8002, AD8001, or AD8057.
It is recommended that a four-layer printed circuit board is used.
With power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Placement
of components should consider to separate noisy circuits, such
as crystal clocks, high-speed logic circuitry and analog circuitry.
To calculate the output full-scale current and voltage the following equations should be used:
There should be a separate analog ground plane (AGND) and
a separate digital ground plane (GND).
VOUT = IOUT ⫻ RLOAD
IOUT = [VREF ⫻ k]/RSET
Power planes should encompass a digital power plane (VDD) and
a analog power plane (VAA). The analog power plane should contain
the DACs and all associated circuitry, and the VREF circuitry.
k = 5.66 [for input ranges 64–940, 64–960, output standards
EIA770.1–3]
The digital power plane should contain all logic circuitry. The analog
and digital power planes should be individually connected to the
common power plane at one single point through a suitable filtering device, such as a ferrite bead.
where:
k = 6.46 [for input ranges 0–1023, output standard RS–170/343A]
VREF = 1.235 V
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
VAA
10nF
0.1F
VDD
VAA
10nF
0.1F
0.1F
24, 35
COMP
VAA
1, 12
VDD
DAC A
Cb/Cr0–Cb/Cr9
Y OUTPUT
300
Cr0–Cr9
Pr (V) OUTPUT
DAC B
300
Y0–Y9
ADV7196A
UNUSED
INPUTS
SHOULD BE
GROUNDED
Pb (U) OUTPUT
DAC C
HSYNC/SYNC
300
VDD
VSYNC/TSYNC
VDD
100
DV
5k
VDD
5k
SCL
100
4.7k
MPU BUS
SDA
RESET
4.7F
6.3V
VREF
27MHz, 74.25MHz OR
74.1758MHz CLOCK
RSET
CLKIN
VDD
ALSB
AGND
GND
26, 33
2.47k OR
2.82k
13, 52
4.7k
Figure 57. Circuit Layout
–30–
REV. 0
ADV7196A
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce noise
pickup due to neighboring digital circuitry.
Due to the high clock rates used, long clock lines to the ADV7196A
should be avoided to minimize noise pickup. Any active pull-up
termination resistors for the digital inputs should be connected
to the digital power plane and not the analog power plane.
Supply Decoupling
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω. This termination resistance should be as close as possible to the ADV7196A
to minimize reflections.
Analog Signal Interconnect
The ADV7196A should be located as close as possible to the output
connectors thus minimizing noise pickup and reflections due to
impedance mismatch.
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of group of VAA or VDD pins should be individually decoupled to ground. This should be done by placing
the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.
Any unused inputs should be tied to ground.
Video Output Buffer and Optional Output Filter
Output buffering is necessary in order to drive output devices,
such as progressive scan or HDTV monitors .
Digital Signal Interconnect
Analog Devices produces a range of suitable op amps for this
application. Suitable op amps would be the AD8009, AD8002,
AD8001, or AD8057. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital signal
lines should not overlay the analog power plane.
+5V
0.1F
DAC A
10F
LPF
75 COAX
AD8057
75
75
0.1F
ADV7196A
10F
–5V
+5V
0.1F
DAC B
PROGRESSIVE
SCAN
MONITOR
10F
LPF
75 COAX
AD8057
75
75
0.1F
10F
+5V
+5V
0.1F
DAC C
10F
LPF
75 COAX
AD8057
75
75
0.1F
10F
–5V
Figure 58. Output Buffer and Optional Filter
REV. 0
–31–
ADV7196A
An optional analog reconstruction LPF might be required as an
antialias filter if the ADV7196A is connected to a device that
requires this filtering.
REGISTER SETTINGS
The Eval ADV7196A/7EB evaluation board uses the ML6426
Microlinear IC, which provides buffering and low-pass filtering
for progressive scan applications.
Address
Table XI. Register Settings on Power-Up
The Eval ADV7196A/7EB Rev B and Rev C evaluation board
uses the AD8057 as a buffer and a 6th order LPF.
6.8H
600R
6.8pF
10H
2.2H
22pF
18pF
600R
AD8057
Figure 59. Example for Output Filter: PS Mode/
2x Oversampling
498
63n
0
MAGNITUDE (dB)
–5
398
54n
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Color Y
Color CR
Color Cb
Mode Register 6
Filter Gain
Adaptive Filter Gain 1
Adaptive Filter Gain 2
Adaptive Filter Gain 3
Adaptive Filter Threshold A
Adaptive Filter Threshold B
Adaptive Filter Threshold C
00hex
00hex
00hex
38hex
00hex
00hex
A0hex
80hex
80hex
00hex
00hex
AChex
9Ahex
88hex
28hex
3Fhex
64hex
298
45n
–10
GROUP DELAY (SEC)
–15
198
36n
–20
97.6
27n
PHASE (DEG)
–25
0
18n
–30
–102
9n
–35
2
1M
00hex
01hex
02hex
03hex
04hex
05hex
06hex
07hex
08hex
09hex
10hex
22hex
23hex
24hex
25hex
26hex
27hex
Register Setting
3
4
5 6 7 89
10M
FREQUENCY – Hz
2
3
–202
4 0n
Figure 60. Frequency Response for Filter Current in
Above Figure
Table XII. Internal Colorbars (Hatch), Progressive Scan Mode
Address
00hex
01hex
02hex
03hex
04hex
05hex
06hex
07hex
08hex
09hex
Register Setting
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Color Y
Color CR
Color Cb
Mode Register 6
00hex
05hex
00hex
38hex
00hex
00hex
xxhex
xxhex
xxhex
3Ehex
Table XIII. Internal Colorbars (Field), HDTV Scan Mod e
Address
00hex
01hex
02hex
03hex
04hex
05hex
06hex
07hex
08hex
–32–
Register Setting
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Mode Register 5
Color Y
Color CR
Color Cb
00hex
0Dhex
00hex
39hex
00hex
00hex
xxhex
xxhex
xxhex
REV. 0
ADV7196A
INPUT CODE
INPUT CODE
EIA-770.2, STANDARD FOR Y
940
EIA-770.3, STANDARD FOR Y
940
OUTPUT VOLTAGE
700mV
OUTPUT VOLTAGE
700mV
ACTIVE
VIDEO
300mV
ACTIVE
VIDEO
0mV
64
64
0mV
–300mV
–300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FORPr/Pb
960
OUTPUT VOLTAGE
960
350mV
300mV
ACTIVE
VIDEO
512
ACTIVE
VIDEO
0mV
0mV
512
–300mV
–350mV
64
–300mV
–350mV
64
Figure 61. EIA-770.2 Standard Output Signals (525p)
INPUT CODE
OUTPUT VOLTAGE
350mV
EIA-770.1, STANDARD FOR Y
940
OUTPUT VOLTAGE
782mV
714mV
Figure 63. EIA-770.3 Standard Output Signals (1080i, 720p)
INPUT CODE
Y-OUTPUT LEVELS FOR FULL I/P SECTIONS
1023
ACTIVE
VIDEO
ACTIVE
VIDEO
64
64
OUTPUT VOLTAGE
700mV
0mV
0mV
–300mV
–286mV
INPUT CODE
EIA-770.1, STANDARD FORPr/Pb
960
512
OUTPUT VOLTAGE
ACTIVE
VIDEO
ACTIVE
VIDEO
0mV
–300mV
–350mV
0mV
–300mV
Figure 62. EIA-770.1 Standard Output Signals (525p)
REV. 0
OUTPUT VOLTAGE
700mV
350mV
64
64
PrPb-OUTPUT LEVELS FOR FULL I/P SECTIONS
1023
Figure 64. Output Levels for Full I/P Selection
–33–
ADV7196A
SMPTE293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
INPUT PIXELS
SAMPLE NUMBER
F 0 0 F
F 0 0 V
H*
F 0 0 F
F 0 0 V
H*
4 CLOCK
4 CLOCK
723 736
719
799
DIGITAL
ACTIVE LINE
SAV CODE
853
C
C
Y
b
r
Y
C
Y
r
857 0
719
0HDATUM
DIGITAL HORIZONTAL BLANKING
FVH* = FVH AND PARITY BITS
SAV: LINE 43 – 525 = 200H
SAV: LINE 1 – 42 = 2AC
EAV: LINE 43 – 525 = 274H
EAV: LINE 1 – 42 = 2D8
Figure 65. EAV/SAV Input Data Timing Diagram—SMPTE293M
0HDATUM
SMPTE274M
DIGITAL HORIZONTAL BLANKING
ANALOG WAVEFORM
INPUT PIXELS
4T
272T
4T
1920T
EAV CODE
ANCILLARY DATA (OPTIONAL)
OR BLANKING CODE
SAV CODE
DIGITAL
ACTIVE LINE
C
F 0 0 F C
Y
r
F 0 0 V b
H*
F 0 0 F
F 0 0 V
H*
4 CLOCK
SAMPLE NUMBER
2112
2116 2156
4 CLOCK
0
2199
C
Y
r
440
188
192
2111
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
Figure 66. EAV/SAV Input Data Timing Diagram—SMPTE274M
–34–
REV. 0
ADV7196A
ACTIVE VIDEO
522
523
524
ACTIVE VIDEO
VERTICAL BLANK
525
1
2
5
6
9
8
7
12
13
10
12
11
42
43
44
Figure 67. SMPTE293M (525p)
ACTIVE VIDEO
622
623
624
ACTIVE VIDEO
VERTICAL BLANK
625
1
2
4
6
5
8
7
9
10
11
13
12
43
44
Figure 68. ITU-R. BT1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
5
4
7
6
8
25
26
744
27
Figure 69. SMPTE296M (720p)
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
FIELD 2
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
Figure 70. SMPT274M (1080i)
REV. 0
–35–
570
583
584
585
1123
745
45
ADV7196A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.557 (14.15)
0.537 (13.65)
0.398 (10.11)
0.390 (9.91)
0.094 (2.39)
0.084 (2.13)
0.037 (0.95)
0.026 (0.65)
C02154–1.5–4/01(0)
52-Lead Plastic Quad Flatpack (MQFP)
(S-52)
52
1
40
39
PIN 1
0.398 (10.11)
0.390 (9.91)
0.557 (14.15)
0.537 (13.65)
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.012 (0.30)
0.006 (0.15)
0.008 (0.20)
0.006 (0.15)
13
14
0.0256
(0.65)
BSC
0.014 (0.35)
0.010 (0.25)
PRINTED IN U.S.A.
0.082 (2.09)
0.078 (1.97)
27
26
–36–
REV. 0