Full/Low Speed USB Digital Isolator ADuM4160 Preliminary Technical Data FEATURES USB 2.0 compatible Enhanced system-level ESD performance per IEC 61000-4-x 4.0 V to 5.5V operation 7 mA maximum up-stream supply current @ 1.5 Mbps 8 mA maximum up-stream supply current @ 12 Mbps 2.5mA up-stream idle current Bidirectional communication Up Stream Short Circuit Protection High temperature operation: 105°C Low and Full Speed data rate: 1.5Mbps and 12 Mbps High common-mode transient immunity: >25 kV/μs 16-lead SOIC wide body package RoHS compliant models available Safety and regulatory approvals (Pending) UL recognition: 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A IEC 60601-1: 250 V rms (reinforced) IEC 60950-1: 600 V rms (reinforced) VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak APPLICATIONS USB peripheral isolation Isolated USB Hub Repeaters isolation components provide outstanding performance characteristics and are easily integrated with low and full speed USB compatible peripheral devices. Many microcontrollers implement USB so that it presents only the D+ and D- lines to external pins. This is desirable in many cases because it minimizes external components and simplifies the design; however, this presents particular challenges when isolation is required. Since the USB lines must switch between actively driving D+/D- and allowing external resistors to set the state of the bus, the ADuM4160 provides mechanisms for detecting the direction of data flow and control over state of the output buffers. Data direction is determined on a packet by packet basis. The ADuM4160 uses the edge detection based iCoupler technology in conjunction with internal logic to implement a transparent, easily configured, up-stream facing port isolator. Isolating the up-stream port provides several advantages in simplicity, power management and robust operation. The isolator has propagation delay comparable that of a standard hub and cable. It operates with the supply voltage on either side ranging from 3.0 V to 5.5 V, allowing connection directly to VBUS by internally regulating the voltage to the signaling level. The ADuM4160 provides isolated control of the pull-up resistor to allow the peripheral to control connection timing. The device draws low enough idle current that a suspend state is not required. 1 GENERAL DESCRIPTION Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending. 1 The ADuM4160 is a USB-port isolator, based on Analog Devices, Inc. iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these FUNCTIONAL BLOCK DIAGRAMS Figure 1. ADuM4160 Rev. Pr F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that mayresult from its use. Specifications subjectto change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registeredtrademarks arethe property oftheir respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADuM4160 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications....................................................................................... 1 Pin Configurations and Function Descriptions ............................8 General Description ......................................................................... 1 Application Information................................................................ 10 Functional Block Diagrams............................................................. 1 Functional Description.............................................................. 10 Revision History ............................................................................... 2 Product Useage ........................................................................... 10 Specifications..................................................................................... 3 Power Supply Options ............................................................... 10 Electrical Characteristics............................................................. 3 PC Board Layout ........................................................................ 11 Package Characteristics ............................................................... 5 Regulatory Information............................................................... 5 Propagation Delay-Related Parameters Error! Bookmark not defined. Insulation and Safety-Related Specifications............................ 5 DC Correctness and Magnetic Field Immunity..................... 11 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 6 Insulation Lifetime ..................................................................... 12 Outline Dimensions ....................................................................... 14 Recommended Operating Conditions ...................................... 6 Ordering Guide .......................................................................... 14 Absolute Maximum Ratings............................................................ 7 REVISION HISTORY 6 Rev. Pr F | Page 2 of 14 Preliminary Technical Data ADuM4160 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4.0 V ≤ VBUS1 ≤ 5.5 V, 4.0 V ≤ VBUS2 ≤ 5.5 V; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. All voltages are relative to their respective ground. Table 1. Parameter DC SPECIFICATIONS ADuM4160, Total Supply Current1 1.5 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current 12 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current Idle Current VDD1 or VBUS1 Idle Current Input Currents Single Ended Logic High Input Threshold Single Ended Logic Low Input Threshold Single Ended Input Hysteresis Differential Input Sensitivity Differential Common Mode Voltage Range Logic High Output Voltages Logic Low Output Voltages VDD1 and VDD2 Supply Under Voltage Lockout VBUS1 and VBUS2 Supply Under Voltage Lockout Transceiver capacitance Capacitance Matching Full Speed Driver Impedance Impedance Matching SWITCHING SPECIFICATIONS, I/O pins Low speed Data Rate2 Propagation Delay3 Side 1 Output Rise/Fall Time (10% to 90%) Low Speed Side 2 Output Rise/Fall Time (10% to 90%) Low Speed Low Speed Differential Jitter – Next Transition Low Speed Differential Jitter – Paired Transition SWITCHING SPECIFICATIONS, I/O pins Full speed Maximum Data Rate4 Propagation Delay5 Output Rise/Fall Time (10% to 90%) Full Speed Full Speed Differential Jitter – Next Transition Full Speed Differential Jitter – Paired Transition For All Operating Modes Symbol Typ Max Unit Test Conditions IDD1 (L) IDD2 (L) 5 5 7 7 mA mA 750kHz logic signal rate CL=450pF 750kHz logic signal rate CL=450pF IDD1 (F) IDD2 (F) 6 6 8 8 mA mA 6 MHz logic signal rate CL=50pF 6 MHz logic signal rate CL=50pF 1.7 +0.1 2.5 +1 mA μA IDD1 (I) IDD-, IDD+, IUD+,IUD-, ISPD, IPIN, ISPU, IPDEN VIH VIL VHST VDI VCM Min −1 2.0 0.8 0.7V 0.4 0.2 0.8 VOH VOL VUVLO VUVLOB CIN 2.8 0 2.5 3.6 ZOUTH 4 0 V ≤ VDD-, VDD+, VUD+,VUD-, VSPD, VPIN, VSPU, VPDEN ≤ 3.0 V V V V |VXD+ - VXD-| V V RL=15kΩ VL=0V RL=1.5kΩ VL=3.6V UD+, UD-, DD+, DD- to ground 20 10 pF % Ω % 2.5 3.6 0.3 3.0 4.3 10 10 1.5 tPHL, tPLH tRF/tFF 75 325 300 Mbps CL = 50 pF ns CL = 50 pF ns CL = 200 pF SPD=SPU=low tRF/tFF 75 300 ns CL = 450 pF SPD=SPU=low ns ns CL = 50 pF, CL = 50 pF, Mbps ns ns ns ns CL = 50 pF CL = 50 pF CL = 50 pF SPD=SPU=high CL = 50 pF, CL = 50 pF, |tLJN| |tLJP| 45 15 tPHL, tPLH tRL/tFL |tHJN| |tHJP| 12 20 4 60 3 1 Rev. Pr F | Page 3 of 14 750 20 ADuM4160 Parameter Common-Mode Transient Immunity at Logic High Output6 Common-Mode Transient Immunity at Logic Low Output6 Preliminary Technical Data Symbol |CMH| Min 25 Typ 35 |CML| 25 35 1 Max Unit Test Conditions kV/μs VUD+, VUD-, VDD+, VDD- = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V kV/μs VUD+, VUD-, VDD+, VDD- = 0 V, VCM = 1000 V, transient magnitude = 800 V The supply current values for the device running at a fixed continuous data rate 50% duty cycle alternating J and K states. Supply current values are specified with USB compliant load present. The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 3 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 6 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 2 Rev. Pr F | Page 4 of 14 Preliminary Technical Data ADuM4160 PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 Input Capacitance2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 Symbol RI-O CI-O CI θJCI θJCO Min Typ 1012 2.2 4.0 33 28 Max Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside 1 Device considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM4160 has been approved by the organizations listed in Table 3. Refer to Table 10 and Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 3. UL (Pending) Recognized under 1577 component recognition program1 Double Protection 5000 V rms isolation voltage File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage Reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage File 205078 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 846 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 5000 L(I01) 8.0 min Unit Conditions V rms 1 minute duration mm Measured from input terminals to output terminals, shortest distance through air 8.0 mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 II Material Group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Rev. Pr F | Page 5 of 14 ADuM4160 Preliminary Technical Data DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 5. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 846 1590 V peak V peak 1375 1018 V peak V peak VTR 6000 V peak TS IS1 IS2 RS 150 265 335 >109 °C mA mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure ( see Figure 2) VIO = 500 V 350 RECOMMENDED OPERATING CONDITIONS 300 Table 6. Parameter Operating Temperature Supply Voltages1 Input Signal Rise and Fall Times 250 SIDE #2 200 Symbol Min TA −40 VBUS1,VBUS2, 3.0 Max +105 5.5 1.0 Unit °C V ms 150 SIDE #1 1 100 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 50 0 0 50 100 150 CASE TEMPERATURE (°C) 200 03786-004 SAFETY-LIMITING CURRENT (mA) Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. Pr F | Page 6 of 14 Preliminary Technical Data ADuM4160 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VBUS1, VBUS2, VDD1, VDD2)1 Input Voltage (VUD+,VUD-, VSPU)1, 2 Output Voltage (VDD-, VDD+, VSPD, VPIN)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2(IO2) Common-Mode Transients4 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +6.5 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V ESD CAUTION −10 mA to +10 mA −10 mA to +10 mA −100 kV/μs to +100 kV/μs 1 All voltages are relative to their respective ground. VDDI , VDD2, VBUSI and VBUS2 refer to the supply voltages on the input and output sides of a given channel, respectively.. 3 See Figure 2 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Ratings may cause latchup or permanent damage. 2 Table 8. Maximum Continuous Working Voltage1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Max 565 Unit V peak Constraint 50-year minimum lifetime V peak 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1131 560 V peak V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. Pr F | Page 7 of 14 ADuM4160 Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. ADuM4160 Pin Configuration Table 9. ADuM4160 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic Direction Description Power VBUS1 Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, connect VBUS1 to the USB power bus. Where the isolator will be powered from a 3.3V power supply, connect VBUS1 to VDD1 and to the external 3.3V Power Supply. Bypass to GND1 is required. GND1 Return Ground 1. Ground reference for isolator Side 1. VDD1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, The VDDI pin should be used for a bypass capacitor to GND1, no other connections should be made.. Where the isolator will be powered from a 3.3V power supply, connect VBUS1 to VDD1 and to the external 3.3V Power Supply. Bypass to GND1 is required. PDEN I Pull Down Enable, This pin is read when exiting reset. This pin shall be connected to VDD1 for standard operation. When connected to GND1 while exiting from reset, the down stream pull down resistors are disconnected, allowing buffer impedance measurements. SPU I Speed Select Up-Stream Buffer. Active high logic input. selects Full speed slew rate and timing and logic conventions when SPU is high. This input must be set high or low and must match pin 10. UDI/O Up-stream DUD+ I/O Up-stream D+ GND1 Return Ground 1. Ground reference for isolator Side 1. GND2 Return Ground 2. Ground reference for isolator Side 2. DD+ I/O Down-stream D+ DDI/O Down-stream D-. PIN I Up-stream pull-up enable. SPD controls the power connection to the pull-up for the up-stream port. It may be tied to VDD2 for operation on power up, or tied to an external control signal for application requiring delayed enumeration. SPD I Speed Select Down-Stream Buffer. Active high logic input. selects Full speed slew rate and timing and logic conventions when SPU is high. This input must be set high or low and must match pin 7. VDD2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, The VDDI pin should be used for a bypass capacitor to GND2, no other connections should be made.. Where the isolator will be powered from a 3.3V power supply, connect VBUS2 to VDD2 and to the external 3.0V to 3.3V Power Supply. Bypass to GND2 is required. Return Ground 2. Ground reference for isolator Side 2. GND2 VBUS2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5V to 5.5V, connect VBUS2 to the USB power bus. Where the isolator will be powered from a 3.3V power supply, connect VBUS2 to VDD2 and to the external 3.0V to 3.3V Power Supply. Bypass to GND2 is required. Rev. Pr F | Page 8 of 14 Preliminary Technical Data ADuM4160 Table 10. Truth Table, Control Signals and Power (Positive Logic) VBUS1, VDD1 State VSPU Input VUD+, VUDstate H Active Powered L Active L VBUS2, VDD2 State VDD+, VDDstate VPIN Input VSPD Input Notes Powered Active H H Powered Powered Active H L Active Powered Powered Active H H H Active Powered Powered Active H L X Z Powered Powered Z L X X X Unpowered Powered Z X X X Z Powered X X X Input and output logic set for Full speed logic convention and timing Input and output logic set for Low speed logic convention and timing VSPU and VSPD must be set to the same value, Mixed Speed and Logic convention is not allowed VSPU and VSPD must be set to the same value, Mixed Speed and Logic convention is not allowed Upstream Side 1 presents a disconnected state to the USB cable. When Power is not present on side 1, the side 2 data output drivers will revert to High Z within 32 bit times. Side 2 initializes in high Z state. When Power is not present on the VDD2, the up-stream side will disconnect the pull-up and disable the upstream drivers within 32 bit times. Unpowered Rev. Pr F | Page 9 of 14 ADuM4160 Preliminary Technical Data APPLICATION INFORMATION FUNCTIONAL DESCRIPTION PRODUCT USAGE USB isolation in the D+/D- lines is challenging for several reasons. First, access to the output enable signals is normally required to control the transceiver. Some level of intelligence must be built into the isolator to interpret the data stream and determine when to enable and disable its up-stream and down stream output buffers. Second, the signal must be faithfully be reconstructed on the output side of the coupler while retaining precise timing and not passing transient states such as invalid SE0 and SE1 states. In addition, the part must meet the low power requirements of the Suspend mode. The ADuM4160 is designed to be integrated into a USB peripheral with an upstream facing USB port as shown in Figure 4. The key design points are: The iCoupler technology is based on edge detection, and so lends itself well to the USB application. The flow of data through the device is accomplished by monitoring the inputs for activity, and setting the direction for data transfer based on a transition from the Idle state. Once data directionality is established, data is transferred until either an End Of Packet (EOP), or a sufficiently long idle state is encountered. At this point, the coupler disables its output buffers and monitors its inputs for the next activity During the data transfers, the input side of the coupler holds its output buffers disabled. The output side enables its output buffers and disables edge detection from the input buffers. This allows the data to flow in one direction without wrapping back through the coupler making the iCoupler latch. Timing is based on the differential input signal transition. Logic is included to eliminate any artifacts due to different input thresholds of the differential and single ended buffers. The input state is transferred across the isolation barrier, as one of three valid states, J. K, or SE0. The signal is reconstructed at the output side with a fixed time delay from the input side differential input. 1) The USB host provides power for the upstream side of the ADuM4160 through the cable. 2) The peripheral supply provides power to the downstream side of the ADuM4160 3) The isolator interfaces with the D+/D- lines of the peripheral controller, so it behaves like a single port hub to the peripheral. 4) Peripheral devices have a fixed data rate that is set at design time. The ADuM4160 has configuration pins SPU and SPD that are set by the user to match this speed on the upstream and downstream sides of the coupler. 5) USB enumeration begins when either the D+ or Dline is pulled high at the peripheral end of the USB cable. Control of the timing of this event is provided by the PIN input on the down stream side of the coupler. 6) Integrated pull-up and pull-down resistors are internal to the coupler. The requirement for low power suspend mode is addressed by making the Idle state power consumption lower than the Suspend limit of 2.5mA. The iCoupler has no suspend feature apart from a low Idle current that meets the required level. The ADuM4160 is designed to interface with an up-stream facing Low/Full speed USB port by isolating the D+/D- lines. An upstream facing port supports only one speed of operation so the speed related parameters, J/K logic levels and D+/D- slew rate are set to match the speed of the upstream facing peripheral port (see Table 10). A control line on the downstream side of the ADuM4160 activates the Idle state pull-up resistor. This allows the down stream port to control when the upstream port attaches to the USB bus. The pin can be tied to the peripheral pull-up, a control line, or the Peripheral’s power supply depending on when the initial bus connect is performed. Figure 4 TypicaADuM4160l Application Other than, the delayed application of pull-up resistors, the ADuM4160 is be transparent to USB traffic, and no modifications to the peripheral design are required to isolate. The isolator does add propagation delay to the signals equivalent to a hub and cable so isolates peripherals must be treated as if there was a built in hub when determining the maximum number of hubs in a data chain. POWER SUPPLY OPTIONS In most USB transceivers, 3.3V is derived from the 5V USB bus through an LDO regulator. The ADuM4160 includes an internal LDO regulator on each side to perform this function. It also allows the regulator to be bypassed if 3.3V is available directly. This feature is especially useful in peripherals where there may not be a 5V power rail. Two power input pins are Rev. Pr F | Page 10 of 14 Preliminary Technical Data ADuM4160 present on each side, VBUSx and VDDx. If 5V is available, it is connected to VBUSx and the internal regulator makes 3.3V to run the coupler. If 3.3V is available, it can be provided to both VBUSx and VDDx. This disables the regulator and powers the coupler directly from the 3.3V supply. Figure 5, shows how a typical application is connected if the upstream side of the coupler was getting power directly from the USB bus and the downstream side was receiving 3.3V from the peripheral power supply. PC BOARD LAYOUT The ADuM4160 digital isolator requires no external interface circuitry for the logic interfaces. For full speed operation the D+ and D- line on each side of the device require a 24Ω ±1% series termination resistor. These resistors are not required for low speed applications. Power supply bypassing is required at the input and output supply pins (Figure 5). Install bypass capacitors between VBUSx and VDDx on each side of the chip. The capacitor value should have a minimum value of 0.1 μF and low ESR. The total lead length between both ends of the capacitor and the power supply pin should not exceed 10 mm . Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15 should also be considered, unless the ground pair on each package side is connected close to the package. side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit. The limitation on the ADuM4160’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM4160 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM4160 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 6. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) 100 10 1 0.1 In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input 0.001 1k 10k 100k 10M 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 03786-019 0.01 Figure 5. Recommended Printed Circuit Board Layout Figure 6. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM4160 transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM4160 is extremely immune and can be affected only by extremely large currents operated at Rev. Pr F | Page 11 of 14 ADuM4160 Preliminary Technical Data high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM4160 to affect the component’s operation. DISTANCE = 1m INSULATION LIFETIME 100 All insulation structures will eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependant on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM4160. 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) Figure 7. Maximum Allowable Current for Various Current-to-ADuM4160 Spacings 100M 03786-020 MAXIMUM ALLOWABLE CURRENT (kA) 1000 Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. ADI performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 8 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM4160 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 9, and Figure 10 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines ADI’s recommended maximum working voltage. Rev. Pr F | Page 12 of 14 Preliminary Technical Data ADuM4160 In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50 year service life. The working voltages listed in Table 8 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 91or Figure 10 should be treated as a bipolar ac waveform and its peak voltage should be limited to the 50 year lifetime voltage value listed in Table 8. 05007-021 RATED PEAK VOLTAGE 0V Figure 8. Bipolar AC Waveform 05007-022 RATED PEAK VOLTAGE 0V Figure 9. Unipolar AC Waveform 05007-023 RATED PEAK VOLTAGE 0V Figure 10. DC Waveform 1 The voltage presented in figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0V. Rev. Pr F | Page 13 of 14 Preliminary Technical Data ADuM4160 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 10.00 (0.3937) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 032707-B 1 Figure 11. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimension shown in millimeters and (inches) ORDERING GUIDE Model ADuM4160BRWZ 1,2 EVAL-ADUM4160EBZ 1 2 Number of Inputs, VDD1 Side Number of Inputs, VDD2 Side Maximum Data Rate (Mbps) Maximum Propagation Delay, 5 V (ns) Maximum Jitter (ns) Temperature Range Package Description Package Option 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16 Z = RoHS Compliant Part. Specifications represent full speed buffer configuration. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR08171-0-5/09(PrF) Rev. Pr F | Page 15 of 15