Intel P4 & AMD K7 ACPI Controller Presentation Content 1. Block Diagram 2. Power Function 3. Digital Function 4. Circuit Design 5. Q&A Block Diagram C2 CharPmp C1 S3# S5# DDRTYPE RSMRST# PCI_RST# PCI_BUF# SLOT_RST# HDD_RST# DEV_RST# FP_RST# PWROK CPU_PWGD CHIP_PWGD POK1 5V_DRV 5VUSB_DRV 3VSB_DRV Reset Integrated Circuit PWRGD Integrated Circuit Charge Pump Control Circuit DDR Linear mode DDR PWM mode Control Register (CR00~CR06;CR14~CR17) 5VDUAL (CR03) 3VSB (3VDLDEC#) VLR1 VLR2 AGP1.5V PLED I2C 3VSB_SEN 1.2V VCCVID VRAM_HDRV SVRAM_DRV VRAM_HSEN VRAM_DRV VRAM_SEN VRAM_HDRV SVRAM_DRV VRAM_DRV VRAM_SEN VLR1_DRV VLR1_SEN VLR2_DRV VLR2_SEN VID_DRV VID_SEN VIDGD# VAGP_DRV VAGP_SEN PLED0 PLED1 SDA SCL Power Function • Support voltage regulator: • DDR 1 or DDR 2 voltage regulator – – – – – • DDR 1 or DDR 2 voltage select by DDRTYPE (Pin 9) select pin External DDR standby voltage MOS is request when S3 state Support 2 set Linear mode or PWM mode select by PLED1/EXTRAM (Pin 48) The both mode support Adjustment voltage through I2C bus DDR 1 voltage range : 2.5V,2.55V,2.6V,2.65V,2.7V,2.75V,2.8V,2.85V,2.9V,3.0V,3.1V,3.2V,3.3V and default setting is 2.6V – DDR 2 voltage range : 1.8V,1.85V,1.9V,1.95V,2.0V,2.05V,2.1V,2.15V,2.2V,2.25V,2.3V,2.35V,2.4V and default setting is 1.8V – Watching Dog Timer register (CR0x06) can setting keep or not when power off AGP voltage regulator – Support Linear mode or PWM mode – The both mode support Adjust voltage through I2C bus – AGP voltage range : 1.5V,1.55V,1.6V,1.65V,1.7V,1.75V,1.8V,1.9V,2.0V,2.1V,2.2V and default setting is 1.55V – Watching Dog Timer register (CR0x06) can setting keep or not when power off Power Function (Cont.) • 3VSB regulator – Support Single or Dual mode select by PLED0/3VDLDEC#(Pin47) – Single mode : Used one MOS regulate from 5VSB to 3VSB – Dual mode : Used two MOS when S3 or S5 state standby MOS regulate from 5VSB to 3VSB,When S0 state turn on VCC3 MOS to 3VSB • P4 VCC_VID or K7 VCCA2_5 regulator – The default VREF is 1.2V – For K7 VCCA and left pin 13 • VLR1 and VLR2 regulator – Support standby or main VCC regulator for on board chip or device – Both VREF is 1.2V and up 2,4,6,8,12,16 and 20% VREF by I2C adjust Power Function (Cont.) • Support 5VDUAL for USB and KB/MS voltage • Support 9VSB for use OP-Amp extend extra voltage • DDR1(<1.9V), DDR2(<1.25V),AGP(<1.1V) and 3VSB(<2.45V) support power supply shutdown when under voltage protection Digital Function • • • • • Provide ATX PWR_OK and RST_ BTN input for 2 open drain output buffer (CPU and chip PWR_OK) Provide PWR_OK1 for power sequence or standby voltage isolate (This pin is ATX PWR_OK buffer output it can’t be RST_BTN effect) Provide 1 to 4 PCIRST# output buffer,The SLOT_RST# and BUF_RST# is 3.3V TTL output else is open drain (HDD_RST#, DEV_RST#) RSMRST# is delay 88ms from 3VSB ready Provide PLED0,PLED1 support S0,S1,S3,S5,under voltage indicator: – Under voltage issue PLED0 and PLED1 flash by turns about 1/4Hz (If this condition occur system can’t power on unless plug AC power core) Digital Function 20 VCC3 DRIVER(VCC3) 2 3 1 2 3 4 SOLT_RST#(50mA) OD 2 PCIRST# HDDRST#(50mA) 3 OD DEV_RST#(50mA) 20 VCC3 DRIVER(VCC3) OD 2 3 PCI_BUF#(50mA) OD PWR_OK 4 6 8 9 3 2 5 4 7 6 POK1(24mA) U1 2 3 4 VRAM SS:OK 1 AND3 FP_RST# 13 12 16 delay 50mS 14 OD U2 delay 50uS 2 3 4 CPU_PWROK(50mA) 1 OD S3# AND3 CHIP_PWROK(50mA) P20 RAM_HSEN P21 SVRAM_DRV VDIMM LINEAR OR PWM SELECT C89 VDIMM MODE X_C1000P16X LINEAR REGULATOR PWM REGULATOR VCC3 Q50 N-P45N02LD_TO252 2 S 3VDUAL 1 4 D Q49 3 P19 RAM_HDRV G 1 EC82 + EC80 D 2 CD1000U6.3EL11.5-1 X_CD1000U6.3EL11.5-1 2 C155 + 1 N-APM2054N_SOT89 X_C1000P16X Q48 S G N-P45N02LD_TO252 DDR 2.5V Power 1 1 EC83 + EC81 + EC79 2.5V/7A(DIMM)+5A(NB) 2 CD1000U6.3EL11.5-1 X_CD470U10EL11.5 CD1000U6.3EL11.5-1 2 C0.1U10Y + C88 1 VCC_DDR 2 P17 RAM_SEN P18 RAM_DRV Circuit Design (DDR, Linear mode) EXTRAM PULL LOW PULL HIGH Circuit Design (DDR, PWM mode) VDIMM LINEAR OR PWM SELECT VDIMM MODE LINEAR REGULATOR PWM REGULATOR EXTRAM PULL LOW PULL HIGH P21 DMSB P19 DMV Q48 RAM_VREF C90 VCC5 C1000P16X 5 6 7 8 NN-P2103HV_SO8 Close to MS6+ VCC5_SB 5VDIMM + C1000P16X 4 3 2 1 1 R120 33R C89 EC77 CD470U10EL11.5 2 P18 RAM_DRV P17 RAM_SEN 5VDIMM C91 X_C2200P16X CHOKE11 X_C10000P16X R130 2.55KR1% VCC_DDR Q50 CH-4.2U12A G EC80 EC81 EC78 MS-6+_SOP14 C160 C2.2U10X0805 R128 C0.1U16Y 200R CD1000U6.3EL11.5-1 Q49 N-P50N03LD_TO252 CHOKE12 + C161 G + X_0R C0.22U16X + C92 MS5_RST# R127 C88 8 9 10 11 12 13 14 10/13 UPDATE C159 C2.2U10X0805 R124 CLOSE 10R0805 5VDIMM 5VDIMM TO CHIP N-P50N03LD_TO252 CD1000U6.3EL11.5-1 CD1000U6.3EL11.5-1 CD1000U6.3EL11.5-1 2 5.1KR1% BOOT H_DRV PGND ISEN L_DRV VDD VDDA 1 C2200P16X ISET VREF_IN FB COMP SS GND PWROK 2 51KR1% C157 CH-3.3U4A C4.7U10Y0805 L04-33A7021 S-1N5817_DO214AC X_C100000P16X 2 R126 7 6 5 4 3 2 1 D10 C158 X_C0.22U16Y Assume Idram=10A, P50N03LD Rds,on(max)=12mOhm Rsen(R85)>=1.5*Idram*Rds,on(max)/72uA >=1.5*10*12m/72u >=2.5K Ohm CD1000U6.3EL11.5-1 EC79 1+ 2 1 RAM_VREF C93 D U10 X_33R1% R121 +12V C155 EC82 2 S R123 49.9KR1% R125 X_0R S 5.1KR1% R129 D X_C100000P16X R122 1+ 5VDIMM 1 C156 Circuit Design (AGP, Linear mode) D VCC2_5 S N-P3057LD_TO252 VCC_AGP + 1 P24 VAGP_SEN Q51 G EC83 2 P25 VAGP_DRV CD1000U6.3EL11.5-1 Circuit Design (AGP, PWM mode) P25 VAGP_DRV R120 P24 VAGP_SEN AGP_VREF 33R C89 C1000P16X C88 C1000P16X Close to MS6+ AGP POWER CHOKE11 C159 1+ VCC5 C160 CH-3.3U4A L04-33A7021 C90 R124 3.6KR1% 5 6 7 8 VCC_AGP CHOKE12 CH-3.3U4A L04-33A7021 C158 C2.2U10X0805 10/13 UPDATE 4 3 2 1 NN-APM7313_SO8 MS-6+_SOP14 R130 C0.1U16Y C0.22U16X C157 C2.2U10X0805 200R EC78 EC79 R129 10R0805 VCC5 EC77 CD1000U6.3EL11.5-1 CD1000U6.3EL11.5-1 CD1000U6.3EL11.5-1 CLOSE TO CHIP VCC5 + BOOT H_DRV PGND ISEN L_DRV VDD VDDA CD1000U6.3EL11.5-1 Q79 + C156 X_C0.22U16Y X_0R 8 9 10 11 12 13 14 + 49.9KR1% U10 X_33R1% R125 7 6 ISET R128 51KR1% 5 VREF_IN C92 C2200P16X 4 FB X_33R1% 3 COMP 2 SS C91 X_C10000P16X MS5_RST# 1 GND PWROK R127 X_0R 1 R123 AGP_VREF CD1000U6.3EL11.5-1 EC81 2 1+ X_C100000P16X S-1N5817_DO214AC 2 C93 1 R122 2 R126 1 +12V D8 5.1KR1% 2 X_C100000P16X R121 EC80 2 Rsen(R58)>=1.5*Iagp*Rds,on(max)/72uA >=1.5*6*28m/72u >=3.5K Ohm 3VSB 3VSB MODE SELECT 3VSB MODE 3VDLDEC# SINGLE MOSFET DUAL MOSFET PULL HIGH PULL LOW C88 Q48 X_C1000P16X 1 4 3 5V_DRV 2 1 VCC3 G Q49 N-P3057LD_TO252 CD470U10EL11.5 CD470U10EL11.5 5 6 7 8 VCC5_SB 3VDUAL EC78 NN-P2103HV_SO8 D 2 2 EC77 + + 1 S P23 3VSB_DRV P22 3VSB Q10:Imax=1.76A(P3057LD) VCC5_SB 3VSB REGULATE BY 5VSB 3VSB REGULATE BY 5VSB AND VCC3 THE TWO MODE ONLY ONE MODE PRESENT SINGLE MODE DUAL MODE THIS MODE SELECT BY PIN 47 PULL HIGH 5VSB THIS MODE SELECT BY PIN 47 PULL LOW VID, VLR1, VLR2 P13 VIDGD# P14 VID_SEN VID_GD# C88 X_C10U10X1206 VCC_VID / VID_GOOD Place MOSFET near CPU VLR1 VCC5 D 1.2V/150mA S VCC_VID Q48 G P15 VID_DRV N-NDS351AN_SOT23 C155 VCC3 X_C1000P16X VLR2 D C156 X_C1000P16XQ49 G 191R1% Close to MS7 P28 VLR2_DRV R122 P27 VLR2_SEN 1P2VREF 33R C89 + 332R1% R121 P3VA N-P45N02LD_TO252 S P31 VLR1_SEN 1 R120 2 P32 VLR1_DRV EC77 CD470U10EL11.5 C90 C1000P16X C1000P16X Close to MS6+ 5VDUAL CR03 (5VUSB setting Register, Default 0x00h, Read/Write) Bit0 Condition Bit1 0 0 S0, S3 status support 0 1 S0, S3, S5 status support 1 0 S3, S5 status do not support 5V DUAL Power VCC5_SB C89 Q49 X_C2200P16X P30 5VUSB_DRV 4 3 2 1 P29 5V_DRV 5VDUAL 5 6 7 8 D NN-P2103HV_SO8 FRONT G 2 VCC5 S X_C2200P16X + 1 C88 EC77 CD470U10EL11.5 Q48 N-P45N02LD_TO252 VCC5 REAR DDR VTT VCC3 If VTT_DDR need power at S3, direct connect VCC_DDR to VIN D1 1N4001_DO214AC 1+ EC8 2 VCC_DDR 3VDUAL U2 W83310DS_SOIC8 BOOT_SEL VOUT EC11 C15 + C0.1U10Y 4 + C17 3 1 VREF1 R19 EC12 C0.1U10Y CD1000U6.3EL11.5-1 CD1000U6.3EL11.5-1 2 VCTRL GND2 1KR1% 2 1 5 ENABLE R18 VTT_DDR 1 2 6 VIN GND9 7 VREF2 9 8 X_CD1000U6.3EL11.5-1 1KR1% Q&A