SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
FOSVOS TEL: 021-58998693
Table of Contents
Product List ................................................................................................................................................................... 3
Description .................................................................................................................................................................... 3
Features ........................................................................................................................................................................ 3
Pin Configuration ........................................................................................................................................................... 4
Block Diagram ............................................................................................................................................................... 5
Pin Description .............................................................................................................................................................. 6
Special Function Register (SFR) .................................................................................................................................... 7
Function Description .................................................................................................................................................... 10
1. General Features................................................................................................................................................... 10
1.1.
Embedded Flash ..................................................................................................................................... 10
1.2.
IO Pads .................................................................................................................................................. 10
1.3.
Instruction timing Selection ..................................................................................................................... 10
1.4.
The Clock Output Selection..................................................................................................................... 10
1.5.
RESET ................................................................................................................................................... 11
1.5.1.
Hardware RESET function .......................................................................................................... 11
1.5.2.
Software RESET function ........................................................................................................... 11
1.5.3.
Reset status ............................................................................................................................... 11
1.5.4.
Time Access Key register (TAKEY) ............................................................................................. 12
1.5.5.
Software Reset register (SWRES) .............................................................................................. 12
1.5.6.
Example of software reset .......................................................................................................... 12
1.6.
Clocks..................................................................................................................................................... 12
2. Instruction Set ....................................................................................................................................................... 13
3. Memory Structure .................................................................................................................................................. 17
3.1.
Program Memory .................................................................................................................................... 17
3.2.
Data Memory .......................................................................................................................................... 18
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) ................................................................................ 18
3.2.2.
Data memory - higher 128 byte (80h to FFh)............................................................................... 18
4. CPU Engine .......................................................................................................................................................... 19
4.1.
Accumulator............................................................................................................................................ 19
4.2.
B Register ............................................................................................................................................... 19
4.3.
Program Status Word .............................................................................................................................. 20
4.4.
Stack Pointer........................................................................................................................................... 20
4.5.
Data Pointer............................................................................................................................................ 20
4.6.
Data Pointer 1 ......................................................................................................................................... 21
4.7.
Interface control register.......................................................................................................................... 21
5. GPIO ..................................................................................................................................................................... 22
6. Timer 0 and Timer 1............................................................................................................................................... 23
6.1.
Timer/counter mode control register (TMOD)........................................................................................... 23
6.2.
Timer/counter control register (TCON)..................................................................................................... 24
6.3.
T0、T1 signal swapping .......................................................................................................................... 24
7. Serial interface ...................................................................................................................................................... 25
7.1.
Mode 0 ................................................................................................................................................... 26
7.2.
Mode 1 ................................................................................................................................................... 26
7.3.
Mode 2 ................................................................................................................................................... 27
7.4.
Mode 3 ................................................................................................................................................... 27
7.5.
Multiprocessor communication ................................................................................................................ 27
7.6.
Baud rate generator ................................................................................................................................ 28
8. Watchdog timer ..................................................................................................................................................... 29
9. Interrupt................................................................................................................................................................. 33
10. Power Management Unit ....................................................................................................................................... 38
10.1. Idle mode................................................................................................................................................ 38
10.2. Stop mode .............................................................................................................................................. 38
11. PWM - Pulse Width Modulation.............................................................................................................................. 39
12. IIC function ............................................................................................................................................................ 42
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-1-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
13. LVI – Low Voltage Interrupt .................................................................................................................................... 46
14. 10-bit Analog-to-Digital Converter (ADC)................................................................................................................ 47
15. EEPROM .............................................................................................................................................................. 50
16. Comparator ........................................................................................................................................................... 52
DC Characteristics ....................................................................................................................................................... 54
ADC Characteristics..................................................................................................................................................... 56
Comparator Characteristics.......................................................................................................................................... 56
LVI& LVR Characteristics ............................................................................................................................................. 56
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ISSFD-M067
Ver B SM39R08A5 04/22/2013
-2-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Features
Product List
SM39R08A5W10MP
Description
The SM39R08A5 is a 1T (one machine cycle per clock)
single-chip 8-bit microcontroller. It has 8K-byte
embedded Flash for program, and executes all ASM51
instructions fully compatible with MCS-51.
SM39R08A5 contains 256B on-chip RAM, up to 8 GPIOs
(10L package), various serial interfaces and many
peripheral functions as described below. It can be
programmed via writers. Its on-chip ICE is convenient for
users in verification during development stage.
The high performance of SM39R08A5 can achieve
complicated manipulation within short time. About one
third of the instructions are pure 1T, and the average
speed is 8 times of traditional 8051, the fastest one
among all the 1T 51-series.Its excellent EMI and ESD
characteristics are advantageous for many different
applications.
Ordering Information
SM39R08A5ihhkL yymmv
i: process identifier {U = 1.8V ~ 5.5V}
hh: pin count
k: package type postfix {as table below }
L:PB Free identifier
{No text is Non-PB free，”P” is PB free}
yy: year
mm: month
v: version identifier{ A, B,…}
Postfix
Package
M
MSOP (118 mil)
Operating Voltage: 1.8V ~ 5.5V
1~8T modes are software programmable.
Instruction-set compatible with MCS-51.
22.1184MHz Internal RC oscillator, with
programmable clock divider
8K Bytes on-chip flash program memory.
256 bytes RAM as standard 8052,
One serial peripheral interfaces in full duplex mode.
1.1 Synchronous mode, fixed baud rate,
1.2 8-bit UART mode, variable baud rate.
1.3 9-bit UART mode, fixed baud rate,
1.4 9-bit UART mode, variable baud rate.
Additional Baud Rate Generator
Two 16-bit Timer/Counters. (Timer 0, 1)
8 GPIOs(10L MSOP)
Programmable watchdog timer.
One IIC interface. (Master/Slave mode)
10 bit PWM x 4 channel
8 channel 10-bit analog-to-digital converter (ADC)
On-Chip Comparator x 1
On–chip flash memories support IAP/ICP and
EEPROM functions.
On-Chip in-circuit emulator (ICE) functions with
On-Chip Debugger (OCD).
EMI reduction mode (ALE output inhibited).
LVI/LVR.
IO PAD ESD over 4KV.
Enhance user code protection.
External interrupt 0, 1 with four priority levels.
Power management unit for IDLE and power down
modes.
Pin / Pad
Configuration
Page 4
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-3-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Pin Configuration
10 Pin MSOP
TXD/ADC1/Cmp0PIn/T1_2/P3.1
2
ADC2/PWM3/T1_1/P3.2
3
ADC3/PWM2/T0_1/P3.3
4
VSS
5
SM39R08A5
1
(10 Pin Top View)
RXD/ADC0/Cmp0NIn/T0_2/P3.0
10
VCC
9
P3.7/INT1_0/Cmp0Out/ADC7
8
P3.6/PWM0/RESET/ADC6
7
6
P3.5/INT1_1/PWM1/SCL/CLKOUT/ADC5
P3.4/INT0_0/SDA/ADC4
Notes：
1. The pin Reset/P3.6 factory default is GPIO(P3.6). User can configure it to Reset by a flash programmer.
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-4-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
MAX810
Analog
comparator
SRAM
256Bytes
INT0/1
ADC
TXD
RXD
ADC[7:0]
Cmp0PIn
IIC
Cmp0NIn
PWM
Cmp0Out
SCL
SDA
RESET
PWM0~3
Block Diagram
UART
Port 3
Port 3
Timer 0/1
T0
T1
Flash 8KBytes
CPU
Watchdog
Interrupt
ICE
ICP
SDA
SCL
Interface control
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-5-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Pin Description
10 Pin
1
2
3
4
5
Symbol
- P3.0
- RXD
- T0_2
- Cmp0Nin
- ADC0
- P3.1
- TXD
- T1_2
- Cmp0PIn
- ADC1
- P3.2
- PWM3
- ADC2
- T1_1
- P3.3
- PWM2
- ADC3
- T0_1
VSS
I/O
I/O
I/O
I/O
I/O
I
6
- P3.4
- INT0_0
- SDA
- ADC4
I/O
7
- P3.5
- INT1_1
- PWM1
- SCL
- CLKOUT
- ADC5
I/O
8
9
10
- P3.6
- RESET
- PWM0
- ADC6
- P3.7
- INT1_0
- Cmp0Out
- ADC7
VDD
I/O
I/O
I
Description
- Bit 0 of port 3
- Serial interface receive data
- Timer 0 external input 2
- Comparator 0 negative input
- ADC input channel 0
- Bit 1 of port 3
- Serial interface transmit data
- Timer 1 external input 2
- Comparator 0 positive input
- ADC input channel 1
- Bit 2 of port 3
- PWM channel 3
- ADC input channel 2
- Timer 1 external input 1
- Bit 3 of port 3
- PWM channel 2
- ADC input channel 3
- Timer 0 external input 1
Power supply
- Bit 4 of port 3
- External interrupt 0
- IIC SDA pin & On-Chip Instrumentation Command and data
I/O pin synchronous to SCL in ICE and ICP functions
- ADC input channel 4
- Bit 5 of port 3
- External interrupt 1
- PWM channel 1
- IIC SCL pin & On-Chip Instrumentation Clock I/O pin of ICE
and ICP functions
- Clock output
- ADC input channel 5
- Bit 6 of port 3
- Reset pin
- PWM channel 0
- ADC input channel 6
- Bit 7 of port 3
- External interrupt 1
- Comparator 0 output
- ADC input channel 7
Power supply
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ISSFD-M067
Ver B SM39R08A5 04/22/2013
-6-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin
F8
F0
E8
E0
D8
D0
X000
X001
X010
X011
X100
X101
X110
IICS
IICCTL
IICA1
IICA2
IICRWD
IICEBT
CMP0CON
B
ACC
OPPIN
ISPFAH
ISPFAL
ISPFD
P3M0
P3M1
ISPFC
LVC
X111
TAKEY
SWRES
PSW
PWMMDH PWMMDL
C8
C0
B8
B0
A8
A0
IRCON
98
90
88
80
SCON
IEN1
P3
IEN0
IP1
SRELH
PWMD0H PWMD0L PWMD1H
PWMD2H PWMD2L PWMD3H PWMD3L
IP0
SRELL
ADCC1
ADCC2
PWMD1L
PWMC
WDTC
WDTK
ADCDH
ADCDL
ADCCS
RSTS
SBUF
IEN2
AUX
TCON
IRCON2
TMOD
TL0
TL1
TH0
TH1
SP
DPL
DPH
DPL1
DPH1
CKCON
IFCON
PCON
Bin/Hex
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
Note: Special Function Registers reset values and description for SM39R08A5
Register
Location
Reset value
Description
SP
81h
07h
Stack Pointer
DPL
DPH
DPL1
DPH1
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
IFCON
82h
83h
84h
85h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
10h
00h
Data Pointer 0 low byte
Data Pointer 0 high byte
Data Pointer 1 low byte
Data Pointer 1 high byte
Power Control
Timer/Counter Control
Timer Mode Control
Timer 0, low byte
Timer 1, low byte
Timer 0, high byte
Timer 1, high byte
Clock control register
Interface control register
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-7-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
AUX
SCON
91h
98h
00h
00h
Auxiliary register
Serial Port Control Register
SBUF
IEN2
RSTS
IEN0
IP0
SRELL
99h
9Ah
A1h
A8h
A9h
AAh
00h
00h
00h
00h
00h
00h
Serial Port Data Buffer
Interrupt Enable Register 2
Reset status register
Interrupt Enable Register 0
Interrupt Priority Register 0
Serial Port Reload Register, low byte
ADCC1
ABh
00h
ADC Control 1 Register
ADCC2
ADCDH
ADCDL
ADCCS
P3
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMC
WDTC
WDTK
IEN1
IP1
SRELH
PWMD0H
PWMD0L
PWMD1H
PWMD1L
IRCON
PWMMDH
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BCh
BDh
BEh
BFh
C0h
CEh
00h
00h
00h
00h
FFh
00h
00h
00h
00h
00h
04h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
ADC Control 2 Register
ADC data high byte
ADC data low byte
ADC clock select
Port 3
PWM 2 Data register high byte
PWM 2 Data register low byte
PWM 3 Data register high byte
PWM 3 Data register low byte
PWM control register
Watchdog timer control register
Watchdog timer refresh key.
Interrupt Enable Register 1
Interrupt Priority Register 1
Serial Port Reload Register, high byte
PWM 0 Data register high byte
PWM 0 Data register low byte
PWM 1 Data register high byte
PWM 1 Data register low byte
Interrupt Request Control Register
PWM Max Data Register, high byte.
PWMMDL
PSW
P3M0
P3M1
ACC
CFh
D0h
DAh
DBh
E0h
00h
00h
00h
00h
00h
PWM Max Data Register, low byte.
Program Status Word
Port 3 output mode 0
Port 3 output mode 1
Accumulator
ISPFAH
ISPFAL
ISPFD
ISPFC
LVC
SWRES
E1h
E2h
E3h
E4h
E6h
E7h
0Fh
FFh
FFh
00h
20h
00h
ISP Flash Address-High register
ISP Flash Address-Low register
ISP Flash Data register
ISP Flash control register
Low voltage control register
Software Reset register
B
OPPIN
F0h
F6H
00h
00h
B Register
Op/Cmp pin select
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-8-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
TAKEY
IICS
F7h
F8h
00h
00h
Time Access Key register
IIC status register
IICCTL
IICA1
IICA2
IICRWD
IICEBT
CMP0CON
F9h
FAh
FBh
FCh
FDh
FEh
04h
A0h
60h
00h
00h
00h
IIC control register
IIC channel Address 1 register
IIC channel Address 2 register
IIC channel Read / Write Data buffer
IIC Enable Bus Transaction
Comparator 0 control
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Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
-9-
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Function Description
1. General Features
SM39R08A5 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following
sections.
1.1. Embedded Flash
The program can be loaded into the embedded 8KB Flash memory via its writer. The high-quality Flash has a 100K-write
cycle life, suitable for re-programming and data recording as EEPROM.
1.2. IO Pads
The SM39R08A5 has an I/O port: Port 3. Port 3 is 8-bit port. These are: quasi-bidirectional (standard 8051 port outputs),
push-pull, open drain, and input-only. As described in section 5.
The RESET Pin can be configured as I/O port P3.6, when the user uses on-chip hardware RESET mechanism.
1.3. Instruction timing Selection
The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM39R08A5 is a 1T to 8T MCU,
i.e., its machine cycle is one-clock to eight-clock. In the other words, it can execute one instruction within one clock to only
eight clocks.
Mnemonic: CKCON
7
6
5
ITS
4
3
-
2
-
Address: 8Eh
1
0
Reset
CLKOUT
10H
ITS: Instruction timing select.
ITS [6:4]
Instruction timing
000
1T mode
001
2T mode (default)
010
3T mode
011
4T mode
100
5T mode
101
6T mode
110
7T mode
111
8T mode
The default is in 2T mode, and it can be changed to another Instruction timing mode if CKCON [6:4] (at address 8Eh) is
change any time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for all
the instructions are given in the next section.
1.4. The Clock Output Selection
The SM39R08A5 can generate a clock output signal at P3.5. The CKCON [1:0] (at address 8Eh) can change any time.
CLKOUT: Clock output select.
CKCON [1:0]
Mode.
00
GPIO (P3.5)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 10 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
01
10
11
Fosc
Fosc/2
Fosc/4
1.5. RESET
1.5.1. Hardware RESET function
SM39R08A5 provides on-chip hardware RESET mechanism,，the reset duration is programmable by writer or ICP。
on-chip hardware RESET duration
25ms (default)
200ms
100ms
50ms
16ms
8ms
4ms
1.5.2. Software RESET function
SM39R08A5 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must
write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register
(SWRES) write attribute. After SWRES register obtain the write authority, the firmware can write FFh to the SWRES
register. The hardware will decode a reset signal that “OR” with the other hardware reset. The SWRES register is
self-reset at the end of the software reset procedure.
Mnemonic
Description
TAKEY
SWRES
Time Access Key register
Software Reset register
Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Software Reset function
F7h
TAKEY [7:0]
E7h
SWRES [7:0]
Bit 1
Bit 0
RESET
00H
00H
1.5.3. Reset status
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 11 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
1.5.4. Time Access Key register (TAKEY)
Mnemonic: TAKEY
7
6
5
4
3
TAKEY [7:0]
2
1
Address: F7H
0
Reset
00H
Software reset register (SWRES) is read-only by default; software must write three specific values
55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That
is:
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
1.5.5. Software Reset register (SWRES)
Mnemonic: SWRES
7
6
5
4
3
SWRES [7:0]
2
1
Address: E7H
0
Reset
00H
SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure.
SWRES [7:0] = FFh, software reset.
SWRES [7:0] = 00h ~ FEh, MCU no action.
1.5.6. Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #0FFh ; software reset MCU
1.6. Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in Table 1-1, the clock
source can set by writer or ICP.
Table 1-1: Selection of clock source
Clock source
22.1184MHz from internal OSC
11.0592MHz from internal OSC
5.5296MHz from internal OSC
2.7648MHz from internal OSC
1.3824MHz from internal OSC
There may be having a little variance in the frequency from the internal OSC. The max variance as giving in Table 1-1
Table 1-1: Temperature with variance
Temperature Max Variance
25℃
±2%
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 12 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
2. Instruction Set
All SM39R08A5 instructions are binary code compatible and perform the same functions as they do with the industry
standard 8051. The following tables give a summary of the instruction set cycles of the SM39R08A5 Microcontroller core.
Mnemonic
ADD A,Rn
ADD A,direct
Table 2-1: Arithmetic operations
Description
Add register to accumulator
Add direct byte to accumulator
Code
28-2F
25
Bytes
1
2
Cycles
1
2
ADD A,@Ri
ADD A,#data
ADDC A,Rn
ADDC A,direct
Add indirect RAM to accumulator
Add immediate data to accumulator
Add register to accumulator with carry flag
Add direct byte to A with carry flag
26-27
24
38-3F
35
1
2
1
2
2
2
1
2
ADDC A,@Ri
Add indirect RAM to A with carry flag
36-37
1
2
ADDC A,#data
SUBB A,Rn
SUBB A,direct
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
34
98-9F
95
2
1
2
2
1
2
SUBB A,@Ri
SUBB A,#data
INC A
INC Rn
INC direct
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment accumulator
Increment register
Increment direct byte
96-97
94
04
08-0F
05
1
2
1
1
2
2
2
1
2
3
INC @Ri
INC DPTR
DEC A
DEC Rn
Increment indirect RAM
Increment data pointer
Decrement accumulator
Decrement register
06-07
A3
14
18-1F
1
1
1
1
3
1
1
2
DEC direct
DEC @Ri
MUL AB
DIV
DA A
Decrement direct byte
Decrement indirect RAM
Multiply A and B
Divide A by B
Decimal adjust accumulator
15
16-17
A4
84
D4
2
1
1
1
1
3
3
5
5
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 13 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic
ANL A,Rn
Table 2-2: Logic operations
Description
AND register to accumulator
Code
58-5F
ANL A,direct
AND direct byte to accumulator
ANL A,@Ri
ANL A,#data
ANL direct,A
ANL direct,#data
Bytes
1
Cycles
1
55
2
2
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
56-57
54
52
53
1
2
2
3
2
2
3
4
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,#data
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
48-4F
45
46-47
44
1
2
1
2
1
2
2
2
ORL direct,A
OR accumulator to direct byte
42
2
3
ORL direct,#data
XRL A,Rn
XRL A,direct
OR immediate data to direct byte
Exclusive OR register to accumulator
Exclusive OR direct byte to accumulator
43
68-6F
65
3
1
2
4
1
2
XRL A,@Ri
Exclusive OR indirect RAM to accumulator
66-67
1
2
XRL A,#data
XRL direct,A
XRL direct,#data
CLR A
Exclusive OR immediate data to accumulator
Exclusive OR accumulator to direct byte
Exclusive OR immediate data to direct byte
Clear accumulator
64
62
63
E4
2
2
3
1
2
3
4
1
CPL A
RL A
RLC A
RR A
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
F4
23
33
03
1
1
1
1
1
1
1
1
RRC A
SWAP A
Rotate accumulator right through carry
Swap nibbles within the accumulator
13
C4
1
1
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 14 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic
MOV A,Rn
MOV A,direct
Table 2-3: Data transfer
Description
Move register to accumulator
Move direct byte to accumulator
Code
E8-EF
E5
Bytes
1
2
Cycles
1
2
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV Rn,direct
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
E6-E7
74
F8-FF
A8-AF
1
2
1
2
2
2
2
4
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct1,direct2
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
78-7F
F5
88-8F
85
2
2
2
3
2
3
3
4
MOV direct,@Ri
MOV direct,#data
MOV @Ri,A
MOV @Ri,direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
86-87
75
F6-F7
A6-A7
2
3
1
2
4
3
3
5
MOV @Ri,#data
Move immediate data to indirect RAM
76-77
2
3
MOV DPTR,#data16
Load data pointer with a 16-bit constant
90
3
3
MOVC A,@A+DPTR
MOVC A,@A+PC
PUSH direct
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Push direct byte onto stack
93
83
C0
1
1
2
3
3
4
POP direct
XCH A,Rn
XCH A,direct
XCH A,@Ri
XCHD A,@Ri
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low-order nibble indir. RAM with A
D0
C8-CF
C5
C6-C7
D6-D7
2
1
2
1
1
3
2
3
3
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 15 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic
ACALL addr11
Table 2-4: Program branches
Description
Absolute subroutine call
Code
xxx11
LCALL addr16
Long subroutine call
RET
RETI
AJMP addr11
LJMP addr16
Bytes
2
Cycles
6
12
3
6
from subroutine
from interrupt
Absolute jump
Long iump
22
32
xxx01
02
1
1
2
3
4
4
3
4
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
Short jump (relative addr.)
Jump indirect relative to the DPTR
Jump if accumulator is zero
Jump if accumulator is not zero
80
73
60
70
2
1
2
2
3
2
3
3
JC rel
Jump if carry flag is set
40
2
3
JNC
JB bit,rel
JNB bit,rel
Jump if carry flag is not set
Jump if direct bit is set
Jump if direct bit is not set
50
20
30
2
3
3
3
4
4
JBC bit,direct rel
Jump if direct bit is set and clear bit
10
3
4
CJNE A,direct rel
CJNE A,#data rel
CJNE Rn,#data rel
CJNE @Ri,#data rel
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immed. to reg. and jump if not equal
Compare immed. to ind. and jump if not equal
B5
B4
B8-BF
B6-B7
3
3
3
3
4
4
4
4
DJNZ Rn,rel
DJNZ direct,rel
NOP
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
D8-DF
D5
00
2
3
1
3
4
1
Mnemonic
CLR C
CLR bit
Table 2-5: Boolean manipulation
Description
Clear carry flag
Clear direct bit
Code
C3
C2
SETB C
SETB bit
CPL C
CPL bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
ANL C,bit
ANL C,/bit
ORL C,bit
ORL C,/bit
MOV C,bit
MOV bit,C
Bytes
1
2
Cycles
1
3
D3
D2
B3
B2
1
2
1
2
1
3
1
3
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
82
B0
72
A0
2
2
2
2
2
2
2
2
Move direct bit to carry flag
Move carry flag to direct bit
A2
92
2
2
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 16 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
3. Memory Structure
The SM39R08A5 memory structure follows general 8052 structure. It is 8KB program memory.
3.1. Program Memory
The SM39R08A5 has 8KB on-chip flash memory which can be used as general program memory or EEPROM. The
address range for the 8K byte is $0000 to $1FFF. It can be used to record any data as EEPROM. The procedure of this
EEPROM application function is described in the section 15.
1FFF
8K Program
Memory space
0000
Fig. 3-1: SM39R08A5 programmable Flash
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 17 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
3.2. Data Memory
The SM39R08A5 has 256Bytes on-chip SRAM; 256 Bytes of it are the same as general 8052 internal memory structure
FF
FF
Higher 128 Bytes (Accessed by
indirect addressing mode only)
SFR (Accessed by direct addressing
mode only)
80
7F
80
Lower 128 Bytes (Accessed by
direct & indirect addressing mode )
00
Fig. 3-2: RAM architecture
3.2.1. Data memory - lower 128 byte (00h to 7Fh)
Data memory 00h to FFh is the same as 8052.
The address 00h to 7Fh can be accessed by direct and indirect addressing modes.
Address 00h to 1Fh is register area.
Address 20h to 2Fh is memory bit area.
Address 30h to 7Fh is for general memory area.
3.2.2. Data memory - higher 128 byte (80h to FFh)
The address 80h to FFh can be accessed by indirect addressing mode.
Address 80h to FFh is data area.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 18 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
4. CPU Engine
The SM39R08A5 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM39R08A5 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following chapter describes the main engine register.
Mnemonic
Description
Direct
Bit 7
ACC
B
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 0
Data pointer high
0
Auxiliary register
Interface control
register
E0h
F0h
ACC.7
B.7
D0h
CY
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
IFCON
Bit 6
Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
AC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
ACC.4
B.4
ACC.3
B.3
ACC.2
B.2
ACC.1
B.1
ACC.0
B.0
00H
00H
OV
PSW.1
P
00H
F0
RS[1:0]
81h
82h
SP[7:0]
DPL[7:0]
07H
00H
83h
DPH[7:0]
00H
84h
DPL1[7:0]
00H
85h
DPH1[7:0]
00H
91h
BRGS
-
-
8Fh
-
CDPR
-
PTS[1:0]
-
-
PINTS[1:0]
DPS
00H
-
ISPE
00H
-
4.1. Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
ACC.7 ACC.6
5
ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0
00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2. B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
7
6
B.7
B.6
5
B.5
4
B.4
3
B.3
2
B.2
1
B.1
Address: F0h
0
Reset
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 19 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
4.3. Program Status Word
Mnemonic: PSW
7
6
CY
AC
5
F0
4
3
RS [1:0]
2
OV
1
F1
Address: D0h
0
Reset
P
00h
CY: Carry flag.
AC: Auxiliary Carry flag for BCD operations.
F0: General purpose Flag 0 available for user.
RS[1:0]: Register bank select, used to select working register bank.
RS[1:0]
Bank Selected
Location
00
Bank 0
00h – 07h
01
Bank 1
08h – 0Fh
10
Bank 2
10h – 17h
11
Bank 3
18h – 1Fh
OV: Overflow flag.
F1: General purpose Flag 1 available for user.
P: Parity flag, affected by hardware to indicate odd/even number of “one” bits in the
Accumulator, i.e. even parity.
4.4. Stack Pointer
The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL
instructions, causing the stack to start from location 08h.
Mnemonic: SP
7
6
5
4
3
2
1
SP [7:0]
Address: 81h
0
Reset
07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other
words, it always points to the top of the stack.
4.5. Data Pointer
The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte
register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access
the external code or data space (e.g. MOVC A, @A+DPTR, @DPTR respectively).
Mnemonic: DPL
7
6
5
3
DPL [7:0]
2
1
Address: 82h
0
Reset
00h
4
3
DPH [7:0]
2
1
Address: 83h
0
Reset
00h
4
DPL[7:0]: Data pointer Low 0
Mnemonic: DPH
7
6
5
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 20 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
4.6. Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM39R08A5 core the standard data pointer is called DPTR; the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located
in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently
selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
2
1
Address: 84h
0
Reset
00h
4
3
DPH1 [7:0]
2
1
Address: 85h
0
Reset
00h
4
2
1
PINTS[1:0]
Address: 91h
0
Reset
DPS
00H
2
-
Address: 8Fh
0
Reset
ISPE
00H
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
BRGS
-
5
-
3
PTS[1:0]
DPS: Data Pointer selects register.
DPS = 1 is selected DPTR1.
4.7. Interface control register
Mnemonic: IFCON
7
6
5
CDPR
-
4
-
3
-
1
-
CDPR: code protect (Read Only)
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 21 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
5. GPIO
The SM39R08A5 has one I/O ports: Port 3. These are quasi-bidirectional (standard 8051 port outputs), push-pull, open
drain, and input-only. Two configuration registers for each port select the output type for each port pin. All I/O port pins on
the SM39R08A5 may be configured by software to one of four types on a pin-by-pin basis, shown as below:
Mnemonic
Description
P3M0
P3M1
Port 3 output mode 0
Port 3 output mode 1
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Direct
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
I/O port function register
DAh
P3M0[7:0]
DBh
P3M1[7:0]
Bit 2
Bit 1
Bit 0
RESET
00H
00H
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The RESET Pin can be configured as I/O port P3.6, when the user uses on-chip hardware RESET mechanism.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic
Description
Port 3
Port 3
Mnemonic: P3
7
6
P3.7
P3.6
Direct
Bit 7
B0h
P3.7
5
P3.5
4
P3.4
Bit 6 Bit 5
Ports
P3.6 P3.5
3
P3.3
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
P3.4
P3.3
P3.2
P3.1
P3.0
FFh
2
P3.2
1
P3.1
Address: B0h
0
Reset
P3.0
FFh
P3.7~ 0: Port3 [7] ~ Port3 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 22 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
6. Timer 0 and Timer 1
The SM39R08A5 has two 16-bit timer/counter registers: Timer 0 and Timer 1. All can be configured for counter or timer
operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machine cycles, which means that it
counts up after every 12 periods of the clock signal.
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic
Description
Direct
TL0
TH0
TL1
TH1
TMOD
TCON
AUX
Timer 0 , low byte
Timer 0 , high byte
Timer 1 , low byte
Timer 1 , high byte
Timer Mode Control
Timer/Counter Control
Auxiliary register
8Ah
8Ch
8Bh
8Dh
89h
88h
91h
Bit 7 Bit 6 Bit 5
Timer 0 and 1
GATE
TF1
BRGS
C/T
TR1
-
Bit 4
M1
TF0
-
Bit 3
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
M0 GATE
TR0
IE1
PTS[1:0]
Bit 2
Bit 1
C/T
M1
IT1
IE0
PINTS[1:0]
Bit 0
RESET
M0
IT0
DPS
00h
00h
00h
00h
00h
00h
00H
6.1. Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE
C/T
M1
Timer 1
4
M0
3
GATE
2
1
C/T
M1
Timer 0
Address: 89h
0
Reset
M0
00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a
counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is performed,
when cleared to 0, the corresponding register will function as a timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1
M0
Mode
Function
0
0
Mode0
13-bit counter/timer, with 5 lower bits in TL0 or TL1
register and 8 bits in TH0 or TH1 register (for Timer 0
and Timer 1, respectively). The 3 high order bits of
TL0 and TL1 are hold at zero.
0
1
Mode1
16-bit counter/timer.
1
0
Mode2
8 -bit auto-reload counter/timer. The reload value is
kept in TH0 or TH1, while TL0 or TL1 is incremented
every machine cycle. When TLx overflows, a value
from THx is copied to TLx.
1
1
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.
If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts
as two independent 8 bit timers / counters.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 23 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
6.2. Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
TF1
TR1
TF0
4
TR0
3
IE1
2
IT1
1
IE0
Address: 88h
0
Reset
IT0
00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
6.3. T0、T1 signal swapping
The T0、T1 signal can be configured to other I/O.
Mnemonic: AUX
7
6
BRGS
PTS [1:0]
0x00
0x01
0x10
0x11
5
-
4
3
PTS [1:0]
T0
P3.3(PA03)
P3.0(PA00)
-
2
1
PINTS[1:0]
Address: 91h
0
Reset
DPS
00H
T1
P3.2(PA02)
P3.1(PA01)
-
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 24 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
7. Serial interface
The serial buffer consists of two separate registers, a transmit buffer and a receive buffer.
Writing data to the Special Function Register SBUF sets this data in serial output buffer and starts the transmission.
Reading from the SBUF reads data from the serial receive buffer. The serial port can simultaneously transmit and receive
data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the first byte
before transmission of the second byte is completed.
Mnemonic
Description
Direct
PCON
AUX
Power control
Auxiliary register
Serial Port
control register
Serial Port
data buffer
Serial Port
reload register
low byte
Serial Port
reload register
high byte
87H
91h
SCON
SBUF
SRELL
SRELH
98H
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Serial interface 0
SMOD
BRGS
PTS[1:0]
SM0
SM1
SM2
REN
99H
Bit 1
Bit 0
RESET
STOP
PINTS[1:0]
IDLE
DPS
40H
00H
RI
00H
RB8
TI
SBUF[7:0]
SREL
.7
AAH
SREL
.6
SREL
.5
BAH
Mnemonic: AUX
7
6
BRGS
-
TB8
Bit 2
SREL
.4
SREL
.3
-
5
-
4
3
PTS[1:0]
2
1
PINTS[1:0]
00H
SREL
.2
SREL
.1
SREL
.0
00H
SREL
.9
SREL
.8
00H
Address: 91h
0
Reset
DPS
00H
BRGS: BRGS = 0 –Baud rate generator use Timer 1 TH1 SFR.
BRGS = 1 –Baud rate generator use SREL SFR.
Mnemonic: SCON
7
6
5
SM0
SM1
SM2
4
REN
3
TB8
2
RB8
1
TI
Address: 98h
0
Reset
RI
00h
SM0,SM1: Serial Port mode selection.
SM0 SM1
Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART, Mode 0 ~ 3, are explained later.
SM2: Enables multiprocessor communication feature
REN: If set, enables serial reception. Cleared by software to disable reception.
TB8: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
RB8: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM2 is 0, RB8 is
the stop bit. In mode 0, this bit is not used. Must be cleared by software.
TI: Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI: Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 25 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
The Serial Interface can operate in the following 4 modes:
SM0
0
0
1
1
SM1
0
1
0
1
Mode
0
1
2
3
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
7.1. Mode 0
Pin RXD serves as input and output. TXD outputs the shift clock. 8 bits are transmitted with LSB first. The baud rate is
fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in SCON as follows: RI = 0 and
REN = 1. In other modes, a start bit when REN = 1 starts receiving serial data.
Fig. 7-1: Transmit mode 0
Fig. 7-2: Receive mode 0
7.2. Mode 1
Pin RXD serves as input, and TXD serves as serial output. No external shift clock is used, 10 bits are transmitted: a start
bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8
data bits are available by reading SBUF, and stop bit sets the flag RB8 in the Special Function Register SCON. In mode 1
either internal baud rate generator or timer 1 can be use to specify baud rate.
Fig. 7-3: Transmit mode 1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 26 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Fig. 7-4: Receive mode 1
7.3. Mode 2
This mode is similar to Mode 1, with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of
oscillator frequency and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit,
and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB8 in SCON is
output as the 9th bit, and at receive, the 9th bit affects RB8 in Special Function Register SCON.
7.4. Mode 3
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate generator or timer 1 can be
use to specify baud rate.
Fig. 7-5: Transmit modes 2 and 3
Fig. 7-6: Receive modes 2 and 3
7.5. Multiprocessor communication
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface can be used for multiprocessor communication. In this
case, the slave processors have bit SM2 in SCON. When the master processor outputs slave’s address, it sets the 9th bit
to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with their
network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the message, while other
slaves will leave SM2 bit unaffected and ignore this message. After addressing the slave, the host will output the rest of
th
the message with the 9 bit set to 0, so no serial port receive interrupt will be generated in unselected slaves.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 27 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
7.6. Baud rate generator
Serial interface modes 1 and 3
(a) When BRGS = 0 (in SFR AUX):
2SMOD FOSC
Baud Rate
32 12 256 TH1
(b) When BRGS = 1 (in SFR AUX):
Baud Rate
2SMOD FOSC
64 210 SREL
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 28 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
8. Watchdog timer
The Watch Dog Timer (WDT) is an 8-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software
dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is
different from Timer0, Timer1 of general 8052. To prevent a WDT reset can be done by software periodically clearing the
WDT counter. User should check WDTF bit of WDTC register whenever un-predicted reset happened. After an external
reset the watchdog timer is disabled and all registers are set to zeros.
The watchdog timer has a free running on-chip RC oscillator (23 KHz). The WDT will keep on running even after the
system clock has been turned off (for example, in sleep mode). During normal operation or sleep mode, a WDT time-out
(if enabled) will cause the MCU to reset. The WDT can be enabled or disabled any time during the normal mode. Please
refer the WDTE bit of WDTC register. The default WDT time-out period is approximately 178.0ms (WDTM [3:0] = 0100b).
The WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit3 ~ bit0
(WDTM [3:0]) of Watch Dog Timer Control Register (WDTC) should be set accordingly.
23KHz
2 WDTM
256
Watchdog reset time =
WDTCLK
WDTCLK
WDTM [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 8.1 WDT time-out period
Divider
(23 KHz RC oscillator in)
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
Time period @ 23KHz
11.1ms
22.2ms
44.5ms
89.0ms
178.0ms (default)
356.1ms
712.3ms
1.4246s
2.8493s
5.6987s
11.397s
22.795s
45.590s
91.180s
182.36s
364.72s
Note: RC oscillator (23 KHz), about ± 20% of variation
When MCU is reset, the MCU will be read WDTEN control bit status. When WDTEN bit is set to 1, the watchdog function
will be disabled no matter what the WDTE bit status is. When WDTEN bit is clear to 0, the watchdog function will be
enabled if WDTE bit is set to 1 by program. User can to set WDTEN on the writer or ISP.
The program can enable the WDT function by programming 1 to the WDTE bit premise that WDTEN control bit is clear to
0. After WDTE set to 1, the 8 bit-counter starts to count with the selected time base source clock which set by WDTM [3:0].
It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when MCU been reset,
either hardware reset or WDT reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 29 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero by writing 0x55 to
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start
to count from the beginning. The watchdog timer must be refreshed regularly to prevent reset request signal from
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
Power on reset
External reset
Software write “0”
23KHz RC
oscillator
1
TAKEY
(55, AA, 5A)
Clear
WDTF = 0
WDTF
Set WDTF = 1
WDTCLK
WDT
Counter
2WDTM
Enable/Disable
WDT
WDTM[3:0]
Refresh
WDT Counter
WDTC
Enable WDTC
write attribute
WDT time-out reset
WDTK
(0x55)
WDTEN
Fig. 8-1: Watchdog timer block diagram
Mnemonic
TAKEY
WDTC
WDTK
RSTS
Description
Time Access
Key register
Watchdog
timer control
register
Watchdog
timer refresh
key
Reset status
register
Direct
Bit 7
Bit 6
Bit 5
Bit 4
Watchdog Timer
F7h
Bit 2
Bit 1
Bit 0
TAKEY [7:0]
B6h
CWDTR
WDTE
B7h
A1h
Bit 3
-
00H
WDTM [3:0]
04H
WDTK[7:0]
-
Mnemonic: TAKEY
7
6
5
-
4
3
TAKEY [7:0]
-
RESET
00H
PDRF
WDTF
SWRF
LVRF
2
1
Address: F7h
0
Reset
00H
PORF
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 30 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: RSTS
7
6
-
5
-
4
PDRF
3
WDTF
2
SWRF
1
LVRF
Address: A1h
0
Reset
PORF
00H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
Mnemonic: WDTC
7
6
CWDTR
5
WDTE
4
-
3
2
1
WDTM [3:0]
Address: B6h
0
Reset
04H
CWDTR: 0: watchdog reset
1: watchdog interrupt
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN, the bit7 of information block OP3, is "0". If
the WDTEN bit is "0", then WDT can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN, the bit7 of information block OP3, is "1". That is, if
the WDTEN bit is "1", WDT is always disabled no matter what the WDTE bit status is.
The WDTE bit can be read and written.
WDTM [3:0]: WDT clock source divider bit. Please see table 7.8.1 to reference the WDT time-out
period.
Mnemonic: WDTK
7
6
5
4
3
WDTK[7:0]
2
1
Address: B7h
0
Reset
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 31 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
For example 2, if enable WDT and select time-out Interrupt period is 178.0ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #64h
; Set WDTM [3:0] = 0100b. Set WDTE =1 to enable WDT function
; and Set CWDTR =1 to enable period interrupt function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 32 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
9. Interrupt
The SM39R08A5 provides 9 interrupt sources with four priority levels. Each source has its own request flag(s) located in
a special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled
by the enable bits in SFR’s IEN0, and IEN1.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 9.1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been next
when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are
polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is
set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector
address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is
7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 9-1: Interrupt vectors
Interrupt Vector
Interrupt Request Flags
Address
IE0 – External interrupt 0
0003h
TF0 – Timer 0 interrupt
000Bh
IE1 – External interrupt 1
0013h
TF1 – Timer 1 interrupt
001Bh
RI/TI – Serial channel interrupt
0023h
Interrupt Number
*(use Keil C Tool)
0
1
2
3
4
PWMIF – PWM interrupt
ADCIF – A/D converter interrupt
0043h
0053h
8
10
LVIIF – Low Voltage Interrupt
IICIF – IIC interrupt
0063h
006Bh
12
13
WDTIF–WDT interrupt
008Bh
17
Comparator interrupt
0093h
18
*See Keil C about C51 User’s Guide about Interrupt Function description
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ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 33 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic
Description
Direct
Bit 7
Bit 6
AUX
Auxiliary register
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt Enable
2 register
Interrupt request
register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
91h
BRGS
-
A8H
EA
-
-
ES0
ET1
EX1
B8H
-
-
IEIIC
IELVI
-
IEADC
9AH
-
-
-
-
-
ECmpI
C0H
-
-
IICIF
LVIIF
-
97H
-
-
-
-
A9H
-
-
IP0.5
B9H
-
-
IP1.5
IEN0
IEN1
IEN2
IRCON
IRCON2
IP0
IP1
Mnemonic: AUX
7
6
BRGS
-
5
-
4
Bit 5
Interrupt
-
3
PTS[1:0]
Bit 4
Bit 3
Bit 2
Bit 0
RESET
DPS
00H
EX0
00H
IEPWM
00H
IEWDT
-
00H
ADCIF
-
PWMIF
00H
-
CmpIF
WDTIF
-
00H
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
00H
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
00H
PTS[1:0]
Bit 1
PINTS[1:0]
2
1
PINTS[1:0]
ET0
-
Address: 91h
0
Reset
DPS
00H
The INT0、INT1 signal can be configured to other I/O.
PINTS [1:0]
0x00
0x01
INT0
-
INT1
P3.7
P3.5
Interrupt Enable 0 register (IEN0)
Mnemonic: IEN0
7
6
EA
-
5
-
4
ES0
3
ET1
2
EX1
1
ET0
Address: A8h
0
Reset
EX0
00h
EA: EA=0 – Disable all interrupt.
EA=1 – Enable all interrupt.
ES0: ES0=0 – Disable Serial channel 0 interrupt.
ES0=1 – Enable Serial channel 0 interrupt.
ET1: ET1=0 – Disable Timer 1 overflow interrupt.
ET1=1 – Enable Timer 1 overflow interrupt.
EX1: EX1=0 – Disable external interrupt 1.
EX1=1 – Enable external interrupt 1.
ET0: ET0=0 – Disable Timer 0 overflow interrupt.
ET0=1 – Enable Timer 0 overflow interrupt.
EX0: EX0=0 – Disable external interrupt 0.
EX0=1 – Enable external interrupt 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 34 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Interrupt Enable 1 register (IEN1)
Mnemonic: IEN1
7
6
-
5
IEIIC
4
IELVI
3
-
2
IEADC
1
-
3
-
2
ECmpI
1
IEWDT
3
-
2
ADCIF
1
-
Address: B8h
0
Reset
00h
IEPWM
IELVI: LVI interrupt enable.
IELVI = 0 – Disable LVI interrupt.
IELVI = 1 – Enable LVI interrupt.
IEIIC: IIC interrupt enable.
IEIICS = 0 – Disable IIC interrupt.
IEIICS = 1 – Enable IIC interrupt.
IEADC: A/D converter interrupt enable
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
IEPWM: PWM interrupt enable.
IEPWM = 0 – Disable PWM interrupt.
IEPWM = 1 – Enable PWM interrupt.
Interrupt Enable 2 register (IEN2)
Mnemonic: IEN2
7
6
-
5
-
4
-
Address: 9Ah
0
Reset
00H
ECmpI: Enable Comparator 0 interrupt
IEWDT: WDT interrupt enable.
IEWDT = 0 – Disable WDT interrupt.
IEWDT = 1 – Enable WDT interrupt.
Interrupt request register (IRCON)
Mnemonic: IRCON
7
6
-
5
IICIF
4
LVIIF
Address: C0h
0
Reset
PWMIF
00H
LVIIF: LVI interrupt flag. Clear by hardware automatically
IICIF: IIC interrupt flag. Clear by hardware automatically
ADCIF: A/D converter end interrupt flag.
PWMIF: PWM interrupt flag. Clear by hardware automatically
Interrupt request register 2 (IRCON2)
Mnemonic: IRCON2
7
6
-
5
-
4
-
3
-
2
CmpIF
1
WDTIF
0
-
Address: 97h
Reset
00H
CmpIF: Comparator interrupt flag
HW will clear this flag automatically when enter interrupt vector.
SW can clear this flag also.(in case analog comparator INT disable)
WDTIF: WDT interrupt flag.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 35 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
All interrupt sources are combined in groups:
Table 9-2: Priority level groups
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Groups
WDT interrupt
Comparator interrupt
-
PWM interrupt
ADC interrupt
-
Serial channel interrupt
-
-
LVI interrupt
IIC interrupt
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit
in the special function register IP0 and one in IP1. If requests of the same priority level will be received simultaneously, an
internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0
Reset
IP0.0
00h
Mnemonic: IP1
7
6
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0
Reset
IP1.0
00h
Table 9-3: Priority levels
IP1.x
IP0.x
Priority Level
0
0
Level0 (lowest)
0
1
Level1
1
0
Level2
1
1
Level3 (highest)
Table 9-4: Groups of priority
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
External interrupt 0
Timer 0 interrupt
Group
WDT interrupt
PWM interrupt
-
External interrupt 1
Timer 1 interrupt
Serial channel interrupt
-
Comparator interrupt
-
ADC interrupt
LVI interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 36 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Table 9-5: Polling sequence
Sequence
Polling sequence
Interrupt source
External interrupt 0
PWM interrupt
Timer 0 interrupt
WDT interrupt
External interrupt 1
Comparator interrupt
ADC interrupt
Timer 1 interrupt
Serial channel 0 interrupt
LVI interrupt
IIC interrupt
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 37 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
10. Power Management Unit
Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving
function.
Mnemonic: PCON
7
6
SMOD
-
5
-
4
-
3
-
2
-
1
STOP
Address: 87h
0
Reset
IDLE
40h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode.
Stop bit is always read as 0
IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode.
Idle bit is always read as 0
10.1.
Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode leaves internal clocks and peripherals
running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or
a reset.
10.2.
Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turn off. The CPU will
exit this state only if interrupts asserted from external INT0/1, LVI and WDT interrupt, or hardware reset by WDT and
LVR.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 38 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
11. PWM - Pulse Width Modulation
SM39R08A5 provides four-channel PWM outputs.
The interrupt vector is 43h.
Mnemonic
PWMC
PWMD0H
PWMD0L
PWMD1H
PWMD1L
PWMD2H
PWMD2L
PWMD3H
PWMD3L
PWMMDH
PWMMDL
Description
PWM Control
register
PWM 0 Data
register high
byte
PWM 0 Data
register low
byte
PWM 1 Data
register high
byte
PWM 1 Data
register low
byte
PWM 2 Data
register high
byte
PWM 2 Data
register low
byte
PWM 3 Data
register high
byte
PWM 3 Data
register low
byte
PWM Max
Data register
high byte
PWM Max
Data register
low byte
Direct
Bit 7
B5h
Bit 6
Bit 5 Bit 4
PWM
PWMCS[2:0]
BCh
PWMP0
-
-
-
BDh
Bit 2
Bit 1
Bit 0
PWM3EN PWM2EN PWM1EN PWM0EN
-
-
PWMD0[9:8]
PWMD0[7:0]
BEh
PWMP1
-
-
-
BFh
-
PWMP2
-
-
-
B2h
-
-
PWMD1[9:8]
PWMP3
-
-
-
B4h
-
-
PWMD2[9:8]
-
-
CFh
-
-
-
-
PWMD3[9:8]
4
-
00H
00H
00H
00H
-
PWMMD[9:8]
PWMMD[7:0]
5
00H
00H
PWMD3[7:0]
CEh
00H
00H
PWMD2[7:0]
B3h
RESET
00H
PWMD1[7:0]
B1h
Mnemonic: PWMC
7
6
PWMCS[2:0]
Bit 3
00H
FFH
Address: B5h
3
2
1
0
Reset
PWM3EN PWM2EN PWM1EN PWM0EN
00H
PWMCS[2:0]: PWM clock select.
PWMCS [2:0]
Mode
000
Fosc
001
Fosc/2
010
Fosc/4
011
Fosc/6
100
Fosc/8
101
Fosc/12
110
Timer 0 overflow
111
P3.4
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 39 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
PWM3EN: PWM channel 3 enable control bit.
PWM3EN = 1 – PWM channel 3 enable.
PWM3EN = 0 – PWM channel 3 disable.
PWM2EN: PWM channel 2 enable control bit.
PWM2EN = 1 – PWM channel 2 enable.
PWM2EN = 0 – PWM channel 2 disable.
PWM1EN: PWM channel 1 enable control bit.
PWM1EN = 1 – PWM channel 1 enable.
PWM1EN = 0 – PWM channel 1 disable.
PWM0EN: PWM 0 enable control bit.
PWM0EN = 1 – PWM channel 0 enable.
PWM0EN = 0 – PWM channel 0 disable.
Mnemonic: PWMD0H
7
6
5
PWMP0
Mnemonic: PWMD0L
7
6
5
4
-
3
-
4
3
PWMD0[7:0]
2
-
2
Address: BCh
1
0
Reset
PWMD0[9:8]
00H
1
Address: BDh
0
Reset
00H
PWMP0: PWM channel 0 idle polarity select.
“0” – PWM channel 0 will idle low.
“1” – PWM channel 0 will idle high.
PWMD0[9:0]: PWM channel 0 data register.
Mnemonic: PWMD1H
7
6
5
PWMP1
Mnemonic: PWMD1L
7
6
5
4
-
3
-
4
3
PWMD1[7:0]
2
-
2
Address: BEh
1
0
Reset
PWMD1[9:8]
00H
1
Address: BFh
0
Reset
00H
PWMP1: PWM channel 1 idle polarity select.
“0” – PWM channel 1 will idle low.
“1” – PWM channel 1 will idle high.
PWMD1[9:0]: PWM channel 1 data register.
Mnemonic: PWMD2H
7
6
5
PWMP2
Mnemonic: PWMD2L
7
6
5
4
-
3
-
4
3
PWMD2[7:0]
2
-
2
Address: B1h
1
0
Reset
PWMD2[9:8]
00H
1
Address: B2h
0
Reset
00H
PWMP2: PWM channel 2 idle polarity select.
“0” – PWM channel 2 will idle low.
“1” – PWM channel 2 will idle high.
PWMD2[9:0]: PWM channel 2 data register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 40 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: PWMD3H
7
6
5
PWMP3
Mnemonic: PWMD3L
7
6
5
4
-
3
-
4
3
PWMD3[7:0]
2
-
2
Address: B3h
1
0
Reset
PWMD3[9:8]
00H
1
Address: B4h
0
Reset
00H
PWMP3: PWM channel 3 idle polarity select.
“0” – PWM channel 3 will idle low.
“1” – PWM channel 3 will idle high.
PWMD3[9:0]: PWM channel 3 data register.
Mnemonic: PWMMDH
7
6
5
Mnemonic: PWMMDL
7
6
5
4
-
3
-
4
3
PWMMD[7:0]
2
-
2
Address: CEh
1
0
Reset
PWMMD[9:8]
00H
1
Address: CFh
0
Reset
FFH
PWMMD[9:0]: PWM Max Data register.
PWM count from 0000h to PWMMD[9:0]. When PWM count data equal PWMMD[9:0]
is overflow.
PWMPx = 0 & PWMDx = 00h
PWMx
Low
PWMPx = 0 & PWMDx ≠ 00h
PWMx
PWMPx = 1 & PWMDx = 00h
PWMx
High
PWMPx = 1 & PWMDx ≠ 00h
PWMx
PWMMD 1
PWM clock
PWMDx
Leader pulse
PWM clock
PWM period
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 41 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
12. IIC function
The IIC module uses the SCL (clock) and the SDA (data) line to communicate with external IIC interface. Its speed can be
selected to 400Kbps (maximum) by software setting the IICBR [2:0] control bit. The IIC module provided 2 interrupts
(RXIF, TXIF). It will generate START, repeated START and STOP signals automatically in master mode and can detects
START, repeated START and STOP signals in slave mode. The maximum communication length and the number of
devices that can be connected are limited by a maximum bus capacitance of 400pF.
The interrupt vector is 6Bh.
Mnemonic
IICCTL
IICS
IICA1
IICA2
IICRWD
IICEBT
Description
IIC control
register
IIC status
register
IIC Address 1
register
IIC Address 2
register
IIC Read/Write
register
IIC Enaable Bus
Transaction
Direct
Bit 7
Bit 6 Bit 5 Bit 4
IIC function
F9h
IICEN
MSS
MAS AB_EN
F8h
-
MPIF
LAIF
Bit 3
RXIF
IICA1[7:1]
FBh
IICA2[7:1]
FDh
Mnemonic: IICCTL
7
6
5
IICEN
MSS
MAS
Bit 1
BF_EN
FAh
FCh
Bit 2
TXIF
RXAK
Bit 0
IICBR[2:0]
04H
TXAK
00H
RW,BB
MATCH1or
RW1
MATCH2 or
RW2
IICRWD[7:0]
FU_EN
4
AB_EN
2
A0H
60H
00H
-
3
BF_EN
RESET
1
IICBR[2:0]
00H
Address: F9h
0
Reset
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
AB_EN: Arbitration lost enable bit. (Master mode only)
If set AB_EN bit, the hardware will check arbitration lost. Once arbitration lost occurred,
hardware will return to IDLE state. If this bit is cleared, hardware will not care arbitration lost
condition. Set this bit when multi-master and slave connection. Clear this bit when single master
to single slave.
BF_EN: Bus busy enable bit. (Master mode only)
If set BF_EN bit, hardware will not generate a start condition to bus until BF=0. Clear this bit will
always generate a start condition to bus when MStart is set. Set this bit when multi-master and
slave connection. Clear this bit when single master to single slave.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 42 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
011
Fosc/256
100
Fosc/512
101
Fosc/1024
110
Fosc/2048
111
Fosc/4096
Mnemonic: IICS
7
6
MPIF
5
LAIF
4
RXIF
3
TXIF
2
RXAK
1
TxAK
Address: F8H
0
Reset
RW
00H
MPIF: The Stop condition Interrupt Flag
The stop condition occurred and this bit will be set. Software need to clear this bit
LAIF: Arbitration lost bit. (Master mode only)
The Arbitration Interrupt Flag, the bus arbitration lost occurred and this bit will be set.
Software need to clear this bit
RxIF: The data Receive Interrupt Flag (RXIF) is set after the IICRWD (IIC Read Write Data
Buffer) is loaded with a newly receive data.
TxIF: The data Transmit Interrupt Flag (TXIF) is set when the data of the IICRWD (IIC Read
Write Data Buffer) is downloaded to the shift register.
RxAK: The Acknowledge Status indicate bit. When clear, it means an acknowledge signal has
been received after the complete 8 bits data transmit on the bus.
TxAK: The Acknowledge status transmit bit. When received complete 8 bits data, this bit will
set (NoAck) or clear (Ack) and transmit to master to indicate the receive status.
RW: Master Mode:
Bus busy bit
If detect scl=0 or sda=0 or bus start, this bit will be set. If detect stop,this bit will be
cleared. This bit can be cleared by software to return ready state.
Slave Mode:
The slave mode read (received) or wrote (transmit) on the IIC bus. When this bit is clear,
the slave module received data on the IIC bus (SDA).(Slave mode only)
th
Fig. 11-1: Acknowledgement bit in the 9 bit of a byte transmission
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 43 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: IICA1
7
6
5
4
IICA1[7:1]
R/W
3
2
1
Address: FAH
0
Reset
Match1 or RW1
A0H
R or R/W
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
Fig. 11-2: RW bit in the 8th bit after IIC address
Mnemonic: IICA2
7
6
5
Address: FBh
4
IICA2[7:1]
R/W
3
2
1
0
Match2 or RW2
R or R/W
Reset
60h
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus gets or send first data, this bit will clear automatically.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicates the slave with which it wants to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 44 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: IICRWD
7
6
5
4
3
IICRWD[7:0]
2
1
Address: FCh
0
Reset
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
7
6
FU_EN
5
-
4
-
3
-
2
-
1
-
Address: FDH
0
Reset
00H
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out
address which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generate a stop condition on the SDA/SCL.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Notice:
1. FU_EN[7:6] should be set as 01 before read/write data transfer for bus
release; otherwise, SCL will be locked(pull low).
2. FU_EN[7:6] should be set as 01 after read/write data transfer for receiving
a stop condition from bus master.
3. In transmit data mode (slave mode), the output data should be filled into
IICRWD before setting FU_EN[7:6] as 01.
4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6]
repeatedly is necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 45 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
13. LVI – Low Voltage Interrupt
The interrupt vector 63h.
Mnemonic
RSTS
LVC
Description
Reset status
register
Low voltage
control register
Direct
Bit 7
A1h
-
-
-
E6h
LVI_EN
-
LVRE
Mnemonic: RSTS
7
6
-
5
-
Bit 6
Bit 5
Bit 4
Watchdog Timer
4
PDRF
3
WDTF
Bit 3
Bit 2
Bit 1
Bit 0
RESET
PDRF
WDTF
SWRF
LVRF
PORF
00H
LVIF
-
-
2
SWRF
1
LVRF
LVIS
20H
Address: A1h
0
Reset
PORF
00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag
clear by software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by
software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear
by software.
Mnemonic: LVC
7
6
5
LVI_EN
LVRE
4
LVIF
3
-
2
-
1
Address: E6h
0
Reset
LVIS[1:0]
20H
LVI_EN: Low voltage interrupt function enable bit.
LVI_EN = 0 - disable low voltage detect function.
LVI_EN = 1 - enable low voltage detect function.
LVRE: External low voltage reset function enable bit.
LVRE = 0 - disable external low voltage reset function.
LVRE = 1 - enable external low voltage reset function.
LVIF: Low Voltage interrupt Flag (Read only)
LVIS LVI level select:
00: 1.7V
01: 2.60V
10: 3.2V
11: 4.0V
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 46 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
14. 10-bit Analog-to-Digital Converter (ADC)
The SM39R08A5 provides eight channels 10-bit ADC. The Digital output DATA [9:0] were put into ADCD [9:0].
The ADC interrupt vector is 53H.
VDD
ADCC1[7:0
]
ADCCH[2:0]
Start
ADC0
AVDD
…
…
…
…
MUX
ADC6
High Speed
10 Bits
ADC Module
ADC7
ADC
Clock
Divider
Fos
c
The ADC SFR show as below:
Mnemonic Description
Direct
ADCC2
ADCDH
ADCDL
ADCCS
ADC Control
register 1
ADC Control
register 2
ADC data
high byte
ADC data low
byte
ADC clock
select
Bit 7
Bit 6
ADC_ISR
AVSS
ADCCS[4:0]
ADC clock=Fosc/2…Fosc/64=15KHZ~12.5MHZ
ADC conversion rate Max = 960KHZ
ADCC1
ADCD[9:0]
Bit 5
ADC
Bit 4
Bit 3
VSS
Bit 2
Bit 1
Bit 0
RESET
ABh ADC7ENADC6ENADC5ENADC4ENADC3ENADC2ENADC1ENADC0EN
00H
ACh
00H
Start
ADJUST
-
-
-
ADCCH[2:0]
ADh
ADCDH [7:0]
00H
AEh
ADCDL [7:0]
00H
AFh
-
-
-
ADCCS[4:0]
00H
Mnemonic: ADCC1
Address: ABh
7
6
5
4
3
2
1
0
Reset
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN 00H
ADC7EN: ADC channels 7 enable.
ADC7EN = 1 – Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
ADC6EN = 1 – Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
ADC5EN = 1 – Enable ADC channel 5
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 47 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel
Mnemonic: ADCC2
7
6
5
Start ADJUST
-
4
-
3
-
4
3
2
1
0
2
1
ADCCH[2:0]
Address: ACh
0
Reset
00H
Start: When this bit is set, the ADC will be start conversion continuous.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1: ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
Channel
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
ADJUST = 0:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] 00H
Mnemonic: ADCDL
7
6
5
-
4
-
3
-
2
-
Address: AEh
1
0
Reset
ADCD[1] ADCD[0] 00H
ADJUST = 1:
Mnemonic: ADCDH
7
6
5
-
4
-
3
-
2
-
Address: ADh
1
0
Reset
ADCD[9] ADCD[8] 00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] 00H
ADCD[9:0]: ADC data register.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 48 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: ADCCS
7
6
5
-
Address: AFh
4
3
2
1
0
Reset
ADCCS[4] ADCCS[3] ADCCS[2] ADCCS[1] ADCCS[0]
00H
ADCCS[4:0]: ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 960KHz.
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fosc /2
46
00001
Fosc/4
92
00010
Fosc /6
138
00011
Fosc /8
184
00100
Fosc /10
230
00101
Fosc /12
276
00110
Fosc /14
322
00111
Fosc /16
368
01000
Fosc /18
414
01001
Fosc /20
460
01010
Fosc /22
506
01011
Fosc /24
552
01100
Fosc /26
598
01101
Fosc /28
644
01110
Fosc /30
690
01111
Fosc /32
736
10000
Fosc /34
782
10001
Fosc /36
828
10010
Fosc /38
874
10011
Fosc /40
920
10100
Fosc /42
966
10101
Fosc /44
1012
10110
Fosc /46
1058
10111
Fosc /48
1104
11000
Fosc /50
1150
11001
Fosc /52
1196
11010
Fosc /54
1242
11011
Fosc /56
1288
11100
Fosc /58
1334
11101
Fosc /60
1380
11110
Fosc /62
1426
11111
Fosc /64
1472
Fosc
2 ( ADCCS 1)
ADC_Clock
ADC _ Conversion _ Rate
13
ADC _ Clock
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 49 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
15. EEPROM
The SM39R08A5 can generate flash control signal by internal hardware circuit. The SM39R08A5 provides internal flash
control signals which can do flash program/page erase functions.
ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC:
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Description
Time Access Key
register
Interface Control
register
ISP Flash
Address - High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
ISP Flash Control
register
Direct
Bit 7
Bit 6
Bit 5
ISP function
F7h
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
TAKEY [7:0]
8Fh
-
CDPR
-
-
00H
-
-
-
ISPE
00H
E1h
ISPFAH [7:0]
FFH
E2h
ISPFAL [7:0]
FFH
E3h
ISPFD [7:0]
FFH
E4h
-
Mnemonic: TAKEY
7
6
5
-
-
-
4
3
TAKEY [7:0]
-
2
ISPF.2
1
ISPF.1
ISPF.0
00H
Address: F7H
0
Reset
00H
ISP enable bit (ISPE) is read-only by default, software must write three specific values 55h, AAh and 5Ah
sequentially to the TAKEY register to enable the ISPE bit write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: IFCON
7
6
CDPR
5
-
4
-
3
-
2
-
1
-
Address: 8FH
0
Reset
ISPE
00H
The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R08A5 EEPROM function by
setting ISPE bit to 1, to disable overall EEPROM function by set ISPE to 0. The function of ISPE behaves like a
security key. User can disable overall ISP function to prevent software program be erased accidentally. ISP
registers ISPFAH, ISPFAL, ISPFD and ISPFC are read-only by default. Software must be set ISPE bit to 1 to
enable these 4 registers write attribute.
Mnemonic: ISPFAH
Address: E1H
7
6
5
4
3
2
1
0
Reset
ISPFAH7 ISPFAH6 ISPFAH5 ISPFAH4 ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0
FFH
ISPFAH [7:0]: Flash address-high for EEPROM function
Mnemonic: ISPFAL
7
6
ISPFAL7 ISPFAL6
5
ISPFAL5
4
ISPFAL4
3
ISPFAL3
2
ISPFAL2
1
ISPFAL1
Address: E2H
0
Reset
ISPFAL0
FFH
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 50 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
ISPFAL [7:0]: Flash address-Low for EEPROM function
Mnemonic: ISPFD
7
6
ISPFD7
ISPFD6
5
ISPFD5
4
ISPFD4
3
ISPFD3
2
ISPFD2
1
ISPFD1
Address: E3H
0
Reset
ISPFD0
FFH
ISPFD [7:0]: Flash data for byte programming function.
Mnemonic: ISPFC
7
6
-
5
-
4
-
3
-
2
ISPF[2]
1
ISPF[1]
Address: E4H
0
Reset
ISPF[0]
00H
ISPF [2:0]: ISP function select bit.
ISPF[2:0]
ISP function
000
Byte program
010
Page erase
One page of flash memory is 128 byte
The choice EEPROM function will start to execute once the software write data to ISPFC register.
To perform byte program/page erases function, user need to specify flash address at first. When performing
page erase function, SM39R08A5 will erase entire page which flash address indicated by ISPFAH & ISPFAL
registers located within the page.
e.g. flash address: $XYMN
page erase function will erase from $XY00 to $XY7F or $XY80 to $XYFF
e.g. ISP service program to do the byte program - to program #22H to the address $1005H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
ORL IFCON, #01H
MOV ISPFAH, #10H
MOV ISPFAL, #05H
MOV ISPFD, #22H
MOV ISPFC, #00H
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah
ANL IFCON, #0FEH
; enable ISPE write attribute
; enable SM39R08A5 ISP function
; set flash address-high, 10H
; set flash address-low, 05H
; set flash data to be programmed, data = 22H
; start to program #22H to the flash address $1005H
; enable ISPE write attribute
; disable SM39R08A5 ISP function
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 51 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
16. Comparator
SM39R08A5 had integrated a Comparator in chip. This module supports Comparator modes individually according
to user’s configuration. When use it as comparator, the comparator output is logical one when positive input greater
than negative input, otherwise the output is a zero.
Mnemonic
OPPIN
CMP0CON
Description
Comparator
pin select
Comparator
0 control
Addr
Bit 7
F6h
-
Bit 6
Bit 5
Bit 4
Op/Comparator
C0POS C0POS
CMP0EN
VBG
PAD
FEh HYS0EN CMP0O
Mnemonic: OPPIN
7
6
5
4
CMP0EN C0POSVBG C0POSPAD
CMF0MS[1:0]
3
-
Bit 3
Bit 2
Bit 1
Bit 0
RESET
-
-
-
-
00h
CMF0
Cmp0
OutEN
-
-
00h
2
-
1
-
0
-
Address: F6h
Reset
00h
CMP0EN : Cmp0 enable.
1: Comparator_0 circuit enable and switch to corresponding signal in
multi-function pin P3.0/P3.1/P3.7 by HW automatically.
C0POSVBG: Select Comparator_0 positive input source
1: set positive input source as internal reference voltage (1.2V±10%)
C0POSPAD: Select Comparator_0 positive input source
1: set positive input source as external pin
Comparator setting table:
CMP0EN
C0POSVBG
0
1
1
1
1
1
1
X
0
0
0
1
1
1
C0POSPAD Cmp0OutEN
X
0
1
1
0
0
1
Mnemonic: CMP0CON
7
6
5
HYS0EN CMP0O
X
X
0
1
0
1
X
4
CMF0MS[1:0]
3
Cmp0PIn
IO
Error
CMP
CMP
IO
IO
Error
2
Cmp0
CMF0
OutEN
Comparator
Cmp0NIn
IO
Error
CMP
CMP
CMP
CMP
Error
1
0
-
-
Cmp0Out
IO
Error
IO
CMP
IO
CMP
Error
Address:FEh
Reset
00h
HYS0EN: Hysteresis function enable
0: disable Hysteresis at comparator_0 input
1: enable
CMP0O: Comparator_0 output (read only)
0: The positive input source was lower than negative input source
1: The positive input source was higher than negative input source
CMF0MS[1:0] : CMF0(Comparator_0 Flag) setting mode select
00: CMF0 will be set when comprator_0 output toggle
01: CMF0 will be set when comprator_0 output rising
10: CMF0 will be set when comprator_0 output falling
11: reserved
CMF0: Comparator_0 Flag
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 52 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
This bit is setting by hardware according to meet CMF0MS [1:0] select condition.
This bit must clear by software.
Cmp0OutEN: Comparator_0 Output Enable
0: Comparator_0 will not output to external Pin
1: Comparator_0 will output to external Pin
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 53 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
DC Characteristics
TA = -40℃ to 85℃, VCC = 5.0V
Symbol
Parameter
Valid
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
P3.0/P3.1/P3.4/P3.7
0.45
V
IOL=20mA
Vcc=5V
P3.2/P3.3/P3.5/P3.6
0.45
V
IOL=38mA
Vcc=5V
90%Vcc
V
IOH= -8mA
P3.2/P3.3/P3.5/P3.6 90%Vcc
V
IOH= -15mA
Port 3
V
IOH= -250uA
VIL1
Input Low-voltage
Port 3
VIL2
Input Low-voltage
RES
VIH1
Input High-voltage
Port 3
VIH2
Input High-voltage
RES
VOL
Output Low-voltage
VOH1
Output High-voltage
(1)
using Strong Pull-up
P3.0/P3.1/P3.4/P3.7
Min
Typ
Conditions
Vcc=5V
IIL
Output High-voltage
(2)
using Weak Pull-up
Logic 0 Input Current
Port 3
-75
uA
Vin= 0.45V
ITL
Logical Transition Current Port 3
-650
uA
Vin= 2.0V
ILI
Input Leakage Current
±10
uA
0.45V<Vin<Vcc
300
kΩ
10
pF
2.6
3.5
mA
2.2
3
mA
2
6
uA
VOH2
Port 3
RRST Reset Pull-down Resistor RES
CIO
ICC
Notes：
2.4
50
Pin Capacitance
Power Supply Current
VDD
Freq= 1MHz, Ta= 25℃
Active mode IRC
22.1184MHz
VCC =5V 25 ℃
Idle mode, IRC
22.1184 MHz
VCC =5V 25 ℃
Power down mode VCC
=5V 25 ℃
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 54 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
TA = -40℃ to 85℃, VCC = 3.0V
Symbol
Parameter
Valid
Max
Units
-0.5
0.8
V
0
0.8
V
2.0
VCC + 0.5
V
70%Vcc
VCC + 0.5
V
P3.0/P3.1/P3.4/P3.7
0.45
V
IOL=14mA
Vcc=3V
P3.2/P3.3/P3.5/P3.6
0.45
V
IOL=15mA
Vcc=3V
V
IOH= -5mA
V
IOH= -10mA
V
IOH= -77uA
VIL1 Input Low-voltage
Port 0,1,3
VIL2 Input Low-voltage
RES, XTAL1
VIH1 Input High-voltage
Port 0,1,3
VIH2 Input High-voltage
RES, XTAL1
VOL
VOH1
Output Low-voltage
IIL
ITL
Logical Transition Current
ILI
Input Leakage Current
RRST Reset Pull-down Resistor
CIO
ICC
Notes：
TYP
90%Vcc
Output High-voltage using P3.0/P3.1/P3.4/P3.7
(1)
Strong Pull-up
P3.2/P3.3/P3.5/P3.6 90%Vcc
Output High-voltage using
Port 0,1,3
(2)
Weak Pull-up
Logic 0 Input Current
Port 0,1,3
VOH2
Min
2.4
Vcc=3.0V
-75
uA Vin= 0.45V
Port 0,1,3
-650
uA Vin=1.5V
Port 0,1,3
±10
uA 0.45V<Vin<Vcc
300
kΩ
10
pF Freq= 1MHz, Ta= 25℃
Active mode ,IRC
mA 22.1184 MHz
VCC = 3.0 V 25 ℃
Idle mode, IRC
mA 22.1184 Mhz
VCC =3.0V 25 ℃
Power down mode
uA
VCC =3.0V 25 ℃
RES
50
Pin Capacitance
Power Supply Current
Conditions
VDD
2.2
3
2.1
3
1
5
1. Port in Push-Pull Output Mode
2. Port in Quasi-Bidirectional Mode
Absolute Maximum Ratings
SYMBOL
PARAMETER
Maximum sourced current Total I/O pins
(Push-pull)
Maximum sunk current
Total I/O pins
Max. Junction Temperature
Tj
MAX
100
UNIT
mA
100
150
mA
℃
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 55 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
ADC Characteristics
Operation
Symbol
Test Condition
MIN
VDD
VDD
2.7
TYP
Resolution
MAX
Unit
5.5
V
10
bit
Conversion time
13tADC
us
Sample rate
870k
Hz
Integral Non-Linearity Error
INL
-1
1
LSB
Differential Non-Linearity
DNL
-1
1
LSB
-5.25
MHz
Clock frequency
ADCCLK
11.36
Comparator Characteristics
Ta=25℃
Symbol
Test Condition
VDD
Condition
Description
MIN
TPY
MAX
Unit
Operating current
5
-
-
10
10
uA
-
Power Down Current
5
-
-
-
0.1
uA
-
Offset voltage
5
-
-10
-
+10
mV
VCM
Input voltage commom mode
range
-
-
Vss
-
Vdd-1.5
V
Tp
Propagation delay
5
△
Vin=10mV
-
3
6
us
IOP
LVI& LVR Characteristics
1.8V ~ 5.5V
Min
VIL=1.4V
LVR
Typical
VIL=1.5V
LVI
Min
Typical
LVIS[1:0] = 00
VIL=1.6V
VIL=1.7V
LVIS[1:0] = 01
VIL=2.5V
VIL=2.6V
LVIS[1:0] = 10
VIL=3.1V
VIL=3.2V
LVIS[1:0] = 11
VIL=3.9V
VIL=4.0V
Notes : The VLVI always above VLVR about 0.2V
Max
VIL=1.6V
Max
VIL=1.8V
VIL=2.7V
VIL=3.3V
VIL=4.1V
FOSVOS TEL: 021-58998693
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067
Ver B SM39R08A5 04/22/2013
- 56 -