a FEATURES Pin Selectable 1-, 2-, or 3-Phase Operation Static and Dynamic Current Sharing Characteristics Backward Compatible to IMVP-II Superior Load Transient Response with ADOPT® Analog Devices’ Optimal Positioning Technology Noise-Blanking for Speed and Stability Synchronous Rectifier Control Extends Battery Life Smooth Output Transition During VID Code Change Cycle-by-Cycle Current Limiting Hiccup or Latched Overload Protection Transient-Glitch-Free Power Good Soft Start Eliminates Power-On In-Rush Current Surge Two-Level Overvoltage and Reverse Voltage Protection APPLICATIONS IMVP-II and IMVP-III Core DC-to-DC Converters Fixed Voltage Mobile CPU Core DC-to-DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies 3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs ADP3204* FUNCTIONAL BLOCK DIAGRAM VCC HYSSET ADP3204 DSHIFT VR BSHIFT DPRSHIFT HYSTERESIS SETTING AND SHIFT-MUX BOM DPSLP DPRSLP OUT3 OUT2 OUT1 CS3 CLIM CS2 CURRENT SENSE MUX EN CS1 CS+ CS– CORE RAMP REG VID4 VID3 5-BIT VID DAC AND FIXED REF VID MUX AND REG VID2 VID1 VID0 DPRSLP VID GEN BOM DPSLP DACOUT DPSLP DPRSLP DACRAMP BOM GENERAL DESCRIPTION The ADP3204 is a 1-, 2-, or 3-phase hysteretic peak current dc-to-dc buck converter controller dedicated to power a mobile processor’s core. The optimized low voltage design is powered from the 3.3 V system supply. The nominal output voltage is set by a 5-bit VID code. To accommodate the transition time required by the newest processors, the ADP3204 features high speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3204 features active voltage positioning with ADOPT optimal compensation to ensure a superior load transient response. The output signals interface with a maximum of three ADP3415 MOSFET drivers that are optimized for high speed and high efficiency for driving both the top and bottom MOSFETs of the buck converter. The ADP3204 is capable of controlling the synchronous rectifiers to extend battery lifetime in light load conditions. PHASE SPLITTER VID TRANSIENT DETECTOR AND SHIFT SELECTOR VR COREGD MONITOR COREFB SS-HICCUP TIMER AND OCP DPRSLP DRVLSD PWRGD ENABLE UVLO-MAIN BIAS SD SS SR CONTROL PWRGD BLANKER OVP AND RVP CLAMP PM MODULE GND ADOPT is a trademark of Analog Devices, Inc. *Protected by U.S.Patent No. 5,969,657; other patents pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ⱕ T ⱕ 100°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V ADP3204–SPECIFICATIONS1 (0°C V (V ), V = V = V = 1.25 V, C = 100 pF, R = R = R A DAC DACOUT COREFB REG CS– VID DACRAMP OUT1 OUT2 = = OUT3 100 k, COUT1 = COUT2 = COUT3 =10 pF, CSS = 0.047 F, RPWRGD = 680 to 1.2 V, RCLAMP = 5.1 k to VCC, HYSSET, BSHIFT, DSHIFT, and DPRSHIFT are open, BOM = H, DPSLP = H, DPRLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a negative sign. Negative sign is disregarded for min and max values. Parameter Symbol SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current ICC ICCUVLO ICCSD UVLO Threshold VCCH VCCL UVLO Hysteresis Shutdown Threshold (CMOS Input) POWER GOOD Core Feedback Threshold Voltage Power Good Output Voltage (Open-Drain Output) Masking Time2 SOFT START/HICCUP TIMER Charge/Discharge Current Min SD = L, 3.0 V ≤ VCC ≤ 3.6 V SD = H VCC ramping up, VSS = 0 V VCC ramping down, VSS floating Typ Max Unit 7 11 425 mA A A 2.95 V V 70 2.60 VCCHYS 55 mV VSDTH VCC/2 V VCOREFBH VPWRGD 0.9 V < VDAC < 1.675 V VCOREFB ramping up VCOREFB ramping down VCOREFB ramping up VCOREFB ramping down VCOREFB = VDACOUT VCOREFB = 0.8 VDACOUT tPWRGDMSK3 ISS Soft Start Enable/Hiccup Termination Threshold VSSEN Soft Start Termination/Hiccup Enable Threshold VSSTERM VID DAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-Up) Output Voltage Accuracy Conditions VSS = 0 V VSS = 0.5 V VREG = 1.25 V, VRAMP = VCOREFB = 1.27 V VSS ramping down VRAMP = VCOREFB = 1.27 V VSS ramping up 1.12 VDAC 1.10 VDAC 0.88 VDAC 0.86 VDAC 0.95 VCC 0 100 1.14 VDAC 1.12 VDAC 0.90 VDAC 0.88 VDAC VCC 0.8 A A –55 1.2 1.70 VVID0..4 V V V V V V s 200 300 mV 2.00 2.25 V VCC/2 V 85 A IVID0..4 VID0 to VID4 = L VDAC ⌬VDAC/VDAC See VID Code, Table 1 0.600 1.750 V 1.750 V ≥ VDAC ≥ 0.850 V 0.825 V ≥ VDAC ≥ 0.600 V CDACRAMP = 100 pF CDACRAMP = 1 nF –1.0 –8.5 +1.0 +8.5 % mV s s k⍀ Settling Time tDACS4 DACRAMP Inner Resistance5 RDACRAMP –2– 3.5 25 10 REV. 0 ADP3204 Parameter Symbol Conditions CORE COMPARATOR Input Offset Voltage (Ramp-Reg) Input Bias Current Output Voltage (OUT1, OUT2, and OUT3) Propagation Delay Time VCOREOS IREG, IRAMP VOUT_H VOUT_L tRMPOUT_PD6 VREG = 1.25 V VREG = VRAMP = 1.25 V VCC = 3.0 V VCC = 3.6 V TA = 25°C TA = Full Range Rise and Fall Time (OUT1, OUT2, and OUT3) Noise Blanking Time CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Propagation Delay Time CURRENT SENSE MULTIPLEXER Trans-Resistance Hysteresis Reference Voltage CURRENT LIMIT SETTING Hysteresis Current REV. 0 Typ Max ± 1.5 ±1 Unit OUT L-H Transition OUT H-L Transition 35 45 7 7 70 130 mV A V V ns ns ns ns ns ns VCLIMOS ICS+, ICS– tCLPD6 VCS– = 1.25 V VCS+ = 1.25 V TA = 25° C TA = Full Range ±1 –3 55 65 mV A ns ns RCS1–CS+, RCS2–CS+, RCS3–CS+ MUX switch is ON MUX switch is OFF 150 50 ⍀ M⍀ tOUT_R7 tOUT_F7 tBLNK Common-Mode Voltage Range HYSTERESIS SETTING Hysteresis Current Min VCS1 = VCS2 = VCS3 IRAMP_H, –ICS+_H VREG = 1.25 V VRAMP = 1.23 V IHYSSET = 10 A IHYSSET = 100 A VRAMP = 1.27 V IHYSSET = 10 A IHYSSET = 100 A 2.5 0 0 VRAMP = 1.23 V VREG = VCS– = VCOREFB = 1.25 V VCS+ = 1.23 V IHYSSET = 10 A IHYSSET = 100 A VCS+ = 1.27 V IHYSSET = 10 A IHYSSET = 100 A VCS+ = 1.23 V, BOM = L –3– 2 V –8 –85 –10 –100 –12 –115 A A 8 85 10 100 VDAC 12 115 A A V –27 –270 –31.5 –36 –301.5 –333 A A –18 –180 –21.5 –25 –201.5 –223 A A VHYSSET ICS– 3.0 0.4 ADP3204 Parameter Symbol Conditions Min SHIFT SETTING Battery-Shift Current IRAMPB, ICS+B VVID = 1.25 V IBSHIFT = –100 µA, BOM = L DPSLP = H –92.5 Battery-Shift Reference Voltage VBSHIFT Deep Sleep-Shift Current IRAMPD, ICS+D Deep Sleep-Shift Reference Voltage Deeper Sleep-Shift Current VDSHIFT Deeper Sleep-Shift Reference Voltage SHIFT CONTROL INPUTS BOM Threshold (CMOS Input) DPSLP Threshold (CMOS Input) DPRSLP Mode Threshold8 (CMOS Input) LOW SIDE DRIVE CONTROL Output Voltage (CMOS Output) Output Current IREGDPR ICOREFBDPR8 Typ –100 Max Unit –107.5 mA VDAC VVID = 1.25 V IDSHIFT = –100 µA, BOM = H DPSLP = L –92.5 –100 V –107.5 VDAC IDPRSHIFT = –100 µA, DPRSLP = H VVID = 1.25 V, IDPRSHIFT = –100 µA, DPRSLP = H –90 110 –100 130 mA V –110 150 µA µA VDPRSHIFT VDAC V VBOM VCC/2 V VDSLP VCC/2 V VDPRSLP VCC/2 V VDRVLSD IDRVLSD OVER/REVERSE VOLTAGE PROTECTION CORE FEEDBACK Overvoltage Threshold VCOREFB, OVP9 Reverse-Voltage Threshold VCOREFB, RVP9 Output Current ICLAMP (Open-Drain Output) DPRSLP = H DPRSLP = L DPRSLP = H, VDRVLSD = 1.5 V DPRSLP = L, VDRVLSD = 1.5 V VCOREFB VCOREFB VCOREFB = 2.2 V, VCLAMP = 1.5 V VCOREFB = VDAC, VCLAMP = 1.5 V 0 0.7 VCC +0.4 –0.4 0.4 VCC 2.0 –0.3 10 2 6 V V mA mA V V µA mA NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (V COREFB, BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay time. 2) PWRGD is forced to fail (V COREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good-window (V COREFB, GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time. 3 Guaranteed by design 4 Measured from 50% of VID code transition amplitude to the point where V DACOUT settles within ± 1% of its steady state value. 5 Measured between DACRAMP and DACOUT pins. 6 40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. 7 Measured between the 30% and 70% points of the output voltage swing. 8 DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design. 9 COREFB pin has a resistor divider to GND whose resistance is 41.3 k⍀ (typ), guaranteed by design. –4– REV. 0 ADP3204 Junction to Air Thermal Resistance (θJA) . . . . . . . . . . . 98°C/W Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C ABSOLUTE MAXIMUM RATINGS* Input Supply Voltage (VCC) . . . . . . . . . . . . . . . –0.3 V to +7 V All Other Inputs/Outputs . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Junction Temperature Range . . . . . . . . . . . . . . 0°C to +150°C *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ORDERING GUIDE Temperature Range Model ADP3204JCP-REEL 0ºC to 100ºC ADP3204JCP-REEL7 0ºC to 100ºC Package Description Package Option Quantity per Reel LFCSP-32 LFCSP-32 CP-32 CP-32 5000 1500 Table I. VID CODE VID4 VID3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 VID0 VOUT 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 1.250 1.200 1.150 1.100 1.050 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.750 0.725 0.700 0.675 0.650 0.625 0.600 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3204 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– ADP3204 RAMP REG CS– CS+ DSHIFT 32 31 30 HYSSET BSHIFT DPRSHIFT PIN CONFIGURATION 29 28 27 26 25 VID4 1 24 VCC PIN 1 IDENTIFIER VID3 2 23 CS3 22 CS2 VID2 3 VID1 4 21 CS1 ADP3204 VID0 5 20 OUT3 TOP VIEW (Not to Scale) BOM 6 19 OUT2 18 OUT1 DPSLP 7 17 GND DACOUT DACRAMP SS 14 15 16 COREFB SD 12 13 DRVLSD 10 11 CLAMP 9 PWRGD DPRSLP 8 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1–5 VID[4:0] Voltage Identification Inputs. These are the VID inputs for logic control of the programmed reference voltage that appears at the DACOUT pin, and, via external component configuration, is used for setting the output voltage regulation point. The VID pins have a specified internal pull-up current that, if left open, will default the pins to a logic high state. The VID code does not set the DAC output voltage directly but through a transparent latch that is clocked by the BOM pin’s GMUXSEL signal rising and falling edge. 6 BOM Battery Optimized Mode Control (Active Low). This digital input pin corresponds to the system’s GMUXSEL signal that corresponds to Battery Optimized Mode of the CPU operation in its active low state and Performance Optimized Mode (POM) in its deactivated high state. The signal also controls the optimal positioning of the core voltage regulation level by offsetting it downward in Battery Optimized Mode according to the functionality of the BSHIFT and RAMP pins. It is also used to initiate a masking period for the PWRGD signal whenever a GMUXSEL signal transition occurs. 7 DPSLP Deep Sleep Mode Control (Active Low). This is a digital input pin corresponding to the system’s STPCPU signal that, in its active state, corresponds to Deep Sleep Mode of the CPU operation, which is a subset operating mode of either BOM or POM operation. The signal controls the optimal positioning of the core voltage regulation level by offsetting it downward according to the functionality of the DSHIFT and RAMP pins. 8 DPRSLP Deeper Sleep Mode Control (Active High). This is a digital input pin corresponding to the system’s DPRSLPVR signal corresponding to Deeper Sleep Mode of the CPU operation. When the signal when it is activated it controls the DAC output voltage by disconnecting the VID signals from the DAC input and setting a specified internal Deeper Sleep code instead. At de-assertion of the DPRSLPVR signal, the DAC output voltage returns to the voltage level determined by the externalVID code. The DPRSLPVR signal is also used to initiate a blanking period for the PWRGD signal to disable its response to a pending dynamic core voltage change that corresponds to the VID code transition. 9 PWRGD Power Good (Active High). This open-drain output pin, via the assistance of an external pull-up resistor to the desired voltage, indicates that the core voltage is within the specified tolerance of the VID programmed value, or else is in a VID transition state as indicated by a recent state transition of either the BOM or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is disabled in UVLO mode, or starting up, or the COREFB voltage is out of the core power-good window. The open-drain output allows external wired ANDing (logical NORing) with other open drain/collector power-good indicators. 10 SD Shutdown (Active Low). This is a digital input pin coming from a system signal that, in its active state shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum power savings. –6– REV. 0 ADP3204 PIN FUNCTION DESCRIPTIONS (continued) Pin Mnemonic Function 11 CLAMP Clamp (Active High). This is open-drain output pin, via the assistance of an external pull-up resistor, indicates that the core voltage should be clamped for its protection. To allow the highest level of protection, the CLAMP signal is developed using both a redundant reference and a redundant feedback path with respect to those of the main regulation loop. In a preferred and more conservative configuration, the core voltage is clamped by an external FET. The initial protection function is served when it is activated by detection of either an overvoltage or a reverse-voltage condition on the COREFB pin. Due to loss of the latched signal at IC power-off, a backup protection function is served by connecting the pull-up resistor to a system “ALWAYS” regulator output (e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage clamped until the ADP3204 has power reapplied, thus keeping protection for the CPU even after a hard-failure power-down and restart (e.g., a shorted top or bottom FET). 12 DRVLSD Drive-Low Shutdown (Active Low). In its active state, this digital output pin indicates that the lower FET of the core VR should be disabled. In the suggested application schematic, this pin is directly connected to the pin of the same name on the ADP3415 or other driver IC. Drive-low shutdown is normally activated by the DPRSLP signal corresponding to a light load condition, but a number of dynamic conditions can override the control of this pin as needed. 13 SS Soft Start. The output of this analog I/O pin is a controlled current source used to charge or discharge an external grounded capacitor; the input is the detected voltage that is indicative of elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during overload, including but not limited to short circuit. Hiccup operation was added to reduce short circuit power dissipation by more than an order of magnitude, while still allowing an automatic restart when the failure mode ceased. The hiccup operation can be overwritten and changed to latched-off operation by clamping the SS pin voltage to a voltage level somewhere above ~ 0.2 V. In this configuration, the controller does not restart after a hiccup cycle is initiated, but stays latched off. 14 COREFB Core Feedback. This high impedance analog input pin is used to monitor the output voltage for setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filter the noise from the monitored core voltage, as suggested by the application schematic. 15 DACRAMP DAC Output Ramp Rate Setting. The rate at which the DAC output voltage can ramp up or down from one voltage to another when the VID code changes can be controlled by an external DACRAMP capacitor connected from this pin to the DACOUT pin. The time constant of the DACOUT voltage variation is determined by the internal resistance appearing across the DACRAMP and DACOUT pins, and the capacitance of the DACRAMP capacitor. Not having any DACRAMP capacitor connected to these pins results in the fastest rate. Use of the DACRAMP rate control and the Deeper Sleep Shift adjustment features are exclusive. 16 DACOUT Digital-to-Analog Converter Output of the VID input. This output voltage is the VID controlled reference voltage whose primary function is to determine the output voltage regulation point. 17 GND Ground 18–20 OUT1–3 Outputs to Driver 1–3. These digital output pins are used to command the state of theswitched nodes via the drivers. They should be connected to the IN pin of the drivers of the appropriate channels. 21 CS1 Current Sense, Channel 1. This high impedance analog input pin is used for providing negative feedback of the current information for the first channel. 22 CS2 Current Sense, Channel 2. This high impedance analog input pin is used to provide negative feedback of the current information for the second channel. The pin is also used to determine whether the chip is acting as a single or a multiphase controller. If the CS2 pin is tied to VCC but not to a sense resistor, then three-phase operation is disabled. In this condition, the second phase output signal (OUT2) is not switching but stays static low; the first and third phase output signals (OUT1 and OUT2) are switching in phase. It’s the user’s discretion to use only one or both of the two signals to drive a single- or dual-channel power stage. 23 CS3 Current Sense, Channel 3. This high impedance analog input pin is used to provide negative feedback of the current information for the third channel. The pin is also used to determine whether the chip is acting as a dual- or three-phase controller. If the pin is tied to VCC but not to a sense resistor, then three-phase operation is disabled; the chip works as a dual-phase controller. In this condition, the third phase output signal (OUT3) is not switching but stays static low; the first and second phase output signals (OUT1, OUT2) are interleaved out-of-phase signals. In singlephase operation, CS3 should be left open instead of being tied to VCC. REV. 0 –7– ADP3204 PIN FUNCTION DESCRIPTIONS (continued) Pin Mnemonic Function 24 VCC Power Supply. This should be connected to the system’s 3.3 V power supply output. 25 RAMP Regulation Ramp Feedback Input. The RAMP pin voltage is compared against the REG pin for cycle-by-cycle switching response. Several switched current sources also appear at this input: the cycle-by-cycle hysteresis-setting switched current programmed by the HYSSET pin, the BOM shift current programmed by the BSHIFT pin, and the Deep Sleep shift current programmed by the DSHIFT pin. The external resistive termination at this pin sets the magnitude of the hysteresis applied to the regulation loop. 26 REG Regulation Voltage Summing Input. This is a high impedance analog input pin into which the voltage reference of the feedback loop allows the summing of both the DACOUT voltage and the core voltage for programming the output resistance of the core voltage regulator. This is also the pin at which an optimized transient response can be tailored using Analog Devices’ patented ADOPT design technique. 27 CS+ Current Limit Positive Sense. This high impedance analog I/O pin is multiplexed between either of the three current-sense inputs during the high state of the OUT pin of the respective channel. During the common off-time of both channels, the pin voltage reflects the average of the three channels. The multiplexed current sense signal is passed to the core comparator through an external resistive termination connected from this pin to the RAMP pin. The external (RAMP) resistor sets the magnitude of the hysteresis applied to the regulation loop. 28 CS– Current Limit Negative Sense. This high impedance analog input pin which is normally Kelvin connected to the negative node of the current sense resistor(s) via a current-limit programming resistor. A hysteretically-controlled current—three times the current programmed at the HYSSET pin—also flows out of this pin and develops a current-limit-setting voltage across that resistor, which must then be matched by the inductor current flowing in the current sensing resistor in order to trigger the current limit function. When triggered, the current flowing out of this pin is reduced to two-thirds of its previous value, producing hysteresis in the current limiting function. 29 HYSSET Hysteresis Set. This is an analog I/O pin whose output is the VID reference voltage and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set the hysteretic currents for the Core Comparator and the Current Limit Comparator. Modification of the resistance will affect both the hysteresis of the feedback regulation, and the current limit set point and hysteresis. 30 DSHIFT Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the DSLP signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to Deep Sleep Mode of CPU operation. The use of the DACOUT voltage as the reference makes the Deep Sleep offset a fixed percentage of the VID setting, as required by specifications. 31 BSHIFT Battery Optimized Mode (BOM) Shift. This is an analog I/O pin whose output is the VID reference voltage and whose input current is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the BOM signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to Battery Optimized Mode of CPU operation. The use of the DACOUT voltage as the reference makes the DSHIFT a fixed percentage of the VID setting, as required by specifications. –8– REV. 0 ADP3204 PIN FUNCTION DESCRIPTIONS (continued) Pin Mnemonic Function 32 DPRSHIFT Deeper Sleep Shift. This is an analog I/O pin whose output is a fixed voltage reference and whose input current is programmed by an external resistor to ground. The current is used to set two switched bias currents that flow into both the REG and COREFB pins, depending on the DPRSLP signal. When activated, the REG pin bias current creates an upward shift of the regulated core voltage from the internally set (default) Deeper Sleep value to the voltage level specified by the CPU Deeper Sleep operation. The COREFB bias current creates the same amount of downward shift of the COREFB voltage is. The shifted back COREFB voltage compared against the internally set Deeper Sleep voltage to create Power Good information. Use of the Deeper Sleep Shift adjustment and the DACRAMP rate control features are exclusive. V_5S D3 BAR43S C33 0.1F C43 3.3F V_DC R106 2.7 C32 1F 2x0.1F ADP3415 1 IN C2 0.1µF RA243 1% C3 RDPRSHIFT REG 26 RAMP 25 CS– 28 CS+ 27 DSHIFT 30 HYSSET 29 BSHIFT 31 DPRSHIFT 32 CS3 23 1 IN CS2 22 2 SD 3 DRVLSD VID1 CS1 21 VID0 OUT3 20 BOM OUT2 19 DPSLP OUT1 18 GND 17 16 DACOUT 14 COREFB 13 SS 12 DRVLSD 11 CLAMP 10 SD DPRSLP 15 DACRAMP VR_ VID2 VR_PWRGD 2x0.1F R17 0 SW 8 4 DLY GND 7 5 VCC DRVL 6 JP1 RD R9 1.05k 1% 1.05k 1% C6 1000pF C9 10pF V_5S C41 3.3F R16 0 Q4 IR7811W L2 0.32H RCS2 3m R14 D5 MBRS130LT3 10 C21 0.018F Q12 IR7822 D1 BAR43S C13 0.1F V_DC R104 2.7 ADP3415 R90 300k Q3 IR7811W Q11 IR7822 CSS 0.047F C27 . . . C30 4x10F BST 10 DRVH 9 CORE_ON VCC-VID (1.2V) V_DC C32 1F ADP3415 24 4 ADP3204 C23 0.1F VCC VID3 9 PWRGD Q14 IR7822 D2 BAR43S R102 2.7 VID2 BAR43S R15 10 C31 0.018F C42 3.3F 3 D90 RCS3 3m D6 MBRS130LT3 Q13 IR7822 V_5S 2 3k L3 0.32H 4700pF VR_ VID3 V_3S GND 7 DRVL 6 COC OPTIONAL: DEEPERSLEEP VOLTAGE ADJUSTMENT VR_ VID1 5 VR_ VID0 220k 6 GMUXSEL (IMVP-II ONLY) 7 STP_CPU 8 DPRSLPVR 4 DLY 5 VCC Q6 IR7811W RB 54.9k C4 10pF 10pF VID4 8 RC 1.5k 1% RDSHIFT 8.87k 1% 1 SW R18 0 RCL 576 1% RBSHIFT 21.5k 1% VR_ VID4 C1 1µF Q5 IR7811W DRVH 9 3 DRVLSD R4 2.7 RHYSSET 21.5k 1% BST 10 2 SD V_3S C37 . . . C40 4x10F 1 IN 2 SD 3 DRVLSD 4 DLY GND 7 5 VCC DRVL 6 C12 1F 2x0.1F C17 . . . C20 4x10F BST 10 Q1 IR7811W DRVH 9 SW 8 Q2 IR7811W L1 0.32H RCS1 3m R23 D4 MBRS130LT3 10 SET: LATCHED OCP OPEN: HICCUP OCP Q9 IR7822 C11 0.018F Q10 IR7822 V5 R20 5.1k Figure 1. Typical Application REV. 0 –9– VCC CORE Q7 IR7807V C44...C49 6x220F ADP3204–Typical Performance Characteristics 10000 HIGH 1000 UVLO MODE PWRGD SUPPLY CURRENT – A NORMAL OPERATING MODE 100 SHUTDOWN MODE LOW 10 0 20 40 60 AMBIENT TEMPERATURE – C 80 0.15 100 0.05 0.1 0 0.05 0.1 0.15 RELATIVE CORE VOLTAGE – % TPC 1. Supply Current vs. Temperature TPC 4. Power Good vs. Relative Core Voltage Variation 1.77 10 +1% SOFT START TIME – ms DAC OUTPUT – V 1.76 FULL SCALE 1.75 1.74 1 0.1 0.01 1% 1.73 0 20 40 60 AMBIENT TEMPERATURE – C 80 0.001 100 0.615 108.0 DAC OUTPUT – V NORMALIZED BLANKING TIME – % 110.0 +8.5mV 0.605 ZERO SCALE VID [11111] 0.595 100 TPC 5. Soft Start Timing vs. Timing Capacitor 0.620 0.600 10 SOFT START CAPACITANCE – nF TPC 2. DAC Output Voltage vs. Temperature 0.610 1 0.1 8.5mV 0.590 0.585 106.0 104.0 102.0 100.0 98.0 96.0 94.0 92.0 0.580 0 20 40 60 80 90.0 100 0 AMBIENT TEMPERATURE – C TPC 3. DAC Output Voltage vs. Temperature 20 40 60 80 AMBIENT TEMPERATURE – C 100 TPC 6. PWRGD Blanking Time vs. Temperature Normalized to 25°C –10– REV. 0 ADP3204 0 110 ICS – CURRENT LIMIT THRESHOLD – A HYSTERESIS CURRENT – A OUT = HIGH, RHYS = 17k OUT = HIGH, RHYS = 170k 0 OUT = LOW, RHYS = 170k OUT = LOW, RHYS = 17k OUT = LOW, RHYSSET = 170k –50 OUT = HIGH, RHYSSET = 170k –100 –150 –200 OUT = LOW, RHYSSET = 17k –250 –300 OUT = HIGH, RHYSSET = 17k –350 –110 0 20 40 60 80 0 100 TPC 7. Core Hysteresis Current vs. Temperature Power Conversion Control Architecture Driving of the individual channels is accomplished using external drivers, such as the ADP3415. One PWM interface pin per channel, OUT1, OUT2, and OUT3, is provided. A separate pin, DRVLSD, commands the driver to enable or disable synchronous rectifier operation during the off time of each channel. The same DRVLSD pin is connected to all three drivers. The ADP3204 utilizes hysteretic control. The resistor from the HYSSET pin to ground sets up a current that is switched bidirectionally into a resistor interconnected between the RAMP and CS+ pins. The switching of this current sets the hysteresis. In a multichannel configuration, the hysteretic control requires multiplexing information in all channels. The inductor current of the channel that is driven high is controlled against the upper hysteresis limit. During the common offtime of the channels, the inductor currents are averaged together and compared against the lower hysteresis limit. This proprietary offtime averaging technique serves to eliminate a systematic offset that otherwise appears in a fully multiplexed hysteretic control system. REV. 0 60 80 100 Feedback/Current Sensing Featuring a new proprietary 1-, 2-, or 3-channel buck converter hysteretic control architecture developed by Analog Devices, the ADP3204 is the optimal core voltage control solution for both IMVP-II and IMVP-III generation microprocessors. The complex multitiered regulation requirements of either IMVP specification are easily implemented with the highly integrated functionality of this controller. As with all ADI products for core voltage control, the controller is compatible with ADOPT compensation, which provides the optimum output voltage containment within a specified voltage window or along a specified load line using the fewest possible output capacitors. The inductor ripple current is kept at a fixed programmable value while the output voltage is regulated with fully programmable voltage positioning parameters, which can be tuned to optimize the design for any particular CPU regulation specification. By controlling the ripple current rather than the ripple voltage, the frequency variations associated with changes in output impedance for standard ripple regulators will not appear. 40 TPC 8. Current Limit Threshold vs. Temperature THEORY OF OPERATION Overview Compensation 20 AMBIENT TEMPERATURE – C TEMPERATURE – C Accurate current sensing is needed to accomplish output voltage positioning accurately, which, in turn, is required to allow the minimum number of output capacitors to be used to contain transients. A current sense resistor is used between each inductor and the output capacitors. To allow the control to operate without amplifiers, the negative feedback signal is multiplexed from the inductor or upstream side of the current sense resistors, and a positive feedback signal, if needed for load-line tuning, is taken from the output or downstream side. Output Voltage Programming by VID, Offsets, and Load Line In the IMVP-II and IMVP-III specifications, the output voltage is a function of both the core current (according to a specified load line) and the system operating mode (i.e., performance or battery optimized, normal or deep sleep clocking state, or deeper sleep). The VID code programs the “nominal” core voltage. The core voltage decreases as a function of load current along the load line, which is synonymous with an output resistance of the power converter. The core voltage is also offset by a dc value—usually specified as a percentage—depending on the operating mode. The voltage offset is also called a “shift.” Two pins, BSHIFT and DSHIFT, are used to program the magnitude of the voltage shifts. The voltage shifts are accomplished by injecting current at the node of the negative input pin of the feedback comparator. Resistive termination at the pins determines the magnitude of the voltage “shifts.” Two other pins, BOM and DPSLP, are used to activate the respective two shifts only in their active low states. In the ADP3204, the shifts are mutually exclusive, with the Deep Sleep shift (controlled by the DPSLP and DSHIFT pins) being the dominant one. Another pin, DPRSLP, eliminates both shifts only in its active high state. Its assertion corresponds to the Deeper Sleep operating mode. Current Limiting The current programmed at the HYSSET pin and a resistor from the CS– pin to the common node of the current sense resistors set the current limit. If the current limit threshold is triggered, a hysteresis is applied to the threshold so that hysteretic control is maintained during a current limited operating mode. –11– ADP3204 SoftStart and Hiccup A capacitor from the SS pin to ground determines both the soft start time and the frequency at which hiccup will occur under a continuous short circuit or overload. System Signal Interface Several pins of the ADP3204 are meant to connect directly to system signals. The VID pins connect to the system VID control signals. The DPRSLP pin connects to the system’s DPRSLPVR signal. The DPSLP pin connects to the system’s DPSLP or STPCPU signal. The BOM signal connects to the system’s GMUXSEL signal. In an IMVP-II system, the GMUXSEL signal precedes any VID code change with a few nanoseconds, while in an IMVP-III system, it follows it with a maximum 12 µs delay. To comply with both specifications, the ADP3204 has a VID register in front of the DAC inputs that is written by a short pulse generated at the rising or falling edge of the GMUXSEL signal. In an IMVP-II configuration, if the external VID multiplex settling time is longer than the internal VID register’s write pulsewidth, then the insertion of an external RC delay network in the GMUXSEL signal path (in front of the BOM pin) is recommended. The Intel specification calls for maximum 200 ns VID code setup time. This specification can be met with a simple RC network that consists of only a 220 kΩ resistor and no external capacitor, just the BOM pin’s capacitance. Undervoltage Lockout configuration, the latched off state of the system would be indicative of a system failure. The overvoltage/reverse voltage protective means is via not allowing the continued application of energy to the CPU core. The design objective should be, however, to ensure that the CPU core could safely absorb the remaining energy in the power converter, since this energy is not clamped as in the preferred configuration. LAYOUT CONSIDERATIONS Advantages in PCB Layout Analog Devices provides ADP3204/3415 as a dedicated threephase power management solution for IMVP-III Intel P4 mobile core supply. This three-phase solution separates the controller (ADP3204) and the MOSFET drivers (ADP3415). Today, most motherboards only leave small pieces of PCB area for the power management circuit. Therefore, the separation of the controller and the MOSFET drivers gives much greater freedom in layout than any single chip solution. Meanwhile, the separation also provides the freedom to place the analog controller in a relatively quiet area in the motherboard. This can minimize the susceptibility of the controller to injected noise. Any single chip solution with a high speed loop design will suffer larger susceptibility to jitter that appears as modulation of the output voltage. The ADP3204’s supply pin, VCC, has undervoltage lockout (UVLO) functionality to ensure that if the supply voltage is too low to maintain proper operation, the IC will remain off and in a low current state. The ADP3204 maximizes the integration of IMVP-III features. Therefore, no additional externally implemented functions are required to comply with IMVP-III specifications. This saves PCB area for component placement on the motherboard. Overvoltage Protection (OVP) and Reverse Voltage Protection (RVP) PCB Layout Consideration for ADP3204/3415 The ADP3204 features a comprehensive redundantly monitored OVP and RVP implementation to protect the CPU core against an excessive or reverse voltage, e.g., as might be induced by a component or connection failure in the control or power stage. Two pins are associated with the OVP/RVP circuitry—a pin for output voltage feedback, COREFB, which is also used for power good monitoring but not for voltage regulation, and an output pin, CLAMP. The CLAMP pin defaults to a low state at startup of the ADP3204 and remains low until an overvoltage or reverse voltage condition is detected. If either condition is detected, the CLAMP signal is asserted and latched high. For maximum and fastest protection, the CLAMP pin should be used to drive the gate of a power MOSFET whose drain source is connected across the CPU core voltage. Detection of overvoltage or reverse voltage will clamp the core voltage to essentially zero, thus quickly removing the fault condition and preventing further energy from being applied to the CPU core. For a less comprehensively protective and less costly solution, the CLAMP pin may be used to latch the disconnection of input power. The latch should be powered whenever any input power source is present. Typically, such a latching circuit is already present in a system design, so it becomes only a matter of allowing the CLAMP pin to also trigger the latch. In this The following guidelines are recommended for optimal performance of the ADP3204 and ADP3415 in a power converter. The circuitry is considered in three parts: the power switching circuitry, the output filter, and the control circuitry. Placement Overview 1. For ideal component placement, the output filter capacitors will divide the power switching circuitry from the control section. As an approximate guideline considered on a singlesided PCB, the best layout would have components aligned in the following order: ADP3415, MOSFETs and input capacitor, output inductor, current sense resistor, output capacitors, control components, and ADP3204. Note that the ADP3204 and ADP3415 are completely separated for an ideal layout, which is impossible with a single-chip solution. This keeps the noisy switched power section isolated from the precision control section and gives more freedom in the layout of the power switching circuitry. 2. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad if possible and immediately surrounding it, is recommended. Two important reasons for this are: improvement of the current rating through the vias (if it is a current path) and improved thermal performance, especially if there is opportunity to spread the heat with a plane on the opposite side of the PCB. –12– REV. 0 ADP3204 Power Switching Circuitry Control Circuitry ADP3415, MOSFETs, and Input Capacitors ADP3204, Control Components 3. Locate the ADP3415 near the MOSFETs so that the loop inductance in the path of the top gate drive returned to the SW pin is small, and similarly for the bottom gate drive whose return path is the ground plane. The GND pin should have at least one very close via into the ground plane. 12. If the ADP3204 cannot be placed as previously recommended, care should be taken to keep the device and surrounding components away from radiation sources (e.g., from power inductors) and capacitive coupling from noisy power nodes. 4. Locate the input bypass MLC capacitors close to the MOSFETs so that the physical area of the loop enclosed in the electrical path through the bypass capacitor and around through the top and bottom MOSFETs (drain-source) is small and wide. This is the switching power path loop. 13. Noise immunity can be improved by the use of a devoted signal ground plane for the power controller and its surrounding components. Space for a ground plane might readily be available on a signal plane of the PCB since it is often unused in the vicinity of the power controller. 5. Make provisions for thermal management of all the MOSFETs. Heavy copper and wide traces to ground and power planes will help to pull the heat out. Heat sinking by a metal tap soldered in the power plane near the MOSFETs will help. Even just a small airflow can help tremendously. Paralleled MOSFETs to achieve a given resistance will help spread the heat. 14. If critical signal lines (i.e., signals from the current sense resistor leading back to the ADP3204) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals. 6. An external Schottky diode (across the bottom MOSFET) may increase efficiency by a small amount (< ~1%), depending on its forward voltage drop compared to the MOSFET’s body diode at a given current; a MOSFET with a built-in Schottky is more effective. For an external Schottky, it should be placed next to the bottom MOSFET or it may not be effective at all. 15. Absolutely avoid crossing any signal lines over the switching power path loop, described previously. 7. The VCC bypass capacitor should be close to the VCC pin and connected on either a very short trace to the GND pin or to the GND plane. Output Filter Output Inductor and Capacitors, Current Sense Resistor 8. Locate the current sense resistors very near to the output voltage plane. 9. The load-side heads of sense resistors should join as closely as possible for accurate current signal measurement of each phase. 17. The RC filter used for the current sense signal should be located near the control components as this serves the dual purpose of filtering out the effect of the current sense resistors’ parasitic inductance and the noise picked up along the routing of the signal. The former purpose is achieved by having the time constant of the RC filters approximately matched to that of the sense resistors, and is important for maintaining the accuracy of the current signal. APPLICATION INFORMATION Theoretical Background 10. PCB trace resistances from the current sense resistors to the regulation point should be minimized, known (calculated or measured), and compensated for as part of the design if it is significant. (Remote sensing is not sufficient for relieving this requirement.) A square section of 1-ounce copper trace has a resistance of ~0.5 mΩ, which adds to the specified DC output resistance of the power converter. The output capacitors should similarly be close to the regulation point and well tied into power planes as impedance here will add to the “AC output resistance” (i.e., the ESR) that is implicitly specified as well. This application section presents the theoretical background for multiphase dc-to-dc converters using the ADP320x family of controllers for mobile CPUs. Members of that family control multiphase ripple regulators (also called hysteretic regulators) in a configuration that allows employing ADOPT, Analog Devices’ optimal voltage positioning technique to implement the desired output voltage and load line, both statically and dynamically, as required by Intel’s IMVP-II and IMVP-III specifications. Single-Phase Hysteretic Regulator with ADOPT 11. Whenever high currents must be routed between PCB layers, vias should be used liberally to create parallel current paths so that the resistance and inductance are minimized and the via current rating is not exceeded. REV. 0 16. Accurate voltage positioning depends on accurate current sensing, so the control signals that monitor the voltage differentially across the current sense resistor should be Kelvin-connected. Please refer to ADI Evaluation Board of the ADP3204 and its documentation for control signal connection with sense resistors. Figure 2 shows the conventional single-phase hysteretic regulator and the characteristic waveforms. The operation is as follows. During the time the upper transistor, Q1, is turned on, the inductor current, IL, and also the output voltage, VOUT, increase. When VOUT reaches the upper threshold of the hysteretic comparator, Q1 is turned off, Q2 is turned on, and the inductor current and the output voltage decrease. The cycle repeats after VOUT reaches the lower threshold of the hysteretic comparator. –13– ADP3204 and VOUT VIN 2 VH Q1 L VSW VOUT IL CO Q2 COC = + RE LOAD t VSW RCS = t IL t Since there is no voltage error amplifier in the hysteretic regulator, its response to any change in the load current or the input voltage is virtually instantaneous. Therefore, the hysteretic regulator represents the fastest possible dc-to-dc converter. A slight disadvantage of the conventional hysteretic regulator is that its frequency varies with the input and output voltages. In a typical mobile CPU converter application, the worst-case frequency variation due to the input voltage variation is in the order of 30%, which is usually acceptable. In the simplest implementation of the hysteretic converter, shown in Figure 2, the frequency also varies proportionally with the ESR, RE, of the output capacitor. Since the initial value is often poorly controlled, and the ESR of electrolytic capacitors also changes with temperature and age, practical ESR variations can easily lead to a frequency variation in the order of three to one. However, a modification of the hysteretic topology eliminates the dependence of the operating frequency on the ESR. In addition, the modification allows the optimal implementation, ADOPT, of Intel’s IMVP-II and IMVP-III load-line specifications. Figure 3 shows the modified hysteretic regulator. VIN VSW Q2 VH L IL RCS COC VOUT CO RC + RE RD VREF Figure 3. Modified Hysteretic Regulator with ADOPT The implementation requires adding a resistive divider (RC and RD) between the reference voltage and the output, and connecting the tap of the divider to the noninverting input of the hysteretic comparator. A capacitor, COC, is placed across the upper member (RC) of the divider. It is easily shown that the output impedance of the converter can be no less than the ESR of the output capacitor. A straightforward derivation demonstrates that the output impedance of the converter in Figure 3 can be minimized to equal the ESR, RE, when the following two equations are valid (neglecting PCB trace resistance for now): RE R = 1+ D RCS RC RE R 1+ D RC (3) This is the ADOPT configuration and design procedure that allows the maximum possible ESR to be used while meeting a given load-line specification. Figure 2. Conventional Hysteretic Regulator and Its Characteristic Waveforms Q1 (2) From (Equation 2), the series resistance is: VH VREF CO RE RCS RD (1) It can be seen from Equation 3 that unless RD is zero or RC is infinite, RCS will always be smaller than RE. An advantage of the circuit in Figure 3 is that if we select the ratio RD/RC well above unity, the additional dissipation introduced by the series resistance RCS will be negligible. Another interesting feature of the circuit in Figure 3 is that the ac voltage across the two inputs of the hysteretic comparator is now equal only to the ac voltage across RCS. This is due to the presence of the capacitor COC, which effectively couples the ac component of the output voltage to the noninverting input voltage of the comparator. Since the comparator sees only the ac voltage across RCS, in the circuit in Figure 3 the dependence of the switching frequency on the ESR of the output capacitor is completely eliminated. Equation 4 presents the expression for the switching frequency. f = RCS (VIN −VOUT ) VOUT LVH VIN (4) Multiphase Hysteretic Regulator with ADOPT Multiphase converters have very important advantages, including reduced rms current in the input filter capacitor (allowing the use of a smaller and less expensive device), distributed heat dissipation (reducing the hot spot temperature and increasing reliability), higher total power capability, increased equivalent frequency without increased switching losses (allowing the use of smaller equivalent inductances, and thereby shortening the load transient time), and reduced ripple current in the output capacitor (reducing the output ripple voltage and allowing the use of a smaller and less expensive output capacitor). Also, they have some disadvantages, which should be considered when choosing the number of phases. Those disadvantages include the need for more switches and output inductors than in a single-phase design (leading to higher cost than a single-phase solution, at least below a certain power level), more complex control, and the possibility of uneven current sharing among the phases. The family of ADP320x controllers alleviates two of the above disadvantages of multiphase converters. It presents a simple and cost-effective control solution, and provides perfect current sharing among the phases. Figure 4 shows a simplified block diagram of a three-phase converter using the control principle implemented with the ADP3204, the three-phase member of the ADP320x family. As Figure 4 shows, in the multiphase configuration, the ripple current signal is multiplexed from all channels. During the on time of any given channel, its current is compared to the upper threshold of the hysteretic comparator. When the current reaches the upper threshold, the control FET of that channel is –14– REV. 0 ADP3204 turned off. During the common off time of all channels, their currents are averaged and compared to the lower threshold. When the averaged channel current reaches the lower threshold, the hysteretic comparator changes state again, and turns on the control FET of the next channel, as selected by the phase splitter logic. This control concept ensures that the peak currents of all channels will be the same, and therefore the channel currents will be perfectly balanced. The ADOPT compensation can be used the same way as in the single-phase version discussed previously. Since due to second-order effects, the detailed design of a multiphase converter with the ADP320x family is rather complex, a design aid using MathSoft’s MathCAD™ program has been developed. Please contact ADI for further information. PHASE 1 L1 IL1 RCS1 PHASE 2 L2 IL2 RCS2 VIN VOUT RE CO PHASE 3 PHASE SPLITTER OUT 3 OUT 2 OUT 1 L3 IL3 HYSTERETIC CORE COMPARATOR RCS3 CURRENT SENSE MUX CS1 CS2 CS3 COC RD VREF Figure 4. 3-Phase Modified Hysteretic Regulator with ADOPT MathCAD is a trademark of MathSoft. REV. 0 –15– RC LOAD ADP3204 OUTLINE DIMENSIONS 32-Lead Frame Chip Scale Package [LFCSP] (CP-32) 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 0.50 0.40 0.30 32 1 3.25 3.10 SQ 2.95 BOTTOM VIEW 17 16 9 8 3.50 REF 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 PRINTED IN U.S.A. 1.00 0.90 0.80 PIN 1 INDICATOR 0.60 MAX 25 24 12 MAX C02841–0–11/02(0) Dimensions shown in millimeters –16– REV. 0