AD ADSP-21160M

a
SHARC®
DSP Microcomputer
ADSP-21160M
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards-Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4 M Bit On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
80 MHz (12.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
480 MFLOPS Peak and 320 MFLOPS Sustained
Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and
On-Chip Emulation
400-Ball 27 ⴛ 27 mm Metric PBGA Package
FUNCTIONAL BLOCK DIAGRAM
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SHARC is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
World Wide Web Site: http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2001
ADSP-21160M
FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bit On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160M Internal Memory and External
Memory, External Peripherals, Host Processor, Serial
Ports, or Link Ports
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
560M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ms plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 40M Bit/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Up to 40 MHz Operation
GENERAL DESCRIPTION
The ADSP-21160M SHARC DSP is the first processor in
a new family featuring Analog Devices’ Super Harvard
Architecture. Easing portability, the ADSP-21160M is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (Single Instruction,
Single Data) mode. To take advantage of the processor’s
SIMD (Single Instruction, Multiple Data) capability, some
code changes are needed. Like other SHARCs, the
ADSP-21160M is a 32-bit processor that is optimized for
high performance DSP applications. The ADSP-21160M
includes an 80 MHz core, a dual-ported on-chip SRAM, an
integrated I/O processor with multiprocessing support, and
multiple internal buses to eliminate I/O bottlenecks.
The ADSP-21160M introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160M can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160M has a 12.5 ns instruction cycle time. With its SIMD computational hardware
running at 80 MHz, the ADSP-21160M can perform 480
million math operations per second.
Table 1 shows performance benchmarks for the
ADSP-21160M.
Table 1. ADSP-21160M Benchmarks
Benchmark Algorithm
Speed
1024 Point Complex FFT (Radix 4, with
reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3ⴛ3] ⴛ [3ⴛ1]
Matrix Multiply (pipelined)
[4ⴛ4] ⴛ [4ⴛ1]
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
115 µs
6.25 ns
25 ns
56.25 ns
100 ns
37.5 ns
56.25 ns
560M Bytes/s
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.
The ADSP-21160M continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4M bit dual
ported SRAM memory, host processor interface, I/O
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
multiprocessing.
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The functional block diagram on page 1 shows a block
diagram of the ADSP-21160M, illustrating the following
architectural features:
• Two processing elements, each made up of an ALU, Multiplier, Shifter, and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycle
• Interval timer
• On-Chip SRAM (4 Mbit)
• External port that supports:
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
ADSP-21160M SHARCs
• Host port
• DMA controller
• Serial ports and link ports
• JTAG test access port
Figure 1 shows a typical single-processor system. A multiprocessing system appears in Figure 4.
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SIMD Computational Engine
The ADSP-21160M contains two computational processing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
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Figure 1. Single-Processor System
Within each processing element is a set of computational
units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximizing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These computation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
Data Register File
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The ADSP-21160M includes the following architectural features of the ADSP-2116x family core. The
ADSP-21160M is code compatible at the assembly level
with the ADSP-21060, ADSP-21061, and ADSP-21062.
Independent, Parallel Computation Units
ADSP-21160M Family Core Architecture
A general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY
as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21160M features an enhanced Harvard architecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instructions and data (see the functional block diagram on page 1).
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With the ADSP-21160M’s separate program and data
memory buses and on-chip instruction cache, the processor
can simultaneously fetch four operands and an instruction
(from the cache), all in a single cycle.
Instruction Cache
The ADSP-21160M includes an on-chip instruction cache
that enables three-bus operation for fetching an instruction
and four data values. The cache is selective—only the
instructions whose fetches conflict with PM bus data
accesses are cached. This cache allows full-speed execution
of core, providing looped operations such as digital filter
multiply- accumulates and FFT butterfly processing.
Data Address Generators with Hardware
Circular Buffers
The ADSP-21160M’s two data address generators (DAGs)
are used for indirect addressing and provide for implementing circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures required in digital signal processing, and are
commonly used in digital filters and Fourier transforms.
The two DAGs of the ADSP-21160M contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example,
the ADSP-21160M can conditionally execute a multiply, an
add, and subtract, in both processing elements, while
branching, all in a single instruction.
ADSP-21160M Memory and I/O Interface Features
Augmenting the ADSP-2116x family core, the
ADSP-21160M adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21160M contains four megabits of on-chip
SRAM, organized as two blocks of 2 Mbits each, which can
be configured for different combinations of code and data
storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor. The dual-ported memory in combination with three
separate on-chip buses allows two data transfers from the
core and one from I/O processor, in a single cycle. On the
ADSP-21160M, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of
16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four
megabits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the
amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is done in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data, using the DM
bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and
PM bus in this way, with one dedicated to each memory
block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in
the cache.
Off-Chip Memory and Peripherals Interface
The ADSP-21160M’s external port provides the processor’s interface to off-chip memory and peripherals. The
4G word off-chip address space is included in the
ADSP-21160M’s unified address space. The separate
on-chip buses—for PM addresses, PM data, DM addresses,
DM data, I/O addresses, and I/O data—are multiplexed at
the external port to create an external system bus with a
single 32-bit address bus and a single 64-bit data bus. The
lower 32 bits of the external data bus connect to even
addresses and the upper 32 bits of the 64 connect to odd
addresses. Every access to external memory is based on an
address that fetches a 32-bit word, and with the 64-bit bus,
two address locations can be accessed at once. When
fetching an instruction from external memory, two 32-bit
data locations are being accessed (16 bits are unused).
Figure 3 shows the alignment of various accesses to
external memory.
The external port supports asynchronous, synchronous,
and synchronous burst accesses. ZBT synchronous burst
SRAM can be interfaced gluelessly. Addressing of external
memory devices is facilitated by on-chip decoding of
high-order address lines to generate memory bank select
signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21160M
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold, and
disable time requirements.
DMA Controller
The ADSP-21160M’s on-chip DMA controller allows
zero-overhead data transfers without processor intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the
ADSP-21160M’s internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the ADSP-21160M’s internal memory
and its serial ports or link ports. External bus packing to
16-, 32-, 48-, or 64-bit words is performed during DMA
transfers. Fourteen channels of DMA are available on the
ADSP-21160M—six via the link ports, four via the serial
ports, and four via the processor’s external port (for either
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Figure 3. ADSP-21160M External Data Alignment Options
or rotating priority. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 320M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ms and can be used
to implement reflective semaphores.
Six link ports provide for a second method of multiprocessing communications. Each link port can support
communications to another ADSP-21160M. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.
Figure 2. ADSP-21160M Memory Map
Link Ports
host processor, other ADSP-21160Ms, memory or I/O
transfers). Programs can be downloaded to the
ADSP-21160M using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.
Multiprocessing
The ADSP-21160M offers powerful features tailored to
multiprocessing DSP systems as shown in Figure 4. The
external port and link ports provide integrated glueless multiprocessing support.
The external port supports a unified address space (see
Figure 2) that allows direct interprocessor accesses of each
ADSP-21160M’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection
of systems containing up to six ADSP-21160Ms and a host
processor. Master processor changeover incurs only one
cycle of overhead. Bus arbitration is selectable as either fixed
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The ADSP-21160M features six 8-bit link ports that
provide additional I/O capabilities. With the capability of
running at 80 MHz rates, each link port can support 80M
bytes/s. Link port I/O is especially useful for point-to-point
interprocessor communication in multiprocessing systems.
The link ports can operate independently and simultaneously. Link port data is packed into 48- or 32-bit words,
and can be directly read by the core processor or
DMA-transferred to on-chip memory. Each link port has its
own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit
or receive. For data throughput information, see link port
timing details in Table 18 on page 34.
Serial Ports
The ADSP-21160M features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
each with a maximum data rate of 40M bit/s. Independent
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tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional
µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
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Host Processor Interface
$ The ADSP-21160M host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160M’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160M,
and can access the DMA channel setup and mailbox registers. Vector interrupt support provides efficient execution
of host commands.
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Power Supplies
The ADSP-21160M has separate power supply connections
for the internal (VDDINT), external (VDDEXT), and analog
(AVDD/AGND) power supplies. The internal and analog
supplies must meet the 2.5 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same supply.
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Phased Locked Loop
The ADSP-21160M uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
port operates.
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The internal memory of the ADSP-21160M can be booted
at system power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
for booting.
Figure 4. Shared Memory Multiprocessing System
transmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automatically transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
multichannel mode. The serial ports can operate with lit-
Note that the analog supply (AVDD) powers the
ADSP-21160M’s clock generator PLL. To produce a stable
clock, the system must provide an external circuit to filter
the power input to the AVDD pin. Place the filter as close as
possible to the pin. For an example circuit, see Figure 5. To
prevent noise coupling, use a wide trace for the analog
ground (AGND) signal and install a decoupling capacitor
as close as possible to the pin.
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Figure 5. Analog Power (AVDD) Filter Circuit
Development Tools
The ADSP-21160M is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and VisualDSP++1 development environment. The same emulator hardware that supports other
ADSP-2116x DSPs, also fully emulates the
ADSP-21160M.
The VisualDSP++ project management environment lets
programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. Two key points
for these tools are:
• Compiled ADSP-2116x C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to ADSP-2116x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
• ADSP-2106x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-2116x.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all
1
of the ADSP-2116x development tools, including the syntax
highlighting in the VisualDSP++ editor. This capability
permits:
• Control how the development tools process inputs and
generate outputs.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21160M processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-2116x processor
family. Hardware tools include ADSP-2116x PC plug-in
cards. Third Party software tools include DSP libraries,
real-time operating systems, and block diagram
design tools.
Designing an Emulator-Compatible DSP Board
(Target)
The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The
emulator uses the TAP to access the internal features of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers.
The DSP must be halted to send data and commands, but
once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on
system timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices’ JTAG DSP
is a 14-pin header, as shown in Figure 6. The customer must
supply this header on the target board in order to communicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on
0.1" ⴛ 0.1" spacing, with a minimum post length of 0.235".
Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the
target board.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
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Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
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Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
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Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in Place)
As can be seen in Figure 6, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are optionally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure 7. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 8 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure 9 displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
BC
B*C
Figure 9. JTAG Pod Connector Keep-Out Area
B
C
B
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B))C
Figure 8. JTAG Pod Connector Dimensions
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website—use site search on
“EE-68” (www.analog.com). This document is updated
regularly to keep pace with improvements to emulator
support.
Additional Information
This data sheet provides a general overview of the
ADSP-21160M architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.
PIN FUNCTION DESCRIPTIONS
ADSP-21160M pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for
TMS, TDI). Inputs identified as asynchronous (A) can be
asserted asynchronously to CLKIN (or to TCK for TRST).
–8–
REV. 0
ADSP-21160M
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31–0, DATA63–0, FLAG3–0, and inputs
that have internal pull-up or pull-down resistors (PA, ACK,
BRST, PAGE, CLKOUT, MS3–0, RDx, WRx, DMARx,
DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7–0,
LxCLK, LxACK, TMS, TRST and TDI)—these pins can
be left floating. These pins have a logic-level hold circuit
(only enabled on the ADSP-21160M with ID2–0 = 00x)
that prevents input from floating internally.
The following symbols appear in the Type column of
Table 2: A = Asynchronous, G = Ground, I = Input,
O = Output, P = Power Supply, S = Synchronous,
(A/D) = Active Drive, (O/D) = Open Drain, and
T = Three-State (when SBTS is asserted, or when the
ADSP-21160M is a bus slave).
Table 2. Pin Function Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
DATA63–0
I/O/T
MS3–0
O/T
RDL
I/O/T
RDH
I/O/T
WRL
I/O/T
WRH
I/O/T
PAGE
O/T
External Bus Address. The ADSP-21160M outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ms. The
ADSP-21160M inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s
ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
External Bus Data. The ADSP-21160M inputs and outputs data and instructions on
these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only
enabled on the ADSP-21160M with ID2–0 = 00x).
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank size must be defined in the
SYSCON control register. The MS3–0 outputs are decoded memory address lines. In
asyn- chronous access mode, the MS3–0 outputs transition with the other address
outputs. In synchronous access modes, the MS3–0 outputs assert with the other address
lines; however, they de-assert after the first CLKIN cycle in which ACK is
sampled asserted.
Memory Read Low Strobe. RDL is asserted whenever ADSP-21160M reads from the
low word of external memory or from the internal memory of other ADSP-21160Ms.
External devices, including other ADSP-21160Ms, must assert RDL for reading from
the low word of ADSP-21160M internal memory. In a multiprocessing system, RDL
is driven by the bus master.
Memory Read High Strobe. RDH is asserted whenever ADSP-21160M reads from the
high word of external memory or from the internal memory of other ADSP-21160Ms.
External devices, including other ADSP-21160Ms, must assert RDH for reading from
the high word of ADSP-21160M internal memory. In a multiprocessing system, RDH
is driven by the bus master.
Memory Write Low Strobe. WRL is asserted when ADSP-21160M writes to the low
word of external memory or internal memory of other ADSP-21160Ms. External
devices must assert WRL for writing to ADSP-21160M’s low word of internal memory.
In a multiprocessing system, WRL is driven by the bus master.
Memory Write High Strobe. WRH is asserted when ADSP-21160M writes to the high
word of external memory or internal memory of other ADSP-21160Ms. External
devices must assert WRH for writing to ADSP-21160M’s high word of internal
memory. In a multiprocessing system, WRH is driven by the bus master.
DRAM Page Boundary. The ADSP-21160M asserts this pin to signal that an external
DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160M’s memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160M with ID2–0 = 00x).
REV. 0
–9–
ADSP-21160M
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
IRQ2–0
I/A
FLAG3–0
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
REDY
I/A
O (O/D)
DMAR1
I/A
DMAR2
I/A
ID2–0
I
DMAG1
O/T
Sequential Burst Access. BRST is asserted by ADSP-21160M or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160M, ADSP-21160M automatically increments the
address as long as BRST is asserted. BRST is asserted after the initial access of a burst
transfer. It is asserted for every cycle after that, except for the last data request cycle
(denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160M
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory. A keeper latch on the DSP’s ACK pin maintains the input at the level it was
last driven (only enabled on the ADSP-21160M with ID2–0 = 00x).
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the
following cycle. If the ADSP-21160M attempts to access external memory while SBTS
is asserted, the processor will halt and the memory access will not be completed until
SBTS is deasserted. SBTS should only be used to recover from host processor and/or
ADSP-21160M deadlock or used with a DRAM controller.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four CLKIN cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160M’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-21160M that is bus master will relinquish the bus and assert HBG. To relinquish
the bus, the ADSP-21160M places the address, data, select, and strobe lines in a high
impedance state. HBR has priority over all ADSP-21160M bus requests (BR6–1) in a
multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor
may take control of the external bus. HBG is asserted (held low) by the ADSP-21160M
until HBR is released. In a multiprocessing system, HBG is output by the
ADSP-21160M bus master and is monitored by all others.
Chip Select. Asserted by host processor to select the ADSP-21160M.
Host Bus Acknowledge. The ADSP-21160M deasserts REDY (low) to add waitstates
to a host access when CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA
services.
Multiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used
by ADSP-21160M. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and
so on. Use ID = 000 or ID = 001 in single-processor systems. These lines are a system
configuration selection which should be hardwired or only changed at reset.
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21160M to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
–10–
REV. 0
ADSP-21160M
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
DMAG2
O/T
BR6–1
I/O/S
RPBA
I/S
PA
I/O/T
DTx
DRx
TCLKx
O
I
I/O
RCLKx
TFSx
RFSx
LxDAT7–0
I/O
I/O
I/O
I/O
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
BMS
I/O/T
CLKIN
I
CLK_CFG3–0
I
CLKOUT
O/T
RESET
I/A
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160M to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ms to arbitrate
for bus mastership. An ADSP-21160M only drives its own BRx line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ms, the unused BRx pins should be pulled high; the
processor’s own BRx line must not be pulled high or low because it is an output.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160M. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160M.
Priority Access. Asserting its PA pin allows an ADSP-21160M bus slave to interrupt
background DMA transfers and gain access to the external bus. PA is connected to all
ADSP-21160Ms in the system. If access priority is not required in a system, the PA pin
should be left unconnected.
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal
pull-up resistor.
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
Transmit Frame Sync (Serial Ports 0, 1).
Receive Frame Sync (Serial Ports 0, 1).
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal
pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.
EPROM Boot Select. For a description of how this pin operates, see Table 3. This
signal is a system configuration selection that should be hardwired.
Link Boot. For a description of how this pin operates, see Table 3. This signal is a
system configuration selection that should be hardwired.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see Table 3. This input is a system configuration selection that should
be hardwired.
Local Clock In. CLKIN is the ADSP-21160M clock input. The ADSP-21160M
external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple
of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
Core/CLKIN Ratio Control. ADSP-21160M core clock (instruction cycle) rate is equal
to n ⴛ CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the RESET & CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
Local Clock Out. CLKOUT is driven at the CLKIN frequency by the current bus
master. This output is three-stated when the ADSP-21160M is not the bus master, or
when the host controls the bus (HBG asserted). A keeper latch on the DSP’s CLKOUT
pin maintains the output at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
Processor Reset. Resets the ADSP-21160M to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET input must be asserted (low) at power-up.
REV. 0
–11–
ADSP-21160M
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
CIF
O/T
VDDINT
P
VDDEXT
AVDD
P
P
AGND
GND
NC
G
G
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21160M. TRST has a
20 kΩ internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160M emulator target board
connector only. EMU has a 50 kΩ internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master.
Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor
(40 pins).
I/O Power Supply. Nominally 3.3 V dc (46 pins).
Analog Power Supply. Nominally 2.5 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as VDDINT, except that added filtering
circuitry is required. For more information, see Power Supplies on page 6.
Analog Power Supply Return.
Power Supply Return. (83 pins)
Do Not Connect. Reserved pins that must be left open and unconnected (5 pins).
Table 3. Boot Mode Selection
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
–12–
REV. 0
ADSP-21160M
ADSP-21160M SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
1
Signal
K Grade Parameter1
Min
Max
Unit
VDDINT
AVDD
VDDEXT
VIH1
VIH2
VIL
TCASE
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
High Level Input Voltage2, @ VDDEXT =Max
High Level Input Voltage3, @ VDDEXT =Max
Low Level Input Voltage2,3, @ VDDEXT =Min
Case Operating Temperature4
2.37
2.37
3.13
2.2
2.3
–0.5
0
2.63
2.63
3.47
VDDEXT +0.5
VDDEXT +0.5
0.8
85
V
V
V
V
V
V
ºC
Specifications subject to change without notice.
2
Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,
ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.
3
Applies to input pins: CLKIN, RESET, TRST.
4
See Environmental Conditions on page 45 for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter1
VOH
VOL
IIH
IIL
IILPU1
IILPU2
IOZH
IOZL
IOZHPD
IOZLPU1
IOZLPU2
IOZHA
IOZLA
IDD-INPEAK
IDD-INHIGH
IDD-INLOW
IDD-IDLE
AIDD
CIN
1
Test Conditions
2
High Level Output Voltage
Low Level Output Voltage2
High Level Input Current4,5,6
Low Level Input Current4
Low Level Input Current
Pull-Up15
Low Level Input Current
Pull-Up26
Three-State Leakage Current7,8,9,10
Three-State Leakage Current7
Three-State Leakage Current
Pull-Down10
Three-State Leakage Current
Pull-Up18
Three-State Leakage Current
Pull-Up29
Three-State Leakage Current11
Three-State Leakage Current11
Supply Current (Internal)12
Supply Current (Internal)13
Supply Current (Internal)14
Supply Current (Idle)15
Supply Current (Analog)16
Input Capacitance17,18
Min
Max
Unit
0.4
10
10
250
V
V
µA
µA
µA
@ VDDEXT =Max, VIN =0 V
500
µA
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =VDD Max
10
10
250
µA
µA
µA
@ VDDEXT =Max, VIN =0 V
250
µA
@ VDDEXT =Max, VIN =0 V
500
µA
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
tCCLK =12.5 ns, VDDINT =Max
@AVDD =Max
fIN =1 MHz, TCASE =25°C, VIN =2.5 V
25
4
1400
875
625
80
10
4.7
µA
mA
mA
mA
mA
mA
mA
pF
3
@ VDDEXT =Min, IOH =–2.0 mA
@ VDDEXT =Min, IOL =4.0 mA3
@ VDDEXT =Max, VIN =VDD Max
@ VDDEXT =Max, VIN =0 V
@ VDDEXT =Max, VIN =0 V
2.4
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,
DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK,
BMS, TDO, EMU.
3
See Output Drive Currents on page 42 for typical drive current capabilities.
4
Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK, CLK_CFG3-0.
REV. 0
–13–
ADSP-21160M
5
Applies to input pins with internal pull-ups: DR0, DR1.
6
Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.
7
Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO.
8
Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.
9
Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.
10
Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.
11
Applies to ACK pulled up internally with 2 kΩ during reset or ID2–0 = 00x.
12
The test program used to measure IDD-INPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual
internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page 42.
13
IDDINHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on page 42.
14
IDDINLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on page 42.
15
Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on page 42.
16
Characterized, but not tested.
17
Applies to all signal pins.
18
Guaranteed, but not tested.
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 . . .–0.3 V to +3.0 V
Analog (PLL) Supply Voltage (AVDD) . . . . .–0.3 V to +3.0 V
External (I/O) Supply Voltage (VDDEXT) . . . .–0.3 V to +4.6 V
Input Voltage. . . . . . . . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Output Voltage Swing . . . . . . . . . . . –0.5 V to VDDEXT +0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Storage Temperature Range . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . 185ºC
1
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION:
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160M features proprietary ESD protection
circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
–14–
REV. 0
ADSP-21160M
Timing Specifications
The ADSP-21160M’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160M’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN frequency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:
• tCCLK = (tCK) / CR
• tLCLK = (tCCLK) ⴛ LR
• tSCLK = (tCCLK) ⴛ SR
Where:
•
•
•
•
•
•
•
LCLK = Link Port Clock
SCLK = Serial Port Clock
tCK = CLKIN Clock Period
tCCLK = (Processor) Core Clock Period
tLCLK = Link Port Clock Period
tSCLK = Serial Port Clock Period
CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
• LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
• SR = Serial Port/Core Clock Ratio (wide range,
determined by ⴛCLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaningful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive
longer times.
See Figure 32 under Test Conditions for voltage reference
levels.
REV. 0
–15–
ADSP-21160M
Clock Input
Table 4. Clock Input
80 MHz
Parameter
Timing Requirements:
CLKIN Period
tCK
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
CLKIN Rise/Fall (0.4V–2.0V)
Min
Max
25
10.5
10.5
80
40
40
3
Unit
ns
ns
ns
ns
, , !
, Figure 10. Clock Input
Reset
Table 5. Reset
Parameter
Min
Timing Requirements:
RESET Pulsewidth Low1
tWRST
tSRST
RESET Setup Before CLKIN High2
4tCK
8
Max
Unit
ns
ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
after reset.
,( , Figure 11. Reset
–16–
REV. 0
ADSP-21160M
Interrupts
Table 6. Interrupts
1
2
Parameter
Min
Timing Requirements:
IRQ2–0 Setup Before CLKIN High1
tSIR
tHIR
IRQ2–0 Hold After CLKIN High1
tIPW
IRQ2–0 Pulsewidth2
6
0
2+tCK
Max
Unit
ns
ns
ns
Only required for IRQx recognition in the following cycle.
Applies only if tSIR and tHIR requirements are not met.
, , !
% $
, (
Figure 12. Interrupts
Timer
Table 7. Timer
Parameter
Min
Max
Unit
Switching Characteristic:
CLKIN High to TIMEXP
tDTEX
1
7
ns
, , Figure 13. Timer
REV. 0
–17–
ADSP-21160M
Flags
Table 8. Flags
Parameter
Min
Timing Requirements:
FLAG3–0 IN Setup Before CLKIN High1
tSFI
tHFI
FLAG3–0 IN Hold After CLKIN High1
tDWRFI
FLAG3–0 IN Delay After RDx/WRx Low1
tHFIWR
FLAG3–0 IN Hold After RDx/WRx Deasserted1
Switching Characteristics:
FLAG3–0 OUT Delay After CLKIN High
tDFO
FLAG3–0 OUT Hold After CLKIN High
tHFO
tDFOE
CLKIN High to FLAG3–0 OUT Enable
tDFOD
CLKIN High to FLAG3–0 OUT Disable
1
Max
4
1
Unit
ns
ns
ns
ns
12
0
9
ns
ns
ns
ns
1
1
5
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
, " , " , " , " , !" " $ #
" # #
, "
, ! "
" $ , ( " , !" ( @
( " #
Figure 14. Flags
–18–
REV. 0
ADSP-21160M
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 9. Memory Read—Bus Master
Parameter
Min
Max
Unit
Timing Requirements:
Address, CIF, Selects Delay to Data
tCK – 0.25tCCLK – 11+W
tDAD
Valid1,2
RDx Low to Data Valid1,3
0.75tCK – 11+W
tDRLD
tHDA
Data Hold from Address, Selects4
0
tSDS
Data Setup to RDx High1
8
tHDRH
Data Hold from RDx High3,4
1
tDAAK
ACK Delay from Address, Selects2,5
tCK – 0.5tCCLK – 12+W
ACK Delay from RDx Low3,5
tCK – 0.75tCCLK – 11+W
tDSAK
tSAKC
ACK Setup to CLKIN3,5
0.5tCCLK +3
tHAKC
ACK Hold After CLKIN3
1
Switching Characteristics:
Address, CIF, Selects Hold After RDx
0.25tCCLK – 1+H
tDRHA
High3
tDARL
Address, CIF, Selects to RDx Low2
0.25tCCLK – 3
tRW
RDx Pulse width3
tCK – 0.5tCCLK – 1+W
RDx High to WRx, RDx, DMAGx Low3 0.5tCCLK – 1+HI
tRWR
W = (number of wait states specified in WAIT register) ⴛ tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, BMS is referenced.
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page 44 for the calculation of
hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet tDAAK, tDSAK, or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2
@"
, , ! , (
, , , , ! !
, , ( , , , ! ( @
Figure 15. Memory Read—Bus Master
REV. 0
, ! –19–
ADSP-21160M
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 10. Memory Write—Bus Master
Parameter
Min
Max
Timing Requirements:
ACK Delay from Address, Selects1,2
tCK – 0.5tCCLK–12+W
tDAAK
tDSAK
ACK Delay from WRx Low1,3
tCK – 0.75tCCLK – 11+W
ACK Setup to CLKIN1,3
0.5tCCLK +3
tSAKC
tHAKC
ACK Hold After CLKIN1,3
1
Switching Characteristics:
Address, CIF, Selects to WRx
tCK – 0.25tCCLK – 3+W
tDAWH
Deasserted2,3
tDAWL
Address, CIF, Selects to WRx Low2
0.25tCCLK – 3
tWW
WRx Pulse width3
tCK – 0.5tCCLK – 1+W
Data Setup before WRx High3
tCK – 0.25tCCLK – 12.5+W
tDDWH
tDWHA
Address Hold after WRx Deasserted3
0.25tCCLK – 1+H
tDWHD
Data Hold after WRx Deasserted3
0.25tCCLK – 1+H
tDATRWH
Data Disable after WRx Deasserted3,4
0.25tCCLK – 2+H
0.25tCCLK+2+H
tWWR
WRx High to WRx, RDx, DMAGx
0.5tCCLK – 1+HI
Low3
tDDWR
Data Disable before WRx or RDx Low 0.25tCCLK – 1+I
tWDE
WRx Low to Data Enabled
–0.25tCCLK – 1
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
The falling edge of MSx, BMS is referenced.
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4
See Example System Hold Time Calculation on page 44 for calculation of hold times given capacitive and dc loads.
2
–20–
REV. 0
ADSP-21160M
@ @
"
, ( !
, ( , ( ! ,( (
( , ( , ( !
, ( !
, , ( ! , , , ! @
Figure 16. Memory Write—Bus Master
REV. 0
–21–
,( ( , ( ADSP-21160M
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for
accessing a slave ADSP-21160M (in multiprocessor
memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and
writes except where noted (see Memory Read—Bus Master
on page 19 and Memory Write—Bus Master on page 20).
When accessing a slave ADSP-21160M, these switching
characteristics must meet the slave’s timing requirements
for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on page 24). The slave
ADSP-21160M must also meet these (bus master) timing
requirements for data and acknowledge setup and hold
times.
Table 11. Synchronous Read/Write—Bus Master
Parameter
Min
Timing Requirements:
Data Setup Before CLKIN1
tSSDATI
tHSDATI
Data Hold After CLKIN1
tSACKC
ACK Setup Before CLKIN1
tHACKC
ACK Hold After CLKIN1
Switching Characteristics:
tDADDO
Address, MSx, BMS, BRST, CIF Delay After CLKIN
tHADDO
Address, MSx, BMS, BRST, CIF Hold After CLKIN
tDPGO
PAGE Delay After CLKIN
tDRDO
RDx High Delay After CLKIN1
tDWRO
WRx High Delay After CLKIN1
tDRWL
RDx/WRx Low Delay After CLKIN
tDDATO
Data Delay After CLKIN
tHDATO
Data Hold After CLKIN
tDACKMO
ACK Delay After CLKIN2
tACKMTR
ACK Disable Before CLKIN2
tDCKOO
CLKOUT Delay After CLKIN
tCKOP
CLKOUT Period
CLKOUT Width High
tCKWH
tCKWL
CLKOUT Width Low
Max
5.5
1
0.5tCCLK +3
1
ns
ns
ns
ns
10
1.5
1.5
0.25tCCLK – 1
0.25tCCLK – 1
0.25tCCLK – 1
1.5
0.25tCCLK +3
0.25tCCLK – 3
2
tCK – 1
tCK/2 – 2
tCK/2 – 2
Unit
11
0.25tCCLK+9
0.25tCCLK +9
0.25tCCLK +9
12.5
0.25tCCLK +9
5
tCK3 +1
tCK/2+23
tCK/2+23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.
Applies to broadcast write, master precharge of ACK.
3
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.
2
–22–
REV. 0
ADSP-21160M
, , ( !
, , ( # , , ! @ @
"
, , ! , , , # , ( , , , ! ( , ( , ( (
, ! , # Figure 17. Synchronous Read/Write—Bus Master
REV. 0
–23–
ADSP-21160M
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21160M bus master
accesses of a slave’s IOP registers or internal memory (in
multiprocessor memory space). The bus master must meet
these (bus slave) timing requirements.
Table 12. Synchronous Read/Write—Bus Slave
Parameter
Min
Timing Requirements:
Address, BRST Setup Before CLKIN
tSADDI
tHADDI
Address, BRST Hold After CLKIN
RDx/WRx Setup Before CLKIN
tSRWI
tHRWI
RDx/WRx Hold After CLKIN
tSSDATI
Data Setup Before CLKIN
tHSDATI
Data Hold After CLKIN
Switching Characteristics:
Data Delay After CLKIN
tDDATO
tHDATO
Data Hold After CLKIN
tDACKC
ACK Delay After CLKIN
ACK Hold After CLKIN
tHACKO
Max
5
1
5
1
5.5
1
ns
ns
ns
ns
ns
ns
12.5
1.5
10
1.5
–24–
Unit
ns
ns
ns
ns
REV. 0
ADSP-21160M
, , ! , ! , , ( , ! ( , ! , # ( , ! ( , ( (
, Figure 18. Synchronous Read/Write—Bus Slave
REV. 0
–25–
, ! ADSP-21160M
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership
between multiprocessing ADSP-21160Ms (BRx) or a host
processor (HBR, HBG).
Table 13. Multiprocessor Bus Request and Host Bus Request
Parameter
Min
Timing Requirements:
HBG Low to RDx/WRx/CS Valid
tHBGRCSV
HBR Setup Before CLKIN1
tSHBRI
tHHBRI
HBR Hold After CLKIN1
tSHBGI
HBG Setup Before CLK/=’]IN
tHHBGI
HBG Hold After CLKIN High
tSBRI
BRx, PA Setup Before CLKIN
tHBRI
BRx, PA Hold After CLKIN High
tSPAI
PA Setup Before CLKIN
tHPAI
PA Hold After CLKIN High
tSRPBAI
RPBA Setup Before CLKIN
tHRPBAI
RPBA Hold After CLKIN
Switching Characteristics:
tDHBGO
HBG Delay After CLKIN
tHHBGO
HBG Hold After CLKIN
tDBRO
BRx Delay After CLKIN
tHBRO
BRx Hold After CLKIN
tDPASO
PA Delay After CLKIN, Slave
tTRPAS
PA Disable After CLKIN, Slave
tDPAMO
PA Delay After CLKIN, Master
tPATR
PA Disable Before CLKIN, Master
tDRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low2
REDY (O/D) Disable or REDY (A/D) High from HBG2
tTRDYHG
tARDYTR
REDY (A/D) Disable from CS or HBR High2
Max
Unit
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
1
6
1
9
1
9
1
6
2
2
8
1.5
8
1.5
0.25tCCLK +9
0.25tCCLK – 5
0.5tCK
tCK +25
11
1
Only required for recognition in the current cycle.
2
(O/D) = open drain, (A/D) = active drive.
–26–
REV. 0
ADSP-21160M
, ! , ! ! ! , ! , !! ! # , , ! # , , # , , # , ! , !! ! , , ! , , ! , , ! ! , ! , , , ! ! # (
= @ = Figure 19. Multiprocessor Bus Request and Host Bus Request
REV. 0
–27–
ADSP-21160M
is returned by the ADSP-21160M, the host can drive the
RDx and WRx pins to access the ADSP-21160M’s internal
memory or IOP registers. HBR and HBG are assumed low
for this timing
Asynchronous Read/Write—Host to ADSP-21160M
Use these specifications (Table 14 and Table 15) for asynchronous host processor accesses of an ADSP-21160M,
after the host has asserted CS and HBR (low). After HBG
Table 14. Read Cycle
Parameter
Min
Timing Requirements:
Address Setup/CS Low Before RDx Low
tSADRDL
tHADRDH
Address Hold/CS Hold Low After RDx
tWRWH
RDx/WRx High Width
tDRDHRDY
RDx High Delay After REDY (O/D) Disable
RDx High Delay After REDY (A/D) Disable
tDRDHRDY
Switching Characteristics:
Data Valid Before REDY Disable from Low
tSDATRDY
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RDx Low
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read
tHDARWH
Data Disable After RDx High
Max
0
2
5
0
0
Unit
ns
ns
ns
ns
ns
2
10
tCK
2
6
ns
ns
ns
ns
, , ! !
,( ( !
, ! ( !
# , , , ! , Figure 20. Read Cycle (Asynchronous Read—Host to ADSP-21160M)
–28–
REV. 0
ADSP-21160M
Table 15. Write Cycle
Parameter
Min
Timing Requirements:
CS Low Setup Before WRx Low
tSCSWRL
tHCSWRH
CS Low Hold After WRx High
tSADWRH
Address Setup Before WRx High
tHADWRH
Address Hold After WRx High
WRx Low Width
tWWRL
tWRWH
RDx/WRx High Width
tDWRHRDY
WRx High Delay After REDY (O/D) or (A/D) Disable
tSDATWH
Data Setup Before WRx High
tHDATWH
Data Hold After WRx High
Switching Characteristics:
REDY (O/D) or (A/D) Low Delay After WRx/CS Low
tDRDYWRL
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
Max
0
0
6
2
7
5
0
5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
( , ( !
, ( , ! ( !
, ! ( !
, ( ( ,( ( !
( , ! ( !
, ( !
, ( , ( , ( ! = @ = Figure 21. Write Cycle (Asynchronous Write—Host to ADSP-21160M)
REV. 0
–29–
Unit
ns
ns
ADSP-21160M
Three-State Timing—Bus Master and Bus Slave
These specifications show how the memory interface is
disabled (stops driving) or enabled (resumes driving)
relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host
transition cycles (HTC) as well as the SBTS pin.
Table 16. Three-State Timing—Bus Slave, HBR, SBTS
Parameter
Timing Requirements:
tSTSCK
SBTS Setup Before CLKIN
tHTSCK
SBTS Hold After CLKIN
Switching Characteristics:
Address/Select Enable After CLKIN
tMIENA
tMIENS
Strobes Enable After CLKIN1
tMIENHG
HBG Enable After CLKIN
tMITRA
Address/Select Disable After CLKIN
tMITRS
Strobes Disable After CLKIN1
HBG Disable After CLKIN
tMITRHG
tDATEN
Data Enable After CLKIN2
tDATTR
Data Disable After CLKIN2
tACKEN
ACK Enable After CLKIN2
tACKTR
ACK Disable After CLKIN2
tCDCEN
CLKOUT Enable After CLKIN
tCDCTR
CLKOUT Disable After CLKIN
tMTRHBG
Memory Interface Disable Before HBG
Low3
tMENHBG
Memory Interface Enable After HBG
High3
Min
Max
6
1
Unit
ns
ns
1.5
1.5
1.5
0.25tCCLK – 1
0.25tCCLK – 4
3.5
1.5
1.5
1.5
1.5
1.5
tCCLK – 3
tCK – 6
9
9
9
0.25tCCLK +4
0.25tCCLK
8
10
5
9
5
9
tCCLK +1
tCK +2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK – 5
tCK +5
ns
1
Strobes = RDx, WRx, DMAGx.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).
2
–30–
REV. 0
ADSP-21160M
, , ! , @, @, !
, @ , @, !
" , , , , , , # !
, ! , ! " " = @ @( @ @"@! @ @ B Figure 22. Three-State Timing—Bus Slave, HBR, SBTS
REV. 0
–31–
ADSP-21160M
DMA Handshake
These specifications describe the three DMA handshake
modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or
enabling of data externally. For external handshake mode,
the data transfer is controlled by the ADDR31–0, RDx,
WRx, PAGE, MS3–0, ACK, and DMAG signals. For Paced
Master mode, the data transfer is controlled by ADDR31–0,
RDx, WRx, MS3–0, and ACK (not DMAG). For Paced
Master mode, the Memory Read-Bus Master, Memory
Write-Bus Master, and Synchronous Read/Write-Bus
Master timing specifications for ADDR31–0, RDx, WRx,
MS3–0, PAGE, DATA63–0, and ACK also apply.
Table 17. DMA Handshake
Parameter
Min
Max
Timing Requirements:
DMARx Setup Before CLKIN1
3
tSDRC
tWDR
DMARx Width Low (Nonsynchronous)2 tCCLK +4.5
tSDATDGL
Data Setup After DMAGx Low3
0.75tCK – 7
tHDATIDG
Data Hold After DMAGx High
2
tDATDRH
Data Valid After DMARx High3
tCK +10
tDMARLL
DMARx Low Edge to Low Edge4
tCK
tDMARH
DMARx Width High2
tCCLK +4.5
Switching Characteristics:
tDDGL
DMAGx Low Delay After CLKIN
0.25tCCLK +1
0.25tCCLK +9
tWDGH
DMAGx High Width
0.5tCCLK – 1+HI
tWDGL
DMAGx Low Width
tCK – 0.5tCCLK – 1
tHDGC
DMAGx High Delay After CLKIN
tCK – 0.25tCCLK +1.5
tCK – 0.25tCCLK +9
tVDATDGH
Data Valid Before DMAGx High5
tCK – 0.25tCCLK – 8
tCK – 0.25tCCLK +5
tDATRDGH
Data Disable After DMAGx High6
0.25tCCLK – 3
0.25tCCLK +1.5
tDGWRL
WRx Low Before DMAGx Low
–1.5
2
tDGWRH
DMAGx Low Before WRx High
tCK – 0.5tCCLK – 2 +W
tDGWRR
WRx High Before DMAGx High7
–1.5
2
tDGRDL
RDx Low Before DMAGx Low
–1.5
2
tDRDGH
RDx Low Before DMAGx High
tCK – 0.5tCCLK –2+W
RDx High Before DMAGx High7
–1.5
2
tDGRDR
tDGWR
DMAGx High to WRx, RDx, DMAGx
0.5tCCLK – 2+HI
Low
Address/Select Valid to DMAGx High
18
tDADGH
tDDGHA
Address/Select Hold after DMAGx High 1
W = (number of wait states specified in WAIT register) ⴛ tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Only required for recognition in the current cycle.
Maximum throughput using DMARx/DMAGx handshaking equals tWDR + tDMARH = (tCCLK +4.5) + (tCCLK +4.5)=34ns (29.4 MHz). This throughput limit
applies to non-synchronous access mode only.
3
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
the write, the data can be driven tDATDRH after DMARx is brought high.
4
Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
5
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
tVDATDGH = tCK – .25tCCLK – 8 + (n × tCK) where n equals the number of extra cycles that the access is prolonged.
6
See Example System Hold Time Calculation on page 44 for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.
2
–32–
REV. 0
ADSP-21160M
, , , , ( , !
, ! , ,( ,( !
" ( , !
, !
" , !
, , ! " " ( D ! ! , ( , ( !
(
, ( , , , !
, !
D # @ ( # @ ! # ( # " " [email protected] @( @ $ ! B
Figure 23. DMA Handshake Timing
REV. 0
–33–
, !
ADSP-21160M
Link Ports
Calculation of link receiver data setup and hold relative to
link clock is required to determine the maximum allowable
skew that can be introduced in the transmission path
between LDATA and LCLK. Setup skew is the maximum
delay that can be introduced in LDATA relative to LCLK
(setup skew = tLCLKTWH Min – tDLDCH – tSLDCL). Hold skew is the
maximum delay that can be introduced in LCLK relative to
LDATA (hold skew = tLCLKTWL Min – tHLDCH – tHLDCL). Calculations made directly from speed specifications will result in
unrealistically small skew times because they include
multiple tester guardbands.
Table 18. Link Port—Maximum Data Throughput for
Transmit/Receive Pairs (Continued)
Transmit
Link Port
Receive
Link Port
Maximum Operating
Frequency (MHz)
2
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
68.97
71.43
71.43
80
76.92
74.07
64.52
66.67
66.67
71.43
71.43
71.43
64.52
66.67
66.67
74.07
74.07
71.43
62.5
66.67
64.52
71.43
71.43
71.43
3
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Maximum throughput varies across link port transmit/receive pairs. Table 18 shows maximum throughput for
all transmit/receive pairs based on setup skew of 0.5 ns
(setup skew=tLCLKTWH min–tDLDCH –tSLDCL =0.5 ns). Hold skew
results indicate 80 MHz operation across all link ports. All
hold time skews are equal to 0.5 ns or greater for all link
port transmit/receive pairs at 80 MHz. Based upon these
values, all link port transmit/receive pairs can be operated
at maximum throughput for LxCLK:CCLK ratios of 2:1,
3:1, and 4:1 at 80 MHz CCLK. To operate all link port
transmit/receive pairs at LxCLK:CCLK ratio of 1:1, the
core clock frequency must be no greater than 62.5 MHz.
4
5
Maximum data throughput values are based upon the reset
value of the LAR Link Port Assignment Register (Link
Buffer 0 assigned to Link Port 0, Link Buffer 1 assigned to
Link Port 1, etc.). Throughputs are not guaranteed for LAR
settings other than the reset LAR value. For additional
details on LAR, refer to the ADSP-21160 DSP Hardware
Reference manual.
Table 18. Link Port—Maximum Data Throughput for
Transmit/Receive Pairs
Transmit
Link Port
Receive
Link Port
Maximum Operating
Frequency (MHz)
0
0
1
2
3
4
5
0
1
2
3
4
5
71.43
74.07
71.43
80
80
76.92
68.97
71.43
68.97
80
76.92
74.07
1
–34–
REV. 0
ADSP-21160M
Table 19. Link Ports—Receive
Parameter
Min
Timing Requirements:
Data Setup Before LCLK Low
tSLDCL
tHLDCL
Data Hold After LCLK Low
tLCLKIW
LCLK Period
tLCLKRWL
LCLK Width Low
LCLK Width High
tLCLKRWH
Switching Characteristics:
LACK Low Delay After LCLK High1
tDLALC
1
Max
2.5
2.5
tLCLK
6.0
6.0
ns
ns
ns
ns
ns
12
17
LACK goes low with tDLALC relative to rise of LCLK after first nibble, but doesn’t go low if the receiver’s link buffer is not about to fill.
, (
, ( !
, ( , ! , 'E
, # Figure 24. Link Ports—Receive
REV. 0
–35–
Unit
ns
ADSP-21160M
Table 20. Link Ports—Transmit
Parameter
Min
Timing Requirements:
LACK Setup Before LCLK High
tSLACH
tHLACH
LACK Hold After LCLK High
Switching Characteristics:
Data Delay After LCLK High
tDLDCH
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low
LCLK Width High
tLCLKTWH
tDLACLK
LCLK Low Delay After LACK High
Max
Unit
14
–2
ns
ns
6.0
–2
0.5tLCLK – 1.5
0.5tLCLK – 1.5
0.5tLCLK +5
0.5tLCLK +1.5
0.5tLCLK +1.5
3tLCLK +11
ns
ns
ns
ns
ns
, ( !
, ( " ! !
, !
, ! !
'E
#
, !
, ! !
, ! , ! % # ! " " ! " B
Figure 25. Link Ports—Transmit
–36–
REV. 0
ADSP-21160M
Serial Ports
To determine whether communication is possible between
two devices at clock speed n, the following specifications
must be confirmed: 1) frame sync delay and frame sync
setup and hold, 2) data delay and data setup and hold, and
3) SCLK width.
Table 21. Serial Ports—External Clock
1
2
Parameter
Min
Timing Requirements:
TFS/RFS Setup Before TCLK/RCLK1
tSFSE
tHFSE
TFS/RFS Hold After TCLK/RCLK1,2
tSDRE
Receive Data Setup Before RCLK1
tHDRE
Receive Data Hold After RCLK1
tSCLKW
TCLK/RCLK Width
tSCLK
TCLK/RCLK Period
3.5
4
1.5
4
14
2tCCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 22. Serial Ports—Internal Clock
1
2
Parameter
Min
Timing Requirements:
TFS Setup Before TCLK1; RFS Setup Before RCLK1
tSFSI
TFS/RFS Hold After TCLK/RCLK1,2
tHFSI
tSDRI
Receive Data Setup Before RCLK1
tHDRI
Receive Data Hold After RCLK1
8
1
6.5
3
Max
Unit
ns
ns
ns
ns
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 23. Serial Ports—External or Internal Clock
1
Parameter
Min
Switching Characteristics:
RFS Delay After RCLK (Internally Generated RFS)1
tDFSE
tHOFSE
RFS Hold After RCLK (Internally Generated RFS)1
3
Max
Unit
13
ns
ns
Max
Unit
13
ns
ns
ns
ns
Referenced to drive edge.
Table 24. Serial Ports—External Clock
1
Parameter
Min
Switching Characteristics:
TFS Delay After TCLK (Internally Generated TFS)1
tDFSE
tHOFSE
TFS Hold After TCLK (Internally Generated TFS)1
tDDTE
Transmit Data Delay After TCLK1
tHDTE
Transmit Data Hold After TCLK1
3
16
0
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter
Min
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally Generated TFS)1
tHOFSI
TFS Hold After TCLK (Internally Generated TFS)1
–1.5
REV. 0
–37–
Max
Unit
4.5
ns
ns
ADSP-21160M
Table 25. Serial Ports—Internal Clock (Continued)
Parameter
tDDTI
tHDTI
tSCLKIW
1
Min
1
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK1
TCLK/RCLK Width
Max
Unit
7.5
0
0.5tSCLK – 2.5
0.5tSCLK +2
ns
ns
ns
Min
Max
Unit
Referenced to drive edge.
Table 26. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics:
Data Enable from External TCLK1
tDDTEN
tDDTTE
Data Disable from External TCLK1
tDDTIN
Data Enable from Internal TCLK1
tDDTTI
Data Disable from Internal TCLK1
1
4
10
0
3
ns
ns
ns
ns
Referenced to drive edge.
–38–
REV. 0
ADSP-21160M
F F , (
, (
, " , " , " , ! " , ! " , !" " , " , ! " , , ! " , ! , E ! ! " " @ # ! B
F F , (
, (
, " , " , ! " , " , !" , ! " "
, " "
, , , ! , ! E ! ! " " @ # ! B
, , , , Figure 26. Serial Ports
REV. 0
–39–
, ! " ADSP-21160M
Table 27. Serial Ports—External Late Frame Sync
Parameter
Min
Switching Characteristics:
Data Delay from Late External TFS or External RFS with
tDDTLFSE
MCE = 1, MFD = 01
tDDTENFS
Data Enable from late FS or MCE = 1, MFD = 01
1
1.0
Max
Unit
13
ns
ns
MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.
" ( ! = @ " = , " , ! " " , , " , !
, " "
, " , ! " "
, " , , ! , " Figure 27. External Late Frame Sync
–40–
REV. 0
ADSP-21160M
JTAG Test Access Port and Emulation
Table 28. JTAG Test Access Port and Emulation
Parameter
Min
Timing Requirements:
TCK Period
tTCK
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
tHSYS
tTRSTW
TRST Pulsewidth
Switching Characteristics:
TDO Delay from TCK Low
tDTDO
tDSYS
System Outputs Delay After TCK Low2
Max
tCK
5
6
7
18
4tCK
Unit
ns
ns
ns
ns
ns
ns
13
30
1
ns
ns
System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,
PA, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN,
RESET.
2
System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,
FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.
, , , ! , , # , # # Figure 28. IEEE 11499.1 JTAG Test Access Port
REV. 0
–41–
, ! ADSP-21160M
Output Drive Currents
Figure 29 shows typical I–V characteristics for the output drivers of the ADSP-21160M. The curves represent the current
drive capability of the output drivers as a function of output voltage.
# #$1 =B
' @G
)
[email protected] *G
=B @)*G $
$
=B
' @G
$
[email protected] *G
$)
=B @)*G
$ $ B*
B*
B*
# $
B*
Figure 29. ADSP-21160M Typical Drive Currents
Power Dissipation
Total power dissipation has two components, one due to internal circuitry and one due to the switching of external output
drivers.
Internal power dissipation is dependent on the instruction execution sequence and the data operands involved. Using the
current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from Electrical Characteristics on page 13 and the current-versus-operation information in Table 29, engineers can estimate the ADSP-21160M’s internal power supply (VDDINT) input
current for a specific application, according to the following formula:
% Peak × IDDINPEAK
% High × I DDINHIGH
% Low × I DDINLOW
+ % Idle × I DDIDLE
-------------------------------------------------I DDINT
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on:
•
•
•
•
the number of output pins that switch during each cycle (O)
the maximum frequency at which they can switch (f)
their load capacitance (C)
their voltage swing (VDD)
and is calculated by:
PEXT = O × C × VDD2 × f
–42–
REV. 0
ADSP-21160M
The load capacitance should include the processor’s
package capacitance (CIN). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2tCK). The write strobe can switch every cycle at a
frequency of 1/tCK. Select pins switch at 1/(2tCK), but selects
can switch on each cycle.
Table 29. ADSP-21160M Operation Types vs. Input Current
Operation
Peak Activity1
High Activity1
Low Activity1
Instruction Type
Instruction Fetch
Core Memory Access2
Multifunction
Cache
2 per tCK cycle
(DMⴛ64 and PMⴛ64)
1 per 2 tCCLK cycles
1 per external port cycle (ⴛ64)
Worst case
Multifunction
Internal Memory
1 per tCK cycle
(DMⴛ64)
1 per 2 tCCLK cycles
1 per external port cycle (ⴛ64)
Random
Single Function
Internal Memory
None
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
1
None
None
N/A
Peak Activity=IDDINPEAK, High Activity=IDDINHIGH, and Low Activity=IDDINLOW. The state of the PEYEN bit (SIMD versus SISD mode) does not influence
these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on page 15.
REV. 0
–43–
ADSP-21160M
• External data memory writes occur every other cycle, a
rate of 1/(4 tCK), with 50% of the pins switching
• The bus cycle time is 40 MHz (tCK = 25 ns).
Example: Estimate PEXT with the following assumptions:
• A system with one bank of external data memory—asynchronous RAM (64-bit)
• Four 64K × 16 RAM chips are used, each with a load of
10 pF
The PEXT equation is calculated for each class of pins that
can drive:
Table 30. External Power Calculations (3.3 V Device)
Pin Type
# of Pins
% Switching
×C
×f
× VDD2
= PEXT
Address
MS0
WRx
Data
CLKOUT
15
1
2
64
1
50
0
–
50
–
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
× 12.5 MHz
× 12.5 MHz
× 25 MHz
× 12.5 MHz
× 25 MHz
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
= 0.046 W
= 0.000 W
= 0.024 W
= 0.064 W
= 0.001 W
PEXT = 0.135 W
A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:
PTOTAL = PEXT + PINT + PPLL
Where:
• PEXT is from Table 30
• PINT is IDDINT × 2.5V, using the calculation IDDINT listed in
Power Dissipation on page 42
• PPLL is AIDD × 2.5V, using the value for AIDD listed in
ABSOLUTE MAXIMUM RATINGS on page 14
Note that the conditions causing a worst-case PEXT are
different from those causing a worst-case PINT. Maximum
PINT cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in
ADSP-21160M specifications on page 13 include output
disable time, output enable time, and capacitive loading.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time tENA is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(Figure 30). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate tDECAY using the equation given above.
Choose –V to be the difference between the
ADSP-21160M’s output voltage and the input threshold for
the device requiring the hold time. A typical –V will be 0.4 V.
CL is the total bus capacitance (per data line), and IL is the
total leakage or three-state current (per data line). The hold
time will be tDECAY plus the minimum disable time (i.e.,
tDATRWH for the write cycle).
Output Disable Time
RE F E R E NCE
S IG NA L
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by –V is dependent on the capacitive load, CL and the load current, IL. This decay time can
be approximated by the following equation:
tDECAY = (CL∆V)/IL
The output disable time tDIS is the difference between
tMEASURED and tDECAY as shown in Figure 30. The time tMEASURED
is the interval from when the reference signal switches to
when the output voltage decays –V from the measured
output high or output low voltage. tDECAY is calculated with
test loads CL and IL, and with –V equal to 0.5 V.
t MEASURED
t ENA
t DIS
V OH (MEASURED)
V OH (MEASURED) – D V
2.0V
V OL (MEASURED) + D V
1.0V
V OL (MEASURED)
t DECAY
O UT P UT S T O PS
DR IV IN G
O UT P UT S T AR T S
DR IV IN G
HIG H -IM P E D AN CE S T AT E .
T E S T CO ND ITIO N S CA US E T HIS V O L T AG E
T O BE A PP R O X IM A TE L Y 1.5V
Figure 30. Output Enable/Disable
–44–
REV. 0
ADSP-21160M
*B
# #
" $ +8
B
B*
*4"
!
B*
=B)AHB
*B
" B
=B'
HB*
*B
Figure 31. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
# # #
B
*
*
$4"
*
Figure 34. Typical Output Rise Time (10%–90%,
VDDEXT = Min) vs. Load Capacitance
B*
B
## ! $ +8
Figure 32. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive
loads: 50 pF on all pins (see Figure 31). The delay and hold
specifications given should be derated by a factor of
1.5 ns/50 pF for loads other than the nominal value of
50 pF. Figure 33 and Figure 34 show how output rise time
varies with capacitance. Figure 35 graphically shows how
output delays and holds vary with load capacitance. (Note
that this graph or derating does not apply to output disable
delays; see Output Disable Time on page 44.) The graphs
of Figure 33, Figure 34, and Figure 35 may not be linear
outside the ranges shown.
*B
B
=B)**$B)'
*B
B
$*B
*
*
$4"
*
Figure 35. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
B
Environmental Conditions
The ADSP-21160M is tested for performance over the
commercial temperature range, 0°C to 85°C.
" $ +8
*B
B
Thermal Characteristics
=B))'HB)
*B
"
B
=B'')HBAA
*B
B
*
*
$4"
*
The ADSP-21160M is packaged in a 400-ball Plastic Ball
Grid Array (PBGA). The ADSP-21160M is specified for a
case temperature (TCASE). To ensure that the TCASE data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. Use the center block of ground pins
(PBGA balls: H8–13, J8–13, K8–13, L8–13, M8–13, and
N8–13) to provide thermal pathways to the printed circuit
board’s ground plane. A heatsink should be attached to the
ground plane (as close as possible to the thermal pathways)
with a thermal adhesive.
Figure 33. Typical Output Rise Time (10%–90%,
VDDEXT = Max) vs. Load Capacitance
REV. 0
–45–
ADSP-21160M
T CASE = T AMB + ( PD × θ CA )
• TCASE = Case temperature (measured on top surface
of package)
• PD = Power dissipation in W (this value depends upon
the specific application; a method for calculating PD is
shown under Power Dissipation).
• θCA = Value from Table 31.
• θ JB= 6.46°C/W
Table 31. Airflow Over Package Versus θCA
Airflow (Linear Ft./Min.)
θCA (°C/W)1
1
θJC = 3.6 °C/W.
0
12.13
200
9.86
400
8.7
400-BALL METRIC PBGA PIN CONFIGURATIONS
Table 32 lists the pin assignments for the PBGA package,
and the pin configurations diagram on page 51 shows the
pin assignment summary.
–46–
REV. 0
ADSP-21160M
Table 32. 400-ball Metric PBGA Pin Assignments
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
DATA[14]
DATA[13]
DATA[10]
DATA[8]
DATA[4]
DATA[2]
TDI
TRST
RESET
RPBA
IRQ0
FLAG1
TIMEXP
VDDEXT
NC
TFS1
RFS1
RCLK0
DT0
L0DAT[4]
DATA[30]
DATA[29]
DATA[23]
DATA[21]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
GND
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L1DAT[6]
L1DAT[5]
L1ACK
L1DAT[1]
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
DATA[22]
DATA[16]
DATA[15]
DATA[9]
DATA[6]
DATA[3]
DATA[0]
TCK
EMU
IRQ2
FLAG3
FLAG0
VDDEXT
NC
DT1
RCLK1
RFS0
TCLK0
L0DAT[5]
L0DAT[2]
DATA[34]
DATA[33]
DATA[27]
DATA[26]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L1DAT[4]
L1DAT[3]
L1DAT[0]
L2DAT[7]
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
DATA[24]
DATA[18]
DATA[17]
DATA[11]
DATA[7]
DATA[5]
DATA[1]
TMS
TD0
IRQ1
FLAG2
VDDEXT
NC
TCLK1
DR1
DR0
L0DAT[7]
L0DAT[6]
L0ACK
L0DAT[0]
DATA[38]
DATA[35]
DATA[32]
DATA[31]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L1DAT[2]
L2DAT[6]
L2DAT[4]
L2CLK
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
DATA[28]
DATA[25]
DATA[20]
DATA[19]
DATA[12]
VDDEXT
VDDINT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDEXT
TFS0
L1DAT[7]
L0CLK
L0DAT[3]
L0DAT[1]
L1CLK
DATA[40]
DATA[39]
DATA[37]
DATA[36]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[5]
L2ACK
L2DAT[3]
L2DAT[1]
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
REV. 0
–47–
ADSP-21160M
Table 32. 400-ball Metric PBGA Pin Assignments (Continued)
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
DATA[44]
DATA[43]
DATA[42]
DATA[41]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L2DAT[2]
L2DAT[0]
HBG
HBR
NC
NC
DATA[48]
DATA[51]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[5]
L3DAT[6]
L3DAT[4]
L3CLK
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
CLK_CFG_0
DATA[46]
DATA[45]
DATA[47]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
BR6
BR5
BR4
BR3
DATA[49]
DATA[50]
DATA[52]
DATA[55]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
L3DAT[2]
L3DAT[1]
L3DAT[3]
L3ACK
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
CLKIN
CLK_CFG_1
AGND
CLK_CFG_2
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
BR2
BR1
ACK
REDY
DATA[53]
DATA[54]
DATA[57]
DATA[60]
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
L4DAT[5]
L4DAT[6]
L4DAT[7]
L3DAT[0]
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
AVDD
CLK_CFG_3
CLKOUT
GND
VDDEXT
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
PAGE
SBTS
PA
L3DAT[7]
DATA[56]
DATA[58]
DATA[59]
DATA[63]
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDEXT
L4DAT[3]
L4ACK
L4CLK
L4DAT[4]
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
–48–
REV. 0
ADSP-21160M
Table 32. 400-ball Metric PBGA Pin Assignments (Continued)
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
Pin Name
PBGA Pin#
DATA[61]
DATA[62]
ADDR[3]
ADDR[2]
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
L5DAT[7]
L4DAT[0]
L4DAT[1]
L4DAT[2]
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
ADDR[4]
ADDR[6]
ADDR[7]
ADDR[10]
ADDR[14]
ADDR[18]
ADDR[22]
ADDR[25]
ADDR[28]
ID0
ADDR[1]
MS1
CS
RDL
DMAR2
L5DAT[0]
L5DAT[2]
L5ACK
L5DAT[4]
L5DAT[6]
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
ADDR[5]
ADDR[9]
ADDR[12]
ADDR[15]
ADDR[17]
ADDR[20]
ADDR[23]
ADDR[26]
ADDR[29]
ID1
ADDR[0]
BMS
MS2
CIF
RDH
DMAG2
LBOOT
L5DAT[1]
L5DAT[3]
L5DAT[5]
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
ADDR[8]
ADDR[11]
ADDR[13]
ADDR[16]
ADDR[19]
ADDR[21]
ADDR[24]
ADDR[27]
ADDR[30]
ADDR[31]
ID2
BRST
MS0
MS3
WRH
WRL
DMAG1
DMAR1
EBOOT
L5CLK
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
REV. 0
–49–
ADSP-21160M
400-BALL METRIC PBGA PIN CONFIGURATIONS (BOTTOM VIEW, SUMMARY)
)
A
'
*
)
A
'
*
"
!
#
(
E
D
D # ! " # E
! )[email protected])[email protected] )[email protected])[email protected] )[email protected] )$ ! ! ( # # 7
# B
–50–
REV. 0
ADSP-21160M
OUTLINE DIMENSIONS
The ADSP-21160M comes in a 27mm ⴛ 27mm, 400-ball Metric PBGA package with 20 rows of balls.
400-BALL METRIC PBGA (B-400)
'B
'B %
) )
A ' * A
'
*
B) "
!
#
(
B
%
B
B %
BA B' B * !
(
(
BA
B
A
B
B*
B
B'
B**
B*
B*
E
B @ B* ! ! B
B " # B
B ! # " ! ( ! B " ! B
B'
BA
B
B'*
B
B ! # " ! ( ! B " ! B
REV. 0
–51–
B*
B ADSP-21160M
ORDERING GUIDE
Part Number1, 2
Case Temperature
Range
Instruction Rate
On-Chip
SRAM
Operating Voltage
ADSP-21160MKB-80
0°C to 85°C
80 MHz
4 Mbit
2.5 INT/3.3 EXT V
1
PRINTED IN U.S.A.
C02426–2.5–4/01(0)
B = Plastic Ball Grid Array (PBGA) package.
2
See ADSP-21160N data sheet for ordering information for higher-performance derivative.
–52–
REV. 0
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.