Charge Pump Regulator for Color TFT Panel ADM8832 FEATURES FUNCTIONAL BLOCK DIAGRAM C5 2.2µF VCC ADM8832 VOLTAGE DOUBLER C1+ C1 2.2µF C1– VOUT CLKIN SCAN/ BLANK LDO_ON/ OFF LDO IN OSCILLATOR LDO VOLTAGE REGULATOR CONTROL LOGIC DOUBLE C6 2.2µF +5VOUT +5VIN C2+ C2– APPLICATIONS TRIPLE TIMING GENERATOR Handheld instruments TFT LCD panels Cellular phones C3– C4+ VOLTAGE SHUTDOWN DISCHARGE INVERTER CONTROL C4– C4 1µF –10VOUT GND +5.1V C7 2.2µF C3 1µF +15VOUT VOLTAGE TRIPLER SHDN C3+ C2 1µF +15.3V C8 1µF –10.2V C9 1µF 03759-A-001 3 output voltages (+5.1 V, +15.3 V, −10.2 V) from one 3 V input supply Power efficiency optimized for use with TFT in mobile phones Low quiescent current Low shutdown current (<1 µA) Fast transient response Shutdown function Power saving during blanking period Option to use external ldo Figure 1. GENERAL DESCRIPTION The ADM8832 is a charge pump regulator used for color thin film transistor (TFT) liquid crystal displays (LCD). Using charge pump technology, the device can be used to generate three output voltages (+5.1 V ±2%, +15.3 V, −10.2 V) from a single 3 V input supply. These outputs are then used to provide supplies for the LCD controller (+5.1 V) and the gate drives for the transistors in the panel (+15.3 V and −10.2 V). Only a few external capacitors are needed for the charge pumps. An efficient low dropout voltage regulator also ensures that the power efficiency is high and provides a low ripple 5.1 V output. This LDO can be shut down and an external LDO used to regulate the 5 V doubler output and drive the input to the charge pump section, which generates the +15.3 V and −10.2 V outputs if so required by the user. mode where the current is highest. During blanking periods, the ADM8832 switches to an external, lower frequency clock. This allows the user to vary the frequency and maximize power efficiency during blanking periods. The tolerances on the output voltages are seamlessly maintained when switching from scanning mode to blanking mode or vice versa. The ADM8832 has an internal 100 kHz oscillator for use in scanning mode, but the part must be clocked by an external clock source in blanking (low current) mode. The internal oscillator is used to clock the charge pumps during scanning The ADM8832 is fabricated using CMOS technology for minimal power consumption. The part is packaged in a 20-lead LFCSP (lead frame chip scale package). The ADM8832 power saving features include low power shutdown and reduced quiescent current consumption during the blanking periods. The 5.1 V output consumes the most power, so power efficiency is also maximized on this output with an oscillator enabling scheme (Green Idle™). This effectively senses the load current that is flowing and turns on the charge pump only when charge needs to be delivered to the 5 V pump doubler output. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADM8832 TABLE OF CONTENTS Specifications..................................................................................... 3 Theory of Operation ...................................................................... 10 Timing Specifications .................................................................. 4 Scanning and Blanking.............................................................. 10 Absolute Maximum Ratings............................................................ 5 Power Sequencing ...................................................................... 10 Thermal Characteristics .............................................................. 5 Transient Response .................................................................... 10 ESD Caution.................................................................................. 5 External Clock ............................................................................ 10 Pin Configuration and Function Descriptions............................. 6 Outline Dimensions ....................................................................... 11 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 11 REVISION HISTORY 4/04—Changed from Rev. 0 to Rev. A Changes to Outline Dimensions................................................... 11 Updated Ordering Guide............................................................... 11 7/03—Revision 0: Initial Version Rev. A | Page 2 of 12 ADM8832 SPECIFICATIONS VCC = 2.6 V to 3.6 V, TA = −40°C to +85°C, unless otherwise noted; C1, C5, C6, C7 = 2.2 µF, C2, C3, C4, C8, C9 = 1 µF, CLKIN = 1 kHz in blanking mode. Table 1. Parameter INPUT VOLTAGE, VCC SUPPLY CURRENT, ICC +5.1 V OUTPUT Output Voltage Output Current Min 2.6 150 70 Output Ripple −10.2 V OUTPUT Output Voltage Output Current Output Ripple POWER EFFICIENCY (+15.3 V and −10.2 V Outputs) CHARGE PUMP FREQUENCY CONTROL PINS SHDN Input Voltage, VSHDN Max 3.6 400 140 1 Unit V µA µA µA Unloaded, Scanning Period Unloaded, Blanking Period Shutdown Mode, TA = 25°C 5.1 4 5 50 80 70 10 5 5.2 5 8 200 V mA mA µA % % mV p-p µs IL = 10 µA to 8 mA Scanning Period Scanning Period, VCC > 2.7 V Blanking Period VCC = 3 V, IL = 5 mA (Scanning) VCC = 3 V, IL = 200 µA (Blanking) 8 mA Load IL Stepped from 10 µA to 8 mA 14.4 15.3 50 1 50 15.6 100 10 V µA µA mV p-p IL = 1 µA to 100 µA Scanning Period Blanking Period IL = 100 µA −10.4 −100 −10 −10.2 −50 −1 50 90 80 100 −9.6 V µA µA mV p-p % % kHz IL = –1 µA to −100 µA Scanning Period Blanking Period IL = –100 µA Relative to 5.1 V Output, IL = 100 µA (Scanning) Relative to 5.1 V Output, IL = 10 µA (Blanking) Scanning Period V V µA pF SHDN Low = Shutdown Mode SHDN High = Normal Mode V V µA pF Low = BLANK Period High = SCAN Period V V µA pF Low = External LDO High = Internal LDO 60 140 0.3 VCC 0.7 VCC Digital Input Current Digital Input Capacitance1 SCAN/BLANK Input Voltage ±1 10 0.3 VCC 0.7 VCC Digital Input Current Digital Input Capacitance1 LDO_ON/OFF Input Voltage ±1 10 0.3 VCC 0.7 VCC Digital Input Current Digital Input Capacitance1 Test Conditions 5.0 Power Efficiency Output Ripple Transient Response +15.3 V OUTPUT Output Voltage Output Current Typ ±1 10 Footnotes after table. Rev. A | Page 3 of 12 ADM8832 Parameter CLKIN Minimum Frequency Input Voltage VIL VIH Digital Input Current Digital Input Capacitance1 Min Typ 0.9 1 Max 0.3 VCC 0.7 VCC ±1 10 Unit Test Conditions kHz Duty Cycle = 50%, Rise/Fall Times = 20 ns V V µA pF 1 Guaranteed by design. Not 100% production tested. Specifications are subject to change without notice. TIMING SPECIFICATIONS VCC = 2.6 V to 3.6 V, TA = –40°C to +85°C, unless otherwise noted; C1, C5, C6, C7 = 2.2 µF, C2, C3, C4, C8, C9 = 1 µF, CLKIN = 1 kHz in blanking mode. Table 2. Parameter POWER-UP SEQUENCE +5 V Rise Time, tR5V +15 V Rise Time, tR15V −10 V Fall Time, tF10V Delay between −10 V Fall and +15 V, tDELAY POWER-DOWN SEQUENCE +5 V Fall Time, tF5V +15 V Fall Time, tF15V −10 V Rise Time, tR10V Min Typ Max Unit Test Conditions/Comments 300 8 12 3 µs ms ms ms 10% to 90%, Figure 17 10% to 90%, Figure 17 90% to 10%, Figure 17 Figure 17 75 40 40 ms ms ms 90% to 10%, Figure 17 90% to 10%, Figure 17 10% to 90%, Figure 17 Rev. A | Page 4 of 12 ADM8832 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL CHARACTERISTICS Table 3. Parameter Supply Voltage Input Voltage to Digital Inputs Output Short Circuit Duration to GND Output Voltage +5.1 V Output −10.2 V Output +15.3 V Output Operating Temperature Range Power Dissipation (Derate 33 mW/°C above 25°C) Storage Temperature Range ESD Ratings −0.3 V to +4.0 V −0.3 V to +4.0 V 10 sec −0.3 V to +6 V −12 V to +0.3 V −0.3 V to +17 V −40°C to +85°C 3.55 W 20-Lead LFCSP: θJA = 31°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −65°C to +150°C Class I ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 12 ADM8832 20 C1+ 19 C1– 18 GND 17 –10VOUT 16 C4+ PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 3 4 5 PIN 1 INDICATOR ADM8832 TOP VIEW 15 C4– 14 C2+ 13 C2– 12 C3+ 11 C3– 03759-A-002 1 LDO_ON/OFF 6 SHDN 7 SCAN/BLANK 8 CLKIN 9 +15VOUT 10 VCC VOUT LDO_IN +5VOUT +5VIN Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic VCC VOUT 3 4 LDO_IN +5VOUT 5 6 +5VIN LDO_ON/OFF 7 SHDN 8 SCAN/BLANK 9 CLKIN 10 +15VOUT 11, 12 13, 14 15, 16 17 C3−, C3+ C2−, C2+ C4−, C4+ −10VOUT 18 19, 20 GND C1−, C1+ Function Positive Supply Voltage Input. Connect this pin to 3 V supply with a 2.2 µF decoupling capacitor. Voltage Doubler Output. This is derived by doubling the 3 V supply. A 2.2 µF capacitor to ground is required on this pin. Voltage Regulator Input. The user has the option to bypass this circuit using the LDO_ON/OFF pin. +5.1 V Output Pin. This is derived by doubling and regulating the +3 V supply. A 2.2 µF capacitor to ground is required on this pin to stabilize the regulator. +5.1 V Input Pin. This is the input to the voltage tripler and doubler inverter charge pump circuits. Control Logic Input. 3 V CMOS logic. A logic high selects the internal LDO for regulation of the 5 V voltage doubler output. A logic low isolates the internal LDO from the rest of the charge pump circuits. This allows the use of an external LDO to regulate the 5 V voltage doubler output. The output of this LDO is then fed back into the voltage tripler and doubler/inverter circuits of the ADM8832. Digital Input. 3 V CMOS logic. Active low shutdown control. This pin shuts down the timing generator and enables the discharge circuit to dissipate the charge on the voltage outputs, thus driving them to 0 V. Drive Mode Input. 3 V CMOS logic. A logic high places the part in scan (high current) mode, and the charge pump is driven by the internal oscillator. A logic low places the part in blanking (low current) mode, and the charge pump is driven by the (slower) external oscillator. This is a power saving feature on the ADM8832. External CLOCK Input. During a blanking period, the oscillator circuit selects this pin to drive the charge pump circuit. This is at a lower frequency than the internal oscillator, resulting in lower quiescent current consumption, thus saving power. +15.3 V Output Pin. This is derived by tripling the +5.1 V regulated output. A 1 µF capacitor is required on this pin. External capacitor C3 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C2 is connected between these pins. A 1 µF capacitor is recommended. External capacitor C4 is connected between these pins. A 1 µF capacitor is recommended. −10.2 V Output Pin. This is derived by doubling and inverting the +5.1 V regulated output. A 1 µF capacitor is required on this pin. Device Ground Pin. External capacitor C1 is connected between these pins. A 2.2 µF capacitor is recommended. Rev. A | Page 6 of 12 ADM8832 90 85 70 84 LDO POWER EFFICIENCY (%) 60 50 40 30 83 82 81 80 79 10 10 30 50 70 90 110 130 150 OUTPUT CURRENT (µA) 170 03759-A-003 20 190 78 0 Figure 3. LDO Efficiency in Blanking Mode with VCC = 3 V 1 2 3 4 5 OUTPUT CURRENT (mA) 6 7 8 03759-A-006 LDO POWER EFFICIENCY (%) TYPICAL PERFORMANCE CHARACTERISTICS Figure 6. LDO Efficiency in Scanning Mode with VCC = 3 V 100 5.0752 5.0750 +15V/–10V EFFICIENCY (%) LDO OUTPUT VOLTAGE (V) 5.0748 5.0746 5.0744 5.0742 5.0740 5.0738 90 80 70 10000 100 60 2 Figure 4. LDO Output Voltage (Unloaded) vs. Blanking Mode Frequency 4 6 OUTPUT CURRENT (µA) 8 Figure 7. +15 V/−10 V Efficiency vs. Output Current in Blanking Mode, VCC = 3 V 5.104 100 5.102 +15/–10V EFFICIENCY (%) 90 5.100 5.098 5.096 5.094 80 70 60 50 5.092 5.090 0 1 2 3 4 5 6 ILOAD (mA) 7 8 03759-A-005 LDO O/P (V) 10 03759-A-007 1000 BLANKING FREQUENCY (Hz) 03759-A-008 5.0734 100 03759-A-004 5.0736 40 0 20 40 60 OUTPUT CURRENT (µA) 80 Figure 8. +15 V/−10 V Efficiency vs. Output Current in Scanning Mode, VCC = 3 V Figure 5. LDO O/P Voltage vs. Load Current in Scanning Mode, VCC = 3.3 V Rev. A | Page 7 of 12 ADM8832 5.30 TEK STOP: SINGLE SEQ 10.0MS/s [ T ] 5.25 5.20 LOAD ENABLE DEVICE 1 @ +85°C T 2 5.0V O/P (V) 5.15 DEVICE 1 @ +25°C 5.10 T 5.05 DEVICE 1 @ –40°C 5V OUTPUT 1 5.00 2.7 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 CH1 20.0mV Figure 9. LDO Variation over Supply and Temperature 2.00V M5.00µs CH2 1.20V Figure 12. 5 V Output Transient Response for Max load Current 300 TEK STOP: SINGLE SEQ 10.0MS/s [ T ] T 250 SUPPLY CURRENT (µA) CH2 03759-A-012 4.90 2.6 03759-A-009 4.95 LOAD DISABLE 200 2 ICC (SCAN) 150 5V OUTPUT 100 ICC (BLANK) T 1 2.7 2.8 2.9 3.0 3.1 3.2 VCC (V) 3.3 3.4 3.5 3.6 CH1 20.0mV Figure 10. Supply Current vs. Voltage TEK STOP: 2.50MS/s [ 23 ACQS T CH2 2.00V M5.00µs CH2 1.20V 03759-A-013 0 2.6 03759-A-010 50 Figure 13. 5 V Output Transient Response, Load Disconnected TEK STOP: SINGLE SEQ 5.00KS/s [ T ] VOUT ] +15V OUTPUT T 2 5V OUTPUT RIPPLE 1 T T 2 T VCC RIPPLE T –10V OUTPUT 3 CH2 100mV M20.0µs CH1 –2.8mV 03759-A-011 CH1 20.0mV CH3 50.0mV 1 CH1 CH3 Figure 11. Output Ripple on LDO (5 V Output) 5.00V 5.00V CH2 5.00V M10.0ms CH2 1.3V Figure 14. +15 V and −10 V Outputs at Power-Up Rev. A | Page 8 of 12 03759-A-014 T 5VOUT ADM8832 5 ACQS T [ 20.1 ] 20.0 +15V OUTPUT T DISSIPATED POWER (mW) TEK STOP: 500S/s 1 –10V OUTPUT T 19.9 19.8 19.7 19.6 19.5 CH1 CH3 5.00V 5.00V CH2 5.00V M10.0ms CH1 0V 19.4 –40 03759-A-015 5VOUT 2 Figure 15. +15 V and −10 V Outputs at Power-Down (Unloaded) –20 0 20 40 TEMPERATURE (°C) 60 90 03759-A-016 T Figure 16. Power Dissipation over Temperature, VCC = 3.6 V, Scanning Mode with All O/Ps at Maximum Load Rev. A | Page 9 of 12 ADM8832 THEORY OF OPERATION SCANNING AND BLANKING TRANSIENT RESPONSE A TFT LCD panel is made up of a bank of capacitors, each representing a pixel in the display. These capacitors store different levels of charge, depending on the amount of luminescence required for a given pixel. When a picture is displayed on the panel, a scan of all the pixel capacitors is performed, placing different levels of charge on each in order to create the image. The process of updating the display like this is called scanning. Once scanned, an image is held by pixel capacitance, and the controller and source line drivers can be put into a low power mode. This low power mode is referred to as the blanking mode on the ADM8832. Over a finite period of time, this pixel charge will leak and the capacitors will need to be refreshed in order to maintain the image. The ADM8832 features extremely fast transient response, making it very suitable for fast image updates on TFT LCD panels. This means that even under changing load conditions there is still very effective regulation of the 5 V output. Figure 12 and Figure 13 show how the 5.1 V output responds when a maximum load is dynamically connected and disconnected. Note that the output settles within 5 µs to less than 1% of the output level. The ADM8832 has an internal 100 kHz oscillator, but an external clock source can also be used to clock the part. This clock source must be applied to the CLKIN pin. Power is saved during blanking periods by disabling the internal oscillator and by switching to the lower frequency external clock source. To achieve optimum performance of the charge pump circuitry, it is important that the duty cycle of the external clock source is 50% and that the rise and fall times are less than 20 ns. 90% 10% tF tR: RISE TIME tF: FALL TIME tH @ 100% = DUTY CYCLE tT tH tT POWER SEQUENCING Figure 18. Duty Cycle of External Clock 0.400 0.050 1.950 0.500 SHDN 2.100 0.280 0.750 0.100 The gate drive supplies must be sequenced such that the −10 V supply is up before the +15 V supply for the TFT panel to power on correctly. The ADM8832 controls this sequence. When the device is turned on (a logic high on SHDN), the ADM8832 allows the −10 V output to ramp immediately, but holds off the +15 V output. It continues to do this until the negative output reaches −3 V. At this point, the positive output is enabled and allowed to ramp up to +15 V. This sequence is shown in Figure 17. VCC 03759-A-017 tR 0.900 The ADM8832 uses scanning and blanking modes, as follows. When the TFT LCD panel is in scanning mode, a logic high on the SCAN/BLANK input places the device in high current power mode, providing extra power (extra current) to the LCD controller and the source line drivers. If the panel continues to be updated (as when a moving picture is being displayed), the ADM8832 can be continually operated in scanning mode. If the same image is kept on the panel, a logic low is applied to the SCAN/BLANK input, and the ADM8832 enters blanking (low current) mode. Depending on how often the image is updated, the ADM8832 can be operated with a variable SCAN/ BLANK duty cycle. This helps to maximize power efficiency and, therefore, extends the battery life. EXTERNAL CLOCK tR5V 90% 10% +5V tF5V tR15V tF15V +15V –10V 90% 10% –3V 0.875 tR10V 0.200 0.250 SOLDER MASK BOARD METALLIZATION tF10V LOAD Figure 19. Suggested LFCSP 4 mm × 4mm 20 Lead Land Pattern 03759-A-018 SCAN/BLANK EXTERNAL CLOCK Figure 17. Power Sequence Rev. A | Page 10 of 12 03759-A-019 tR15V ADM8832 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 16 15 20 1 2.25 2.10 SQ 1.95 EXPOSED PAD 3.75 BCS SQ (BOTTOM VIEW) 0.75 0.55 0.35 12° MAX 0.90 0.85 0.80 SEATING 0.50 PLANE BSC 11 10 0.80 MAX 0.65 TYP 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF 6 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 20. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body (CP-20) Dimensions shown in millimeters ORDERING GUIDE Model ADM8832ACP ADM8832ACP-REEL ADM8832ACP-REEL7 ADM8832ACPZ1 ADM8832ACPZ-REEL1 ADM8832ACPZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Lead Frame Chip Scale Package Z = Pb-free part. Rev. A | Page 11 of 12 Package Option CP-20 CP-20 CP-20 CP-20 CP-20 CP-20 ADM8832 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03759–0–5/04(A) Rev. A | Page 12 of 12