High Performance HDMI/DVI Transmitter AD9889B Preliminary Technical Data FEATURES APPLICATIONS DVD players and recorders Digital set-top boxes A/V receivers Digital cameras and camcorders HDMI repeater/splitter GENERAL DESCRIPTION The AD9889B is a 165 MHz, high definition multimedia interface (HDMI) v. 1.2a transmitter. It supports HDTV formats up to 1080p, and computer graphic resolutions up to UXGA (1600 × 1200 @ 60 Hz). With the inclusion of HDCP, the AD9889B allows the secure transmission of protected content as specified by the HDCP v. 1.1 protocol. FUNCTIONAL BLOCK DIAGRAM SCL SDA INT MCL MDA INTERRUPT HANDLER I2C SLAVE HPD HDCP CORE HDCP-EDID MICROCONTROLLER REGISTER CONFIGURATION LOGIC I2C MASTER CLK DDCSDA DDCSCL VSYNC HSYNC VIDEO DATA CAPTURE DE D[23:0] Tx0[1:0] COLOR SPACE CONVERSION 4:2:2 TO 4:4:4 CONVERSION HDMI Tx CORE XOR MASK Tx1[1:0] Tx2[1:0] TxC[1:0] S/PDIF MCLK I2S[3:0] AUDIO DATA CAPTURE LRCLK AD9889B SCLK 06291-001 General HDMI™/DVI transmitter compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.1 Single 1.8 V power supply Video/audio inputs accept logic levels from 1.8 V to 3.3 V 80-lead LQFP, Pb-free package 64-lead LFCSP, Pb-free package 76-ball CSP_BGA, Pb-free package Digital video 165 MHz operation supports all resolutions from 480i to 1080p and UXGA at 60 Hz Programmable two-way color space converter Supports RGB, YCbCr, and DDR Supports ITU656-based embedded syncs Automatic input video format timing detection (CEA-861B) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel, uncompressed, LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C® master to perform HDCP operations and EDID reading operations 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI events through interrupts and registers Figure 1. The AD9889B supports both S/PDIF and 8-channel I2S audio. Its high fidelity, 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio, including DTS®, THX®, and Dolby® Digital. The AD9889B helps reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on the I2C and hot plug detect pins. Fabricated in an advanced CMOS process, the AD9889B is available in a space-saving, 76-ball CSP_BGA or 64-lead LFCSP surface-mount package, and an 80-lead LQFP surface-mount package. All packages are available as Pb-free and are specified from −25°C to +85°C. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9889B Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Design Resources ..........................................................................9 Applications....................................................................................... 1 Document Conventions ...............................................................9 General Description ......................................................................... 1 PCB Layout Recommendations.................................................... 10 Functional Block Diagram .............................................................. 1 Power Supply Bypassing ............................................................ 10 Specifications..................................................................................... 3 Digital Inputs .............................................................................. 10 Absolute Maximum Ratings............................................................ 5 External Swing Resistor............................................................. 10 Explanation of Test Levels ........................................................... 5 Output Signals ............................................................................ 10 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 11 Pin Configuration and Function Descriptions............................. 6 Ordering Guide .......................................................................... 12 Applications....................................................................................... 9 Rev. PrA | Page 2 of 12 Preliminary Technical Data AD9889B SPECIFICATIONS Table 1. Parameter DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) THERMAL CHARACTERISTICS Thermal Resistance θJC Junction-to-Case θJA Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current, IIL Input Clamp Voltage Differential High Level Output Voltage Differential Output Short-Circuit Current POWER SUPPLY VDD (All) Supply Voltage VDD Supply Voltage Noise Power-Down Current IAVDD 2 IPVDD2 IDVDD2 Transmitter Supply Current2 Conditions Temp Test Level 1 Full Full 25°C VI VI V 1.4 Full Full VI VI VDD − 0.1 Full V V V 25°C 25°C 25°C −16 mA +16 mA VI V V V Min Typ Transmitter Total Power AC SPECIFICATIONS CLK Frequency TMDS Output CLK Duty Cycle Worst Case CLK Input Jitter Input Data Setup Time Input Data Hold Time TMDS Differential Swing VSYNC and HSYNC Delay from DE Falling Edge VSYNC and HSYNC Delay to DE Rising Edge DE High Time DE Low Time Differential Output Swing Low-to-High Transition Time High-to-Low Transition Time Rev. PrA | Page 3 of 12 Unit 3.5 0.7 V V pF 3 −25 15.2 59 +25 −10 0.4 V V +85 °C/W °C/W °C +10 μA V V V 10 μA 1.89 50 V mV p-p mA −0.8 +0.8 AVCC IV With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern With active video applied, 165 MHz, typical random pattern Max Full Full 25°C IV V IV 1.71 1.8 25°C IV TBD 25°C IV TBD 25°C IV TBD 25°C IV TBD mA Full VI TBD mW 25°C 25°C Full Full Full IV IV IV IV IV VI VI 9 13.5 48 1 1 800 80 52 2 1000 1 VI 1 25°C 25°C VI VI 138 25°C 25°C VII VII 75 75 1200 MHz % ns ns ns mV UI 3 UI 8191 UI UI 490 490 ps ps AD9889B Parameter AUDIO AC TIMING Sample Rate I2S Cycle Time I2S Setup Time I2S Hold Time Audio Pipeline Delay Preliminary Technical Data Conditions Temp Test Level 1 I2S and S/PDIF Full 25°C 25°C 25°C 25°C IV IV IV IV IV 1 See Explanation of Test Levels section. Using low output drive strength. 3 UI = unit interval. 2 Rev. PrA | Page 4 of 12 Min Typ 32 15 0 75 Max Unit 192 1 kHz UI ns ns μs Preliminary Technical Data AD9889B ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 2. Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5 V to 0.0 V 20 mA −40°C to +85°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing. VII. Limits defined by HDMI specification; guaranteed by design and characterization testing. ESD CAUTION Rev. PrA | Page 5 of 12 AD9889B Preliminary Technical Data DVDD DVDD DVDD DVDD D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 GND 59 GND 3 58 D15 HSYNC 4 57 D16 VSYNC 5 56 D17 CLK 6 55 D18 S/PDIF 7 54 D19 MCLK 8 53 D20 AD9889B 52 D21 TOP VIEW (Not to Scale) 51 D22 50 D23 I2S3 12 49 MCL SCLK 13 48 MDA LRCLK 14 47 SDA GND 15 46 SCL PVDD 16 45 DDCSDA GND 17 44 DDCSCL GND 18 43 GND PVDD 19 42 GND PVDD 20 41 AVDD DVDD 1 9 I2S1 10 I2S2 11 06291-002 INT GND Tx2+ Tx2– AVDD Tx1+ Tx1– PD/A0 TxC+ TxC– GND HPD AVDD EXT_SWG GND PVDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 DVDD Figure 2. 80-Lead LQFP Pin Configuration (Top View) PIN 1 INDICATOR + AD9889B TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DVDD D15 D16 D17 D18 D19 D20 D21 D22 D23 MCL MDA SDA SCL DDCSDA DDCSCL 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PVDD EXT_SWG AVDD HPD TxC– TxC+ AVDD Tx0– Tx0+ PD/A0 Tx1– Tx1+ AVDD Tx2– Tx2+ INT DVDD D0 DE HSYNC VSYNC CLK S/PDIF MCLK I2S0 I2S1 I2S2 I2S3 SCLK LRCLK PVDD PVDD NOTES 1. GND PADDLE ON BOTTOM OF PACKAGE. Figure 3. 64-Lead LFCSP Pin Configuration (Top View) Rev. PrA | Page 6 of 12 06291-003 I2S0 Tx0+ DE PIN 1 INDICATOR Tx0– 2 AVDD D0 Preliminary Technical Data AD9889B 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J 06291-004 K BOTTOM VIEW (Not to Scale) Figure 4. 76-Ball BGA Configuration (Top View) Table 3. Pin Function Descriptions Pin No. LFCSP 39 to 47, 50 to 63, 2 LQFP 50 to 58, 65 to 78, 2 Mnemonic D[23:0] Type1 I Description Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. 6 6 CLK I C2 3 3 DE I C1 4 4 HSYNC I D2 5 5 VSYNC I J3 18 23 EXT_SW I K3 20 25 HPD I E2 7 7 S/PDIF I E1 8 8 MCLK I F2, F1, G2, G1 9 to 12 9 to 12 I2S[3:0] I H2 H1 13 14 13 14 SCLK LRCLK I I J72 262 332 PD/A0 I K1, K2 21, 22 27, 28 TxC−/TxC+ O K10, J10 30, 31 37, 38 Tx2−/Tx2+ O K7, K8 27, 28 34, 35 Tx1−/Tx1+ O K4, K5 24, 25 30, 31 Tx0−/Tx0+ O H10 32 40 INT O J2, J5, J8, K9 19, 23, 29 24, 29, 36, 41 AVDD P Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level. I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9889B. 1.8 V to 3.3 V CMOS logic level. Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level. Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS logic level. Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended. 1.8 V Power Supply for TMDS Outputs. BGA A1 to A10, B1 to B10, C9, C10, D9, D10 D1 Rev. PrA | Page 7 of 12 AD9889B Preliminary Technical Data BGA D5, D6, D7, E7 Pin No. LFCSP 1, 48, 49 G4, G5, J1 LQFP 1, 61, 62, 63, 64 Mnemonic DVDD Type1 P 15, 16, 17, 16, 19, 20, 21 PVDD P D4, E4, F4, J4, G6, J6, K6, F7, G7, H9, J9 64, paddle on bottom side GND P F9 36 15, 17, 18, 22, 26, 32, 39, 42, 43, 59, 60, 79, 80 47 SDA C3 F10 35 46 SCL C3 E10 37 48 MDA C3 E9 38 49 MCL C3 G9 34 45 DDCSDA C3 G10 33 44 DDCSCL C3 Description 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. 1.8 V PLL Power Supply. The most sensitive portion of the AD9889B is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889B be assembled on a single, solid ground plane with careful attention given to ground current paths. Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level. Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS logic level. 1 I = input, O = output, P = power supply, C = control. Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the powerdown control function occurs whenever the state of the pin is changed from its original state at power-up. 3 For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from [email protected]. 2 Rev. PrA | Page 8 of 12 Preliminary Technical Data AD9889B APPLICATIONS DESIGN RESOURCES DOCUMENT CONVENTIONS Analog Devices, Inc. evaluation kits, reference design schematics, and other support documentation are available under NDA from [email protected]. In this data sheet, data is represented using the conventions described in Table 4. Table 4. Document Conventions Other resources include: EIA/CEA-861B which describes audio and video infoframes as well as the E-EDID structure for HDMI. It is available from Consumer Electronics Association (CEA). The HDMI v. 1.3, a defining document for HDMI Version 1.2a, and the HDMI Compliance Test Specification Version 1.2a are available from HDMI Licensing, LLC. Data Type 0xNN 0bNN NN Bit The HDCP v. 1.1 is the defining document for HDCP Version 1.1 available from Digital Content Protection, LLC. Rev. PrA | Page 9 of 12 Format Hexadecimal (Base-16) numbers are represented using the C language notation, preceded by 0x. Binary (Base-2) numbers are represented using the C language notation, preceded by 0b. Decimal (Base-10) numbers are represented using no additional prefixes or suffixes. Bits are numbered in little endian format, that is, the least significant bit of a byte or word is referred to as Bit 0. AD9889B Preliminary Technical Data PCB LAYOUT RECOMMENDATIONS The AD9889B is a high precision, high speed analog device. As such, to obtain the maximum performance from the part, it is important to have a well laid out board. Other Input Signals POWER SUPPLY BYPASSING The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9889B supplies are applied/enabled. For example, if the PD/A0 pin is low (when the supplies are turned on), then the device address is 0x72 and the power-down is active high. If the PD/A0 pin is high (when the supplies are turned on), the device address is 0x7A and the power-down is active low. It is recommended to bypass each power supply pin with a 0.1 μF capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers/grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9889B, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make a power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVDD (the PLL supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is best practice to provide separate regulated supplies for each of the analog circuitry groups (AVDD and PVDD). It is also recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. DIGITAL INPUTS Video and Audio Data Input Signals The digital inputs on the AD9889B are designed to work with signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra components need to be added when using 3.3 V logic. Any noise that gets onto the clock input (labeled CLK) trace adds jitter to the system. Therefore, minimize the video clock input (Pin 6: CLK) trace length and do not run any digital or other high frequency traces near it. Make sure to match the length of the input data signals to optimize data capture, especially for high frequency modes such as 1080p and UXGA and double data rate input formats. The HPD must be connected to the HDMI connector. A 10 kΩ pull-down resistor to ground is also recommended. The SCL and SDA pins should be connected to the I2C master. A pull-up resistor of 2 kΩ to 1.8 V or 3.3 V is recommended. EXTERNAL SWING RESISTOR The external swing resistor must be connected directly to the EXT_SWG pin and ground. The external swing resistor must have a value of 887 Ω (±1% tolerance). Avoid running any high speed ac or noisy signals next to, or close to, the EXT_SWG pin. OUTPUT SIGNALS TMDS Output Signals The AD9889B has three TMDS data channels (0, 1, and 2) that output signals up to 800 MHz as well as the TMDS output data clock. To minimize the channel-to-channel skew, make the trace length of these signals the same. Additionally, these traces need to have a 50 Ω characteristic impedance and need to be routed as 100 Ω differential pairs. Best practice recommends routing these lines on the top PCB layer avoiding the use of vias. Other Output Signals (non TMDS) DDCSCL and DDCSDA The DDCSCL and DDCSDA outputs need to have a minimum amount of capacitance loading to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50 pF to meet the HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector and a pull-up resistor to 5 V is required. The pull-up resistor must have a value between 1.5 kΩ and 2 kΩ. INT Pin The INT pin is an output that should be connected to the microcontroller of the system. A pull-up resistor to 1.8 V or 3.3 V is required for proper operation—the recommended value is 2 kΩ. MCL and MDA The MCL and MDA outputs should be connected to the EEPROM containing the HDCP key (if HDCP is implemented). Pull-up resistors of 2 kΩ are recommended. Rev. PrA | Page 10 of 12 Preliminary Technical Data AD9889B OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE 20 41 40 21 VIEW A VIEW A 0.65 BSC LEAD PITCH ROTATED 90° CCW 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 6. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters 9.00 BSC SQ 0.30 0.25 0.18 0.60 MAX 0.60 MAX 49 48 PIN 1 INDICATOR 64 1 PIN 1 INDICATOR + 8.75 BSC SQ TOP VIEW (BOTTO M VIEW) 0.45 0.40 0.35 1.00 0.85 0.80 12° MAX 33 32 17 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 4.85 4.70 SQ* 4.55 EXPOSED PAD** 0.20 REF 64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE) * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION **Note: PAD is CONNECTED to GND DIMENSIONS in Millimeters Figure 7. 64-Lead Lead Frame Chip Scale Package [LFCSP] (CP-64-1) Dimensions shown in millimeters Rev. PrA | Page 11 of 12 16 AD9889B Preliminary Technical Data A1 CORNER INDEX AREA 6.10 6.00 SQ 5.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C 4.50 BSC SQ D E 0.50 BSC F G H J K BOTTOM VIEW 0.75 REF DETAIL A *1.40 MAX DETAILA 0.65 MIN 0.15 MIN COPLANARITY 0.08 MAX *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 012006-0 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER Figure 8. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 6 mm × 6 mm × 1.4 mm (BC-76) Dimensions shown in millimeters ORDERING GUIDE Model AD9889BBCPZ-80 1 AD9889BBCPZ-1651 AD9889BBSTZ-801 AD9889BBSTZ-1651 AD9889BBBCZ-801 AD9889BBBCZ-1651 AD9889BBBCZRL-801 AD9889BBBCZRL-1651 AD9889B/PCB 1 Temperature Range −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C −25°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] 100-Lead Low Profile Quad Flat Package [LQFP] 100-Lead Low Profile Quad Flat Package [LQFP] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Package Option CP-64-1 CP-64-1 ST-80-2 ST-80-2 BC-76 BC-76 BC-76 BC-76 Z = Pb-free part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06291-0-11/06(PrA) Rev. PrA | Page 12 of 12