a FEATURES 80 MHz Pipelined Operation Triple 8-Bit D/A Converters RS-343A/RS-170 Compatible Outputs TTL Compatible Inputs +5 V CMOS Monolithic Construction 40-Pin DIP or 44-Pin PLCC Package Plug-In Replacement for BT101 Power Dissipation: 400 mW APPLICATIONS High Resolution Color Graphics CAE/CAD/CAM Applications Image Processing Instrumentation Video Signal Reconstruction Desktop Publishing SPEED GRADES 80 MHz 50 MHz 30 MHz CMOS 80 MHz, Triple 8-Bit Video DAC ADV101* FUNCTIONAL BLOCK DIAGRAM FS ADJUST VAA VREF REFERENCE AMPLIFIER ADV101 COMP CLOCK RED REGISTER 8 8 GREEN REGISTER 8 8 BLUE REGISTER 8 8 R0 R7 PIXEL INPUT PORT G0 DAC IOR DAC IOG DAC IOB SYNC CONTROL ISYNC G7 B0 B7 REF WHITE CONTROL REGISTER BLANK SYNC GND GENERAL DESCRIPTION The ADV101 is a digital-to-analog video converter on a single monolithic chip. The part is specifically designed for high resolution color graphics and video systems. It consists of three, high speed, 8-bit, video D/A converters (RGB); a standard TTL input interface and high impedance, analog output, current sources. The ADV101 has three separate, 8-bit, pixel input ports, one each for red, green and blue video data. Additional video input controls on the part include sync, blank and reference white. A single +5 V supply, an external 1.23 V reference and pixel clock input are all that are required to make the part operational. PRODUCT HIGHLIGHTS 1. Fast video refresh rate, 80 MHz. 2. Compatible with a wide variety of high resolution color graphics video systems. 3. Guaranteed monotonic with a maximum differential nonlinearity of ± 0.5 LSB. Integral nonlinearity is guaranteed to be a maximum of ± 1 LSB. The ADV101 is capable of generating RGB video output signals, which are compatible with RS-343A and RS-170 video standards, without requiring external buffering. The ADV101 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The part is packaged in both a 0.6", 40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC. *ADV is a registered trademark of Analog Devices Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 = +5 V 6 5%; V = +1.235 V; R = 37.5 V, C = 10 pF; R = 560 V. I ADV101–SPECIFICATIONS (Vconnected to IOG. All Specifications T to T unless otherwise noted.) AA REF L MIN Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on IOR, IOB Blank Level on IOG Sync Level on IOG LSB Size DAC to DAC Matching Output Compliance, VOC Output Impedance, ROUT2 Output Capacitance, COUT2 VOLTAGE REFERENCE Voltage Reference Range, VREF Input Current, IVREF POWER REQUIREMENTS VAA IAA Power Supply Rejection Ratio Power Dissipation DYNAMIC PERFORMANCE Glitch Impulse2, 3 DAC Noise2, 3, 4 Analog Output Skew All Versions Units L MAX SET SYNC 1 Test Conditions/Comments 8 Bits ±1 ± 0.5 ±5 LSB max LSB max Guaranteed Monotonic % Gray Scale max Max Gray Scale Current: IOG = (VREF* 12,082/RSET) mA Max Gray Scale Current: IOR, IOB = (VREF* 8,627/RSET) mA Binary 2 0.8 ±1 10 V min V max µA max pF max 15 22 mA min mA max 17.69 20.40 16.74 18.50 0.95 1.90 0 50 6.29 9.5 0 50 69.1 2 –1 +1.4 100 30 mA min mA max mA min mA max mA min mA max µA min µA max mA min mA max µA min µA max µA typ % typ V min V max kΩ typ pF max 1.14/1.26 +10 V min/V max µA typ 5 125 100 0.5 625 500 V nom mA max mA max %/% max mW max mW max Typically 80 mA: 80 MHz Parts Typically 70 mA: 50 MHz & 35 MHz Parts Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF Typically 400 mW: 80 MHz Parts Typically 350 mW: 50 MHz & 30 MHz Parts 50 200 2 pV secs typ pV secs typ ns max Typically 1 ns VIN = 0.4 V or 2.4 V Typically 19.05 mA Typically 17.62 mA Typically 1.44 mA Typically 5 µA Typically 7.62 mA Typically 5 µA IOUT = 0 mA VREF = 1.235 V for Specified Performance NOTES 1 Temperature Range (T MIN to T MAX); 0°C to +70°C. 2 Sample tested at +25°C to ensure compliance. 3 TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 4 This includes effects due to clock and data feedthrough as well as RGB analog crosstalk. Specifications subject to change without notice. –2– REV. B ADV101 TIMING CHARACTERISTICS1 (VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V. ISYNC connected to IOG. All Specifications TMIN to TMAX2 unless otherwise noted.) Parameter 80 MHz Version 50 MHz Version 30 MHz Version Units Conditions/Comments fMAX t1 t2 t3 t4 t5 t6 80 3 2 12.5 4 4 30 20 3 12 50 6 2 20 7 7 30 20 3 15 30 8 2 33.3 9 9 30 20 3 15 MHz max ns min ns min ns min ns min ns min ns max ns typ ns max ns typ Clock Rate Data & Control Setup Time Data & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time Analog Output Delay t7 t8 3 Analog Output Rise/Fall Time Analog Output Transition Time NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. See timing notes in Figure 1. 2 Temperature range (T MIN to TMAX): 0°C to +70°C. 3 Sample tested at +25°C to ensure compliance. Specifications subject to change without notice. t3 t4 t5 CLOCK t1 DIGITAL INPUTS (R0–R7, G0–G7, B0–B7; t2 DATA SYNC, BLANK, REF WHITE) t6 t8 ANALOG OUTPUTS (IOR, IOG, IOB, I SYNC ) t7 NOTES 1. OUTPUT DELAY ( t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. TRANSITION TIME ( t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. 3. OUTPUT RISE/FALL TIME ( t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL TRANSITION. Figure 1. Video Input/Output Timing REV. B –3– ADV101 ABSOLUTE MAXIMUM RATINGS 1 VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Voltage on Any Digital Pin . . . . GND – 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C IOR, IOB, IOG, ISYNC to GND2 . . . . . . . . . . . . . . 0 V to VAA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units Power Supply Ambient Operating Temperature Output Load Reference Voltage VAA 4.75 5.00 5.25 Volts TA RL VREF 0 +70 37.5 1.235 1.26 °C Ω Volts 1.14 ORDERING GUIDE NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration. 1 Speed 50 MHz Package Option2 80 MHz Plastic DIP (N-40A) ADV101KN80 ADV101KN50 ADV101KN30 PLCC3 (P-44A) ADV101KP80 30 MHz ADV101KP50 ADV101KP30 NOTES 1 All devices are specified for 0°C to +70°C operation. 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier. 3 PLCC: Plastic Leaded Chip Carrier (J-lead). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV101 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN CONFIGURATIONS 35 GND B6 7 ADV101 34 IOB B5 8 TOP VIEW (NOT TO SCALE) 33 IOR 31 ISYNC 30 VAA 29 GND B1 13 28 FS ADJUST B2 14 27 VREF B3 15 26 COMP B5 B6 41 40 7 39 B7 R0 8 38 R4 R1 9 37 R5 36 R6 R3 11 ADV101 35 R7 G0 12 TOP VIEW (Not to Scale) 34 G4 G1 13 33 G5 G2 14 32 G6 G3 15 31 G7 30 BLANK REF WHITE 16 29 SYNC COMP 17 –4– 22 23 24 25 26 27 28 GND 21 G0 21 IOB 22 G1 R3 20 20 IOR 23 G2 R2 19 19 IOG R1 18 VREF 18 24 G3 VAA 25 REF WHITE R0 17 ISYNC CLOCK 16 42 R2 10 32 IOG B0 12 43 VAA GND 11 44 GND VAA 10 1 GND B4 9 2 CLOCK FS ADJUST B7 6 3 B4 36 SYNC 4 VAA 37 BLANK R4 5 5 GND R5 4 6 B0 38 G7 GND R6 3 B1 39 G6 B3 40 G5 R7 2 B2 G4 1 VAA PLCC DIP REV. B ADV101 PIN FUNCTION DESCRIPTION Pin Mnemonic BLANK SYNC CLOCK REF WHITE R0–R7, G0–G7, B0–B7 IOR, IOG, IOB ISYNC FS ADJUST COMP VREF VAA GND REV. B Function Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored. Composite sync control input (TTL compatible). A logical zero on the SYNC input; switches off a 40 IRE current source on the ISYNC output. SYNC does not override any other control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK. Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC, BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched on the rising edge of clock. Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular PCB power or ground plane. Red, green and blue current outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not they are all being used. Sync current output. This high impedance current source can be directly connected to the IOG output. This allows sync information to be encoded onto the green channel. ISYNC does not output any current while SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by: ISYNC (mA) = 3,455 × VREF (V)/RSET (Ω) If sync information is not required on the green channel, ISYNC should be connected to AGND. Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 12,082 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR and IOB is given by: IOR, IOB (mA) = 8,628 × VREF (V)/ RSET (Ω) Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and VAA. Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. Analog power supply (5 V ± 5%). All VAA pins on the ADV101 must be connected. Ground. All GND pins must be connected. –5– ADV101 TERMINOLOGY Raster Scan Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture. The most basic method of sweeping a CRT one line at a time to generate and display images. Color Video (RGB) The maximum positive polarity amplitude of the video signal. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Sync Level The peak level of the SYNC signal. Video Signal That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed. Sync Signal (SYNC) The position of the composite video signal which synchronizes the scanning process. Gray Scale The discrete levels of video signal between reference black and reference white levels. An 8-bit DAC contains 256 different levels, while a 6-bit DAC contains 64. The REF WHITE control input drives the RGB video outputs to the white level. This function could be used to overlay a cursor or crosshair onto the RGB video output. CIRCUIT DESCRIPTION AND OPERATION The ADV101 contains three 8-bit D/A converters, with three input channels, each containing an 8-bit register. Also integrated on board the part is a reference amplifier and CRT control functions BLANK, SYNC and REF WHITE. Table I details the resultant effect on the analog outputs of BLANK, SYNC and REF WHITE. Digital Inputs All these digital inputs are specified to accept TTL logic levels 24-bits of pixel data (color information) R0–R7, G0–G7 and B0–B7 are latched into the device on the rising edge of each clock cycle. This data is presented to the three 8-bit DACs and is then converted to three analog (RGB) output waveforms. (See Figure 2.) Clock Input The CLOCK input of the ADV101 is typically the pixel clock rate of the system. It is also known as the dot rate. The dot rate and hence the required CLOCK frequency, will be determined by the on-screen resolution, according to the following equation. Three other digital control signals are latched to the analog video outputs in a similar fashion. BLANK, SYNC and REF WHITE are each latched on the rising edge of CLOCK to maintain synchronization with the pixel data stream. Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/ Dot Rate = (Retrace Factor) The BLANK and SYNC functions allow for the encoding of these video synchronization signals onto the RGB video output. This is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the BLANK and SYNC digital inputs. Figure 3 shows the analog output, RGB video waveform of the ADV101. The influence of SYNC and BLANK on the analog video waveform is illustrated. Horiz Res = Number of pixels/line Vert Res = Number of lines/frame Refresh Rate = Horizontal Scan Rate. This is the rate at which the screen must be refreshed, typically 60 Hz for a noninterlaced system or 30 Hz for an interlaced system. Retrace Factor = Total blank time factor. This takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). CLOCK DIGITAL INPUTS DATA (R0–R7, G0–G7, B0–B7; SYNC, BLANK, REFWHITE) ANALOG OUTPUTS (IOR, IOG, IOB, ISYNC ) Figure 2. Video Data Input/Output –6– REV. B ADV101 If we, therefore, have a graphics system with a 1024 × 1024 resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then: The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV101 on the rising edge of CLOCK, as previously described in the “Digital Inputs” section. It is recommended that the CLOCK input to the ADV101 be driven by a TTL buffer (e.g., 74F244). Dot Rate = 1024 × 1024 × 60/0.8 Dot Rate = 78.6 MHz RED, BLUE GREEN mA V mA V 19.05 0.714 26.67 1.000 WHITE LEVEL 92.5 IRE 1.44 0.054 9.05 0.340 7.62 0.286 BLACK LEVEL 7.5 IRE 0 0 BLANK LEVEL 40 IRE 0 0 SYNC LEVEL NOTES 1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD. 2. VREF = 1.235V, R SET = 560Ω, I SYNC CONNECTED TO IOG. 3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 3. RGB Video Output Waveform Table I. Video Output Truth Table Description IOG (mA)1 IOR, IOB (mA) REF WHITE SYNC BLANK DAC Input Data WHITE LEVEL WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL 26.67 26.67 video + 9.05 video + 1.44 9.05 1.44 7.62 0 19.05 19.05 video + 1.44 video + 1.44 1.44 1.44 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 0 0 xxH FFH data data 00H 00H xxH xxH NOTE 1 Typical with full-scale IOG = 26.67 mA. VREF = 1.235 V, R SET = 560 Ω, ISYNC connected to IOG. Video Synchronization and Control Reference Input The ADV101 has a single composite video sync (SYNC) input control. Many graphics processors and CRT controllers have the ability of generating horizontal sync (HSYNC), vertical sync (VSYNC) and composite SYNC. An external 1.23 V voltage reference is required to drive the ADV101. The AD589 from Analog Devices is an ideal choice of reference. It is a two-terminal, low cost, temperature compensated bandgap voltage reference which provides a fixed 1.23 V output voltage for input currents between 50 µA and 5 mA. Figure 4 shows a typical reference circuit connection diagram. The voltage reference gets its current drive from the ADV101’s VAA through an external 1 kΩ resistor to the VREF pin. A 0.1 µF ceramic capacitor is required between the COMP and VAA. This is necessary so as to provide compensation for the internal reference amplifier. In a graphics system which does not automatically generate a composite SYNC signal, the inclusion of some additional logic circuitry will enable the generation of a composite SYNC signal. The ISYNC current output is typically connected directly to the IOG output, thus encoding video synchronization information onto the green video channel. If it is not required to encode sync information onto the ADV101, the SYNC input should be tied to logic low and ISYNC should be connected to analog GND. REV. B –7– ADV101 A resistance RSET connected between FS ADJUST and GND determines the amplitude of the output video level according to the following equations: IOR, IOG, IOB Z O = 75Ω DACs (CABLE) IOG (mA) = 12,082 × VREF (V)/RSET (Ω) (1) IOR, IOB (mA) = 8,628 × VREF (V)/RSET (Ω) (2) Z L= 75Ω Z S = 75Ω (MONITOR) (SOURCE TERMINATION) If SYNC is not being encoded onto the green channel, then Equation 1 will be similar to Equation 2. Using a variable value of RSET, as shown in Figure 4, allows for accurate adjustment of the analog output video levels. Use of a fixed 560 Ω RSET resistor yields the analog output levels as quoted in the specification page. These values also correspond to the RS-343A video waveform values as shown in Figure 3. TERMINATION REPEATED THREE TIMES FOR RED, GREEN AND BLUE DACs Figure 5a. Analog Output Termination for RS-343A IOR, IOG, IOB ANALOG POWER PLANE +5V 0.1µF Z O = 75Ω DACs (CABLE) Z S = 150Ω COMP (SOURCE TERMINATION) VAA (MONITOR) I REF ~ ~ 4mA 1kΩ VREF TERMINATION REPEATED THREE TIMES FOR RED, GREEN AND BLUE DACs TO DACs FS ADJUST Figure 5b. Analog Output Termination for RS-170 AD589 500Ω RSET 560Ω required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement will develop RS-343A video output voltage levels across a 75 Ω monitor. (1.235V VOLTAGE REFERENCE) 100Ω GND ADV101* Z L= 75Ω A suggested method of driving RS-170 video levels into a 75 Ω monitor is shown in Figure 5b. The output current levels of the DACs remain unchanged, but the source termination resistance, ZS, on each of the three DACs is increased from 75 Ω to 150 Ω. *ADDITIONAL CIRCUITRY, INCLUDING DECOUPLING COMPONENTS, EXCLUDED FOR CLARITY More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is available in an application note entitled “Video Formats & Required Load Terminations” available from Analog Devices, publication number E1228-15-1/89. Figure 4. Reference Circuit D/A Converters The ADV101 contains three matched 8-bit D/A converters. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either the analog output (bit = “1”) or GND (bit = “0”) by a sophisticated decoding scheme. As all this circuitry is on one monolithic device, matching between the three DACs is optimized. As well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The onboard operational amplifier stabilizes the full-scale output current against temperature and power supply variations. Figure 3 shows the video waveforms associated with the three RGB outputs driving the doubly terminated 75 Ω load of Figure 5a. As well as the gray scale levels, black level to white level, the diagram also shows the contributions of SYNC and BLANK. These control inputs add appropriately weighted currents to the analog outputs, producing the specific output level requirements for video applications. Table I details how the SYNC and BLANK inputs modify the output levels. Gray Scale Operation The ADV101 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel used for video information). Any one of the three channels, red, green or blue can be used to input the digital video data. The two unused video data channels should be tied to logical zero. Analog Outputs The ADV101 has three analog outputs, corresponding to the red, green and blue video signals. A fourth analog output (ISYNC) can be used if it is required to encode video synchronization information onto the green signal. In this case, ISYNC is connected to IOG. (See “Video Synchronization and Control” section.) The red, green and blue analog outputs of the ADV101 are high impedance current sources. Each one of these three RGB current outputs is capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the –8– REV. B ADV101 The unused analog outputs should be terminated with the same load as that for the used channel. In other words, if the red channel is used and IOR is terminated with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG should be terminated with 37.5 Ω resistors. (See Figure 6.) VIDEO INPUT The ADV101 is specified to drive transmission line loads, which is what most monitors are rated as. The analog output configurations to drive such loads are described in the Analog Interface section and illustrated in Figure 5. However, in some applications it may be required to drive long “transmission line” cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion. Buffers with large full power bandwidths and gains between 2 and 4 will be required. These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices produces a range of suitable op amps for such applications. These include the AD84X series of monolithic op amps. In very high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is given in the relevant op amp data sheets. DOUBLY TERMINATED 75Ω LOAD IOR R0 Video Output Buffers R7 IOG G0 37.5Ω G7 B0 IOB B7 37.5Ω ADV101 Use of buffer amplifiers also allows implementation of other video standards besides RS-343A and RS-170. Altering the gain components of the buffer circuit will result in any desired video level. GND Figure 6. Input and Output Connections for Stand-Alone Gray Scale or Composite Video Z2 Z1 +V S IOR, IOG, IOB 2 0.1µF Z O = 75Ω 7 AD848 6 DACs Z S = 75Ω (SOURCE TERMINATION) 3 4 75Ω 0.1µF (CABLE) Z1 GAIN (G) = 1 + Z2 Figure 7. AD848 As an Output Buffer REV. B Z L= 75Ω (MONITOR) –V S –9– ADV101 PC BOARD LAYOUT CONSIDERATIONS Ground Planes The ADV101 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV101, it is imperative that great care be given to the PC board layout. Figure 8 shows a recommended connection diagram for the ADV101. The ADV101, and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. This ground plane should connect to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be located as close as possible (within 3 inches) to the ADV101. The layout should be optimized for lowest noise on the ADV101 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing. The analog ground plane should encompass all ADV101 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces and any output amplifiers. The regular PCB ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the ADV101. COMP C6 0.1µF R0 ANALOG POWER PLANE R7 VIDEO DATA INPUTS VAA G0 G7 L1 (FERRITE BEAD) C3 0.1µF B0 B7 C4 0.1µF R4 1kΩ C5 0.1µF VREF Z1 (AD589) ADV101 + 5V (VCC ) C1 33µF C2 10µF ANALOG GROUND PLANE GND GROUND RSET 560Ω R1 75Ω R2 75Ω R3 75Ω L2 (FERRITE BEAD) FS ADJUST CLOCK IOR VIDEO CONTROL INPUTS REF WHITE RGB VIDEO OUTPUT IOG SYNC ISYNC IOB BLANK COMPONENT C1 C2 C3, C4, C5, C6 L1, L2 R1, R2, R3 R4 RSET Z1 DESCRIPTION 33µF TANTALUM CAPACITOR 10µF TANTALUM CAPACITOR 0.1µF CERAMIC CAPACITOR FERRITE BEAD 75Ω 1% METAL FILM RESISTOR 1kΩ 1% METAL FILM RESISTOR 560Ω 1% METAL FILM RESISTOR 1.235V VOLTAGE REFERENCE VENDOR PART NUMBER FAIR-RITE 27430011 OR MURATA BL01/02/03 DALE CMF-55C DALE CMF-55C DALE CMF-55C ANALOG DEVICES AD589JH Figure 8. Typical Connection Diagram and Component List –10– REV. B ADV101 Power Planes Digital Signal Interconnect The PC board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. The analog power plane should encompass the ADV101 (VAA) and all associated analog circuitry. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 8. This bead should be located within three inches of the ADV101. The digital signal lines to the ADV101 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV101 should be avoided so as to minimize noise pickup. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV101 power pins, voltage reference circuitry and any output amplifiers. The PCB power and ground planes should not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. Supply Decoupling Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors. (See Figure 8.) Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. It is important to note that while the ADV101 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and the main PCB. Alternatively, consideration could be given to using a three-terminal voltage regulator. REV. B Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane. Analog Signal Interconnect The ADV101 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV101 so as to minimize reflections. Additional information on PCB design is available in an application note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from Analog Devices, publication number E1309–15–10/89. –11– ADV101 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C1380–24–4/90 44-Terminal Plastic Leaded Chip Carrier (P-44A) PRINTED IN U.S.A. 40-Pin Plastic DIP (N-40A) –12– REV. B