TOSHIBA TC90A92AFG

TC90A92AFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A92AFG
3D comb & Video Decoder
TC90A92AFG is a 1chip LSI of 3 dimensional Y/C separation and color decoder.
TC90A92AFG has 10bit A/D converter and 8bit A/D converter for analog Video signal and 1H component signal.
and it also has 4Mbit DRAM for NTSC 3D comb. In case of PAL system, 3 line comb is available.
The internal color decoder is adaptive to multi color system.
Feature
• Multi color system
• Input I/F ：CVBS / S / YCbCr
• 3DYCS ：NTSC system
• 3lineYCS+3D YNR/CNR : Multi color system
（SECAM：BPF YCS）
• Output I/F ：656 / 601
• Picture improvement
Y ：Vertical enhance / LTI / Contrast / Set up adjust
C ：TOF / ACC / Color decode /
Color gain /CTI / offset adjust
QFP100-P-1420-0.65Q
Mass : 1.6g (TYP)
• S/N detection / ID1 data slice / CCD data slice
2
• I C bus control
• Package：QFP 100
• Power supply：1.5V，2.5V，3.3 V
Version 1.5
TOSHIBA is continually working to improve the quality and the reliability of its product. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to
observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA
product could cause loss of human life, bodily injury or damage to property. In developing your
designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth
in the most recent products specifications. Also, please keep in mind the precautions and conditions
set forth in the TOSHIBA Semiconductor Reliability Handbook.
Aug./2003
1
TC90A92AFG
1. Block diagram
42M
X'tal
HD/VD
D/A
Sync Sep.
Clock
Gene.
×8
Timing
reference
clock
Clamp
27M
10bit ADC
CVBS/Y
Vertical enhance
LTI
contrast adust
delay adjust
3line
comb
27M
→4fsc
ID1
S/N detection
CCD slice
3D comb
4M
DRAM
656/601
Format
ITU-R656
encodｅ
ＡＣＣ
color decord
ＴＩＮＴadjust
Color adjust
Motion
Det.
MPX
Cb
Cr
SW
C
27M
8bit ADC
IIC-BUS
Digital I/F
SCL SDA
2. Pin layout
Analog input I/F
VRTYAD
BIASYAD
VRMYAD
3 VCOFIL
OEPK
4 VSSPLL
80
79
78
77
5 VDDXO
VDOUT
76
6
XOIN
HDOUT
75
7
XOOUT
COUT9
74
TC90A92AFG
8 VSSXO
9
BUSSEL
1 1 DIN9
DVSS5 7 3
Top view
1 2 DIN8
1 3 DIN7
COUT8
72
COUT7
71
DVDD5
70
COUT6
69
COUT5
68
1 4 DVSS12
VSSIO3 6 7
1 5 DIN6
COUT4
66
1 6 DIN5
COUT3
65
1 7 DVDD2
VDDIO3 6 4
1 8 DIN4
COUT2
DVSS4
63
1 9 DIN3
2 0 VSSRAM1
COUT1
61
2 1 VDDRAM1
COUT0
60
2 2 DIN2
DVDD4
59
2 3 DIN1
CKOUT
58
2 4 VDDIO1
YOUT0
57
2 5 DIN0
YOUT1
56
2 6 GC14IN
YOUT2
55
2 7 VSSIO1
YOUT3
54
62
3 1 3 2 3 3 3 4 35 36 37 38 3 9 4 0 4 1 4 2 43 44 45
YOUT4
VSSRAM2
YOUT5
YOUT6
YOUT7
VSSIO2
YOUT8
YOUT9
VDDIO2
TESTM6
DVSS3
VDDRAMD1 5 3
VSSRAMD1 5 2
TESTM5
TESTM4
DVDD3
TESTM3
TESTM2
SCL
SDA
3 0 RESET
TESTM1
2 9 TESTM0
CSYNC IN
2 8 TESTIN
Aug./2003
YCLAMPP
VBI READY
UVFLAG
output I/F
YIN
VSSYAD
VDDYAD
VRBYAD
BIASCAD
CIN
VRTCAD
Cr IN
VDDCAD
Cb IN
85 84 83 82 81
2 PLLIN
1 0 DVDD1
Digital inut I/F
VSSCAD
VDDDA
VRBCAD
DAOUT
VSSDA
9 9 9 8 9 7 9 6 95 94 93 92 9 1 9 0 8 9 8 8 87 86
BIASDA
1 VDDPLL
10
0
VREFDA
42M XO X8PLL
NCO DAC
VDDRAM2
51
46 47 48 49 50
Output I/F
2
TC90A92AFG
3. Terminal description
Pin
No. Pin Name
1
2
3
4
5
6
7
8
9
VDDPLL
PLLIN
VCOFIL
VSSPLL
VDDXO
XOIN
XOOUT
VSSXO
BUSSEL
10 DVDD1
11 DIN9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DIN8
DIN7
DVSS12
DIN6
DIN5
DVDD2
DIN4
DIN3
VSSRAM1
VDDRAM1
DIN2
DIN1
VDDIO1
DIN0
GC14IN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VSSIO1
TESTIN
TESTM0
RESET
SDA
SCL
TESTM1
TESTM2
TESTM3
DVDD3
TESTM4
CSYNCIN
DVSS3
TESTM5
TESTM6
VDDIO2
YOUT9
44
45
46
47
48
49
50
YOUT8
VSSIO2
YOUT7
YOUT6
YOUT5
YOUT4
VSSRAM2
Aug./2003
Function
Power supply for X8 PLL circuit
Input terminal of X8 PLL circuit
Filter terminal for X8 PLL circuit
GND for X8 PLL circuit
Power supply for X’ tal OSC circuit
X’ tal OSC circuit input terminal
X’ tal OSC circuit output terminal
GND for X’ tal OSC circuit
Select IIC slave address
（L：B0 Hi：B2）
Power supply for Logic circuit
Composite video signal digital input terminal
(MSB) （DIN0∼DIN9：input terminal for GR）
（In case not use :DIN0-9 are connected to GND）
Composite video signal digital input terminal
GND for Logic circuit
Composite video signal digital input terminal
Power supply for Logic circuit
Composite video signal digital input terminal
GND for internal DRAM
Power supply for internal DRAM
Composite video signal digital input terminal
Power supply for I/O
Composite video signal digital input terminal
External 4fsc clock input terminal for
Using DIN0-9 terminal
（In case not use : connect to GND）
GND for I/O
Clock terminal for Test mode
Terminal for Test mode
Reset terminal (Low :Reset Hi :normal)
Ｉ
Ｉ
Ｃ ＳＤＡterminal (5V input possible）
Ｉ
Ｉ
Ｃ ＳＣＬterminal (5V input possible)
Terminal for Test mode
Power supply for Logic circuit
Terminal for Test mode
External composite Sync signal input
GND for Logic circuit
Terminal for Test mode
Power supply for I/O
Digital video port output（MSB）
（656/ 601 8bit mode：
YCbCr 601：
Y）
Digital video port output8
GND for I/O
Digital video port output7
Digital video port output6
Digital video port output5
Digital video port output4
GND for internal DRAM
Durabl
e
I/O
voltage
(V)
2.5
VDD
2.5
IN
2.5
Bypass
0
GND
3.3
VDD
3.3
IN
3.3
OUT
0
GND
3.3
IN
Circuit
System
(Analog or
Digtal)
Analog
Analog
Analog
Analog
Digital
Digital
Digital
Digital
Digital
DC of
standard
operation
（Ｖ）
2.5
1.25
1.2
0
3.3
0
-
Analog signal
effective level
（Vp-p）
0.5∼VDDPLL*0.8
-
1.5
3.3
VDD
IN
Digital
Digital
1.5
-
-
3.3
3.3
0
3.3
3.3
1.5
3.3
3.3
0
1.5
3.3
3.3
3.3
3.3
3.3
IN
IN
GND
IN
IN
VDD
IN
IN
GNG
VDD
IN
IN
VDD
IN
IN
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
0
1.5
0
1.5
3.3
-
-
0
3.3
3.3
3.3
5
5
3.3
3.3
3.3
1.5
3.3
5
0
3.3
3.3
3.3
3.3
GND
IN
IN
IN
I/O
IN
IN
IN
IN
VDD
IN
IN
GND
IN
IN
VDD
OUT
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
0
0
0
3.3
0
0
0
1.5
0
0
0
0
0
3.3
-
-
3.3
0
3.3
3.3
3.3
3.3
0
OUT
GND
OUT
OUT
OUT
OUT
GND
Digital
Digital
Digital
Digital
Digital
Digital
Digital
0
0
-
3
TC90A92AFG
Pin
No. Pin Name
51
52
53
54
55
56
VDDRAM2
VSSRAMD1
VDDRAMD1
YOUT3
YOUT2
YOUT1
57 YOUT0
58 CKOUT
59 DVDD4
60 COUT0
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
COUT1
DVSS4
COUT2
VDDIO3
COUT3
COUT4
VSSIO3
COUT5
COUT6
DVDD5
COUT7
COUT8
DVSS5
COUT9
HDOUT
VDOUT
OEPK
UVFLAG
VBIREADY
Function
Power supply for internal DRAM
GND for internal DRAM
Power supply for internal DRAM
Digital video port output
Digital video port output
(In case 8bit output mode : fixed to Low)
System Clock output terminal for digital video signal output
656 : 27MHz 601 : 13.5MHz
Power supply for Logic circuit
ＣbＣr digital video signal output (LSB）
（656：
fixed Low 601：CbCr）
（In case 16bit mode: LSB and 2’nd LSB are fixed Low)
GND for Logic circuit
ＣbＣr digital video signal output
Power supply for I/O
ＣbＣr digital video signal output
GND for I/O
ＣbＣr digital video signal output
Power supply for Logic circuit
ＣbＣr digital video signal output
95 VRBCAD
96 VDDDA
97 DAOUT
GND for Logic circuit
ＣbＣr digital video signal output （MSB）
Horizontal reference timing pulse
Vertical reference timing pulse
Field detection output / Pedestal pulse output
Reference pulse of multiplexed Cb/Cr signal
Reference pulse of IIC read for VBI data slice
Function (Hi level at 23 line and 286 line)
Clamp signal for YIN
The bias terminal for internal 10bit ADC
The reference top voltage terminal of internal
10bit ADC
The reference middle voltage terminal of
Internal 10bit ADC
GND for internal 10bit ADC
Analog CVBS/Y signal input terminal for
Internal 10bit ADC
Power supply for internal 10bit ADC
The reference bottom voltage terminal of
Internal 10bit ADC
The bias terminal for internal 8bit ADC
The reference top voltage terminal of
Internal 8bit ADC
Analog C signal input terminal for Internal
8bit ADC
Power supply for internal 8bit ADC
Analog Cr signal input terminal for Internal
8bit ADC
GND for internal 8bit ADC
Analog Cb signal input terminal for Internal
8bit ADC
The reference bottom voltage terminal of internal 8bit ADC
Power supply for internal DAC of NCO
Output terminal of DAC of NCO
98 VSSDA
99 BIASDA
100 VREFDA
GND for internal DAC of NCO
The bias terminal for internal DAC
The reference voltage terminal of DAC
80 YCLAMPP
81 BIASYAD
82 VRTYAD
83 VRMYAD
84 VSSYAD
85 YIN
86 VDDYAD
87 VRBYAD
88 BIASCAD
89 VRTCAD
90 CIN
91 VDDCAD
92 CRIN
93 VSSCAD
94 CBIN
Durabl
e
voltage
(V)
1.5
0
2.5
3.3
3.3
3.3
DC of
standard
operation
（Ｖ）
1.5
0
2.5
-
Analog signal
effective level
（Vp-p）
VDD
GND
VDD
OUT
OUT
OUT
Circuit
System
(Analog or
Digtal)
Digital
Digital
Digital
Digital
Digital
Digital
3.3
3.3
OUT
OUT
Digital
Digital
-
-
1.5
3.3
VDD
OUT
Digital
Digital
1.5
-
-
3.3
0
3.3
3.3
3.3
3.3
0
3.3
3.3
1.5
3.3
3.3
0
3.3
3.3
3.3
3.3
3.3
3.3
OUT
GND
OUT
VDD
OUT
OUT
GND
OUT
OUT
VDD
OUT
OUT
GND
OUT
OUT
OUT
OUT
OUT
OUT
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
0
3.3
0
1.5
0
-
-
3.3
2.5
2.5
OUT
Bypass
Bypass
Digital
Analog
Analog
0.8
1.75
-
2.5
Bypass
Analog
1.25
-
0
2.5
GND
IN
Analog
Analog
0
-
VDDYADx0.4
2.5
2.5
VDD
Bypass
Analog
Analog
2.5
0.75
-
2.5
2.5
Bypass
Bypass
Analog
Analog
0.8
1.75
-
2.5
IN
Analog
1.25
VDDCADx0.4
2.5
2.5
VDD
IN
Analog
Analog
2.5
-
VDDCADx0.4
0
2.5
GND
IN
Analog
Analog
0
-
VDDCADx0.4
2.5
2.5
2.5
Bypass
VDD
OUT
Analog
Analog
Analog
0.75
2.5
2
0
2.5
2.5
GND
Bypass
Bypass
Analog
Analog
Analog
0
0.9
1.5
VDDDA -VDDDA*0.
6
-
I/O
-
(Note) Please the capacitor of the power supply terminal and the BIASAD terminal is placed near the terminal.
Aug./2003
4
TC90A92AFG
4.1 Introduction
TC90A92AFG is a signal processor for normal scan (525i, 625i) signal.
1. TC90A92AFG has input interface for CVBS, S and component video signals.
2. TC90A92AFG has a 3D YCS function for M-NTSC signal with internal 4Mbit DRAM.
And in case of 3line YCS mode it is available to use 3D YNR & CNR function.
3. TC90A92AFG has a 3D YNR & CNR for S terminal input and 1H component signal.
4. TC90A92AFG has a digital input interface for Ghost reduction LSI.
5. TC90A92AGF has color decoder circuit for multi video system and cync separation circuit.
6. Selectable automatic color system detection mode and forced color system mode.
7. TC90A92AFG has picture quality improve function.
8. TC90A92AFG has ITUR-656 and 601 output interface.
9. TC90A92AFG has S/N detection, ID-1 data slice and CCD data slice function for M-NTSC and
it is available to read via IIC read mode.
4.2 Function
(1) Input stage
The input video signal (CVBS/S / YCbCr) is converted to digital video signal by internal A/D converter
of TC90A92AFG. TC90A92AFG generates the fH synchronous clock (27MHz) from the digital video signal by
using
PLL circuit, H sync separation circuit and H sync regeneration circuit.
This clock is generated by internal digital VCO circuit which has 42MHz X’tal oscillation circuit as a reference
clock.
(2) Input interface
a) Setting for input mode
Input signal can be set via INSEL at sub address 00 hex.
INSEL : 00: CVBS 01: S input 10: YCbCr 11: GR digital input
b) Dynamic range of the internal ADC
TC90A92AFG has a 10bit ADC for analog CVBS, Y signal of S input and Y signal of component.
For color signal (chroma & CbCr), TC90A92AFG has a another 8bit ADC.
Dynamic range of the internal ADC is designed by AVDD×0.4(Reference level : 1Vp-p).
Recommend amplitude of analog video signal input is 0.7Vp-p (140IRE).
Aug./2003
5
TC90A92AFG
100
767
80
60
40
20
0
256
-20
-40
52
Fig-1 : YAD Input Level (Example : CVBS Input )
Fig-2 : CAD Input Level (Example : Cb Input Signal)
When using YCbCr mode, it is cautious of the input level to CAD (color system 8bit AD).
As shown in Fig-2, the standard input level of the CAD is 0.7Vp-p.
c) Clamping
The clamp control circuit controls the correct clamping of the analog input signals.
Clamp level for CVBS and Y signal is 256 LSB (10bit unit). For C and Cb/Cr are 128 LSB (8bit unit).
d) Cb /Cr input
Cb and Cr signals are multiplexed in front of internal 8bit ADC.
Offset adjustment is available independently.
Aug./2003
6
TC90A92AFG
(4) TV system detection for CVBS and S input
TV system auto detection is set via register [AUTODET] at sub address 00 hex.
00 : forced TV mode (color system is set via [TVM ] at sub address 00 hex.
It is fixed to color system which is selected by [Select FSC], [Select FV], [Select PAL], [Select SECAM].
When there is difference between selected TV system and input TV system, it can’t detect fsc signal for read
mode.
There is no relation to setting [Select FV] and input signal gives priority.
01 : European mode (fsc detection : 4.43MHz / 3.58MHz)
Color system is determined by result of vertical frequency detection, fsc detection, SECAM detection.
The order of priority for distinction is 4.43PAL, NTSC, SECAM, ACK.
10 : South American mode (fsc detection : 3.57954MHz /3.5756MHz /3.5820MHz)
Color system is determined by result of fsc detection, vertical frequency detection.
The order of priority for distinction is 3.58PAL, 3.58NTSC, ACK.
11 : full multi mode
Color system is determined by result of vertical frequency detection, fsc detection, SECAM detection.
The order of priority for distinction is PAL, NTSC, SECAM, ACK.
And the distinction of 50/60Hz are independently, there is no priority.
(In case of non signal, it keeps the value of last time.)
(5) Sync processing
TC90A92AFG has a H/V sync separation circuit and regenerates HD/VD pulse.
The phase of HD and VD signals are selectable. (Adapt to 656 format and synchronized with input signal
phase)
(6) Y/C separation and noise reduction
TC90A92AFG has an adaptive comb filter and noise reduction circuit.
M-NTSC : Motion adaptive 3D comb (The sensitivity of motion detection for Y & C are set independently.)
Other color system (Not M-NTSC and not SECAM) : 3D YNR and CNR after 3line comb
SECAM : BPF+3D YNR. 3D CNR is simple motion (Not edge detection).
The function is shown in a table-1.
TV signal
PAL
N PAL
SECAM
NTSC-50
Component-5
0
M NTSC
4.43NTSC
M PAL
PAL-60
SECAM-60
Component-6
0
Field
Frequenc
y
50Hz
60Hz
Input signal
CVBS
S
YCbCr
−
−
−
2DYCS+3DYNR+3DCNR
2DYCS or BPF+3DYNR+3DCNR
BPF +3DYNR
2DYCS or BPF+3DYNR+3DCNR
−
3DYNR+3DCNR
3DYNR+3DCNR
3DYNR
3DYNR+3DCNR
−
3DYCS
or
2DYCS+3DYNR+3DCNR
2DYCS or BPF+3DYNR+3DCNR
2DYCS or BPF+3DYNR+3DCNR
2DYCS or BPF+3DYNR+3DCNR
BPF +3DYNR
−
3DYNR+3DCNR
−
3DYNR+3DCNR
3DYNR+3DCNR
3DYNR+3DCNR
3DYNR
−
−
−
−
3DYNR+3DCNR
3DYNR+3DCNR
Table-1
Note : Field noise reduction for 625 system
Aug./2003
8
TC90A92AFG
(7) Take off filter (TOF)
TC90A92AFG has a take off filter in front of internal color decoder.
Characteristic of TOF is set via [TOF] at sub address 0F hex.
000 : OFF
001 : BPF for cross color reduction is active.
010 –111： type2 – type7
(8) Y process
a) Vertical enhance : available to set coring, gain and non-linear performance
b) LTI function
f0 is selectable (3.3MHz/ 2.2MHz).
Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE).
Gain is selectable (OFF/ x1/8 / x1/4 / x1/2).
c) Sharpness
f0 is selectable (4.2MHz/ 3.3MHz).
Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE).
Gain is selectable (OFF/ x1/8 / x1/4 / x1/2).
d) Noise chancellor
f0 is 4.2MHz.
Gain is selectable (OFF/ x1/4 / x1/2 / x1).
Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE).
LTI
＋
Sharpness
Noise cancel
ｆ
0/Gain/Coring
ｆ
0/Gain/Coring
e) Contrast
Control range is –6dB --- +7.6dB (The color becomes a saturation depending on input level.)
f) Brightness control
Control range is 0LSB ---+ 60LSB (10bit unit)
Brightness control is effective at the period of picture area.
(9) C process
a) ACC control : A reference level is set up by register ACC LEVEL. (Recommended value is under 3)
b) Killer control : sensitivity of killer is set via [COLOR KILL LEVEL] at sub address 0E hex.
In case Killer detection, comb filter for Y becomes off.
c) HUE control : Hue control is available for CVBS and C signal of NTSC system.
Hue bias : 0 --- +45degree
Hue range : -45 degree --- +43.6degree
Base band Tint control is available for component signal input mode.
Hue range : -45 degree --- +43.6degree
Aug./2003
9
TC90A92AFG
d)Sub color gain control
Amplitude of Cb and Cr signals are controlled via IIC.
Control range is –6dB --- +2.8dB
e)CTI function
f0 is selectable (1.7MHz/ 3.3MHz).
Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2IRE).
Gain is selectable (OFF/ x1/8 / x1/4 / x1/2).
f) Offset control of the period of picture area
The DC level of the Cb and Cr signals are controlled via IIC independently.
Control range : -8LSB ---- +7LSB (10bit unit)
(10) Output format
656 output mode / 601 output mode (CKOUT ：the polarity is selectable)
8bit mode /10bit mode selectable
Y ：pedestal = 16LSB (8bit unit)
C ：128LSB (8bit unit) (except the period of picture area)
It is selectable 601 or 656 format at sub address 01hex :D4 [FORMATO]
It can limit to the signal under 16LSB(in 8 bit) at sub address 23hex :D2 [CLP]
In case of standard 656 output, it is necessary to set to limit.
YOUT, COUT and CKOUT can be set Hi-Z mode via IIC.
Pin
YOUT [0-9]
Bit
8/10
Data rate
13.5MHz/27MHz
COUT [0-9]
8/10
6.75MHz
Aug./2003
Comment
601mode:Y signal
656 mode: YCbCr (CK:27MHz)
Cb/Cr (CK:13.5MHz)
10
TC90A92AFG
a) Vertical output timing
a-1 ) 525ｉ
/60Hz input
(first field)
ＣＶＢＳ
５２５
１
２
３
４
５
６
７
８
９
１０
…
１９
ＨＤＯＵＴ
Sync
through
Mode
656
Mode
ＶＤＯＵＴ
ＯＤＤ/ＥＶＥＮ
FIELD 1
ＶＤＯＵＴ
ＯＤＤ/ＥＶＥＮ
FIELD 1
(2n’d field)
ＣＶＢＳ
ＨＤＯＵＴ
Sync
through
ＶＤＯＵＴ
Mode
ＯＤＤ/ＥＶＥＮ
656
Mode
ＶＤＯＵＴ
ＯＤＤ/ＥＶＥＮ
Aug./2003
FIELD 2
FIELD 2
11
２０
TC90A92AFG
a-2 ) 625/50Hz input mode
（first, 3thd field）
ＣＶＢＳ
６２１
６２２
６２３
６２４
６２５
１
２
３
４
５
６
…
２２
２３
ＨＤＯＵＴ
ＶＤＯＵＴ
Sync
through
Mode
656
Mode
ＯＤＤ/ＥＶＥＮ
FIELD 1
ＶＤＯＵＴ
ＯＤＤ/ＥＶＥＮ
FIELD 1
(2’nd 4thd field)
ＣＶＢＳ
３０９
３１０
３１１ ３１２
３１３
３１４
３１５
３１６
３１７
３１８
３１９
…
３３５ ３３６
ＨＤＯＵＴ
Sync
through
ＶＤＯＵＴ
Mode
ＯＤＤ/ＥＶＥＮ
656
Mode
ＶＤＯＵＴ
ＯＤＤ/ＥＶＥＮ
FIELD 2
FIELD 2
Width of HD and VD pulse at Sync through mode
525
625
HD pulse
4.74us (128ck at 27MHz)
VD pulse
3H
2.5H
Width of HD pulse at 656 format is the same as the period between EAV and SAV.
In case of input signal is non standard at 656 format, it may not be above value.
Aug./2003
12
TC90A92AFG
(11) Feature function
a) S/N detection
Noise detection is performed in the vertical blanking period. Detection is performed at every field and the data
is updated each field. A S/N detection result is 8bit data and it can be read via IIC.
b)ID-1 data slice function
TC90A92AFG has a data slice circuit for ID-1 signal at the line 20 and 283.
Sliced data can be read via IIC.
This function is only output of sliced data level.
It is necessary to check a continuation of signal between some fields for ID-1 signal detection.
c) CCD data slice function
TC90A92AFG has a data slice circuit for closed caption data at the line 21 and 284.
CRI detection, start bit detection and sliced data can be read via IIC.
VBI READY (Pin79) is a reference timing pulse for S/N detection and VBI data slice function.
VBI READY outputs Hi pulse at the line 23 and 286.
d)Others
TC90A92AFG has IIC read registers.
50/60Hz detection/ signal detection / V sync detection / locked unlocked detection / 4.43MHz fsc detection
/ PAL detection / SECAM detection / Killer detection
Aug./2003
13
TC90A92AFG
5.IIC BUS
The slave address of TC90A92AFG can use two, B0hex and B2hex. A slave address is chosen by BUS SELL of
a terminal 9 (BUS SELL=L:B0hex , BUS SELL=H:B2hex).
In addition to usual transmission, a transmission format can use continuation transmission and the auto
increment mode.
(a) Continuation transmission
（The sub-address of a register to change is specified. MSB of a sub-address is set to 0 at this time.）
S
Slave
ADD
0
A
Sub ADD a
A
DATA 7-0
A
Sub ADD b
A
DATA 7-0
A
(b) Auto increment
（The increment of the sub-address is carried out one by one from N. MSB of a sub-address is set to 1 at this time.）
S
Slave
ADD
0
A
Sub ADD n
A
(Sub ADD n+1）
DATA 7-0
A
DATA 7-0
A
(c) IIC read
If it sets to 1 for LSB of slave address , it can read data.
It starts data output from TC90A92AFG after
TC90A92F is the master and the micro controller is slave.
To suspend transmission, deliberately generate an acknowledge error.
S
Aug./2003
Slave ADD (R)
0
A
DATA 07-00
A
DATA 0F-08
A
DATA 17-10
A
DATA 1F-18
A
14
TC90A92AFG
I2C BUS control format outline
The BUS control format of TC90A92F is based on the PHILIPSI2C BUS control format.
Data transmission format
S
Slave Address
↑
0 A
Sub Address
A
↑ 8bit
↑ 8bit
7bit
(1) Start conditions, Stop conditions
(2) Bit transmission
SDA
SCL
S: Start conditions
P: Stop conditions
A: Acknowledgement
MSB
MSB
MSB
A P
Data
SDA
S
P
Start conditions
SCL
Stop conditions
SDA is not changed.
SDA is changed.
(3) Acknowledgement
SDA from a master
SCL from a master
S
High impedance
1
8
9
A6 A5 A4
1 0 1
1
A6 A5 A4
1 0 1
A3 A2 A1 A0 R/W
1 0 0 0
X
A3 A2 A1 A0 R/W
1 0 0 0
X
Start conditions
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights
to use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.
Aug./2003
15
TC90A92AFG
IIC BUS MAP
Sub
00H
D6
INSEL
Select input signal
00:CVS (Composite Signal）
01:Y/C （
Y/C Sep. Signal）
10:YCbCr （Component signal）
11:4fsc Data （Digital Signal）
INIT:03H
01H
Aug./2003
D7
3D DET
Preset mode
D5
D4
TVM3
TVM2
Select FSC
Select FV
0：3.58MHz
0：60Hz
1：4.43MHz
１：50Hz
0000：NT358
0100：NT50
0001：don’t use 0101：don’t use
0010：PAL-M
0110：PAL-N
0011：don’t use 0111：don’t use
YCS Mode
YCS mode
D3
TVM1
Select PAL
0：Not PAL
1：PAL
1000：NT443
1001：SEC60
1010：PAL60
1011：don’t use
FORMATO
Output format
D2
TVM0
Select SECAM
0：Not SECAM
1：SECAM
1100：don’t use
1101：SECAM
1110：PAL
1111：don’t use
OUTBITS
D1
D0
AUTODET
Set detection mode for
Video System
00:Manual （00h-D5-D2）
01:European
10:South America
11:Full multi
HIZMODE
Output control
ADPWD
16
TC90A92AFG
Sub
10H
D6
D5
D4
D3
D2
D1
D0
ACMSLP
ACSSLP
AYMSLP
AYSSLP
C slope at 1F (motion scene)
C slope at 1F (still picture scene)
Y slope at 1F (motion scene) Y slope at 1F (still picture scene)
INIT:5DH
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
11H
ACMESET
ACMFSET
ACSESET
ACSFSET
C offset at 1F(edge，motion)
C offset at 1F (flat，motion)
C offset at 1F (edge，still)
C offset at 1F (flat，still)
INIT:AAH 00：still pixel∼11：motion pixel 00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
12H
AYMESET
AYMFSET
AYSESET
AYSFSET
Y offset at 1F(edge，motion)
Y offset at 1F (flat，motion)
Y offset at 1F (edge，still)
Y offset at 1F (flat，still)
INIT:AAH 00：still pixel∼11：motion pixel 00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
13H
BCMSLP
BCSSLP
BYMSLP
BYSSLP
C slope at 2F (motion scene)
C slope at 2F (still picture scene)
Y slope at 2F (motion scene) Y slope at 2F (still picture scene)
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
00：x1/2 ∼ 11：∞
INIT:49H
〔YCSﾓｰﾄﾞのみ有効 〕
〔YCSﾓｰﾄﾞのみ有効 〕
14H
BCMESET
BCMFSET
BCS ESET
BCSFSET
C offset at 2F(edge，motion)
C offset at 2F (flat，motion)
C offset at 2F (edge，still)
C offset at 2F (flat，still)
INIT:51H 00：still pixel∼11：motion pixel 00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
15H
BYMESET
BYMFSET
BYSESET
BYSFSET
Y offset at 2F(edge，motion)
Y offset at 2F (flat，motion)
Y offset at 2F (edge，still)
Y offset at 2F (flat，still)
00：still pixel∼11：motion pixel 00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
00：still pixel∼11：motion pixel
INIT:F5H
16H
BCMUP
CECMP
CSCMP
C 2F Motion
The reference level for C edge detection
The reference level for C signal detection
detection
0：ON
000：
small ∼ 111：large
0000：small ∼ 1111：large
INIT:C3H
1：OFF
〔for NR mode 〕
17H
F1HER
F1VER
MREF
Level for Y horizontal edge
Level for Y vertical edge
The reference level for scene detection
00：OFF
10：3 IRE
00：OFF
10：5 IRE
0000：small ∼ 1111：large
INIT:A4H 01：6 IRE
11：1.5IRE
01：12 IRE
11：2 IRE
18H
CDEYE
YDEYE
MDS
3DSTD
Reference level for scene det. Reference level for scene det. Y
Forced det.
Forced det.
C
00：8%
10：24%
00：8%
10：24%
0：normal Fixed to [0]
Fixed to [0]
0：normal
INIT:10H 01：16%
11：32%
01：16%
11：32%
1：still
1：std sig.
19H
2ASS
2ASEL
2ALEV
2ASSCM
CROS
2F motion det. 2F motion det.
2F motion det. judgment level
2F motion det. of C motion
Reduce
Correction
Select
Cross color
0：OFF
0:Y
000:OFF
00:motion pixel ∼ 11:still pixel
0:ON
INIT:BEH
1：ON
1:C
001:motion pixel ∼ 111:still pixel
1:OFF
1AH
CHLPF
YDCLOFF
YDNRW
CDNRW
YDCMP[3:0]
Band width NR
Sensitivity Y
Sensitivity C
The reference level Y motion detection for 〔NR〕
Non correlation Non correlation
0: wide
0：OFF
0：large
0：large
0000:motion ∼ 1111:still〔1000〕
INIT:08H
1: narrow
1：Non-linear
1：small
1：small
1BH
HDAMP1
HD GAIN1
Time constant 1 for H PLL
Loop gain 1 for H PLL
INIT:89H
000：large ∼ 111：
small
00000：
small ∼ 11111：large
1CH
HDAMP2
HDGAIN2
Time constant 2 for H PLL
Loop gain 2 for H PLL
INIT:88H
000：large ∼ 111：
small
00000：
small ∼ 11111：large
1DH
HDAMP3
HDGAIN3
Time constant 3 for H PLL
Loop gain 3 for H PLL
INIT:A2H
000：large ∼ 111：
small
00000：
small ∼ 11111：large
1EH
SHCTRL
MUTE
C MUTE
H Reference
Mute
Chroma mute
100000：
-4.74μｓ ∼ 000000：
±0μｓ ∼ 011111：+4.46μｓ
0：OFF
0：OFF
INIT:00H
1：ON
1：ON
1FH
DOT DIST
COMB+
1LINE DOT
BCFOFF
CGAIN
Reduce H dots
BSRC filter
Ｙtrap performance for SECAM
00：OFF
10：ｘ0.17
0：OFF
0:ON
0: ON
000：OFF ∼ １１１：
×0.875 (INT:110)
INIT:FEH
01：ｘ0.16
11：ｘ0.18
1：ON
1:OFF
1:OFF
Aug./2003
D7
17
TC90A92AFG
Sub
20H
INIT:8BH
21H
INIT:80H
22H
INIT:90H
23H
INIT:0AH
24H
INIT:00H
25H
INIT:03H
D6
D5
D4
ID1DLY
The start timing of Ｉ
Ｄ１data slice
００００：Falling edge of H +１．４８μｓ ∼ （300ｎｓunit）
8OUTLSB
D1
D0
CCDSBH
CCD start bit (H pulse period)
1111:30CK∼0000:0CK (*CK=74ns)
FIV
FON
Field for
CCD slice
Fixed [0]
［0］
：Normal
Fixed [1]
Fixed [0]
Fixed [1]
Fixed [1]
CCD slice
action
［1］
：ON
0:EVEN
0:both field
1:ODD
1:FIV
EN_NOISEH_S
EN_NOISEH_W
SSMSB
AUTO
The horizontal start timing of S/N detection
The horizontal width of S/N detection
CCD slice
000：35.7uS ∼ 100：+40.5uS ∼ 111：44uS
000：10.2uS ∼ 100：14.9uS ∼ 111：18.5uS
Fixed to[1]
0:Auto
(1step: 32/27MHz)
(1step: 32/27MHz)
1:manual
EN_NOISEV_S
EN_NOISEV_W
CLP
BYFOFF
BLMT
Adjustment for S/N detection start line
S/N detection line number
16LSB limit
BSRY filter
V sepa.
(Ex. NTSC mode)
(output)
Limit
2Fh(D3)=0, 000：12th line∼111：
18th line
00：1H、01：2H、10：3H、11：4H
0:OFF
0:ON
0: 1/8
2Fh(D3)=1, 000：7th line∼111：13th line
1:ON
1:OFF
1: 1/16
HDPH
VDPH
Adjustment Horizontal phase
Adjustment vertical phase
1000：-1.185uS ∼ 0000：0uS ∼ 0111：+1.04uS
0000：0H ∼ 1111：+15H
VPHS
CADSWREV
HDST
SELCK
VDOUT adjustment (601 mode)
Cb/Cr Input
HDOUT adjustment (601)
CKOUT frequency
110:384w
011:192w
000:0w
0：Pin92=Cr- IN,
10:TEST
00:13.5MHz
111:don’t use
100:256w
001:64w
(See p.23)
11:13.5MHz
01::27MHz
Pin94=Cb- IN
101:320w
010:128w 1：Pin92=Cb- IN,
64W=64/27MHz=2.4uS
Pin94=Cr-IN
PHPOLE
HDOUT
polarity
0: positive
1:negative
PVPOLE
VDOUT polarity
26H
D7
D3
D2
PFPOLE
THRHV
INVCK
SEL_BLK
YOLEVEL
HHKIL
Field
H,V-OUT
CKOUT
VBLK
Y Output
Half H killer
Polarity
through
Polarity
Level Select
0:positive
0:positive
0:656
0:positive
0:fixed value
0:x1.7
0：OFF
INIT:18H
1:negative
1:negative
1:through(601)
1:negative
1:through
1:x1.0
1：ON
27H
EN_PIXH_S
EN_PIXH_W
Adjustment horizontal signal processing (start phase)
Adjustment horizontal signal processing (period)
INIT:00H
1000：-1.185μｓ ∼ 0000：
center ∼ 0111：+1.04μｓ
1000：-1.185μｓ ∼ 0000：
center∼ 0111：+1.04μｓ
28H
EN_PIXV_S
EN_PIXV_A
COMB KILL
Adjustment vertical signal processing (start phase)
0：Manual
000：OFF
011：1∼23H 110：1∼26H
0000：line 10 ∼ 1111：line 25
1：
Auto
001：
１∼21H
100：1∼24H 111：
Auto
INIT:07H
010：1∼22H
101：1∼25H
(60:22H,50:23H)
29H
BFP_S
SEL_RDATA
Adjustment burst gate pulse start phas e
[0] Fix
Select read data
INIT:00H
0000：±0 ∼ 0111：+4.44μｓ(4/13.5M step)
(Reference the next page)
2AH
HBLK_S
HBLK_W
Adjustment HBLK start phase
Adjustment HBLK width
INIT:00H
1000：-2.37μｓ ∼ 0000：±0 ∼ 0111：+2.07μｓ
1000：-2.37μｓ ∼ 0000：±0 ∼ 0111：+2.07μｓ
2BH
FHST_S
FVST_S
Adjustment write timing for internal DRAM (horizontal)
Adjustment write timing for internal DRAM (vertical)
INIT:00H
1000：-2.37μｓ ∼ 0000：±0 ∼ 0111：+2.07μｓ
1000：-8H ∼ 0000：center ∼ 0111：+7H
2CH
EXTCLP
SEL77
ACKDET
IIRFIL
Adjustment horizon position fine tuning for exterior clamp
Pin77 Output
Detection
Cb/Cr output filter selection
（6.75MHz unit、Width 2.2us Fix）
change
method change
After input sync edge about +0.5μs ∼ about +3μs
0:ODD/EVEN 0:Level detection
00:Strong ∼ 10:weak
INIT:B2H
1000：+0.5μｓ ∼ 0111：+3μｓ
1:Clamp pulse 1:Gain detection
11:OFF
2DH
GCSFT
FBCLAMP
GC Input DC shift
F/B CLAMP
000000:０、1000000:-128lsb ∼ 0111111:+126lsb
0:Auto
INIT:01H
1:ON
2EH
HGCON12
HGCON21
Threshold from phase difference big to middle.
Threshold from phase difference middle to big.
INIT:48H
0000:OFF ∼ 1111:High
0000:OFF ∼ 1111:High
2FH
RBALT
RBCHG
YADFILON
NOISESEL
NOISEL
THRH_VD
ADC Output
The line select S/N detection VD out phase
Fixed [0]
Fixed [0]
13.5M Trap
Fixed [1]
for S/N
Line
(It is available
Fixed [1]
0:OFF 1:ON
detection
0 : CVBS/Y
when H-V is
Effective only
(See p.24)
1 : digital input Non-standard)
at the time
0:standard
INIT:00H
of a CVBS input
1:V-sep phase
Aug./2003
18
TC90A92AFG
READ MODE
07
｜
00
DET50
Field frequency
0：60Hz
1：50Hz
NOSIG
Sig.nal Det.
0：signal
1：no signal
NOVP
V-Sync Det.
0：V det.
1：non V
CFIELD
Field
0：ODD
1：EVEN
0F
｜
08
DET443
4.43Det.
0:non
1:4.43
PALDET
PAL Det.
0:not PAL
1:PAL
SECAMDET
SECAM Det.
0:not SECAM
1:SECAM
SEL_FSC
fsc detection
00:3.579545M
01:3.575611M
10:3.582056M
11:4.43M
17
｜
10
1F
｜
18
SNDET7
SNDET6
S/N detection
00000000：strong signal →
0
Fixed to [0]
TSLV7
27
｜
20
CFIELD
Field
0：ODD
1：EVEN
TSLV6
SNDET5
UNLOCK
H-PLL
0：un-locked
1：locked
SNDET4
H/VSTD
H-V std
0:std.
1:non-std.
CRI3DET
Fixed to [0]
Fixed to [0]
CKILL
Killer Det.
0:color
1:whit & black
FSCSTD
fsc std Det.
0:std
1:non-std
FSCLOCK
fsc lock
0:un-locked
1:lock
SNDET1
SNDET0
SNDET3
SNDET2
11111111：Weak signal（MSB：SNDET7）
SBDET
CCD SB Det.
0:NG
1:OK
TSLV5
CRI3DET
CCD CRI Det.
0:under 3ck
1:over 3ck
TSLV4
CRIN3
CRIN2
CRIN1
Number of CRI
TSLV3
TSLV2
CRIN0
(MSB)-----((LSB)
TSLV1
CCD Slice
Level
(MSB)
TSLV0
CCD Slice
Level
(LSB)
CCDD Character１
2F
｜
28
37
｜
30
3F
｜
38
47
｜
40
4F
｜
48
57
｜
50
CCD data
LSB
CCD data
CCDD Character２
CCD data
CCD data
MSB
IICR ID1[0]
Reference
Signal
Detection
0:OK
1:NG
IICR ID1[8]
ID1 bit7
(WORD2)
IICR ID1[1]
CRCﾁｪｯｸ
0:OK
1:NG
IICR ID1[2]
ID1 bit0
(WORD0)
IICR ID1[3]
ID1 bit2
(WORD0)
IICR ID1[4]
ID1 bit3
(WORD1)
IICR ID1[5]
ID1 bit4
(WORD1)
IICR ID1[6]
ID1bit5
(WORD1)
IICR ID1[7]
ID1 bit6
(WORD1)
IICR ID1[9]
ID1 bit8
(WORD2)
IICR ID1[10]
ID1 bit9
(WORD2)
IICR ID1[11]
ID1 bit10
(WORD2)
IICR ID1[12]
ID1 bit11
(WORD2)
IICR ID1[13]
ID1 bit12
(WORD2)
IICR ID1[14]
ID1 bit13
(WORD2)
IICR ID1[15]
ID1 bit14
(WORD2)
IICR ID1[16]
ID1 bit15
(CRC code)
IICR ID1[17]
ID1 bit16
(CRC code)
IICR ID1[18]
ID1 bit17
(CRC code)
IICR ID1[19]
ID1 bit18
(CRC code)
IICR ID1[20]
ID1 bit19
(CRC code)
IICR ID1[21]
ID1 bit20
(CRC code)
IICR ID1[22]
Fixed to[0]
IICR ID1[24]
ID1
Slice level
MSB［７］
IICR ID1[25]
ID1
Slice level
IICR ID1[26]
ID1
Slice level
IICR ID1[27]
ID1
Slice level
IICR ID1[28]
ID1
Slice level
IICR ID1[29]
ID1
Slice level
IICR ID1[30]
ID1
Slice level
IICR ID1[23]
Field det.
0:line 20
1:line 283
IICR ID1[31]
ID1
Slice level
LSB［０］
Select Read Data（29H：D1,D0）
The initial of Read Mode is “00”.
SEL_RDAT
1byte
2byte
A
00(Initial)
D1
D0
01
D1
D0
10
D1
D0
11
I3
I2
Aug./2003
3byte
4byte
5byte
6byte
7byte
8byte
9bite
N0
C3
I3
I1
C3
C2
I2
I0
C2
C1
I1
D1
C1
C0
I0
D0
C0
N0
N0
N0
I3
I3
C3
C3
I2
I2
C2
C2
10byte
11byte
I1
I1
C1
C1
I0
I0
C0
C0
19
TC90A92AFG
The explanation for IIC Bus
*Sub address 00h(D7-D6), 01h(D0) ADC power save mode
It can save the power automatically depending on the kind of input signal.
When it is not use the ADC, it can stop working ADC.
ADC Control 1 〔initial:00 〕
Sub 00h D7 D6
Input signal
Y-ADC
C-ADC
00
CVBS
Normal
Power save
01
Y/C
Normal
Normal
10
Component
Normal
Normal
11
Digital
Power save
Power save
Sub 01h D０
Input signal
Y-ADC
C-ADC
0
It does not depend on the
input signal.
Power down
Power down
Normal
Normal
ADC Control 2 〔initial:1 〕
1
*Sub address 01h(D7-D6) 3D DET
It can switch preset mode for motion detection.
00: Preset mode for 3D YC separation
01: Preset mode for 3D NR
10: 3 line comb mode (NR off)
11: manual mode (It is available sub address 10h – 1Ah)
*Sub address 01H(D5-D4) YC separation mode
YC separation mode 〔initial:00 〕
Sub 01h D5 D4
3.58M NTSC system
SECAM system
Other system
00
3DYCS
BPF YCS + 3DNR
3Line YCS + 3DNR
01
3Line YCS + 3DNR
BPF YCS + 3DNR
3Line YCS + 3DNR
10
BPF YCS + 3DNR
BPF YCS + 3DNR
BPF YCS + 3DNR
11
3Line YCS + 3DNR
BPF YCS + 3DNR
3Line YCS + 3DNR
・3DYCS: 3D YC separation
・3Line YCS: 3 line YC separation
・BPF YCS: Band Pass Filter YC separation
・3DNR: 3D Noise Reduction
Aug./2003
20
TC90A92AFG
*Sub address 16h(D7)
BCMUP
It can shift to motion seen for 2F motion detection of chroma signal.
If BCMUP is on, it can decrease a dot noise for continuous color change.
It must be attentive to increase a cross color noise when 2F motion detection for chroma is nearly motion.
*Sub address 19h 2F correction
It can control a phenomenon which the picture is in spite of still, it is treated as motion seen and appeared cross color
noise.
19h(D7) 0:2F correction off 1:2F correction on
19h(D6) select a judgment standard signal
0:Working as base on motion detection result for 2F Y
1:Working as base on motion detection result for 2F C
19h(D5-D3) Setting a judgment level for working this function
000:off (same D7=0)
001:It is little effect
:
:
111:It is much effect
19h(D2) Setting motion detection for 2F correction
00: Moving picture direction
:
11: Still picture direction
Sub address 19h(D0) CROS
In case of moving picture for high frequency of Y signal, it can reduce a cross color noise.
Aug./2003
21
TC90A92AFG
*Sub address 1Ah
Motion detection for 3DNR
1Ah(D7) Select a band width for NR working
0:Wide band (Recommended)
1:Narrow band
1Ah(D6)
When the picture is judged no color, it can control CNR motion detection for decreasing cross color noise.
0:motion detection for CNR is invalid.
1:Using still picture direction parameter
1Ah(D5) Setting non-correlation detection level for motion detection of Y
0:standard
1:two times of standard
1Ah(D4) Setting non-correlation detection level for motion detection of C
0:standard
1:two times of standard
1Ah(D3-D0) Setting Y signal moving amount judgment standard for NR
0000: Moving picture direction (There is little effect of decreasing cross color noise.)
:
1111: Still picture direction (There is many effect of decreasing cross color noise.)
*Sub address 1Fh(D5) COMB+
It has an effect as below for PAL system.
When the horizontal lines of the front and the rear have color and edge element, and the horizontal line of center has no
color, it drops Y signal level for calculated result. Therefore it occurs dots of black in spite of white and gray picture.
When COMB+ is on, it can decrease this noise.
Aug./2003
22
TC90A92AFG
*Sub address 24h Regarding digital output
24h(D7-D4) Setting horizontal phase for HDOUT
When sync signal is the same timing as HDOUT, the difference phase is 0us.
24h(D3-D0) Setting vertical phase for VDOUT
When vertical phase is 0H, timing diagram is as below.
This is available for H,V-OUT through mode. (26h:D4=1)
ＣＶＢＳ
ＨＤＯＵＴ
ＶＤＯＵＴ
*Sub address 25h(D7-D5) VPHS: Setting VDOUT phase
When H,V-OUT through mode is on, it can shift VDOUT phase to horizontal direction. (2.4us step)
*Sub address 25h(D3-D2) HDST: Setting HDOUT phase
When H,V-OUT through mode is on, it can shift HDOUT phase.
It can delay HDOUT pulse from EAV based on standard.
Regarding 525 lines system
HDOUT phase (Default)
It is 32W from first point of EAV. (1W=1/27MHz)
HD width is about 4.73us. (128ck 1ck=1/27MHz)
00:32W(default) , 01:+4ck , 10:+8ck , 11:+16ck
Regarding 625 lines system
HDOUT phase (Default)
It is 24W from first point of EAV. (1W=1/27MHz)
HD width is about 4.73us. (128ck 1ck=1/27MHz)
00:24W(default) , 01:+4ck , 10:+8ck , 11:+16ck
*Sub address 26h(D5) PFPOLE,(D2) SEL_BLK
26h(D5) Setting field polarity
When the polarity is positive, 1st field is low.
26h(D2) the disposal of blanking period
0:It is masked the signal under pedestal level.
1:Through
Aug./2003
23
TC90A92AFG
*Sub address 2Fh(D5) 13.5M Trap
It can decrease the interference with 13.5MHz regarding to fh frequency and 14.3MHz regarding to fsc frequency.
0:OFF
1:ON (In this case, it needs to revise high frequency as below.)
(The relation resister)
Sub address 1Eh(D7-D2) Horizontal reference
When input signal is CVBS, it needs to shift 1 step. (000000→111111)
Sub address 04h(D1) Sharpness fo
Sub address 05h(D7-D6) Sharpness gain
If sharpness fo = 4.2MHz and sharpness gain = x1/8, the frequency characteristic is the same as trap-off.
*Sub address 22h、Sub23h、2Fh(D3) Regarding noise detection
22h(D7-D5) Horizontal start phase from under direction edge of H sync
22h(D4-D2) Horizontal width
23h(D7-D5) Vertical start phase
23h(D4-D2) Vertical line number select
【1-A】When sub address 2Fh (D3)=0, it is the start line number.
Sub address 23h (D7-D5)
000
001
010
011
100
101
110
111
ODD FIELD
NTSC (Line number)
PAL (Line number)
12
9
Non detection
10
13
11
14
12
15
13
16
14
17
15
18
16
EVEN FIELD
NTSC (Line number)
PAL (Line number)
274
321
275
322
276
323
277
324
278
325
279
326
280
327
281
328
【1-B】When sub address 2Fh (D3)=1, it is the start line number.
Sub address 23h (D7-D5)
000
001
010
011
100
101
110
111
Aug./2003
ODD FIELD
NTSC (Line number)
PAL (Line number)
7
4
8
5
9
6
10
7
11
8
12
9
Non detection
10
13
11
EVEN FIELD
NTSC (Line number)
PAL (Line number)
269
316
270
317
271
318
272
319
273
320
274
321
275
322
276
323
24
TC90A92AFG
【Fig4】The line number for vertical period
NTSC (525Line/60Hz) 1st Field (odd)
524
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
NTSC (525Line/60Hz) 2nd Field (even)
261
262
263
264
265
266
PAL (625Line/50Hz) 1st Field (odd)
621
622
623
624
625
1
PAL (625Line/50Hz) 2nd Field (even)
308
309
310
311
312
313
337
*Sub address 2Fh(D2) Signal select for noise detection
Aug./2003
25
TC90A92AFG
【Fig.5】
TC90A92AFG the band limit characteristic
for color decoder （
NTSC）
（Marker：3.58M，4.286M，4.43MHz）
10
Gain (dB)
5
0
-5
-10
-15
-20
0
1
2
3
4
Frequency （MHｚ
）
5
6
7
TC90A92AFG the band limit characteristic
for color decoder（
PAL）
（Marker：3.58M，4.286M，4.43MHz）
10
Gain (dB)
5
0
-5
-10
-15
-20
0
1
2
3
4
Frequency （MHｚ
）
5
6
7
*Sub address 2Fh(D1) VD out phase select when H-V is non-standard and H,V-OUT is through mode.
0: standard phase (VD output after counted standard line number)
1: VD output as base on result of V-sep
*Sub address 21h(D6) 8OUTLSB
It can reduce quantization noise when 10 bit signal convert to 8 bit at output stage.
This effect changes in GND condition.
When output signal is 10 bit, it needs to set to normal mode.
0: Normal
1: ON (Quantization noise reduction is active.)
Aug./2003
26
TC90A92AFG
MAXIMUN RATINGS（Vss=0V, Ta=25℃）
Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes
damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating.
CHARACTERISTIC
Power Supply Voltage1（1.5V System）
Power Supply Voltage2（2.5V System）
Power Supply Voltage3（3.3V System）
Input Voltage
Potential difference between power
terminals （1.5V System）
Potential difference between power
terminals （2.5V System）
Potential difference between power
terminals （3.3V System）
Potential difference between power
terminals （1.5V System＞2.5V System）
Potential difference between power
terminals （2.5V System ＞3.3V System）
Power Dissipation
Storage Temperature
SYNBOL
VDD1
VDD2
VDD3
VIN
SDA/SCL(Note1)
A IN
supply VDG1（Note2）
UNIT
RATING
V
-0.3 ∼ VSS+2.0
V
-0.3 ∼ VSS+3.5
V
-0.3 ∼ VSS+3.9
-0.3 ∼ VDDIO +0.3 V
V
-0.3 ∼ VSS + 5.5
V
-0.3 ∼ VDDAD
0.3
V
supply VDG2（Note2）
0.3
V
supply VDG3（Note2）
0.3
V
supply
VDG4（Note2）
0.3
V
supply VDG5（Note2）
0.3
V
1530
-40 ∼ 125
mW
℃
PD(Note3)
Tstg
(Note1) SDA，SCL： 5V tolerance.
(Note2) 1.5V system power supply terminal is made into the same voltage, 2.5V system power
supply terminal is made into the same voltage, and 3.3V system power supply terminal
is made into the same voltage.
The maximum potential difference should not exceed rating for all power supply
terminals then.
(Note3) Derated above Ta=25℃ in the proportion of 15.3mW/℃.
Recommendation operation conditions（Vss=0V）
Cannot guarantee operation of TC90A92F, when the recommendation power supply voltage
range (1.35V-1.65V, 2.3V-2.7V, 3.0V-3.6V) is exceeded.
Once, when it returns from the over range, it differs from a front condition.
When the memory block exceeds the range especially,
it is necessary to once bring down a power supply and to newly rise.
CHARACTERISTIC
Terminal No.
SYNBOL
MIN
TYP
MAX
Supply Voltage for digital block 10,17,36,59,7
DVDD1-5
1.35
1.5
1.65
UNIT
V
0
Supply Voltage for I/O block
24,42,64
Supply Voltage for DRAM block 21,51
Supply Voltage for DRAM block 53
Supply Voltage for XO block
5
Supply Voltage for PLL block
1
Supply Voltage for Analog block 86,91,96
Ambient operating temperature
-
Aug./2003
VDDIO1-3
VDDRAM1
VDDRAM2
VDDXO
VDDPLL
VDDAD/VDDDA
Ta
3.0
1.35
2.3
3.0
2.3
2.3
-10
3.3
1.5
2.5
3.3
2.5
2.5
−
3.6
1.65
2.7
3.6
2.7
2.7
75
V
V
V
V
V
V
℃
27
TC90A92AFG
The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling
(1)Power Supply rising
These contents are the important items which influence the reliability guarantee of the IC.
It is necessary to satisfy the following condition.
(1) Power rising condition
3.3V (power range : 3.0 ∼3.6V)
more than 3.0V
*note1
VDD=3.3V
more than 0.4V
2.5V (power range : 2.3∼ 2.7V)
more than 2.3V
*note1
VDD=2.5V
more than 0.4V
1.5V (power range : 1.35∼ 1.65V)
*note1
VDD=1.5V
more than 1.35V
more than 0.4V
It needs to rise less than 40ms from starting to rise the power of 2.5V.
(using power on reset of DRAM )
(reset release)
Terminal 30： RESET
After all powers rising, it is necessary to keep resett ing more
than 0.5ms.
And it must not keep the reset conditions more than one minute.
IIC-Bus IN
Terminal31： SDA
Terminal 32：SCL
After reset release, it is necessary to be more than 100ns for
IIC BUS control starting.
*note1
Such the power terminal are embedded the protective diode.
It must not send a penetration electric current.
Condition:
Power level of 3.3V line ≧ Power level of 2.5V line ≧ Power level of 1.5V line
When the power level of 1.5V line is more than 0.4V, 3.3V line and 2.5V line must
reach the level of power more than 0.4V.
And when the power level of 2.5V line is more than 0.4V, 3.3V line must reach the
level of power more than 0.4V.
3.3V power
terminal
2.5V power
terminal
1.5V power
terminal
(2) Power falling condition
It is necessary to fall the power of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the power of 2.5V
line before 3.3V line is fallen.
It must not send a penetration electric current too.
Aug./2003
28
TC90A92AFG
ELECTRICAL CHARACTERRISTICS
(1) DC CHARACTERRISTICS
(Ta= -10∼75℃,VDD1=1.50±0.15V,VDD2=2.50±0.2V,VDD3=3.30±0.3V)
ITEM
Power
Supply
Current
Input
Voltage
Input
Current
Output
Voltage
Terminal No.
10,17,21,36,51,59,70
Symbol
IDD1
Min.
Typ.
Max.
30
42
55
Unit
mA
1,53,86,91,96
IDD2
60
75
95
mA
5,24,42,64
IDD3
10
25
40
mA
6,9,11,12,13,15,16,
18,19,22,23,25,26,
28,29,30,33,34,35,
37,40,41
31,32,38
VIH
VDDx0.8
VDD
V
6,9,11,12,13,15,16,
18,19,22,23,25,26,
28,29,30,33,34,35,
37,40,41
31,32,38
VIL
6,9,11,12,13,15,16,
18,19,22,23,25,26,
28,29,30,33,34,35,
37,40,41
31,32,38
IIH
6,9,11,12,13,15,16,
18,19,22,23,25,26,
28,29,30,33,34,35,
37,40,41
31,32,38
IIL
43,44,46,47,48,49,54,
55,56,57,58,60,61,63,
65,66,68,69,71,72,74
75,76,77,78,79,80
43,44,46,47,48,49,54,
55,56,57,58,60,61,63,
65,66,68,69,71,72,74
75,76,77,78,79,80
31
VOH
VDD3-0.6
VDD3
V
VOL
VSS
0.4
V
Aug./2003
VSS
-10
-10
VDD3x0.
2
10
10
V
μA
μA
Note
Sum total current of 1.5V
system power supply terminal
NTSC:Y/C IN, Color Bar Signal
Sum total current of 2.5V
system power supply terminal
NTSC:Y/C IN, Color Bar Signal
Sum total current of 3.3V
system power supply terminal
Changes with the loads of I/O.
I/O input terminal of
3.3V system
VDD=VDD3
I/O input terminal of
5.0V system
VDD=5.25V
I/O input terminal of
3.3V system
I/O input terminal of
5.0V system
3 I/O input terminal of
3.3V system
I/O input terminal of
5.0V system
I/O input terminal of
3.3V system
I/O input terminal of
5.0V system
I/O output terminal of
3.3V system
Load of 4mA inflow
I/O output terminal of
3.3V system
Load of 4mA inflow
I/O output terminal of
5.0V system
Load of 4mA inflow
29
TC90A92AFG
(2) AC CHARACTERRISTICS
(Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM
Symbol
Typ.
Max.
Unit
Note
AD input level for Y
VYIN
Min.
0.7
0.8
White 100% Signal
AD input level for C
VCIN
0.5
0.8
ADC differentiation error
ADC integration error
Output impedance
DLEa
ILEa
Zy
±4
±4
200
240
Vpp
Vpp
LSB
LSB
Ω
160
Cb/Cr input
(3) PLL CHARACTERRISTICS
(Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM
Symbol
Min.
Drawing-in frequency range
Operation input amplitude
ΔfckN
Vck
-50
0.3
Aug./2003
Typ.
Max.
Unit
Note
0.5
50
2.0
kHz
Vpp
Clock Amplitude:0.5Vp-p
Standard clock frequency input
30
TC90A92AFG
Application Circuit
LPF
LPF
BUF
BUF
2.5V
①
270k
1.5μ
1000p
100
3.3V
②
94
93
92
91
90
89
88
87
86
85
84
83
82
81
VSSDA
DAOUT
VDDDA
VRBCAD
Cb IN
VSSCAD
Cr IN
VDDCAD
CIN
VRTCAD
BIASCAD
VRBYAD
VDDYAD
YIN
VSSYAD
VRMYAD
VRTYAD
BIASYAD
1 VDDPLL
YCLAMPP 8 0
VBI READY 7 9
UVFLAG 7 8
VSSPLL
OEPK 7 7
5
VDDXO
VDOUT 7 6
HDOUT 7 5
6 XOIN
XOOUT
COUT9(MSB) 7 4
8 VSSXO
DVSS5 7 3
9 BUSSEL
COUT8 7 2
1 0 DVDD1
COUT7 7 1
1 1 DIN9(MSB)
DVDD5 7 0
TC90A92AFG
1 2 DIN8
47μ
②
COUT4 6 6
０ DIN5
0.01μ
1.5V
VSSIO3 6 7
1 5 DIN6
0.01μ
COUT3 6 5
GC INPUT Terminal
0.01μ
VDDIO3 6 4
1 8 DIN4
COUT2 6 3
1 9 DIN3
DVSS4 6 2
2 0 VSSRAM1
COUT1 6 1
2 1 VDDRAM1
COUT0 6 0
2 2 DIN2
DVDD4 5 9
2 3 DIN1
CKOUT 5 8
2 4 VDDIO1
YOUT0 5 7
2 5 DIN0(LSB)
YOUT1 5 6
2 6 GC14IN
YOUT2 5 5
2 7 VSSIO1
YOUT3 5 4
3.3V
②
0.01μ
1.5V
0.01μ
DVDD3
TESTM4
CSYNC IN
DVSS3
TESTM5
TESTM6
VDDIO2
YOUT9(MSB)
YOUT8
VSSIO2
YOUT7
YOUT6
YOUT5
YOUT4
VSSRAM2
VSSRAMD1 5 2
TESTM3
VDDRAMD1 5 3
2 9 TESTM0
TESTM2
2 8 TESTIN
TESTM1
②
SCL
47μ
3.3V
SDA
1.5V
0.01μ
COUT5 6 8
1 4 DVSS12
1 7 DVDD2
③
②
COUT6 6 9
1 3 DIN7
②
①
4
7
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
3 0 RESET
5V
可
4.7k
③
③
0.01μ
47μ
4.7k
0.01μ 2.5V
VDDRAM2 5 1
0.01μ
②
1.5V
3.3V
①
②
①
Aug./2003
560
0.01μ
95
BIASDA
0.01μ
96
100p
0.01μ
0.01μ
100μ
0.1μ
0.01μ
0.01μ
97
VREFDA
0.01μ
98
0.01μ
47μ
0.01μ
1.5V
0.1μ
99
47μ
②
0.1μ
①
47μ
0.01μ
47μ
18p
12p
100μ
2 PLLIN
1500ｐF
3 VCOFIL
0.01μ
3.3V
①
100
2.5V
0.1μ
0.01μ
①
①
100μ
100μ
4p
1.2k
①
0.1μ
2.5V
1.5k
18k
0.47μ
2.5V
0.01μ
BUF
2.5V
0.01μ
BUF
LPF
0.01μ
LPF
31
1.5V
TC90A92AFG
●PACKAGE DIMENSIONS
QFP100-P-1420-0.65Q
Aug./2003
32
TC90A92AFG
Marking
TOSHIBA
TC90A92AFG
JAPAN
Lot Code
Management Code of Factory
Explanation for lot code
Production management number
Weekly code
The first week of January is assigned the code number 01, the second
week 02 etc. The last week of December is either 52 or 53. This is
determined as follows.
Provided that the 1st January does not fall on a Friday or Saturday, the
week which runs from the final Sunday of the old year to the first
Saturday of the new year is designated as the first week of the new year
[01]. If the 1st January falls on a Friday or Saturday, the week which runs
from the final Sunday of the old year to the first Saturday of the new year
is designated as the 53rd week of the preceding year [53].
The year of manufacture
(The last two digits for AD)
Mold material: Epoxy resin
Lead material: Copper base alloy
Lead surface treatment: Palladium plating
Country of origin: Japan
Works: TOSHIBA Ooita Works
Aug./2003
33
TC90A92AFG
Packing of QFP100-P-1420 Tray
1.Device Holder
Unit: mm
Package Code
Maximum Number of Packed Product
QFP100 -P-1420-0.65
40 products/tray
200 products/carton
1200 products/container
2.Carton
(Inner size)
Silica gel
Indicator
338±3
Carton
43±1
Packing
132±1
Label
Moisture-proof package
(laminated aluminum)
Label
Label
3.Shipping Container
(Inner size)
161±3
Bar code
281±3
Aug./2003
367±3
Outer size W:291mm L:377mm
H:176mm
34