AGILENT HDMP-1687

Agilent HDMP-1687
Four Channel SerDes Circuit
for Gigabit Ethernet and
Fibre Channel
Data Sheet
Functional Description
The HDMP-1687 is a four channel
SERDES device. HDMP-1687 is in a
208-ball TBGA package with four
1.0625/1.25 Gbps serial I/O. This
integrated circuit provides a lowcost, low-power, small-form-factor
physical-layer solution for multi-link
Gigabit Ethernet/Fibre Channel
interfaces. This IC may be used to
directly drive copper cables, or it
may be used to interface with optical transceivers. Each IC contains
transmit and receive channel circuitry for all four channels.
The transmitter section accepts
10-bit-wide parallel TTL data on
each channel and serializes it into
a high-speed serial stream. The
parallel data is expected to be
8B/10B encoded (or equivalent).
Four banks of parallel data are
latched into the input registers of
the transmitter sections on the rising edge of RFCT.
Receive data are latched out with
separate clock pins for each channel. These pins may be single
106.25/125 MHz TTL clock outputs
RC [0:3] [1] or dual 53.125/62.5
MHz TTL pairs RC [0:3] [0:1] to
serve legacy applications where
single SerDes devices were used
before. The receive clock mode
select (RCM0) pin is used to define the designer’s choice.
RCM0 Receive Clock Mode
0
half speed dual clocks
1
full speed single clocks
The SYNC pin enables bytesync
detection on all four channels.
When a comma character is
detected on any channel, its corresponding SYN [0:3] pin goes high.
A single LOOP pin is provided for
all channels to enable the local
loopback function.
HDMP-1687 Block Diagram
The following is a description of
the blocks in each channel. Except for the transmit PLL section,
circuits for the channels are independent. Figure 1 shows how this
IC may be connected to a protocol
device that controls four channels.
Each channel of the four channel
SERDES (Figure 2) was designed
to transmit and receive 10-bitwide characters over dedicated
differential high-speed lines. The
parallel data applied to the transmitter is expected to be encoded
Features
• Four ANSI x3.230- 1994 Fibre Channel (FC-O) or IEEE 802.3z Gigabit
Ethernet compatible SerDes in
a single package
• Supports serial data rates of 1062.5
MBd (Fibre Channel) & 1250 MBd
(Gigabit Ethernet)
• Based on X3T11 Fibre Channel
”10 bit specification“
• Uses reference clock (RFCT) for Tx
data latching
• Half or full speed Rx clocks
• 5-Volt tolerant TTL I/Os
• Low power consumption
• 208 ball, 23 mm TBGA package
• Single +3.3 V power supply
• 1.5 kV ESD protection on all pins
• Equalizers on inputs
• Copper drive capability
• Buffered line logic outputs
Applications
• 1250 MBd Gigabit Ethernet high
density ports
• 1062.5 MBd Fibre Channel interface
• Mass storage system I/O channel
• Work station/server I/O channel
• FC interface for disk drives and
arrays
• Serial backplanes
• Clusters
per the 8B/10B encoding scheme,
with special reserve characters for
link management purposes. Other
encoding schemes will also work
as long as they provide dc balance
and sufficient transition density.
In order to accomplish this task,
the SERDES circuitry incorporates
the following:
•
•
•
•
TTL parallel I/Os
High-speed phase locked loops
Parallel-to-serial converter
High-speed serial clock and
data recovery circuitry
• Comma character recognition
circuitry for 8B/10B
• Character alignment circuitry
• Serial-to-parallel converter
PARALLEL INPUT LATCH
The transmitter accepts 10-bit
wide single-ended TTL parallel
data at inputs TX [0:3] [0:9]. The
RFCT pin is used as transmit byte
clock. The TX [0:3] [0:9] and
RFCT signals must be properly
aligned, as shown in Figure 3.
RFCT is also used as a clean frequency reference for the receiver
PLLs.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
generates all internal clocks
needed by the transmitter section
to perform its functions. These
clocks are based on the supplied
reference clock (RFCT). RFCT is
used as the frequency reference
clock for the PLL as well as for
the incoming data latches. The
RFCT clock is multiplied by 10 to
generate the serial rate clock
necessary for clocking the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the
10-bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
serial data streams. The data bits
are transmitted sequentially, from
TX [0:3] [0] to TX [0:3] [9].
SERIAL OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
2
In normal operation, LOOP is set
low and the serial data stream is
placed at SO [0:3] ± . When
wrap-mode is activated by setting
LOOP high, the SO [0:3] ± pins
are held static at logic 1 and the
serial output signal is internally
wrapped to the INPUT SELECT
block of the receiver section.
SERIAL INPUT SELECT
The INPUT SELECT block determines whether the signal at
SI [0:3]± or the internal loopback serial signal is used. In
normal operation, LOOP is set
low and the serial data is accepted at SI [0:3] ± . When LOOP
is set high, the outgoing high
speed serial signal is internally
looped-back from the transmitter
section to the receiver section.
This feature allows parallel
loopback testing, exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the incoming serial data stream and
recovering the bit and byte
clocks. The Rx PLL continually
frequency locks onto the reference clock, and then phase locks
onto the selected input data
stream. The frequency lock part
of the PLL is shared among all
channels. Phase locking is performed separately on each channel. An internal signal detection
circuit monitors the presence of
the input, and invokes the phase
detection once the minimum
differential input signal level is
supplied (AC Electrical Specifications). Once bit locked, the receiver generates the high speed
sampling clock at serial data
rates for the input sampler.
SERIAL INPUT SAMPLER
The INPUT SAMPLER converts
the serial input signal into a high
speed serial bit stream. In order
to accomplish this, it uses the
high speed serial clock recovered
from the RX PLL/CLOCK RECOVERY block. This serial bit stream
is sent to the FRAME DEMUX
AND BYTE SYNC block.
FRAME DEMUX, BYTE SYNC
The FRAME DEMUX, BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also responsible for recognizing the
comma character (K28.5+) of
positive disparity (0011111xxx).
When recognized, the FRAME
DEMUX, CHAR SYNC block
works with the RX PLL/CLOCK
RECOVERY block to properly
select the parallel data edge out
of the bit stream so that the
comma character starts at bit
RX [0:3] [0]. When a comma
character is detected and realignment of the receiver byte clock
RC [0:3] [0:1] is necessary, this
clock is stretched, not slivered, to
the next possible correct alignment position. This clock will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
will be aligned with the rising
edge of RC [0:3] [1] and will
follow it with a delay. This delay
guarantees hold time at the receiving ICs input latches. Comma
characters of positive disparity
must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain
their proper recovered frequencies.
PARALLEL OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks RC [0:3]
[0:1] as shown in Figure 5.
These output data buffers provide
single ended TTL compatible
signals.
RFCT
TX3
SI3
TX2
RX3
RC3
SO3
RX2
RC2
RX1
RC1
RX0
RC0
TX1
TX0
4-CHANNEL MAC
SI2
SO2
SI1
SO1
SI0
SO0
HDMP-1687
TX[0:3][0:9]
INPUT
LATCH
Figure 1. Typical application using HDMP-1687.
FRAME
MUX
OUTPUT
SELECT
LOOPBACK
TX PLL
CLOCK
GENERATOR
CAP0
CAP1
INPUT
SELECT
RX PLL
CLOCK
RECOVERY
OUTPUT
DRIVER
RX [0:3][0:9]
FRAME
DEMUX
AND
BYTE SYNC
SYN [0:3] SYNC
Figure 2. Block diagram of HDMP-1687.
3
LOOP
TX CLOCKS
RFCT
RC[0:3][0]
RC[0:3][1]
SO [0:3]±
RX CLOCKS
INPUT
SAMPLER
SI [0:3]±
Timing Characteristics for Gigabit Ethernet – Transmitter Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Ttxsetup
Tx Input Setup Time
ns
1.5
Ttxhold
Tx Input Hold Time
ns
0.5
t_txlat[1]
Transmitter Latency
ns
bits
Typ.
Max.
2.3
2.8
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
Timing Characteristics for Fibre Channel – Transmitter Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Ttxsetup
Tx Input Setup Time
ns
2.0
Ttxhold
Tx Input Hold Time
ns
1.5
t_txlat[1]
Transmitter Latency
ns
bits
Typ.
Max.
3.8
4.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
1.4 V
RFCT
2.0 V
TX [0:3] [0:9]
DATA
DATA
DATA
DATA
DATA
0.8 V
ttxsetup
ttxhold
Figure 3. Transmitter section timing.
TX BYTE A
SO [0:3] ±
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
TX BYTE B
S6
S7
S8
S9
S0
S1
S2
S3
S4
t_txlat
TX [0:3] [0:9]
RFCT
Figure 4. Transmitter latency.
4
TX BYTE B
TX BYTE C
S5
S6
Timing Characteristics for Gigabit Ethernet – Receiver Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
f_lock
Frequency Lock at Powerup
b_sync [1,2]
Bit Sync Time
trxsetup
RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)
trxhold
RX [0:3][0:9] Output Hold Time (Data Valid After Clock)
Tduty
RC [0:3][0] and RC [0:3][1] Duty Cycle
tA-B
Rising Edge Time Difference between RBC0 and RBC1 (Half Rate)
[3]
t_rxlat
Receiver Latency
Units
µs
bits
ns
ns
%
ns
ns
bits
Min.
Typ.
Max.
500
2500
2.5
2.0
40
7.5
60
8.5
20.7
26.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C PLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
Timing Characteristics for Fibre Channel – Receiver Section
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
f_lock
Frequency Lock at Powerup
b_sync [1,2]
Bit Sync Time
trxsetup
RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)
trxhold
RX [0:3][0:9] Output Hold Time (Data Valid After Clock)
Tduty
RC [0:3][0] and RC [0:3][1] Duty Cycle
tA-B
Rising Edge Time Difference between RBC0 and RBC1 (Half Rate)
[3]
t_rxlat
Receiver Latency
Units
µs
bits
ns
ns
%
ns
ns
bits
Min.
Typ.
Max.
500
2500
3.0
1.5
40
8.9
60
9.9
22.4
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C PLL = 0.1 µF.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
trxsetup
trxhold
1.4 V
RC [0:3] [1]
2.0 V
RX [0:3] [0:9]
K28.5+
DATA
DATA
DATA
DATA
0.8 V
2.0 V
SYNC
0.8 V
1.4 V
RC [0:3] [0]
Figure 5a. Receiver section timing (dual receive clocks).
5
tA-B
trxsetup
trxhold
1.4 V
RC [0:3] [1]
2.0 V
RX [0:3] [0:9]
DATA
K28.5
DATA
DATA
DATA
0.8 V
Figure 5b. Receiver section timing (single receive clock).
RX BYTE A
SI [0:3] ±
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
RX BYTE B
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
t_rxlat
RX BYTE A
RX [0:3] [0:9]
RC [0:3] [1]
Figure 6. Receiver latency.
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent damage
to this device. Continuous operation at these minimum or maximum ratings is not recommended.
Symbol
Parameter
Units
Min.
Max.
VCC
Supply Voltage
V
–0.5
4.0
VIN,TTL
TTL Input Voltage
V
–0.7
VCC + 2.8
VIN,HS_IN
HS_IN Input Voltage (Differential)
V
2.2
IO,TTL
TTL Output Sink / Source Current
mA
± 13
Tstg
Storage Temperature
°C
–65
+150
Tj
Junction Temperature
°C
0
+125
TC
Case Temperature
°C
0
+95
Guaranteed Operating Rates
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Parallel Clock Rate (MHz)
Min.
Max.
Serial Baud Rate (MBaud)
Min.
Max.
124.0
126.0
1240
1260
Gigabit Ethernet
105.25
107.25
1052.5
1072.5
Fibre Channel
6
Transceiver Reference Clock Requirements
T = 0°C Ambient to +85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
Max.
f
Nominal Frequency (for Gigabit Ethernet Compliance)
MHz
125
f
Nominal Frequency (for Fibre Channel Compliance)
MHz
106.25
Ftol
Frequency Tolerance
ppm
–100
+100
Symm
Symmetry (Duty Cycle)
%
40
60
TTL I/O DC Electrical Specifications
TA = 0°C Ambient to +85°C Case, V CC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
Max.
VIH,TTL
TTL Input High Voltage Level,
Guaranteed High Signal for All Inputs
V
2
5.5
VIL,TTL
TTL Input Low Voltage Level,
Guaranteed Low Signal for All Inputs
V
0
0.8
VOH,TTL
TTL Output High Voltage Level, IOH = –400 µA
V
2.2
VCC
VOL,TTL
TTL Output Low Voltage Level, IOL = 1 mA
V
0
0.5
IIH,TTL
Input High Current, VIN = 2.4 V, VCC = 3.45 V
µA
40
IIL,TTL
Input Low Current, VIN = 0.4 V, V CC = 3.45 V
µA
–600
ICC,TRx
Transceiver V CC Supply Current, T A = 25°C
mA
800
AC Electrical Specifications (TRx)
TA = 0°C Ambient to +85°C Case, V CC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
Max.
tr,TCi
RFCT Rise Time, 0.8 to 2.0 Volts
ns
0.2
2.4
tf,TCi
RFCT Fall Time, 2.0 to 0.8 Volts
ns
0.2
2.4
tr,TTLin
Input TTL Rise Time, 0.8 to 2.0 Volts
ns
1.0
tf,TTLin
Input TTL Fall Time, 2.0 to 0.8 Volts
ns
1.0
tr,TTLout
Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load
ns
1.5
2.4
tf,TTLout
Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load
ns
1.1
2.4
trs, HS_OUT
HS_OUT Single-Ended SO [0:3]± Rise Time
ps
200
300
tfs, HS_OUT
HS_OUT Single-Ended SO [0:3]± Fall Time
ps
200
300
trd, HS_OUT
HS_OUT Differential Rise Time
ps
200
300
tfd, HS_OUT
HS_OUT Differential Fall Time
ps
200
300
VIP,HS_IN
HS_IN Input Peak-To-Peak Differential Voltage
mV
200
1200
2000
VOP,HS_OUT [1]
HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ohms, Fig.10) mV
1000
1300
1800
Note:
1. Output Peak-to-Peak Differential Voltage specified as SO [0:3]+ minus SO [0:3]–. The output will be 25% higher when terminating into 75 Ω loads.
7
Figure 7a. Eye diagram of a high speed differential output for Gigabit Ethernet.
Figure 7b. Eye diagram of a high speed differential output for Fibre Channel.
Output Jitter Characteristics – Transmitter Section
TA = 0°C Ambient to +85°C Case, V CC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Typ.
RJ[1]
Random Jitter at SO [0:3]±, the High Speed Electrical Data Port,
specified as 1 sigma deviation of the 50% crossing point (RMS)
ps
11
DJ[1]
Deterministic Jitter at SO [0:3]±, the High Speed Electrical Data Port (pk-pk)
ps
36
Note:
1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown
in Figure 8.
8
A 70841B
PATTERN
GENERATOR
A 70311A
CLOCK SOURCE
+K28.5, –K28.5
A 70841B
PATTERN
GENERATOR*
+ DATA
– DATA
1.25 GHz
A 83480A
OSCILLOSCOPE
A 83480A
OSCILLOSCOPE
0000011111
+ DATA
– DATA
TRIGGER
125 MHz
CH1
1.25 GHz
A 70311A
CLOCK SOURCE
CH2
DIVIDE BY 10
CIRCUIT
(DUAL OUTPUT)
DIVIDE
BY 2
TRIGGER
CH1
VARIABLE
DELAY
+SOi
BIAS
TEE
–SOi
HDMP-1687
RFCT
+SOi
VARIABLE
DELAY
TTL
125 MHz
–SIi
+SIi
SYNC
LOOP
RFCT
TXi(0..9)
1.4 V
–SOi
HDMP-1687
LOOP
TXi(0-9)
*PATTERN
GENERATOR
PROVIDES A
DIVIDE BY 10
FUNCTION
CH2
RXi(0..9)
0011111000
(STATIC K28.7)
A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD
B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD
Figure 8. Transmitter jitter measurement method.
Thermal and Power Characteristics (TRx)
T = 0°C Ambient to 85°C Case, VCC = 3.15 V to 3.45 V
Symbol
Parameter
Units
Typ.
Max.
PD, TRx
Transceiver Power Dissipation, Outputs Connected
per Recommended Bias Terminations with Idle Pattern
W
2.6
3.3
θJA[1]
Thermal Resistance: Junction to Ambient
°C/W
15.8
θJC[2]
Thermal Resistance: Junction to Case
°C/W
2.5
ψJT[3]
Thermal Characterization Parameter: Junction to Package Top
°C/W
1.1
Notes:
1. θ JA is measured in a still air environment at 25°C on a standard 3 x 3" FR4 PCB as specified in EIA/JESD 51-7.
2. θ JC data relevant for packages used with external heat sink.
3. To determine the actual junction temperature in a given application, use the following: TJ = TT + (ψJT x PD), where T T is the case temperature
measured on the top center of the package and PD is the power being dissipated.
I/O Type Definitions
I/O Type
Definition
I-TTL
Input TTL, floats high when left open
O-TTL
Output TTL
HS_OUT
50 Ω matched output driver. Will drive AC coupled 50 Ω loads. PECL Level Compatible (Figure 10).
HS_IN
PECL Level Compatible. Must be AC coupled (Figure 10).
C
External Circuit Node
S
Power Supply or Ground
Pin Input Capacitance (TRx)
Symbol
Parameter
Units
Typ.
CINPUT
Input Capacitance on TTL Input Pins
pF
1.6
9
Max.
O_TTL
I_TTL
VCC
VCC
VCC
VBB 1.4 V
GND
GND
ESD
PROTECTION
ESD
PROTECTION
GND
Figure 9. O-TTL and I-TTL simplified circuit schematic.
HS_IN
HS_OUT
VCC
VCC
VCP
Zo
+
–
VCC
Zo
+
–
VCC
SO[0:3]+
Zo = 50 Ω
SI[0:3]+
0.01 µF
2 * Zo = 100 Ω
SO[0:3]–
0.01 µF
GND
Zo = 50 Ω
SI[0:3]–
GND
ESD
*ESD
PROTECTION
PROTECTION
GND
GND
NOTES:
1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
2. CAPACITORS MAY BE PLACED AT THE SENDING END OR THE RECEIVING END.
Figure 10. HS_OUT and HS_IN simplified circuit schematic.
10
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
A
GND
VCC
B
RX07 RX08 RX09 GND RC11 RX11 VCR1 RX17 GND SYN2 RX20 RX22 RX25 RX29 SYN3 RC30 RC31
C
RX04 RX05 RX06 VCR0 VCR1 RX12 GND RX18 N/C RC20 VCR2 RX23 RX26 VCC VCR3 GND RX30
D
RX00 RX01 VCR0 GND GND RX13 RX15 RX19 N/C RC21 GND RX24 RX27 RX31 RX32 RX33 RX34
E
RC00 RC01 RX02 RX03
VCR3 GND RX35 RX36
F
N/C SYN0 VCR0 GND
RX37 RX38 RX39 GND
GND RX21 VCR2 RX28 GND VCR2 GND
GND SYN1 RC10 RX10 RX14 RX16 VCR1 VCC
GND
TX22 TX21 TX20 VCR3
TX14 TX15 TX16 TX17
GNDA
TX26 TX25 TX24 TX23
J
TX10 TX11 TX12 TX13
VCRX
VCC TX29 TX28 TX27
K
N/C
VCC
GND GND
G
TX18 TX19 GND
H
N/C
VCC
GND GND
N/C
VCC
L
TX08 TX09 GND
VCC
VCCA
TX33 TX32 TX31 TX30
M
TX04 TX05 TX06 TX07
VCPX
TX37 TX36 TX35 TX34
N
TX00 TX01 TX02 TX03
P
LOOP VCC TX39 TX38
N/C
N/C
GND SO0– GND SO1– GND CAP0 GND SO2+ GND SO3+ GND
N/C
N/C
R
RFCT N/C
GND
VCC SO0+ GND SO1+ GNDA CAP1 GND SO2– GND SO3– VCC
GND
VCC SYNC
T
RCM0* GND
VCC
VCC VCP0 GND VCP1 GND VCCA GND VCP2 GND VCP3 VCC
GND GND
U
GND GND SIO– SIO+ VCC
N/C
SI1–
SI1+ GND GND SI2–
N/C
N/C
SI2+ GND SI3–
SI3+ GND GND GND
10
13
* Previously RFC1 changed to RFCT for data sheet consistency.
Figure 11. Pinout of HDMP-1687 (top view).
Filtering Schematic
01
02
03
04
05
06
0.1 µF
A
GND
07
08
09
VCC
GND
VCR
GND
C
VCR
VCR
VCR
GND
GND
F
VCR
GND
G
GND
VCC
D
14
VCC
15
16
17
GND
VCR
GND
VCC
VCR
GND
VCR
GND
0.1 µF
GND
VCR
GND
VCR
E
12
10 µF*
0.1 µF
B
11
GND
VCR
GND
0.1 µF
0.1 µF
GND
VCR
0.1 µF
* 10 µF PLACEMENT NOT CRITICAL – INDICATES
NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE
H
VCC
J
GND
GND
L
GND
VCC
0.1 µF
K
HDMP-1687
GND
GND
VCC
M
0.1 µF
N
GND
T
U
GND
GND
GND
VCC
VCC
VCC
GND
VCP
VCC
0.1 µF
GND
VCP
GND
GND
GND
GND
GND VCCA GND
GND GND
0.1 µF
10 µF
11
GND
GND
GND
VCP
GND
GND
0.1 µF
0.1 µF
R
VCC
GND
GND
P
VCP
VCC
GND
VCC
VCC
GND
GND
GND
GND
0.1 µF
TO VCCA PI-FILTER (SEE SCHEMATIC)
GND
Guidelines for Decoupling Capacitor Placements/Connections
+
VCC
10 µF *
C4
C5
D3
0.1 µF
F3
G4
L4
0.1 µF
VCR
VCR
A16
A13
A10
A9
VCR
VCC
B7
0.1 µF
VCR
VCC
A2
0.1 µF
VCR
VCR
VCR
VCR
VCR
VCR
VCC
VCR
VCC
HDMP-1687
GUIDELINES FOR
DECOUPLING CAPACITOR
PLACEMENTS/CONNECTIONS
VCR
C11
C14
C15
0.1 µF
E14
G17
VCC
J14
VCC
K16
VCC
N15
VCC
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VCC
0.1 µF
12
0.1 µF
10 µF
10 µF
+
VCC
VCC
R14
VCP
T14
R16
0.1 µF
* PLACEMENT NOT CRITICAL.
1 µH
+
T13
T11
VCP
VCCA
T9
T7
T5
U5
T3
T4
VCP
VCC
VCP
VCC
VCC
VCC
VCC
R4
+
0.1 µF
INDICATES THE NEED FOR ADDITIONAL
LOW FREQUENCY CAPACITIVE DECOUPLING.
+ OPTIONAL – PROVIDES INCREASED
LOW FREQUENCY DECOUPLING.
TRx I/O Definition
Name
Type
Signal
SI [0:3]+
SI [0:3]–
HS_IN
Serial Data Inputs: High-speed inputs. Serial data is accepted from the SI [0:3]±
inputs when LOOP is low.
SO [0:3]+
SO [0:3]–
HS_ OUT
Serial Data Outputs: High speed outputs. These lines are active when LOOP is
set low. When LOOP is set high, these outputs are held static at logic 1.
SYNC
I-TTL
Enable Byte Sync Input: When high, turns on the internal byte sync functions to
allow clock synchronization to a comma character of positive disparity (0011111XXX).
When the line is low, the function is disabled and will not reset registers and clocks,
or strobe the SYN [0:3] lines.
SYN [0:3]
O-TTL
Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma
character of positive disparity (0011111XXX) when SYNC is enabled.
N/C
These pins need to be left open. Do not apply voltage on this pin.
LOOP
I-TTL
Loopback Enable Input: When set high, the high speed serial signal is internally
wrapped from the transmitter’s serial loopback outputs back to the receiver‘s
loopback inputs. Also when in loopback mode, the SO [0:3]± outputs are held static
at logic 1. When set low, SO [0:3]± outputs and SI [0:3]± inputs are active.
RCM0
I-TTL
Receivers Clocking Mode Definition Pins: These pins define how received
parallel data are driven as follows:
RCM0
Receive Clock Mode
0
half speed dual clocks
1
full speed single clocks
RC [0:3] [0:1]
O-TTL
Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks
RC [0:3] [1]. Alternatively, they may drive half speed clocks RC [0:3] [0:1]. See RCM0
definition.
RFCT
I-TTL
Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host
system. The transmitter sections accept this signal as the frequency reference clock.
It is multiplied by 10 to generate the serial bit clock and other internal clocks. The
transmit sections use this clock as the transmit byte clock for transmitting parallel
data at TX [0:3] [0:9].
RX [0:3] [0]
RX [0:3] [1]
RX [0:3] [2]
RX [0:3] [3]
RX [0:3] [4]
RX [0:3] [5]
RX [0:3] [6]
RX [0:3] [7]
RX [0:3] [8]
RX [0:3] [9]
O-TTL
Data Outputs: Four 10 bit data bytes. RX [0:3] [0] are the first bits received.
CAP0
CAP1
C
Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected
across the CAP0 and CAP1 pins. (typical value = 0.1µF).
13
TRx I/O Definition, continued
Name
Type
Signal
TX [0:3] [0]
TX [0:3] [1]
TX [0:3] [2]
TX [0:3] [3]
TX [0:3] [4]
TX [0:3] [5]
TX [0:3] [6]
TX [0:3] [7]
TX [0:3] [8]
TX [0:3] [9]
I-TTL
Data Inputs: Four 10 bit, 8B/10B encoded data bytes. TX [0:3] [0] are the first bits
transmitted.
VCC
S
Power Supply: Nominally 3.3 volts. Used for logic and TTL inputs.
VCCA
S
Analog Power Supply: Nominally 3.3 volts. Used to provide a clean supply
line for the PLLs and high speed analog cells.
VCR3-0
S
Rx TTL Output Power Supply: Nominally 3.3 volts.
Used for all TTL receiver output buffer cells.
VCP3-0
S
High Speed Output Supply: Nominally 3.3 volts. Used only for the last stage
of the high speed transmitter output cells (HS_OUT) as shown in Figure 10.
Due to high current transitions, this Vcc should be well bypassed to a ground plane.
GND
S
Ground: Nominally 0 volts. All GND pads on the chip are connected to one ground slug
in the package which then distributes these to GND balls.
GNDA
S
Analog Ground: Normally 0 volts. All GND pads on the chip are connected to one
ground slug in the package, which then distributes these to GND balls.
208 Ball 23 mm x 23 mm TBGA Package Drawing
A1 CORNER
HDMP-1687
ABCD–N RE.FG
S YYWW
HONG KONG
TOP VIEW
Procedure to follow for soldering the HDMP-1687, 208-ball TBGA package:
IR or Convective Reflow per IPC/JEDEC J-STD-020A standard for BGA IR Reflow.
14
Package Drawing
D1
A2
S
A
O (4x)
e
e
S
E1
E
D
C
B
A
1 2 3 4 5
Nx0b
(CAVITY DOWN)
(BACKFILL)
DETAIL A
ddd
∅ eee M Z X Y
Z
[–Z–] SEATING PLANE
A1 CORNER
[–X–]
D
[–Y–]
A3
[–Z–]
SEATING PLANE
(BACKFILL)
DETAIL A
E
DIMENSIONS IN MILLIMETERS
SYMBOL
MIN.
NOM.
1.35
1.50
1.65
A1
0.60
0.65
0.70
A2
0.85
0.90
0.95
A3
0.15
D
23.00 ± 0.20
D1
TOLERANCE OF FORM AND POSITION
SYMBOL
MIN.
NOM.
MAX.
15
MAX.
A
20.32 BSC
E
23.00 ± 0.20
E1
20.32 BSC
MD/ME
17
N
208
N1
4
O
0.60
0.60
ddd
0.15
b
eee
0.30
e
0.75
1.27 ± 0.10
0.90
A1
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
September 21, 2001
Obsoletes 5988-1305EN
5988-4080EN